Circuit based on ising model with variable topology and in-memory computing

Abstract

This invention discloses a circuit based on the Ising model with variable topology and in-memory computation, relating to Ising model technology and addressing the insufficient adaptability of existing technologies. It includes a main controller, a global input module, a global output module, a read controller, a minimum topology array, and two first-in-first-out (FIFO) memories. The minimum topology array contains n×n minimum topologies, each containing a 6T memory array module, nine time-domain delay modules, a read driver module, a write driver module, a routing module, and a time-domain exponential function probability calculation module. The advantages are: achieving the versatility of deploying the Ising model on CMOS circuits, enabling efficient deployment of Ising models with different connections within the same chip, and achieving near-complete reuse efficiency for the multiplexed modules. Furthermore, mapping the calculation results to time-domain pulse widths rather than digital-domain bit-width extensions significantly reduces the use of adders.

Description

Technical Field

[0001] This invention relates to Ising model technology, and more particularly to a circuit based on the Ising model with variable topology and in-memory computation. Background Technology

[0002] Combinatorial optimization problems are a class of problems that seek optimal solutions in discrete states. They are widely found in various fields such as defense, transportation, product manufacturing, management decision-making, power, and communications. Typical examples include classic scenarios such as the Traveling Salesman Problem, the Knapsack Problem, the Vehicle Routing Problem, the Workshop Scheduling Problem, the Minimum Vertex Cover Problem, and the Minimum Dominant Set Problem. The vast majority of these problems are NP-hard—meaning that an exact optimal solution cannot be obtained in polynomial time. Therefore, the core objective is to obtain a relatively optimal result in a relatively short time.

[0003] The Ising model, through its highly abstract representation of the phase transition process in ferromagnetic materials, combines the advantages of structural simplicity and efficient solution, enabling it to be quickly adapted and applied to multiple cross-disciplinary scenarios. Based on this characteristic, by mapping a combinatorial optimization problem to the Ising model using precise mathematical formulas, solving for the minimum energy value in the Ising model, and then mapping the result back to the original problem, a relatively optimal solution to the combinatorial optimization problem can be obtained efficiently.

[0004] The Ising model abstracts atoms as spins, with states either up or down. Spin interactions determine whether the influence on a state tends towards uniformity or reversal, based on the sign of the interaction coefficient, and the magnitude of the influence is determined by the magnitude of the interaction coefficient. Based on the state and interaction coefficient of a given spin relative to surrounding spins, the current energy of that spin can be calculated—if it conforms to the relationship determined by the interaction coefficient, its energy will be lower. With other spin states unchanged, we can determine the direction of the lowest energy for a single spin through calculation. However, after successively changing the states of several spins, the previously adjusted spin direction may no longer be the lowest energy direction. Furthermore, it is possible that when every spin is in the direction of the lowest energy point of its current state, the overall system energy is not at its lowest, but in a local optimum state. In this case, changing the direction of any spin will increase the overall system energy. Therefore, a probability flip function A( )=1 / (1+exp( / T) ) (Gibbs algorithm), when energy When the value is negative, it means that the energy is decreasing, and the flip probability will approach 1. When the temperature T is high, the flip probability approaches 0.5. Through simulated annealing algorithm, the temperature slowly decreases from high to low. During this period, the spin is flipped continuously through the probability flip function, so that the overall energy of the system continuously approaches the minimum value while escaping the local optimum, thereby reaching the global optimum.

[0005] When the Ising model is actually deployed in CMOS circuits, it needs to be transformed into Ising models with different topologies depending on the complexity of the combinatorial optimization problem. Common types include lattice graph models (each spin interacts only with spins in the four directions of up, down, left, and right), king graph models (each spin interacts only with spins in the eight directions of a star pattern), and fully connected graph models (each spin interacts with all other spins). Different topologies of the Ising model correspond to different algorithm designs and solution processes, thus "one Figure 1 With the advent of chip-based computing, different interconnected models are difficult to reuse on the same chip. Furthermore, because chip resources are limited, the actual deployment size of the Ising model is constrained. Additionally, when calculating spin energy in a large-scale Ising model, such as a 1024-spin fully connected model where each action coefficient is 5 bits, the energy calculation adder requires 1024 15-bit adders to ensure the result doesn't overflow. Although some large-bit adders can be saved using adder trees, a significant amount of resources inevitably remains idle for extreme cases. After calculating the energy, the Gibbs algorithm, which includes an exponential function, is needed to calculate the flip probability. Calculating the exponential function consumes substantial hardware resources. Current research simplifies the simulation of the exponential function using multi-segment functions, but this leads to a decrease in accuracy.

[0006] In summary, there is still no good solution for an annealing processor architecture that can simultaneously adapt to Ising models with different topologies, adapt to Ising models of different sizes, have few adder resources, and bypass the use of digital hardware to calculate exponential functions. Summary of the Invention

[0007] The purpose of this invention is to provide a circuit based on the Ising model with variable topology and in-memory computation, so as to solve the problems existing in the prior art.

[0008] The circuit based on the Ising model with variable topology and in-memory computation described in this invention includes a main controller, a global input module, a global output module, a read controller, a minimum topology array, and two first-in-first-out (FIFO) memories. The first FIFO memory is used to store control commands and initialization data, and the second FIFO memory is used to store read spin states. The minimum topology array contains n×n minimum topologies, and each minimum topology contains a 6T memory array module, nine time-domain delay modules, a read driver module, a write driver module, a routing module, and a time-domain exponential function probability calculation module.

[0009] The circuit based on the Ising model with variable topology and in-memory computation described in this invention has the advantage of achieving the versatility of deploying the Ising model on CMOS circuits, enabling efficient deployment of Ising models with different connections within the same chip, and achieving near-complete reuse efficiency of the reused modules. This allows for flexible selection of the optimal mapping model based on different combinatorial optimization problems, thereby improving the solution speed. Furthermore, hardware circuit resources are significantly reduced. Traditional digital schemes require a large number of wide-bit adders to calculate spin energy, while this invention maps the calculation result to a time-domain pulse width rather than a digital-domain bit-width extension, significantly reducing the use of adders. Since the calculation result is a time-domain pulse width, a capacitor cross-charging and discharging model is used to calculate the exponential function, accurately calculating the exponential function with a small number of analog devices, further reducing hardware resource consumption. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a circuit based on the Ising model with variable topology and in-memory computation, as described in this invention.

[0011] Figure 2 This is a schematic diagram of the minimum topology structure described in this invention.

[0012] Figure 3 This is a schematic diagram of the method for performing full connectivity using the minimum topology in this invention.

[0013] Figure 4 This is a schematic diagram of the time domain delay module described in this invention.

[0014] Figure 5 This is a schematic diagram of the time-domain exponential function probability calculation module described in this invention. Detailed Implementation

[0015] like Figures 1 to 5 As shown, the circuit based on the Ising model with variable topology and in-memory computation described in this invention includes a main controller, a global input module, a global output module, a read controller, a minimum topology array, and two first-in-first-out (FIFO) memories. The first FIFO memory stores control commands and initialization data, while the second FIFO memory stores read spin states. The minimum topology array contains n×n minimum topologies, each of which includes a 6T memory array module, nine time-domain delay modules, a read-drive module, a write-drive module, a routing module, and a time-domain exponential function probability calculation module.

[0016] The main controller comprises a random spin selector and a finite state machine. The main controller is responsible for controlling the control signals of all modules and inputting initialization data into the minimum topology. The entire calculation process is as follows: When the finite state machine is in the initialization state S0, the main controller reads the control commands and initialization data from the first first-in-first-out memory, converts the commands into control signals, and stores the initialization data into the 6T storage array module through the write driver module of the minimum topology. The initialization data is the interaction coefficients of all spins. Subsequently, the finite state machine enters the spin selection state S1, where the random spin selector in the main controller selects a spin, activates all minimum topologies containing that spin, and sends the spin's direction state and spin interaction coefficients to the time domain delay module. After calculation, the time domain signal is sent to the time domain signal router in the routing module. The finite state machine enters the time domain signal routing state S2, controlling the merging of all time domain signals, and summing all calculation results gives the energy of that spin. The finite state machine then enters the probability calculation state S3, sending the merged signal to the time-domain exponential function probability calculation module. If the output is a flip, the finite state machine enters the spin update state S4, where the main controller sends a signal to update all minimum topologies containing that spin. After the update is complete, the finite state machine re-enters the spin selection state S1. If the output is a non-flip, the finite state machine directly returns to the spin selection state S1. After updating several spins, the main controller lowers the temperature parameter of the time-domain exponential function probability calculation module in the minimum topology, thereby implementing the time-domain simulated annealing algorithm. When the temperature finally drops to 0 and the overall system energy is at its lowest, the finite state machine enters the calculation completion output state S5, outputting a control signal to the read drive module of the minimum topology to read the state of all spins, sending it to the read controller and the second first-in-first-out memory, and finally reading it out to the outside world.

[0017] The global input module and global output module serve as bridges connecting different chips, linking the minimum topology of this chip with the minimum topology of adjacent chips to transmit interaction coefficients, spin state information, and time-domain signals, thereby achieving scalability.

[0018] The read controller reads the spin information of the minimum topology in sequence, sends the spin information into the second first-in-first-out memory in sequence, and then outputs it to the outside world.

[0019] The 6T memory array module contains 16×9×5bit data, representing 16 spins, each containing 9 coefficient storage spaces, each space being 5 bits in size. The 16 spins are evenly divided into left and right groups. By adjusting the data stored in the coefficient storage spaces and optimizing the topology, the resulting King's Graph and fully connected graph can achieve 100% utilization of the coefficient storage space. This makes using different connection graphs within the same chip a reasonable option for solving the Ising model, thus enabling simultaneous adaptation of Ising models with different topologies within the same chip.

[0020] The following will elaborate on the specific data stored in the storage space for the nine coefficients in different connection graphs:

[0021] In a fully connected graph, one coefficient storage space stores the self-interaction coefficient, and eight coefficient storage spaces store the interaction coefficients with the opposite group. For example, in the nine coefficient storage spaces of the first spin on the left, one coefficient storage space stores the self-interaction coefficient, and the remaining eight coefficient storage spaces store the interaction coefficients between the first spin on the left and the eight spins on the right.

[0022] In a king diagram, one coefficient storage space stores the self-interaction coefficient, and eight coefficient storage spaces store the interaction coefficients with spins in eight directions: top left, top, top right, right, bottom right, bottom, bottom left, and left. These directions can span the minimum topologies. For example, in a 2×2 minimum topologies, the stored data for the 8th spin in the right group of the first minimum topology in the first row is as follows: the first coefficient storage space stores the self-interaction coefficient, and the remaining eight coefficient storage spaces store the interaction coefficients with the 7th spin to the left of the first minimum topology in the first row, the 7th spin to the right of the first minimum topology in the first row, the 7th spin to the left of the second minimum topology in the first row, the 8th spin to the left of the second minimum topology in the first row, the 1st spin to the left of the second minimum topology in the second row, the 1st spin to the right of the first minimum topology in the second row, the 1st spin to the left of the first minimum topology in the second row, and the 8th spin to the left of the first minimum topology in the first row.

[0023] The following section will explain how to construct different connection graphs using minimal topology:

[0024] When constructing a fully connected graph, such as a fully connected graph with 24 spins, where each spin needs to be interconnected, 3×3 minimal topologies are required. In the first row, the rightmost eight spins of the three minimal topologies are all spins 1-8. In the second row, the leftmost eight spins of the three minimal topologies are spins 1-8, 9-16, and 17-24, respectively. This achieves full connectivity between spins 1-8 and 1-24 in the first row. Similarly, in the second row, the rightmost eight spins of the three minimal topologies are all spins 9-16, and the leftmost eight spins of the three minimal topologies are also spins 1-8, 9-16, and 17-24, respectively. This achieves full connectivity between spins 9-16 and 1-24. Likewise, the third row achieves full connectivity between spins 17-24 and 1-24. This creates a fully connected graph where each spin is connected to all other spins.

[0025] When constructing a King's Graph, according to its definition, each spin is connected only to the eight spins in the eight different directions surrounding it in a star-shaped pattern. Although this crosses the minimum topology, spin information can be transmitted and retrieved through the routing module. This achieves a King's Graph where each spin is connected only to spins in the eight directions of the star-shaped pattern.

[0026] The time-domain delay module is used to map the calculation results to the time-domain pulse width, rather than performing bit-width expansion in the digital domain. Calculation is required. ,in It is the spin interaction coefficient. It is in a spin state. It is the spin self-action coefficient. This is already set when data is retrieved from storage. Once the product is calculated, the result is a 5-bit signed number. The remaining task is to add these items together.

[0027] The specific operation is as follows: Two analog signals are generated, both initially transitioning from 0 to 1 at time 0. First, the sign bit (the highest bit) is used to determine which signal is delayed: a positive sign bit delays the upper branch, and a negative sign bit delays the lower branch (equivalent to advancing the other branch). The branch requiring delay will pass through delay circuits with delays of 8, 4, 2, and 1 time units respectively, but which can be bypassed. The bypass circuits are controlled by the lower 4 bits. After passing through this delay module, pulse width information containing this 5-bit number is obtained. Nine such delay modules are placed within a minimal topology, and the two signals are sequentially passed through these nine delay modules (each controlled by a different 5-bit number). This yields pulse width information containing nine 5-bit numbers. This calculation result corresponds to the energy of a certain spin within this minimal topology. In a king graph, a spin interacts only with eight other spins and itself, containing only nine coefficients, so its energy has already been calculated. In a fully connected graph, only a portion of the spin's energy has been calculated. Therefore, the pulse width information needs to be sent to the next minimal topology containing the spin's energy, and this process is repeated through all minimal topologies containing the spin's energy to complete the calculation. After confirming the calculation is complete, the two branches are XORed, and the pulse width is the result. A signal is generated indicating whether the pulse width is delayed (positive) or advanced (negative). This pulse width is then sent to the time-domain exponential function probability calculation module.

[0028] The write driver module is responsible for storing the initialized interaction coefficients into the coefficient storage space, while the read driver module is mainly responsible for cooperating with the read controller to read the spins into the second first-in-first-out memory.

[0029] The routing module is responsible for transmitting signals within the minimum topology structure, and includes a time-domain signal router and a multi-module router. The time-domain signal router is primarily responsible for transmitting the time-domain signals calculated within the minimum topology structure. Based on the signals from the central controller and the topology information, the time-domain signal router can transmit the time-domain signals to different minimum topologies. The multi-module router is primarily responsible for transmitting and receiving the spin states and interaction coefficients of adjacent minimum topologies.

[0030] The time-domain exponential function probability calculation module includes a capacitor charging / discharging device and an adjustable resistor. The charging / discharging speed is controlled by the adjustable resistor (equivalent to adjusting the temperature variable in the Ising model). The charging / discharging is determined by the positive or negative value, and the charging / discharging time is controlled by the pulse width output by the internal time-domain delay module. The calculation process is as follows: First, pre-charge to VDD / 2. Then, use the calculated pulse width to open the switch for charging / discharging. The final voltage is the spin flipping probability. Then, compare it with a random voltage ranging from 0 to VDD to determine if the spin has flipped. If the voltage is greater than the random voltage, it does not flip; if the voltage is less, it flips.

[0031] For those skilled in the art, various other corresponding changes and modifications can be made based on the technical solutions and concepts described above, and all such changes and modifications should fall within the protection scope of the claims of this invention.

Claims

1. A circuit based on the Ising model with variable topology and in-memory computation, characterized in that, It includes a main controller, a global input module, a global output module, a read controller, a minimum topology array, and two first-in-first-out (FIFO) memories. The first FIFO memory stores control commands and initialization data, and the second FIFO memory stores the read spin states. The minimum topology array contains n×n minimum topologies, and each minimum topology contains a 6T memory array module, nine time-domain delay modules, a read driver module, a write driver module, a routing module, and a time-domain exponential function probability calculation module.

2. The circuit based on the Ising model with variable topology and in-memory computation according to claim 1, characterized in that, The main controller includes a random spin selector and a finite state machine; the main controller is responsible for the control signals of all modules and inputting the initialization data into the minimal topology.

3. The circuit based on the Ising model with variable topology and in-memory computation according to claim 2, characterized in that, The calculation process of the overall controller is as follows: When the finite state machine is in the initialization state S0, the overall controller reads the control commands and initialization data in the first first-in-first-out memory, converts the control commands into control signals, and stores the initialization data into the 6T storage array module through the write drive module of the minimum topology structure; the initialization data is the interaction coefficient of all spins; The finite state machine then enters the spin selection state S1, where the random spin selector in the main controller selects a spin, activates all the smallest topologies containing that spin, and sends the spin's orientation state and spin interaction coefficient to the time domain delay module. After the calculation is completed, the time domain signal is sent to the time domain signal router in the routing module; the finite state machine enters the time domain signal routing state S2, controls the merging of all time domain signals, and the sum of all calculation results is the energy of the spin; The finite state machine then enters the probability calculation state S3, sending the merged signal to the time-domain exponential function probability calculation module. If the output is a flip, the finite state machine enters the spin update state S4, where the main controller sends a signal to update all minimum topologies containing that spin. After the update is complete, the finite state machine re-enters the spin selection state S1. If the output is no flip, the finite state machine directly returns to the spin selection state S1. After updating several spins, the main controller lowers the temperature parameter of the time-domain exponential function probability calculation module in the minimum topology. When the temperature finally drops to 0 and the overall system energy is at its lowest, the finite state machine enters the calculation completion output state S5, outputting a control signal to the read drive module of the minimum topology to read the state of all spins, sending it to the read controller and the second first-in-first-out memory, and finally reading it out to the outside world.

4. The circuit based on the Ising model with variable topology and in-memory computation according to claim 3, characterized in that, The global input module and global output module are used for communication between different chips, connecting the minimum topology of this chip and the minimum topology of adjacent chips to transmit interaction coefficients, spin state information and time domain signals.

5. The circuit based on the Ising model with variable topology and in-memory computation according to claim 4, characterized in that, The 6T memory array module contains 16×9×5bit data, which means 16 spins, each spin contains 9 coefficient storage spaces, and each storage space is 5 bits in size; the 16 spins are evenly divided into left and right groups.

6. The circuit based on the Ising model with variable topology and in-memory computation according to claim 5, characterized in that, In a fully connected graph, one coefficient storage space stores the self-interaction coefficients, and eight coefficient storage spaces store the interaction coefficients with the opposite group. In the King's Diagram, one coefficient storage space stores the self-interaction coefficient, and eight coefficient storage spaces store the interaction coefficients of the spins in the eight directions: top left, top, top right, right, bottom right, bottom, bottom left, and left. The orientation is set as the minimum topology structure that can be spanned.

7. The circuit based on the Ising model with variable topology and in-memory computation according to claim 6, characterized in that, The time-domain delay module is used to map the calculation results to a time-domain pulse width. ,in It is the spin interaction coefficient. It is in a spin state. It is the spin self-actualization coefficient.

8. The circuit based on the Ising model with variable topology and in-memory computation according to claim 7, characterized in that, The routing module is the module responsible for transmitting signals in the minimum topology, and includes a time-domain signal router and a multi-module router. The time-domain signal router is used to transmit the time-domain signal calculated in the minimum topology. The time-domain signal router transmits the time-domain signal to different minimum topologies according to the signal from the main controller and the topology information. The multi-module router is responsible for transmitting and receiving the spin states and interaction coefficients of adjacent minimum topologies.

9. A circuit based on the Ising model with variable topology and in-memory computation according to claim 8, characterized in that, The time-domain exponential function probability calculation module includes a capacitor charging and discharging device and an adjustable resistor. The charging and discharging speed is controlled by the adjustable resistor, and the charging or discharging is determined by judging the positive or negative value. The charging and discharging time is controlled by the pulse width output by the internal time-domain delay module.

10. A circuit based on the Ising model with variable topology and in-memory computation according to claim 9, characterized in that, The calculation process of the time-domain exponential function probability calculation module is as follows: First, precharge to VDD / 2, and use the calculated pulse width to turn on the switch for charging and discharging. The final voltage is the spin flipping probability. Then, compare it with a random voltage ranging from 0 to VDD to determine whether the spin flips. If the voltage is greater than the random voltage, the spin will not flip; if the voltage is less than the random voltage, the spin will flip.

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