LUT pack method and device based on backend feedback oriented optimization

Abstract

The present disclosure relates to the technical field of FPGA, and discloses a LUT Pack method and device based on backend feedback-oriented optimization, which comprises: in the logic synthesis stage, generating an initial configuration file; performing a first implementation process, performing layout and wiring on the target circuit design, and collecting physical information after layout and wiring; based on the collected physical information, optimizing and updating the constraint parameters in the initial configuration file to generate an updated configuration file; taking the updated configuration file as input, performing the next iteration process until the preset convergence condition is met, and finally outputting the optimized hardware design data. By introducing a closed-loop feedback and iterative optimization mechanism based on real physical information of backend layout and wiring, the present disclosure realizes dynamic self-adaptive adjustment of the LUT packing strategy, thereby overcoming the contradiction between resource utilization rate and timing performance, and achieving a global optimization balance between area efficiency and circuit performance.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of Field Programmable Gate Array (FPGA), in particular to a LUT Pack method and device based on backend feedback oriented optimization. BACKGROUND

[0002] As a high-performance reconfigurable computing platform, Field Programmable Gate Array (FPGA) has been widely used in various communication and computing scenarios. The core logic resources of FPGA are mainly composed of Look-Up Table (LUT), which can realize any Boolean logic function. In order to improve the resource utilization and running efficiency of FPGA, the industry generally adopts LUT Pack technology to merge multiple logically related or input shared LUTs into the same physical unit (such as double-output LUT), thereby reducing logic resource occupation, lowering path delay and optimizing wiring structure.

[0003] However, the related method mainly relies on static logic information in the synthesis stage for one-time packaging, lacks perception and feedback of real physical conditions after placement and routing, and thus leads to serious disconnection between packaging decision and backend implementation, that is, aggressive packaging for high utilization rate may cause timing violation and routing congestion, while conservative packaging for timing protection may cause resource waste. Therefore, there is an urgent need for a closed-loop mechanism that can dynamically adjust the packaging strategy according to the physical implementation feedback, so as to improve the resource utilization and timing performance at the same time, and realize more robust and efficient LUT Pack. SUMMARY

[0004] Therefore, the present disclosure provides a LUT Pack method and device based on backend feedback oriented optimization to solve the problem of how to dynamically adjust the packaging strategy according to the physical implementation feedback, so as to improve the resource utilization and timing performance at the same time, and realize more robust and efficient LUT Pack.

[0005] The present disclosure provides a LUT Pack method based on backend feedback oriented optimization, the method comprising:

[0006] In the logic synthesis stage, an initial configuration file is generated according to the target circuit design, and the initial configuration file contains constraint parameters for controlling LUT packaging;

[0007] A first implementation process is performed, the target circuit design is placed and routed, and physical information after placement and routing is collected, the physical information including but not limited to resource utilization, resource distribution and congestion information, critical path information and critical module information;

[0008] updating the constraint parameters in the initial configuration file based on the collected physical information to generate an updated configuration file;

[0009] performing a next iteration procedure with the updated configuration file as input, the next iteration procedure comprising: re-executing the procedure including logic synthesis and implementation, and collecting physical information and updating the configuration file again; repeating the next iteration procedure until a preset convergence condition is met, and finally outputting the optimized hardware design data.

[0010] The present disclosure also provides a LUT Pack device based on backend feedback oriented optimization, the device comprising:

[0011] an initial configuration generation module configured to generate an initial configuration file based on a target circuit design in a logic synthesis stage, the initial configuration file containing constraint parameters for controlling LUT packing;

[0012] a physical information collection module configured to perform a first implementation procedure, perform layout and routing on the target circuit design, and collect physical information after the layout and routing, the physical information including but not limited to resource utilization, resource distribution and congestion information, critical path information, and critical module information;

[0013] a configuration file optimization module configured to update the constraint parameters in the initial configuration file based on the collected physical information to generate an updated configuration file;

[0014] an iteration control and execution module configured to perform a next iteration procedure with the updated configuration file as input, the next iteration procedure comprising: re-executing the procedure including logic synthesis and implementation, and collecting physical information and updating the configuration file again; repeating the next iteration procedure until a preset convergence condition is met, and finally outputting the optimized hardware design data.

[0015] The present disclosure also provides an electronic device comprising: a memory configured to store a computer program; and a processor configured to implement the steps of any of the above LUT Pack methods based on backend feedback oriented optimization when executing the computer program.

[0016] The present disclosure also provides a computer readable storage medium having a computer program stored therein, wherein the computer program, when executed by a processor, implements the steps of any of the above LUT Pack methods based on backend feedback oriented optimization.

[0017] The present disclosure also provides a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above LUT Pack methods based on backend feedback oriented optimization.

[0018] In the LUT Pack method and device based on backend feedback-oriented optimization in the above-mentioned embodiments of the present disclosure, by introducing a closed-loop feedback and iterative optimization mechanism based on real physical information of backend layout and routing, dynamic adaptive adjustment of the LUT packing strategy is realized, thereby overcoming the contradiction between resource utilization and timing performance, and achieving a global optimization balance between area efficiency and circuit performance. By updating the configuration file according to the physical information extracted in the first implementation process, accurate packing control of timing-sensitive areas and routing bottleneck areas can be realized, the amplification effect of excessive packing on the critical path is effectively inhibited, and the timing convergence capability is significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 The flowchart of the LUT Pack method based on backend feedback-oriented optimization provided by the embodiments of the present disclosure is shown.

[0021] Figure 2 The common input signal diagram of the LUT Pack method based on backend feedback-oriented optimization provided by the embodiments of the present disclosure is shown.

[0022] Figure 3 The iterative flowchart of the LUT Pack method based on backend feedback-oriented optimization provided by the embodiments of the present disclosure is shown.

[0023] Figure 4 The structure diagram of the LUT Pack device based on backend feedback-oriented optimization provided by the embodiments of the present disclosure is shown.

[0024] Figure 5 The structure diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present disclosure.

[0026] In the design and implementation process of FPGA, LUT as the core programmable unit to realize the combination logic, its use efficiency is one of the key indicators to measure the quality of design. The LUT packing technology aims to merge multiple LUTs that have functional or input correlations into the same physical resource unit (such as double-output LUT) in the logic synthesis stage. This technology is an important bridge between connection logic optimization and physical implementation, and the advancement of its strategy directly determines the implementation effect of the final chip in multiple dimensions such as logic density, timing performance and routing feasibility.

[0027] Currently, the industry and academia mainly follow the following two types of technical paths for LUT Pack optimization, which have inherent defects of being disconnected from the physical implementation stage:

[0028] 1. Static heuristic packing strategy based on logic synthesis stage:

[0029] Such strategy is completely completed in the logic synthesis link, and its basis is limited to the logical topology structure information of the netlist after synthesis, such as the input sharing degree between LUTs, the logical connection relationship, etc. By setting fixed rules (for example, prefer to merge the LUT pair with the most shared inputs), the core optimization goal is to maximize the reduction of LUT total number. This method is simple to implement and is the mainstream approach in traditional design process. However, since the synthesis stage cannot predict the real chip state after placement and routing, this purely logic-based blind packing strategy has serious risks. The DLUT cluster generated by pursuing area optimization may be placed in an area with scarce resources or narrow routing channels in the subsequent placement and routing stage, thereby accidentally becoming the center of local routing congestion and an additional delay burden on the critical path. Essentially, this is an open-loop, predictive optimization, and its effect is highly uncertain.

[0030] 2. Conservative packing strategy based on estimated timing:

[0031] In order to alleviate the potential harm of the above strategy to timing, another idea is to introduce timing estimation based on simple models such as logic level in the synthesis stage, and use it to constrain the packing behavior. For example, avoid packing LUTs on paths with large logic depth, or generally use a more relaxed packing scale in the entire design. This method can protect the timing to some extent, but the cost is a significant sacrifice of potential logic compression benefits, resulting in low resource utilization. More importantly, this timing judgment based on early rough models is highly inaccurate, and may over-protect many non-critical paths, while the real critical back-end physical paths are not effectively protected due to model bias, causing mismatch of optimization resources.

[0032] The fundamental limitation of the prior art is its one-way nature and lack of physical feedback. Whether it is an aggressive area-driven or a conservative timing-driven strategy, the packing decision is made once at the early stage of the flow and enters the back-end physical implementation in the form of a fixed netlist. Once timing violations or congestion hotspots caused by improper packing are found after placement and routing, the entire flow lacks an effective closed-loop correction mechanism. Designers face a dilemma: either go back to the synthesis stage and manually adjust the constraints, start the entire time-consuming and lengthy synthesis and implementation cycle again, and try different static strategies; or accept a suboptimal implementation result. This trial-and-error type of broken flow seriously hinders the improvement of design automation and optimization quality.

[0033] Therefore, there is an urgent need in the industry for a new LUTPack method that can break the information barrier between logic synthesis and physical implementation. The ideal method should be able to draw on the true implementation field information (such as accurate timing reports, congestion heat maps, resource distribution) after the first physical implementation, and based on this, dynamically and directionally adjust the packing strategy to achieve adaptive optimization in subsequent iterations. By introducing this feedback-oriented, iterative optimization closed-loop mechanism, we can systematically achieve resource-efficient utilization, timing-reliable convergence, and smooth implementation of high-quality FPGA design in the complex multi-objective trade-off.

[0034] To solve the above problems, the LUTPack method and device based on back-end feedback-oriented optimization provided in various embodiments of the present disclosure, the method comprising: in the logic synthesis stage, generating an initial configuration file according to the target circuit design, the initial configuration file containing constraint parameters for controlling LUT packing; performing a first implementation flow, placing and routing the target circuit design, and collecting physical information after placement and routing, the physical information including but not limited to resource utilization, resource distribution and congestion information, critical path information and critical module information; based on the collected physical information, optimizing and updating the constraint parameters in the initial configuration file to generate an updated configuration file; taking the updated configuration file as input, performing a next iteration flow, the next iteration flow including: re-executing the flow including logic synthesis and implementation, and collecting physical information and optimizing and updating the configuration file again; repeatedly performing the next iteration flow until a preset convergence condition is met, and finally outputting the optimized hardware design data.

[0035] It should be noted that in the description of the present disclosure, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms "first", "second" and the like in the present disclosure are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0036] In order for those skilled in the art to better understand the present disclosure, the present disclosure will be further described in detail below with reference to the drawings and specific embodiments.

[0037] Reference is made to Figure 1 , Figure 1 The flowchart of the LUT Pack method based on backend feedback oriented optimization provided by the embodiments of the present disclosure can include the following steps:

[0038] Step S101, in the logic synthesis stage, an initial configuration file is generated according to a target circuit design.

[0039] In the present embodiment, the target circuit design can refer to a circuit description corresponding to a hardware function to be implemented, which can be written in a hardware description language (HDL), including but not limited to Verilog, VHDL or SystemVerilog.

[0040] After the target circuit design is processed by a logic synthesis tool, it can be converted into a netlist representation composed of basic logic cells (such as LUTs).

[0041] The logic synthesis stage can refer to a key step in the FPGA design process of converting HDL description into technology-dependent netlist. In this stage, the synthesis tool can perform logic optimization, technology mapping, etc. on the circuit, and can execute preliminary LUT packing according to the specified strategy.

[0042] The initial configuration file is a structured data file used to store and transmit LUT packing strategy parameters, which can be in text format (such as JavaScript Object Notation (JSON), eXtensible Markup Language (XML) or special constraint format) or binary format, and is intended to be read by the synthesis tool and used as a dynamic constraint condition in the packing decision process.

[0043] Here, the core content of the initial configuration file can be a set of configurable constraint parameters, which collectively define the scale, range and limit conditions of LUT packing behavior. The set of constraint parameters can refer to a series of quantifiable threshold values or Boolean conditions that collectively guide the synthesis tool to make judgments during the packing process.

[0044] For example, the types of constraint parameters can include but are not limited to: density control class, structure correlation class, timing class, load sensitivity class, etc.

[0045] The process of generating the initial configuration file can be implemented based on a static analysis of a netlist of the target circuit design; the static analysis can be performed at the beginning of the synthesis, by traversing the netlist structure, extracting topological features, and automatically calculating and setting initial values of the constraint parameters according to predefined empirical rules.

[0046] The final generated initial configuration file serves as a basis for the strategy of the first LUT packing operation in the subsequent implementation process.

[0047] In step S102, the first implementation process is performed to perform layout and routing for the target circuit design, and physical information after layout and routing is collected.

[0048] In this embodiment, the first implementation process can refer to the first complete logic synthesis and layout and routing closed loop based on the initial configuration file.

[0049] Specifically, the logic synthesis tool reads the initial configuration file, performs LUT packing operation according to the constraint parameters defined therein, generates a first packed netlist, and inputs the netlist to the layout and routing tool. The layout tool assigns each logic unit (including the DLUT generated by packing) in the netlist to a specific physical location on the FPGA chip according to the physical architecture of the FPGA chip. The routing tool establishes actual electrical connections between the placed logic units according to the configurable connection and switch resources on the chip, and finally generates a configuration file that can be downloaded to the FPGA for running, and simultaneously generates a series of implementation result reports.

[0050] Collecting physical information after layout and routing can refer to systematically extracting key indicators and data that can truly reflect the physical state of the design on a specific chip from various reports and data files generated by the first implementation process.

[0051] Here, the collected physical information can include but is not limited to resource utilization, resource distribution and congestion information, critical path information, and critical module information.

[0052] Specifically, the resource utilization can refer to the percentage or absolute number of various hardware logic and routing resources occupied on the target FPGA chip, such as LUT, Flip-Flop (FF), Digital Signal Processor (DSP), Block RAM (BRAM), and global / local routing resource consumption. The resource utilization can be obtained from the resource summary report generated by the implementation tool, and used to globally evaluate the area overhead and resource tension of the design.

[0053] Resource distribution and congestion information can refer to the spatial distribution of various resources on the two-dimensional plane of the chip, especially the routing congestion information, which can be used to quantify the degree of competition for routing demand in a particular area. Resource distribution and congestion information can be obtained by analyzing the layout and routing database or reading a dedicated congestion heat map, which can directly reveal the local hotspot area in the design and serve as a direct basis for identifying the routing bottleneck that may be caused by excessive packaging.

[0054] Critical path information can refer to one or more signal paths with the worst timing slack or negative slack identified by static timing analysis (STA) based on real routing delays after layout and routing. Critical path information can be extracted from the STA report, including the starting point and ending point of the path, the number of logic stages, the accurate delay of each segment of the unit and the wire network, and the final timing slack. It accurately points out the real bottleneck that restricts the running speed of the design.

[0055] Critical module information can refer to a sub-circuit module that has a significant impact on the overall design performance and realizability according to the comprehensive indicators such as the physical location of the module instance, the timing urgency, resource occupation density and routing congestion degree of the internal and surrounding area after physical implementation. Critical module information can be obtained by cross-analyzing the netlist hierarchy structure, the physical bounding box of the module and the congestion and timing data mentioned above.

[0056] In step S103, based on the collected physical information, the constraint parameters in the initial configuration file are optimized and updated to generate an updated configuration file.

[0057] In this embodiment, the optimization and update can refer to a feedback-driven dynamic parameter adjustment process, and the core logic can be that the physical information reflecting the first implementation of the real result collected in step S102 is taken as input, the constraint parameter values of the initial configuration file generated in step S101 are re-evaluated and revised through the preset analysis rules and decision logic, and a new version of configuration file more suitable for the current design physical state is generated, that is, the updated configuration file.

[0058] It can be understood that the optimization and update process of step S103 can realize reverse mapping and closed-loop correction from physical observation results to logical optimization strategies.

[0059] Specifically, the configuration file updated in this step is completely based on the real physical information obtained after the first implementation, rather than the prediction or estimation in the synthesis stage, which can make the parameter adjustment objective and targeted. The target of updating in this step is the constraint parameters in the initial configuration file, which can be used to guide the packing behavior of LUT. By adjusting their values or switch states, the decision tendency of the packing tool in the next round of synthesis can be directly changed.

[0060] Further, when updating the configuration file in this step, a specific optimization target can also be followed to seek a better balance between resource utilization and timing / routing performance.

[0061] For example, when the resource utilization indicates that the LUT resource usage exceeds the preset threshold, the update logic can tend to relax certain packing conditions (such as reducing the shared input number requirement) to allow more aggressive packing and improve area efficiency.

[0062] For another example, when the critical path information or congestion information represents that there is a timing bottleneck or a routing hotspot in a certain area, the update logic can tighten the packing constraints of LUTs in that area or related paths, or directly split the existing DLUT in that area to reduce coupling, delay or congestion.

[0063] Further, the result output by this step is the updated configuration file, which is compatible in structure with the initial configuration file, but the value of one or more constraint parameters has been modified, and the adjusted packing strategy can be encapsulated therein.

[0064] Through step S103, the embodiment can convert the experience of backend physical implementation into executable improvement instructions for frontend logic synthesis, so that the LUT packing strategy is no longer static and preset, but a dynamic strategy that can evolve adaptively according to the actual physical performance of the design.

[0065] Step S104, taking the updated configuration file as input, executes the next iteration process, which includes: re-executing the process including logic synthesis and implementation, and collecting physical information and updating the configuration file again; repeatedly executing the next iteration process until the preset convergence condition is met, and finally outputting the optimized hardware design data.

[0066] In the embodiment, the next iteration process in this step defines a complete feedback optimization sub-cycle. The sub-cycle specifically takes the updated configuration file generated by step S103 as the starting point, and sequentially executes the following three core sub-steps inside, constituting a complete iteration:

[0067] Step S1041, the logic synthesis tool reads the input configuration file of this iteration, re-packs and synthesizes the LUT based on the latest constraint parameters in the input configuration file, and generates a new netlist. Then, the netlist is sent to the placement and routing tool again to complete a new round of physical implementation.

[0068] Step S1042, from the new implementation results of this round, the physical information such as resource utilization, resource distribution and congestion information, and critical path information is extracted again according to the method of step S102.

[0069] Here, the information collected this time can be used to reflect the latest physical state based on the adjustment of the optimization strategy of the last round.

[0070] Step S1043, based on the latest physical information collected in this round, the constraint parameters of the configuration file used in the current iteration are evaluated and adjusted again according to the optimization logic of step S103, and an input configuration file for the next iteration is generated.

[0071] Further, the repeated execution of the next iteration process can refer to the above-mentioned sub-loop as a whole unit for multiple cycles. The input of each cycle is the configuration file optimized based on the feedback of its own implementation in the last cycle.

[0072] Through this iteration feedback mechanism, the LUT packing strategy can be continuously and dynamically adjusted according to the real physical state after each round of implementation, gradually driving the design to approach a more optimal balance point between resources, timing and routing.

[0073] Further, the iteration process is re-executed until the preset convergence condition is met, and the optimized hardware design data is finally output.

[0074] The preset convergence condition can include but is not limited to performance target achievement, optimization effect saturation or process control limitation.

[0075] The optimized hardware design data can be a data carrier of the optimal or satisfactory result generated when the iteration process terminates, which can usually be a co-optimized circuit netlist generated after the final iteration, or a bitstream file directly used to configure FPGA.

[0076] In the LUT Pack method and device based on backend feedback oriented optimization in the above embodiments of the present disclosure, by introducing a closed-loop feedback and iterative optimization mechanism based on real physical information of backend layout and routing, dynamic adaptive adjustment of the LUT packing strategy is realized, thereby overcoming the contradiction between resource utilization and timing performance, and achieving a global optimization balance between area efficiency and circuit performance. By updating the configuration file according to the physical information extracted in the first implementation process, accurate packing control of the timing sensitive area and the routing bottleneck area can be realized, the amplification effect of excessive packing on the critical path is effectively inhibited, and the timing convergence ability is significantly improved.

[0077] In one possible implementation of the above step S101, the initial configuration file is generated according to the target circuit design, including:

[0078] The netlist of the target circuit design is statically analyzed, and an initial packing constraint threshold is set based on the analysis result to generate the initial configuration file;

[0079] The static analysis and the set packing constraint threshold include at least one of the following:

[0080] Logical level analysis is performed, paths with a logic level exceeding a logic depth threshold are identified as initial critical paths, and constraints are configured to limit packing of LUTs on the initial critical paths;

[0081] Fan-out analysis is performed, and a maximum allowed fan-out number is configured to prohibit packing of candidate LUT pairs whose output fan-out numbers both exceed the maximum allowed fan-out number;

[0082] Input sharing analysis is performed, and a minimum shared input number is configured to select LUT pairs with a shared input number satisfying the minimum shared input number for packing;

[0083] An upper limit of the DLUT proportion is configured to control the overall density of packing.

[0084] In this embodiment, in the initial stage of logic synthesis, a series of automatic static analysis is performed to quickly understand the structural characteristics of the target circuit design, and the constraint parameters of the packing strategy are initialized based on the structural characteristics, thereby generating an initial configuration file with reasonableness and directionality.

[0085] Specifically, the netlist of the target circuit design after preliminary synthesis is received, and then static structural analysis is performed on the netlist. The analysis process can include one or more dimensions.

[0086] Preferably, in the logic level analysis, all paths in the netlist are traversed, the logic level number of each path, i.e., the number of LUTs in series on the path, is calculated, and the paths whose logic level number exceeds a preset logic depth threshold are identified as initial critical paths that need to be protected in priority, and special constraint attributes are marked for the LUTs located on the above paths in the generated configuration file, for example, the packing priority of the LUTs is lowered to the lowest or the packing is directly prohibited, so as to avoid the risk of additional delay on long paths caused by packing in advance in the early stage when accurate backend timing information is lacking.

[0087] In the fan-out analysis, the number of subsequent logic units driven by each LUT output port, i.e., the fan-out number thereof, is counted, and a maximum allowed fan-out number is set as a threshold. When evaluating whether two LUTs are suitable for packing, if the output fan-out numbers of both LUTs exceed the threshold, it is determined that the candidate pair belongs to a high-load signal cluster point, and a rule prohibiting the packing of the candidate pair is generated in the configuration file to avoid further aggregation of potential routing hotspots and to disperse the routing pressure from the source.

[0088] In the input sharing analysis, the number of input signals shared by any two LUTs is calculated, and a minimum shared input number is set as a screening threshold. Only when the shared input number of a candidate LUT pair reaches or exceeds the threshold, it is considered that the candidate LUT pair has sufficient logical correlation and is allowed to be included in the packable candidate set, so as to ensure that the packing operation can effectively utilize the shared resources of the input terminals, improve the area efficiency, and avoid forcibly combining unrelated logic units.

[0089] Here, the more the number of input signals shared between two LUTs, the higher the feasibility of packing between the two LUTs. For example, please refer to Figure 2 , Figure 2 The shared input signal diagram of the LUT Pack method based on backend feedback oriented optimization provided by the embodiments of the present disclosure is shown in Figure 2 As shown, the input signals of LUT6 include inputs 10-15, and the input signals of LUT5 include inputs 11-15, so the number of input signals shared between LUT6 and LUT5 is 5.

[0090] In addition, the upper limit of the DLUT proportion can also be set from a global perspective. The upper limit of the DLUT proportion can control the maximum allowed proportion of the number of DLUTs generated by packing in the entire design to the total LUT resources.

[0091] The synthesis tool dynamically controls the overall density of packing with the upper limit of the proportion as a constraint in the subsequent packing process, to prevent a globally difficult-to-implement resource shortage situation in the backend due to excessive pursuit of compression rate in the initial stage.

[0092] By performing one or more of the above analysis steps, a set of initial, quantified packing constraint thresholds can be automatically calculated and set based on the static characteristics of the target circuit design itself, and the set of packing constraint thresholds are structured written into the initial configuration file, so that the subsequent first LUT packing operation is no longer a blind or completely rule-based operation, but can be guided by the initial configuration file.

[0093] In the LUT Pack method and device based on backend feedback oriented optimization of the above embodiments of the present disclosure, by performing multi-dimensional static analysis on the netlist and setting quantized thresholds, the generated initial configuration file is not arbitrary or empirical, but a preliminary optimization scheme based on the structure characteristics of the design itself, thereby avoiding starting from a completely random or overly aggressive strategy, which can speed up the overall convergence speed. The pre-set rules can effectively avoid known high-risk packing operations before physical implementation, significantly reducing the probability of serious timing violations or un-routable situations in the first implementation result, and improving the robustness of the process. By sharing the lower limit of the input, the logical relevance of the packing is ensured, and by controlling the overall packing density through the upper limit of the DLUT ratio, the initial packing avoids structural chaos and excessive coupling while pursuing resource conservation, leaving necessary optimization freedom and resource margin for the backend placement and routing tool, which is beneficial to achieve the preliminary balance between area and performance.

[0094] In one possible implementation of the above step S102, the physical information after placement and routing is collected, including:

[0095] From the output results of the first implementation process, resource utilization information, resource distribution and congestion information, static timing analysis reports, and physical layout information are extracted;

[0096] Based on the static timing analysis report, at least one critical path is identified; and based on the physical layout information, at least one critical module is identified.

[0097] In this embodiment, the core of the present implementation can be to systematically analyze the standard output files and databases generated by the first implementation process, and to extract multi-dimensional data that can objectively reflect the real physical state of the target circuit design on the target FPGA chip.

[0098] Specifically, after the first implementation process is completed, various standard result files and databases generated by the process are automatically located and read.

[0099] Here, the extraction process can include: obtaining resource utilization information from the resource summary report to quantify the global area overhead;

[0100] The layout and routing database or congestion heat map is parsed to obtain resource distribution and congestion information to represent resource distribution and routing competition hotspots on the physical level;

[0101] reading the static timing analysis report to obtain accurate path delay and slack data;

[0102] accessing the physical design database to obtain physical layout information including the specific locations of the cells.

[0103] Further, after obtaining the above information, the identification operation is started.

[0104] The at least one critical path can be identified based on the static timing analysis report, which can mean that according to the timing performance indicators (such as timing slacks) of each signal path in the static timing analysis report, one or more paths that currently pose the greatest threat to timing constraints are screened out through preset judgment logic.

[0105] The at least one critical module can be identified based on the physical layout information, which can mean that one or more sub-circuit modules that have the most significant impact on the overall performance and realizability of the design are located through preset evaluation logic, in combination with the physical location, range, and physical features (such as resource density, wiring condition) of the module in the surrounding or inside.

[0106] In the LUT Pack method and device based on backend feedback-oriented optimization in the above embodiments of the present disclosure, the multi-dimensional physical information can be automatically extracted from the first implementation process output, which can realize comprehensive quantitative perception of the real physical state of the design on the chip; by identifying the critical path and the critical module based on the static timing analysis report and the physical layout information, respectively, the performance and congestion bottlenecks in the design are preliminarily and accurately located.

[0107] In one possible implementation manner of the above embodiment, the at least one critical path is identified based on the static timing analysis report, including:

[0108] Obtaining the timing slacks and the logic levels of each logic path in the static timing analysis report;

[0109] Grouping the paths with the same logic levels into the same group;

[0110] In each group, the paths are sorted according to the timing slacks from poor to good, and at least one path at the front of the sorting is marked as a critical path.

[0111] In this embodiment, the core of this implementation manner can be that the logic level is introduced as the grouping basis, and the timing criticality is compared within the path set with the same logic complexity, so that misjudgment caused by differences in path structures is avoided, and the real timing bottleneck caused by logic structure rather than pure wiring delay is more accurately located.

[0112] Specifically, first, the static timing analysis report is parsed to obtain the timing slack and the number of logic levels of each logic path. The timing slack represents the tightness of the path, and the smaller the value, the more critical it is. The number of logic levels represents the combinational logic units contained in the path, indicating the logic depth or inherent delay of the path.

[0113] Then, paths with the same number of logic levels are grouped into the same group. Here, since the number of logic levels essentially reflects the logic depth of the path, paths with the same number of levels have comparable structural complexity and inherent logic delay benchmarks.

[0114] Then, within each group, the paths are sorted from poor to good (i.e., in ascending order of numerical values) according to the timing slack of the paths.

[0115] After sorting, one or more paths with the worst timing slack (i.e., the first in the sorting) in each group are marked as critical paths.

[0116] Here, this method can ensure that from each typical logic depth category, the relatively most critical path in that category can be selected as the optimization target.

[0117] Through the above grouping and sorting within the group strategy, the defects of the traditional method of sorting according to the global timing slack can be avoided. The traditional method may misjudge a path with a low number of logic levels (simple structure) and a slightly poor slack due to poor local routing as more critical than a path with a high number of logic levels (complex structure) and a slightly better slack but with great optimization potential. The present implementation directs the optimization focus to the paths with the worst timing performance under the same logic depth through grouping comparison. These paths are often the real bottlenecks that are constrained by logic structure, have great optimization difficulty, and have a profound impact on overall performance.

[0118] In the LUT Pack method and device based on backend feedback guided optimization of the above embodiments of the present disclosure, by taking the number of logic levels as the grouping basis and comparing the timing slack between paths with the same complexity, the inherent structural differences of the paths are effectively eliminated, the accuracy and fairness of critical path identification are improved. The critical paths identified based on this method can better represent the fundamental timing bottlenecks caused by logic coupling or depth in the design. Adjusting the packing strategy for these paths can more effectively address the core issues affecting timing convergence and avoid wasting optimization efforts on secondary paths that only require simple routing adjustments, thereby achieving precise allocation of optimization resources.

[0119] In one possible implementation of the above embodiment, based on the physical layout information, at least one critical module is identified, including the following operations:

[0120] The physical layout information is analyzed to count the congestion degree of each module.

[0121] The modules are ranked according to the congestion degree, and at least one module with a high ranking is marked as a key module.

[0122] In this embodiment, the core of the present implementation can be that the congestion degree of the module is taken as a primary quantitative index for identifying the key module, and the global ranking and screening are performed based on the congestion degree, so that the local bottleneck region caused by the physical layout and routing competition in the design is objectively identified.

[0123] Specifically, after obtaining the physical layout information, each module instance in the design is independently analyzed, which can include:

[0124] According to the physical boundary range of the module, the specific region of the module on the chip is located;

[0125] The routing congestion map data corresponding to the region or the routing resource utilization rate and demand ratio near the port of the module are accessed;

[0126] A numerical congestion degree score representing the routing pressure of the module is generated by weighted calculation.

[0127] Here, the higher the congestion degree score is, the greater the risk of the region where the module is located becoming a routing hotspot is.

[0128] Further, after obtaining the congestion degree scores of all the modules, a ranking and marking operation is performed, all the modules are ranked from high to low (i.e., from the most serious congestion to the least serious congestion) according to the scores, and one or more modules with the highest ranking in the ranking sequence are marked as key modules.

[0129] For example, the top 10% of the modules or the modules with a congestion score exceeding a threshold are marked as key modules.

[0130] In the LUT Pack method and device based on the backend feedback oriented optimization in the above-mentioned embodiments of the present disclosure, the key regions affecting the routing quality are clearly identified from the entire design by statistically ranking the congestion degrees of the modules, and the physical congestion bottleneck is objectively and accurately quantified. By taking the congestion degree as the core basis for identifying the key module, the optimization process can actively focus on and intervene in the routing problems that may be caused by excessive packing, so as to improve the resource utilization rate while ensuring the quality of physical implementation.

[0131] In one possible implementation of the above step S103, based on the collected physical information, the constraint parameters in the initial configuration file are optimized and updated to generate an updated configuration file, including:

[0132] According to the collected physical information, at least one of the following optimization strategies is performed to adjust the constraint parameters:

[0133] If the resource utilization information indicates that the LUT resource utilization exceeds a set utilization threshold, the constraint condition for screening the packable LUT pair is relaxed in the updated configuration file.

[0134] For the LUTs in the identified critical path and / or critical module, constraints are configured in the updated configuration file to prohibit or limit the packing of the LUTs, or to perform splitting on the packed DLUTs in the critical path and / or critical module.

[0135] According to the resource distribution and congestion information, the congestion area after layout and routing is identified, and constraints are configured in the updated configuration file to perform splitting on the DLUTs located in the congestion area.

[0136] In this embodiment, as a preferred embodiment, three explicit and operable optimization strategies are defined, each of which can map a specific type of physical information to a direct modification instruction for the constraint parameters in the initial configuration file, thereby generating a corresponding updated configuration file.

[0137] Specifically, when it is determined according to the collected resource utilization information that the LUT resource usage of the current design has exceeded the preset utilization threshold, it indicates that the design may face area pressure.

[0138] At this time, the optimization update logic can execute the constraint condition for relaxing the screening of the packable LUT pair in the generated updated configuration file.

[0139] For example, increasing the upper limit of the DLUT ratio, reducing the minimum shared input number requirement, or relaxing the fanout limit. This strategy aims to prioritize the area efficiency of the design by encouraging more aggressive packing when resources are scarce, ensuring that it can be implemented in the target device.

[0140] Further, according to the identified critical path and / or critical module information, special constraints are configured for the LUTs located in these critical areas in the updated configuration file. For LUTs that have not been packed, instructions are configured to prohibit or limit packing to prevent the introduction of additional coupling delay. For packed DLUTs that already exist in these areas, explicit splitting instructions are configured.

[0141] Here, this strategy can directly intervene in the identified timing and performance bottlenecks, actively reduce the delay of the critical path by removing or avoiding unfavorable logic coupling, and is a targeted measure to improve timing convergence capability.

[0142] Further, based on the resource distribution and congestion information, the specific congestion area appearing after the first implementation is located. In the updated configuration file, the DLUT configuration split constraint existing in the area can be configured.

[0143] Here, this strategy does not directly change the packing screening rule, but performs a local de-aggregation operation aiming at the physical hot spot caused by the first packing layout, which is designed to directly alleviate the local routing resource competition, improve the signal integrity, and provide more flexible optimization space for the layout and routing tool in the next round of iteration.

[0144] In the LUT Pack method and device based on the backend feedback oriented optimization in the above-mentioned embodiments of the present disclosure, by directly mapping the resource utilization rate, the key area and the congestion information into specific constraint adjustment and split instructions, the LUT packing strategy can be adjusted in real time according to the urgent needs of the design in different aspects (such as area, timing or routing), so as to realize the dynamic adjustment of the packing strategy to the design state. By executing the split instruction on the DLUT in the key area and the congestion area, the reversible optimization capability of the packed structure is realized, which can make the optimization not only limited to prevention, but also capable of repairing the adverse packing results generated in the first implementation, thereby significantly improving the error correction capability and depth of the optimization process.

[0145] In one possible implementation of the above-mentioned embodiments, the preset convergence condition includes at least one of the following:

[0146] The critical timing index reaches or is better than the timing convergence target value, and the critical timing index includes the worst negative timing slack and the total negative timing slack;

[0147] The change rate of global resource utilization rate or congestion degree is lower than a set change rate threshold;

[0148] The number of iterations reaches a preset maximum number of iterations.

[0149] In this embodiment, after the end of each round of iteration process, one or more of the following conditions can be evaluated, which can include: performance target achievement, optimization effect saturation or process control limitation.

[0150] Among them, the performance target achievement specifically refers to checking the critical timing index obtained by static timing analysis.

[0151] Here, the critical timing index includes the worst negative timing slack (WNS), that is, the worst timing slack value in all paths; and the total negative timing slack (TNS), that is, the timing slack sum of all timing violation paths.

[0152] Specifically, the WNS / TNS values after the current iteration are compared with preset timing convergence target values (e.g., WNS≥0 ns, TNS≥0 ns); if the target values are reached or exceeded, it is determined that the design has met the basic timing requirements, and the optimization process can be successfully terminated.

[0153] Optimization effect saturation can refer to the calculation of the change of the key physical indicators between consecutive iterations.

[0154] For example, global resource utilization (such as total LUT usage) or global average congestion can be monitored.

[0155] Specifically, the change rate of these indicators between the current round and the last round is calculated. If the change rate is lower than a preset change rate threshold (e.g., less than 1%), it indicates that the marginal benefit brought by further iteration is very limited, and the optimization tends to be stable, so the process can be terminated to prevent unnecessary consumption of computing resources.

[0156] The process control limit can be to set a maximum number of iterations as a safety upper limit.

[0157] Specifically, regardless of the current optimization state, when the number of executed iteration rounds reaches this preset upper limit, the process will be forcibly terminated, thereby ensuring that the iteration does not run indefinitely due to unexpected situations.

[0158] In the LUT Pack method and device based on backend feedback-oriented optimization of the above-mentioned embodiments of the present disclosure, by setting specific timing convergence targets, the iteration optimization process has a clear performance endpoint, and the final output is a design result that satisfies the timing constraints with certainty, improving the engineering practicality of the process. By monitoring the change rate of the optimization effect, the iteration can be automatically stopped when the benefit decreases, avoiding excessive consumption of computing resources, and making the optimization process efficient and cost-effective. The setting of the maximum number of iterations can provide a final safety guarantee for the entire closed-loop system, ensuring that the process can automatically end within a controllable range in any situation, enhancing the stability and reliability of the overall system.

[0159] In an embodiment, please refer to Figure 3 , Figure 3 The iteration process schematic diagram of the LUT Pack method based on backend feedback-oriented optimization provided by the embodiments of the present disclosure is shown in Figure 3 as follows, which includes the following steps:

[0160] Step S301, determine the initial configuration file.

[0161] Step S302, execute the first implementation process.

[0162] Step S303, generate an updated configuration file.

[0163] Step S304, the next iteration process is repeatedly executed.

[0164] Step S305, it is judged whether the preset convergence condition is met; if yes, the process is ended, and if not, the process returns to step S303.

[0165] Here, if the preset convergence condition is met, the optimized hardware design data is outputted, and the iteration process is ended; if the preset convergence condition is not met, the configuration file is updated again based on the result of the current round, and a new round of iteration is restarted, until the convergence condition is met.

[0166] In an embodiment, a LUT Pack device 400 based on backend feedback oriented optimization is provided, which corresponds to the LUT Pack method based on backend feedback oriented optimization in the above embodiment. As shown in the figure, the device comprises: Figure 4

[0167] An initial configuration generation module 401 is configured to generate an initial configuration file according to a target circuit design in a logic synthesis stage, wherein the initial configuration file contains constraint parameters for controlling LUT packing;

[0168] A physical information collection module 402 is configured to execute a first implementation process, perform layout and routing on the target circuit design, and collect physical information after the layout and routing, wherein the physical information includes but is not limited to resource utilization rate, resource distribution and congestion information, critical path information and critical module information;

[0169] A configuration file optimization module 403 is configured to optimize and update the constraint parameters in the initial configuration file based on the collected physical information, so as to generate an updated configuration file;

[0170] An iteration control and execution module 404 is configured to execute a next iteration process with the updated configuration file as input, wherein the next iteration process includes: re-executing a process including logic synthesis and implementation, and collecting physical information and optimizing and updating the configuration file again; the next iteration process is repeatedly executed until a preset convergence condition is met, and finally the optimized hardware design data is outputted.

[0171] In an embodiment, the initial configuration generation module 401 is specifically configured to perform static analysis on a netlist of the target circuit design, and set an initial packing constraint threshold based on the analysis result, so as to generate the initial configuration file;

[0172] The static analysis and the set packing constraint threshold include at least one of the following:

[0173] ​performing logic level analysis, identifying paths with logic level exceeding a logic depth threshold as initial critical paths, and configuring constraints to limit packing LUTs on the initial critical paths;

[0174] performing fan-out analysis, configuring a maximum allowed fan-out number to prohibit packing candidate LUT pairs with output fan-out numbers exceeding the maximum allowed fan-out number;

[0175] performing input sharing analysis, configuring a minimum shared input number to screen LUT pairs with shared input numbers satisfying the minimum shared input number for packing;

[0176] configuring an upper limit of DLUT proportion to control the overall density of packing.

[0177] In an embodiment, the physical information collection module 402 is specifically configured to extract resource utilization information, resource distribution and congestion information, static timing analysis reports, and physical layout information from the output results of the first implementation process.

[0178] Based on the static timing analysis reports, at least one critical path is identified; and based on the physical layout information, at least one critical module is identified.

[0179] In an embodiment, the physical information collection module 402 is specifically configured to obtain timing slack and logic level of each logic path in the static timing analysis report.

[0180] Paths with the same logic level are grouped into the same group.

[0181] Within each group, the paths are sorted according to the timing slack from poor to good, and at least one path at the front of the sorting is marked as a critical path.

[0182] In an embodiment, the physical information collection module 402 is specifically configured to analyze the physical layout information and count the congestion degree of each module.

[0183] According to the congestion degree, each module is sorted, and at least one module at the front of the sorting is marked as a critical module.

[0184] In an embodiment, the configuration file optimization module 403 is specifically configured to perform at least one of the following optimization strategies to adjust the constraint parameters according to the collected physical information:

[0185] If the resource utilization information indicates that the LUT resource utilization exceeds a set utilization threshold, the constraint condition for screening packable LUT pairs is relaxed in the updated configuration file.

[0186] If the resource utilization information indicates that the LUT resource utilization exceeds a set utilization threshold, the constraint condition for screening packable LUT pairs is relaxed in the updated configuration file.For the identified critical path and / or LUT in the critical module, configure a constraint in the updated configuration file to prohibit or limit packing of the LUT, or perform splitting on the packed DLUT in the critical path and / or critical module.

[0187] According to the resource distribution and congestion information, identify the congestion area after layout and routing, and configure a constraint in the updated configuration file to perform splitting on the DLUT located in the congestion area.

[0188] In an embodiment, the preset convergence condition includes at least one of the following:

[0189] The critical timing index reaches or is better than the timing convergence target value, and the critical timing index includes the worst negative timing slack and the total negative timing slack;

[0190] The change rate of global resource utilization or congestion degree is lower than a set change rate threshold;

[0191] The number of iterations reaches a preset maximum number of iterations.

[0192] It should be noted that: the LUT Pack device based on backend feedback oriented optimization provided in the above embodiments, when implementing the corresponding LUT Pack method based on backend feedback oriented optimization, only the above-mentioned division of each program module is exemplified, and in actual application, the above-mentioned processing can be completed by different program modules according to needs, that is, the internal structure of the above-mentioned device is divided into different program modules to complete all or part of the above-mentioned processing. In addition, the device provided in the above embodiments and the corresponding Figure 1 Embodiments of the method belong to the same concept, and the specific implementation process is described in detail in the method embodiments, which will not be repeated here.

[0193] The embodiments of the present disclosure also provide an electronic device having the above-mentioned Figure 4 The LUT Pack device based on backend feedback oriented optimization shown.

[0194] Figure 5 A structural schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0195] The specific reference will be made below Figure 5which shows a structural schematic diagram suitable for being used to implement an electronic device in the embodiments of the present disclosure. The electronic device can include a processor (such as a central processor, a graphic processor, etc.) 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the electronic device are also stored. The processor 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0196] Generally, the following devices can be connected to the I / O interface 505: an input device 506 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage 508 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 509. The communication device 509 can allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. Although Figure 5 The electronic device with various devices is shown, but it should be understood that all the shown devices are not required to be implemented or possessed, and more or fewer devices can be alternatively implemented or possessed.

[0197] In particular, according to the embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, the embodiments of the present disclosure include a computer program product including a computer program carried on a non-transitory computer readable medium, the computer program containing program codes for executing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network through the communication device 509, or installed from the storage 508, or installed from the ROM 502. When the computer program is executed by the processor 501, the above-mentioned functions defined in the network data stream hardware offload method of heterogeneous descriptor unified processing of the embodiments of the present disclosure are performed.

[0198] Figure 5 The electronic device shown is only an example and should not bring any limitation to the functions and use range of the embodiments of the present disclosure.

[0199] The embodiments of the present disclosure further provide a computer readable storage medium, and the method according to the embodiments of the present disclosure can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented by computer code originally stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk or a solid state disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that the computer, processor, microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, processor or hardware, the hardware offloading method of the network data stream of the heterogeneous descriptor uniform processing shown in the above embodiments is implemented.

[0200] Part of the present disclosure can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present disclosure can be invoked or provided. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source file, executable file, installation package file, etc., and accordingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0201] Although the embodiments of the present disclosure are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present disclosure, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A LUT Pack method based on backend feedback oriented optimization, characterized in that, The method comprises: In a logic synthesis stage, an initial configuration file is generated according to a target circuit design, wherein the initial configuration file contains constraint parameters for controlling LUT packing; A first implementation process is performed, the target circuit design is laid out and routed, and physical information after layout and routing is collected, wherein the physical information includes but is not limited to resource utilization, resource distribution and congestion information, critical path information and critical module information; Based on the collected physical information, the constraint parameters in the initial configuration file are optimized and updated to generate an updated configuration file; The updated configuration file is taken as input, and a next iteration process is performed, which includes re-executing the process including logic synthesis and implementation, and collecting physical information and optimizing and updating the configuration file again; the next iteration process is repeatedly executed until a preset convergence condition is met, and finally optimized hardware design data is output; Wherein, based on the collected physical information, the constraint parameters in the initial configuration file are optimized and updated to generate an updated configuration file, comprising: According to the collected physical information, at least one of the following optimization strategies is executed to adjust the constraint parameters: If the resource utilization information indicates that the LUT resource utilization exceeds a set utilization threshold, the constraint condition for screening packable LUT pairs is relaxed in the updated configuration file; For the LUTs in the identified critical path and / or critical module, constraints are configured in the updated configuration file to prohibit or restrict packing of the LUTs, or to perform splitting on the packed DLUTs in the critical path and / or critical module; According to the resource distribution and congestion information, congested areas after layout and routing are identified, and constraints are configured in the updated configuration file to perform splitting on the DLUTs located in the congested areas.

2. The method of claim 1, wherein, The initial configuration file is generated according to the target circuit design, comprising: The netlist of the target circuit design is statically analyzed, and the initial packing constraint threshold is set based on the analysis result to generate the initial configuration file; Wherein, the static analysis and the set packing constraint threshold include at least one of the following: Perform logic level analysis to identify paths with logic level exceeding a logic depth threshold as initial critical paths, and configure constraints to limit packing of LUTs on the initial critical paths; Perform fan-out analysis and configure a maximum allowed fan-out number to prohibit packing of candidate LUT pairs whose output fan-out numbers all exceed the maximum allowed fan-out number; Perform input sharing analysis and configure a minimum shared input number to screen LUT pairs for packing whose shared input numbers satisfy the minimum shared input number; Configure an upper limit of DLUT proportion to control the overall density of packing.

3. The method of claim 1, wherein, The collected physical information after layout and routing comprises: From the output results of the first implementation process, resource utilization information, resource distribution and congestion information, static timing analysis reports and physical layout information are extracted; Based on the static timing analysis reports, at least one critical path is identified; and based on the physical layout information, at least one critical module is identified.

4. The method of claim 3, wherein, The identifying at least one critical path based on the static timing analysis report comprises: obtaining timing slack and logic level number of each logic path in the static timing analysis report; grouping paths with the same logic level number into the same group; sorting the paths in each group according to the timing slack from poor to good, and marking at least one path at the front of the sorting as a critical path.

5. The method of claim 3, wherein, The identifying at least one critical module based on the physical layout information comprises the following operations: analyzing the physical layout information to count the congestion degree of each module; sorting the modules according to the congestion degree, and marking at least one module at the front of the sorting as a critical module.

6. The method of claim 1, wherein, The preset convergence condition comprises at least one of the following: a critical timing index reaches or is better than a timing convergence target value, the critical timing index comprising a worst negative timing slack and a total negative timing slack; a change rate of global resource utilization or congestion degree is lower than a set change rate threshold; an iteration number reaches a preset maximum iteration number.

7. A LUT Pack device based on backend feedback directed optimization, characterized by, The device comprises: an initial configuration generation module configured to generate an initial configuration file for controlling LUT packing according to a target circuit design in a logic synthesis stage; a physical information collection module configured to perform a first implementation process, layout and wiring on the target circuit design, and collect physical information after the layout and wiring, the physical information comprising but not limited to resource utilization, resource distribution and congestion information, critical path information and critical module information; a configuration file optimization module configured to optimize and update the constraint parameters in the initial configuration file based on the collected physical information to generate an updated configuration file; an iteration control and execution module configured to take the updated configuration file as input to perform a next iteration process, the next iteration process comprising: re-executing a process comprising logic synthesis and implementation, and collecting physical information and optimizing and updating the configuration file again; repeating the next iteration process until a preset convergence condition is met, and finally outputting an optimized hardware design data; wherein the configuration file optimization module is specifically configured to execute at least one optimization strategy to adjust the constraint parameters according to the collected physical information: if the resource utilization information indicates that the LUT resource utilization exceeds a set utilization threshold, then the constraint conditions for screening packable LUT pairs are relaxed in the updated configuration file; for the LUTs in the identified critical path and / or critical module, constraints are configured in the updated configuration file to prohibit or limit the packing of the LUTs, or to perform splitting on the packed DLUTs in the critical path and / or critical module; according to the resource distribution and congestion information, the congested areas after the layout and wiring are identified, and constraints are configured in the updated configuration file to perform splitting on the DLUTs located in the congested areas.

8. An electronic device, comprising: comprise: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the LUT Pack method based on backend feedback-oriented optimization according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the steps of the LUT Pack method based on backend feedback-directed optimization according to any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the LUT Pack method based on backend feedback-directed optimization according to any one of claims 1 to 6.

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