Manufacturing method of high-precision circuit

Abstract

The invention relates to a manufacturing method of a high-precision circuit, and aims to solve the technical problems of serious lateral erosion and limited circuit precision and electrical performance caused by thick copper etching when a fine circuit is manufactured by an existing improved semi-additive method. The method is characterized by comprising the following steps: forming a substrate conductive framework of which the width is smaller than that of a final circuit through controlled thinning of an initial copper foil and negative patterning; depositing a conformal conductive seed layer with the thickness of 0.5 mu m on the overall surface; forming an electroplating anti-corrosion layer nested in the framework on the seed layer by adopting positive film patterning; pattern electroplating is carried out by using the framework as a current path to increase the thickness to 18 [mu] m; and finally, removing the anti-corrosion layer and quickly etching the seed layer with the thickness of only 0.5 mu m to complete pattern separation. By the adoption of the technical scheme, high-precision fine circuit manufacturing with the lateral erosion amount lower than 1.0 microns and the line width tolerance controlled within 5% can be achieved, the circuit perpendicularity and the high-frequency signal integrity are remarkably improved, and the cost advantage of an mSAP and the precision level of the SAP are both achieved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronic manufacturing technology, and relates to a manufacturing method of high-precision lines. BACKGROUND

[0002] Printed circuit board (PCB) is an indispensable core component in modern electronic devices, which bears the key functions of fixing, supporting and electrical connection of electronic components. With the rapid development of electronic information technology, terminal products are increasingly tending to be light, thin, small and multifunctional, which puts unprecedentedly strict requirements on the integration and signal transmission performance of PCB. To meet this demand, the line width and line space of conductive patterns on PCB, i.e. lines, are continuously miniaturized, which has entered the field of more precision from the traditional level of tens of microns. Under this macro background of technology evolution, various mature patterning manufacturing processes have been developed for fine lines of different precision levels, among which, tenting process based on subtractive process, modified semi-additive process (mSAP) and semi-additive process (SAP) are the most representative mainstream technical paths.

[0003] Specifically, for conventional lines with line width greater than 40 um, tenting process with higher cost-effectiveness is usually adopted for production. When the line width and line space enter the range of 25 to 40 um, modified semi-additive process (mSAP) becomes the dominant process. The mSAP process usually starts with a substrate covered with a thin copper foil (e.g. thickness of 1-3 um), and the copper layer in the line area is thickened by pattern plating, and then the excess thin layer of bottom copper in the line gap is removed by chemical etching, thereby forming the final circuit pattern. Further, when the line precision requirement is improved to the level of 15 to 25 um or even finer, more precise semi-additive process (SAP) must be used. The core difference between SAP and mSAP is that the starting substrate of SAP is a copper-free insulating medium layer, and a very thin conductive seed layer (usually only about 0.5 um) is first formed on the entire surface by chemical copper deposition, and the subsequent pattern plating and etching steps are similar to mSAP. Both of these two processes play an important role in solving the technical needs of different periods and form a relatively stable application pattern.

[0004] The fundamental limitation of the mSAP process is that the initial substrate copper foil layer plays a dual role: it is both the conductive base for subsequent pattern plating and the "sacrificial layer" that must be etched away at the end. This structural feature determines that there is a physical lower limit to the thickness of the bottom copper, which cannot be as thin as the chemical copper seed layer of SAP, thereby leading to a theoretical ceiling that is difficult to overcome in etching precision. Simply by optimizing the etching chemicals or equipment, the side etching problem can only be improved to a certain extent, but the inherent defects caused by etching thick bottom copper cannot be fundamentally eliminated.

[0005] Therefore, how to effectively avoid the large side etching problem caused by etching the initial bottom copper on the basis of inheriting the mature, stable and efficient manufacturing advantages of the mSAP process through innovative reconstruction of the process, so as to realize the ultra-fine line manufacturing capability and quality comparable to the SAP process in a more economical way, has become the key challenge and technical problem to be solved for the current technical personnel in the field. SUMMARY

[0006] The purpose of the present application is to provide a high-precision line manufacturing method, aiming to solve the technical problem that the existing modified semi-additive process (mSAP) produces significant side etching when manufacturing fine lines due to etching the bottom copper with a certain thickness on the initial copper-coated substrate, thereby limiting the final line precision and reducing the electrical performance.

[0007] The present application realizes the above-mentioned purpose through the following technical scheme: a high-precision line manufacturing method, the steps comprising: S1, negative etching: forming a base conductive framework with a width smaller than the final line on the initial substrate through a one-time negative etching process, which is used as the current distribution network for subsequent plating; S2, seed layer deposition: depositing a conductive seed layer on the entire substrate surface containing the framework; S3, positive patterning: forming a plating resist layer that accurately defines the final line pattern on the conductive seed layer through a one-time positive patterning process, and the pattern is accurately nested within the outline of the base conductive framework; S4, plating thickening: using the base conductive framework as an efficient current transmission path, the exposed area of the plating resist layer is subjected to pattern plating thickening, forming the final line body; S5, stripping: thoroughly stripping the dry film remaining between the dense fine lines; S6, flash etching: removing only the extremely thin conductive seed layer at the line gap through a one-time rapid etching, thereby fundamentally avoiding etching of the thick copper layer and minimizing side etching, and obtaining high-precision fine lines.

[0008] Specifically, the step of forming the base conductive framework specifically comprises: A copper clad laminate is provided, which has an initial outer layer of copper foil; The initial outer layer of copper foil is subjected to a chemical thinning process to obtain a thickness-controlled copper layer; A negative patterning process is performed on the thickness-controlled copper layer, which includes forming a negative photoresist layer, subjecting the negative photoresist layer to a patterned exposure to solidify the areas defining the pattern of the base conductive framework, developing to expose the copper surface to be etched, etching to remove the exposed copper, and stripping the remaining negative photoresist layer, thereby leaving the base conductive framework on the insulating substrate.

[0009] Specifically, the negative patterning process further includes: Before forming the negative photoresist layer, the surface of the thickness-controlled copper layer is subjected to a pretreatment, which includes a micro-etching process using a sodium persulfate solution to form a micro-topography with a predetermined roughness on the copper surface; The step of forming the negative photoresist layer specifically involves laminating a negative photoresist dry film with a thickness of 30 um onto the surface of the copper layer by hot lamination, wherein the process parameters for hot lamination are: hot lamination temperature 110°C, lamination pressure 4.0 kg / cm 2 , conveying speed 2.0 m / min; The step of patterned exposure specifically involves using a laser direct imaging device with a center wavelength of 355 nm to perform scanning exposure at an exposure energy of 14 mJ / cm 2 after alignment compensation; The step of developing specifically involves using a 1% sodium carbonate aqueous solution as the developing solution to dissolve and remove the unexposed dry film area at a temperature of 30°C; The step of etching specifically involves using an acidic copper chloride etching solution to etch and remove the exposed copper foil in an etching device with vacuum-assisted spraying function; The step of stripping specifically involves using a 4% sodium hydroxide solution to strip the solidified negative photoresist from the surface of the base conductive framework at a temperature of 60°C.

[0010] Further, the chemical thinning process reduces the thickness of the initial outer layer of copper foil from 12 um to 5 um; and the pattern data of the base conductive framework is designed such that the width of the line portion is 80% of the target fine line width, and the size of the pad portion is consistent with the pad size of the target fine line.

[0011] Specifically, the step of depositing a conductive seed layer specifically involves performing a chemical copper deposition process, which includes the following consecutive sub-steps: The substrate with the formed conductive framework is subjected to degreasing, hole-filling and micro-etching treatment; The substrate subjected to the foregoing treatment is immersed in an activation solution containing colloidal palladium-tin particles, so that the palladium catalyst core is uniformly adsorbed on the surface of the conductive framework and the surface of the insulating substrate; The substrate with the adsorbed palladium catalyst core is subjected to a speed-up treatment to remove the hydrated tin oxide shell wrapped outside the palladium core, so as to expose the palladium metal core with catalytic activity; The substrate subjected to the speed-up treatment is placed in a self-catalytic chemical copper plating tank solution, and under the catalytic action of the palladium metal core, a conductive seed layer is formed on all surfaces of the substrate, and the thickness of the conductive seed layer is controlled to be 0.5 um.

[0012] Specifically, the step of forming the electroplating resist layer specifically comprises performing a positive one-time patterning process, which includes: A positive dry electroplating resist film with a thickness of 25 um is laminated on the conductive seed layer by means of hot-pressing film lamination; A laser direct imaging device is used to perform pattern exposure on the positive dry electroplating resist film according to the pattern data of the target fine line, so that the area corresponding to the trench pattern remains unexposed, while the area corresponding to the non-trench pattern is exposed and solidified; A developing solution is used to develop the positive dry electroplating resist film, so as to dissolve and remove the unexposed dry film in the trench pattern area, thereby exposing the trench pattern on the conductive seed layer.

[0013] Further, the step of performing pattern exposure by means of the laser direct imaging device further includes: Before exposure, a camera system built in the laser direct imaging device is used to scan and identify a specific pad pattern on the conductive framework as an alignment reference point; The position of the identified alignment reference point is compared with the computer-aided manufacturing data of the target fine line pattern, and high-precision alignment compensation is performed, so that the alignment compensation accuracy is less than 6 um; After the alignment compensation is completed, exposure is performed according to the pattern data of the target fine line, so as to ensure that the formed trench pattern is accurately nested within the outline range of the conductive framework.

[0014] Specifically, the step of performing pattern plating specifically includes: The substrate with the formed electroplating resist layer is loaded as a cathode in a vertical continuous electroplating device, a phosphorus-containing copper ball is used as an anode, and a high-dispersion power copper electroplating solution containing a special organic additive is used as an electroplating solution; Turning on the direct current power supply to make the current pass through the base conductive framework for low impedance transmission and be distributed to the bottom of the trench pattern uniformly through the conductive seed layer; at a plating current density of 1.7A / dm 2 depositing copper in the trench by electroplating until the formed line body reaches a target thickness of 18um, which is less than the thickness of the electroplating resist layer.

[0015] Specifically, the step of etching to remove the conductive seed layer specifically comprises performing a rapid differential etching once, and the etching uses an etching solution of a hydrogen peroxide-sulfuric acid system, which is only used to remove the conductive seed layer with a thickness of 0.5um between the line bodies, so that the lateral etching amount is controlled to be less than 1.0um.

[0016] Further, the method comprises at least one automatic optical detection step selected from at least one of the following: After forming the base conductive framework and before depositing the conductive seed layer, a first automatic optical detection is performed, and computer-aided manufacturing data of the base conductive framework is taken as a reference standard to detect and confirm the electrical connectivity and structural integrity of the base conductive framework; After etching to remove the conductive seed layer, a second automatic optical detection is performed, and computer-aided manufacturing data of the target fine line is taken as a reference standard, and a multi-angle combined illumination mode is used to detect microscopic defects of the target fine line.

[0017] The beneficial effects of the technical scheme of the present application are: The present application successfully converts the key step of determining precision in the mSAP process, i.e., the final etching, from etching of a log-micron-thick copper foil to rapid differential etching of a sub-micron conductive seed layer, by constructing a double conductive structure of "base conductive framework + conformal conductive seed layer" and combining twice-precise alignment patterning process, thereby inheriting the mSAP process framework and cost advantage while realizing the ultra-fine line manufacturing capability comparable to the SAP process. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The product cross-sectional variation diagram of the manufacturing method of the high-precision line of the present application.

[0019] In the figure, the following are marked: 1 - copper-clad laminate, 11 - insulating base material, 12 - copper foil, 12a - copper layer; 2 - base conductive framework; 3 - conductive seed layer; 4 - electroplating resist layer. DETAILED DESCRIPTION

[0020] The purpose of this invention is to provide a method for manufacturing high-precision circuits, aiming to solve the technical problem that existing modified semi-additive process (mSAP) suffers from significant side etching due to the etching of a certain thickness of base copper on the initial copper-clad substrate during the manufacturing of fine circuits, leading to limited final circuit accuracy and degraded electrical performance. This invention achieves extremely precise control over the final etching amount without completely switching to the high-cost semi-additive process (SAP), through a systematic restructuring of the manufacturing process. This results in linewidth accuracy, circuit sidewall perpendicularity, and high-frequency signal integrity comparable to the SAP process.

[0021] To achieve the above-mentioned invention, this invention provides a method for manufacturing high-precision circuits. Its core technical concept lies in adopting a dual patterning and step-by-step thickening strategy, which deconstructs the single initial copper foil in the traditional mSAP process, which carries the dual functions of conductivity and etching sacrificial layer, into a "substrate conductive framework" that undertakes the main conductivity function and a "conductive seed layer" that undertakes the final patterning etching function. This method first uses a negative etching process to form a substrate conductive framework on the initial substrate, with a width larger than the final circuit, which serves as a current distribution network for subsequent electroplating. Then, an extremely thin, uniform conductive seed layer is deposited on the entire substrate surface containing this framework. Next, a high-precision positive patterning process is used to form an electroplated resist layer on the conductive seed layer, precisely defining the final circuit pattern, with its pattern precisely nested within the outline of the substrate conductive framework. The substrate conductive framework is then used as an efficient current transmission path to pattern-enlarge the exposed areas of the electroplated resist layer, forming the final circuit body. Finally, a rapid differential etching process removes only the extremely thin conductive seed layer at the gaps between the circuits, fundamentally avoiding etching of the thick copper layer, minimizing lateral etching, and obtaining high-precision fine circuits.

[0022] The present invention will be further described in detail below with reference to specific embodiments.

[0023] Example: like Figure 1 As shown, a method for manufacturing high-precision circuits includes the following process steps: S1. Thinning: A copper-clad laminate 1 is selected as the starting substrate, comprising an insulating substrate 11 and a copper foil 12. The initial outer copper foil 2 of the copper-clad laminate 1 has a thickness of 12 μm. The copper-clad laminate 1 is placed in a chemical copper reduction processing line, and a chemical etching solution composed of hydrogen peroxide and sulfuric acid is used at a temperature of 45°C to uniformly thin the outer copper foil 12 until its thickness is precisely controlled at 5 μm. This step aims to provide a copper layer 12a with controlled thickness for the subsequent formation of the substrate conductive framework, while reducing the total etching amount of the first etching.

[0024] S2, negative etching: forming the base conductive framework 2. This step includes a series of sub-steps. First, the thinned copper surface is pre-processed, which includes a brush cleaning process, a micro-etching process, and an acid pickling and drying process. Among them, the micro-etching process uses sodium persulfate solution, with a micro-etching depth of 0.75um, to form a microstructure with a roughness of Rz 1.0um on the copper surface, to enhance the adhesion of the subsequent dry film. Subsequently, on the clean copper surface, a negative photosensitive dry film resist with a thickness of 30um is laminated by hot pressing. The process parameters of hot pressing are set as follows: hot pressing temperature 110℃, lamination pressure 4.0kg / cm 2 , conveying speed 2.0m / min, and Shore A hardness of hot pressing roller 70. Then, the first pattern exposure is performed using a laser direct imaging (LDI) device. The charge-coupled device (CCD) camera system built-in the LDI device first automatically scans and identifies the alignment target on the substrate, compares with the preset computer-aided manufacturing (CAM) data, calculates and performs accurate alignment compensation. Subsequently, a solid-state ultraviolet laser with a central wavelength of 355nm is used to scan and expose the negative photosensitive dry film under the control of a galvanometer scanning system according to the preset base conductive framework pattern data. The base conductive framework pattern data is specially designed, with a line width of 180% of the final target line width, and a pad (PAD) size consistent with the final target pad size. The exposure energy is accurately controlled at 14mJ / cm 2 . After exposure, the substrate is transported to the developing device, and a 1% sodium carbonate aqueous solution is used as the developing solution to dissolve and remove the unexposed dry film area at a temperature of 30℃, with the developing breakpoint controlled at 50% of the total developing length, thereby exposing the copper surface to be etched. Thereafter, the developed substrate is sent to the acidic etching equipment, and the exposed 5um thick copper foil is etched and removed using acidic copper chloride etching solution. The etching equipment has a vacuum-assisted spraying function to ensure that the etching factor is greater than 3.0 and the etching uniformity is greater than 85%. Finally, a 4% sodium hydroxide solution is used to strip the solidified dry film resist from the copper surface at 60℃. After this step, the base conductive framework 2 is formed on the insulating substrate 11, which is composed of a series of wider lines and standard-sized pads.

[0025] S3, one-time detection: the first automatic optical detection (AOI) is performed on the formed substrate conductive framework 2. The substrate is conveyed into the AOI equipment, and the CAM data of the substrate conductive framework 2 is called by the equipment as a reference standard. A high-resolution linear array CCD camera is used to scan the substrate surface at high speed under the illumination of a composite light source composed of a coaxial white light LED and a multi-angle ring-shaped red light LED, and images are collected. The image processing system compares the images collected in real time with the reference data, and automatically identifies macro defects such as open circuits and severe recesses through a preset defect detection algorithm. The purpose of this step is to ensure the electrical connectivity and integrity of the substrate conductive framework, and to provide a fault-free current distribution network for subsequent pattern plating.

[0026] S4, depositing a seed layer: the substrate that has passed the AOI detection is sequentially conveyed through a complete chemical copper deposition treatment line. The treatment line includes the following tanks: an oil removal tank, a hole filling tank, a micro-etching tank, a pre-dipping tank, an activation tank, a speed-up tank, and a chemical copper deposition tank. The substrate first enters the oil removal tank to remove possible organic contaminants on the surface; then enters the hole filling tank to adjust the charge characteristics of the hole wall and the substrate surface through cationic surfactants, thereby improving the hydrophilicity; then enters the micro-etching tank to slightly etch the copper surface of the substrate conductive framework by 0.5 um, so as to activate the copper surface and further clean the substrate surface; the acidic solution in the pre-dipping tank is used to protect the subsequent activation tank from contamination; the core activation step is performed in the activation tank, in which the substrate is immersed in an activation solution containing colloidal palladium-tin particles, and through physical adsorption, palladium catalyst cores with a diameter of tens of nanometers are uniformly attached to all surfaces including the substrate conductive framework surface and the exposed insulating substrate surface; the subsequent speed-up tank uses an acidic solution to remove the hydrated tin oxide shell wrapped outside the palladium core, thereby exposing the palladium metal core with high catalytic activity; finally, the substrate enters the chemical copper deposition tank, which contains a self-catalytic oxidation-reduction reaction solution composed of copper sulfate, formaldehyde, potassium sodium tartrate, sodium hydroxide, and specific stabilizers, and the working temperature is maintained at 45°C and the pH value is 12.5. Under the catalysis of the palladium core, the formaldehyde reduces the copper ions to metallic copper, and a uniform and dense conductive seed layer 3 is deposited on all surfaces of the substrate. The thickness of the conductive seed layer 3 is strictly controlled to be 0.5 um. After this step, the entire substrate surface, including the original substrate conductive framework 2 and the insulating area, is covered with a continuous and extremely thin chemical copper layer.

[0027] S5, Positive film patterning: Forming the secondary photoresist layer 4 for defining the final fine line pattern. This step also contains a series of precisely controlled sub-steps. First, the substrate with the conductive seed layer 3 on top is subjected to a mild pre-treatment, including only water rinsing and drying, without any form of mechanical brushing or chemical micro-etching, in order to protect the 0.5um thick conductive seed layer 3 from being damaged. Subsequently, a 25um thick positive dry film for electroplating resist is laminated on the substrate surface by means of hot lamination. The dry film has excellent resistance to acid and plating chemicals. The lamination process parameters are identical to the negative dry film lamination process described above. Next, a second photo-exposure is performed using a high precision LDI equipment. The CCD alignment system of the equipment will now precisely align and lock onto the specific pad pattern of the underlying conductive framework formed in the first patterning process as the reference point. The alignment is performed with high precision, with an alignment accuracy of less than 6um, by comparing with the CAM data of the final fine line pattern. Subsequently, the laser system will perform the exposure of the positive dry film according to the data of the final fine line pattern. The exposure energy is set to 45mJ / cm 2 In this exposure, the dry film in the line area is exposed to laser irradiation and undergoes a photopolymerization reaction to solidify, while the non-line area remains unexposed. The core of this exposure is that the final fine line pattern is precisely nested within the outline of the previously formed wider underlying conductive framework. After exposure, the substrate is transported to the developing equipment, and a 1% sodium carbonate aqueous solution is used to dissolve and remove the unexposed area of the dry film, thereby forming a series of precise, subsequent electroplating grooves on the conductive seed layer 3. The shape and size of these grooves are the shape and size of the final fine lines to be obtained. In order to ensure the perpendicularity of the groove sidewalls, the developing breakpoint is strictly controlled at 40% of the total developing length.

[0028] S6, Electroplating thickening: Performing pattern plating thickening to form the line body 5. The substrate with the secondary photoresist layer 4 is loaded as the cathode in the vertical continuous electroplating equipment. A copper powder-containing titanium mesh is placed as the anode in the electroplating tank, and the electroplating solution is a high dispersion capacity copper sulfate electroplating solution containing special organic additives for leveling, brightening and grain refinement. When the direct current power is turned on, the current enters the substrate through the hanging point, preferentially transmitting on the underlying conductive framework with extremely low resistance, and then uniformly distributing to the bottom of each groove defined by the electroplating resist layer 4 through the 0.5um conductive seed layer 3 on top. Since the underlying conductive framework 2 acts as a low impedance current distribution bus, it effectively overcomes the problem of uneven current distribution that may occur when electroplating on a very thin conductive layer. The electroplating current density is set to 1.7A / dm 2The thickness of the circuit pattern gradually increases as copper ions continue to be reduced and deposited in the cathode grooves. The plating time is precisely calculated to achieve a target plating thickness of 18 um. This thickness is less than the 25 um thickness of the dry film resist, effectively avoiding the "sandwiching" phenomenon caused by over-plating.

[0029] S7, stripping: The plated resist layer 4 is removed. The substrate after plating is transported to a dedicated stripping line. To completely remove the dry film remaining between the fine lines and avoid short circuits in subsequent etching, a strong stripping solution mainly composed of organic solvents is used. Under the conditions of a temperature of 60°C and a spraying pressure of 2.0 kg / cm 2 , the solidified dry film that has completed its anti-plating mission is completely stripped and dissolved from the surface of the substrate within 2.5 minutes. After stripping, the final line body 5 (composed of 18 um of plated copper and 0.5 um of seed layer copper) is exposed, while the gap area between the lines is exposed to the 0.5 um thick conductive seed layer 3 to be removed.

[0030] S8, flash etching: Fast etching is performed to complete the final patterning. The substrate is sent to a fast etching device that uses an etching solution that has a high etching rate for copper and does not damage the epoxy resin and glass fiber substrate. Since only the 0.5 um thick conductive seed layer 3 in the line gap needs to be removed, the etching process is extremely fast. With very short etching depth, the isotropic lateral etching amount is also greatly suppressed. By precisely controlling the conveying speed and etching solution concentration, the final side etching amount is stably controlled to be less than 1.0 um. After this step, the conductive connection in the line gap is completely cut off, forming the final conductive pattern with nearly vertical sidewalls, high aspect ratio, and extremely high dimensional accuracy. The final total thickness of the line is 18.5 um.

[0031] S9, second inspection: The second and final automatic optical inspection is performed. The finally shaped circuit board is again sent to the AOI device. This time, the CAM data of the final line is used as a reference, and a multi-angle combined illumination mode including vertical light, side light, and oblique light is enabled to maximize the detection ability of different types of defects. The detection algorithm is configured to identify microscopic defects such as line width / line spacing deviation, notches, copper tumors, residual copper, and potential short circuits. All suspected defect points marked by the system are transmitted to a manual rejudication confirmation workstation (VRS) for final determination by an inspector. The line width tolerance of the fine lines produced by this method is stably controlled within 5%, which is significantly better than the traditional mSAP process.

[0032] In summary, by constructing a double conductive structure of "base conductive framework + conformal conductive seed layer" and combining two accurate alignment patterning processes, the present application successfully converts the key step of determining precision in the mSAP process, i.e., the final etching, from etching of a logarithmic micron-thick copper foil into rapid differential etching of a sub-micron conductive seed layer, thereby inheriting the mSAP process framework and cost advantage while realizing the ultra-fine line manufacturing capability comparable to the SAP process.

[0033] The above merely describes some embodiments of the present application. For those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are within the protection scope of the present application.

Claims

1. A method of manufacturing a high-fineness line, characterized by The steps include: S1, negative etching: forming a base conductive framework with a width smaller than the final line on the initial substrate by a one-time negative etching process, which is used as a subsequent plating current distribution network; S2, depositing a seed layer: depositing a conductive seed layer on the entire substrate surface containing the framework; S3, positive patterning: forming a plating resist layer on the conductive seed layer by a one-time positive patterning process, which accurately defines the final line pattern, and the pattern is accurately nested within the outline of the base conductive framework; S4, plating thickening: using the base conductive framework as an efficient current transmission path, the exposed area of the plating resist layer is patterned and thickened by plating, forming the final line body; S5, flash etching: only removing the extremely thin conductive seed layer at the line gap by a one-time rapid differential etching, thereby fundamentally avoiding etching of the thick copper layer and minimizing side etching, and obtaining high-precision fine lines.

2. The method for manufacturing a high-fineness wiring according to claim 1, wherein The step of forming the base conductive framework specifically includes: Providing a copper-clad laminate having an initial outer copper foil; Chemically thinning the initial outer copper foil to obtain a thickness-controlled copper layer; Performing a negative patterning process on the thickness-controlled copper layer, which includes forming a negative photosensitive resist layer, patterned exposure of the negative photosensitive resist layer to solidify the area defining the base conductive framework pattern, developing to expose the copper surface to be etched, etching to remove the exposed copper, and peeling off the remaining negative photosensitive resist layer, thereby leaving the base conductive framework on the insulating substrate.

3. The method for manufacturing a high-fineness wiring according to claim 2, wherein The negative patterning process further includes: Before forming the negative photosensitive resist layer, the surface of the thickness-controlled copper layer is pretreated, and the pretreatment includes a micro-etching process which uses a sodium persulfate solution to form a micro-topography with a predetermined roughness on the copper surface; The step of forming a negative photosensitive resist layer is specifically forming a negative photosensitive dry film resist layer with a thickness of 30 um on the surface of the copper layer by hot lamination, wherein the process parameters of hot lamination are as follows: hot lamination temperature 110 ℃, lamination pressure 4.0 kg / cm 2 , conveying speed 2.0 m / min. The step of forming a negative photosensitive resist layer is specifically forming a negative photosensitive dry film resist layer with a thickness of 30 um on the surface of the copper layer by hot lamination, wherein the process parameters of hot lamination are as follows: hot lamination temperature 110 ℃, lamination pressure 4.0 kg / cm 2 , conveying speed 2.0 m / min. The step of the patterned exposure is specifically scanning exposure with 14 mJ / cm 2 exposure energy by using a laser direct imaging device with a center wavelength of 355 nm after alignment compensation. The developing step specifically uses a 1% sodium carbonate aqueous solution as the developing solution to dissolve and remove the unexposed dry film area at a temperature of 30°C; The etching step specifically uses an acidic copper chloride etching solution to etch and remove the exposed copper foil in an etching device with vacuum-assisted spraying function; The peeling step specifically uses a 4% sodium hydroxide solution to peel off the solidified negative photosensitive resist from the surface of the base conductive framework at a temperature of 60°C.

4. The method for manufacturing a high-fineness line according to claim 2 or 3, wherein The chemical thinning process reduces the thickness of the initial outer copper foil from 12um to 5um; and the pattern data of the base conductive framework is designed such that the width of the line part is 80% of the target fine line width, and the size of the pad part is consistent with the pad size of the target fine line.

5. The method for manufacturing a high-fineness wiring according to Claim 1, wherein The step of depositing a conductive seed layer specifically performs a chemical copper deposition process, which includes the following consecutive sub-steps: Oil removal, hole cleaning, and micro-etching treatment are performed on the substrate on which the base conductive framework is formed; The substrate subjected to the foregoing treatment is immersed in an activation solution containing colloidal palladium-tin particles, so that the palladium catalyst core is uniformly adsorbed on the surface of the base conductive framework and the surface of the insulating substrate; The substrate with the palladium catalyst core adsorbed thereon is subjected to a speed-up treatment to remove the hydrated tin oxide shell wrapped outside the palladium core, and expose the catalytically active palladium metal core; The substrate subjected to the speed-up treatment is placed in a self-catalytic chemical copper plating bath, and under the catalysis of the palladium metal core, a conductive seed layer is formed on all surfaces of the substrate, and the thickness of the conductive seed layer is controlled at 0.5 um.

6. The method for manufacturing a high-fineness circuit according to Claim 1, wherein The step of forming the electroplating resist layer specifically comprises performing a positive one-time patterning process, which comprises: A 25 um thick positive dry electroplating resist film is laminated on the conductive seed layer by means of hot-pressing film lamination; A laser direct imaging device is used to perform pattern exposure on the positive dry electroplating resist film according to the pattern data of the target fine line, so that the area corresponding to the trench pattern remains unexposed, while the area corresponding to the non-trench pattern is exposed and solidified; A developing solution is used to develop the positive dry electroplating resist film, so as to dissolve and remove the unexposed dry film in the trench pattern area, thereby exposing the trench pattern on the conductive seed layer.

7. The method for manufacturing a high-fineness circuit according to Claim 6, wherein The step of performing pattern exposure by means of the laser direct imaging device further comprises: Before exposure, a camera system built in the laser direct imaging device is used to scan and identify a specific pad pattern on the substrate conductive framework as an alignment reference point; The position of the identified alignment reference point is compared with the computer-aided manufacturing data of the target fine line pattern, and high-precision alignment compensation is performed, so that the alignment compensation accuracy is less than 6 um; After the alignment compensation is completed, exposure is performed according to the pattern data of the target fine line, so as to ensure that the trench pattern formed is accurately nested within the outline range of the substrate conductive framework.

8. The method of manufacturing a high-fineness line according to claim 1, wherein The step of performing pattern plating specifically comprises: The substrate with the electroplating resist layer formed thereon is loaded as a cathode in a vertical continuous electroplating device, a copper-containing titanium mesh is used as an anode, and a high-dispersion copper sulfate electroplating solution containing a special organic additive is used as an electroplating solution; A direct current power supply is turned on, so that the current is transmitted through the substrate conductive framework with low impedance, and is uniformly distributed to the bottom of the trench pattern through the conductive seed layer; at a plating current density of 1.7 A / dm 2 copper is electroplated within the trench until the formed line body reaches a target thickness of 18 um, which is less than the thickness of the electroplating resist layer.

9. The method of manufacturing a high-fineness line according to Claim 1, wherein The step of etching to remove the conductive seed layer specifically comprises performing a rapid differential etching, which uses a hydrogen peroxide-sulfuric acid system etching solution, and the etching solution is only used to remove the conductive seed layer with a thickness of 0.5 um between the line bodies, so that the lateral etching amount is controlled to be less than 1.0 um.

10. The method of manufacturing a high-fineness line according to any one of claims 1 to 9, wherein The method comprises at least one automatic optical detection step, and the automatic optical detection step is selected from at least one of the following: After the substrate conductive framework is formed and before the conductive seed layer is deposited, a first automatic optical detection is performed, and the computer-aided manufacturing data of the substrate conductive framework is taken as a reference standard to detect and confirm the electrical connectivity and structural integrity of the substrate conductive framework; After etching away the conductive seed layer, a second automated optical inspection is performed, using a multi-angle combined illumination mode, with computer-aided manufacturing data of the target fine line as a reference standard, to detect microscopic defects of the target fine line.

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