GaAs-based low-capacitance high-bandwidth PIN photodiode and preparation method thereof

Abstract

The application discloses a GaAs-based low-capacitance high-bandwidth PIN photodiode and a preparation method thereof, and relates to the technical field of semiconductors.The PIN photodiode comprises a GaAs substrate, a deformation growth layer and an InP-based PIN functional layer.The deformation growth layer is used for realizing the lattice constant transition from the GaAs substrate to the InP-based PIN functional layer.The InP-based PIN functional layer comprises an n-type contact layer, a first intrinsic layer, an intrinsic absorption layer and a window layer, and the first intrinsic layer is provided with an ion implantation modification area, which is used for forming a high-resistance area to reduce the effective electrical junction area of the device.The application realizes the heterogeneous integration of the GaAs substrate and the InP-based PIN functional layer through the deformation growth layer, significantly reduces the device cost, realizes the physical decoupling of the photosensitive area and the electrical junction area through the ion implantation modification area, and significantly reduces the intrinsic junction capacitance while maintaining a large optical aperture, thereby systematically solving the inherent contradiction among the bandwidth, the responsivity and the cost in a high-speed PIN-PD.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a GaAs-based low-capacitance, high-bandwidth PIN photodiode and its fabrication method. Background Technology

[0002] PIN photodiodes (PIN-PDs) are core detection devices in high-speed optical communication systems. Their basic structure consists of heavily doped P-type and N-type layers, and an unintentionally doped intrinsic absorption layer (i-layer) in between. During operation, a reverse bias voltage is mainly applied to the intrinsic absorption layer, forming a relatively wide depletion region. Incident light is absorbed in this region, generating electron-hole pairs, which are then rapidly separated by an electric field to form a photocurrent, thereby realizing the conversion of optical signals into electrical signals.

[0003] For long-wavelength PIN-PDs used in optical fiber communication (such as those operating at wavelengths of 1310 nm and 1550 nm), their intrinsic absorption layer needs to use narrow-bandgap III-V compounds such as indium antimonide (InGaAs). To obtain high-quality epitaxial crystals, traditional techniques generally use low-resistivity indium phosphide (InP) single crystals as substrates that match the lattice of the InGaAs absorption layer.

[0004] As data rates continue to increase, the requirements for the response bandwidth of long-wavelength PIN-PDs are becoming increasingly stringent. The response bandwidth of a device is primarily limited by the carrier transit time and the RC time constant. When the material and thickness of the intrinsic absorption layer are specifically optimized to reduce the carrier transit time to a sufficiently short level, the RC time constant becomes the key bottleneck determining the bandwidth. Since the time constant is determined by the product of the device's total capacitance and the load resistance, reducing the device's total capacitance is the core approach to further improving bandwidth. Existing technologies mainly reduce the device's total capacitance through two methods: reducing the intrinsic junction capacitance and reducing parasitic capacitance. However, both methods have significant drawbacks.

[0005] The first approach focuses on reducing the core parameter determining bandwidth: intrinsic junction capacitance. Since junction capacitance directly depends on the effective electrical junction area, existing technologies primarily reduce the physical photosensitive area of ​​the device through processes such as mesa etching, thereby reducing the effective electrical junction area and thus lowering the junction capacitance. While this method reduces the total capacitance of the device, it directly leads to a simultaneous reduction in the photosensitive area. This not only reduces the maximum achievable photocurrent (i.e., responsivity) but also makes efficient coupling between the small photosensitive surface and the fiber mode field difficult, severely sacrificing the device's practicality and production yield. Therefore, the fundamental flaw of this method lies in its inability to decouple and independently optimize the two objectives of "reducing the electrical area to lower capacitance" and "maintaining the optical area to maintain high responsivity."

[0006] The second approach focuses on reducing parasitic capacitance introduced by the substrate. Current technologies primarily use high-resistivity (semi-insulating) InP substrates to replace traditional low-resistivity InP substrates. While this method can improve RF characteristics to some extent, it has fundamental limitations: First, the fabrication process for high-resistivity InP substrates is complex and expensive, and the wafer diameter is typically limited to 4 inches or 6 inches, making it difficult to meet the demands of low-cost, large-scale manufacturing. Second, this method only optimizes parasitic capacitance and does not improve the intrinsic junction capacitance that limits bandwidth; therefore, it completely fails to resolve the design contradiction between the effective electrical junction area and the effective photosensitive area.

[0007] In summary, the current long-wavelength high-speed PIN-PD field faces an urgent technical challenge: a new solution that can systematically solve the capacitance problem is needed. This solution must effectively reduce the intrinsic junction capacitance that determines the bandwidth, and at the same time, it must decouple the optimization of the effective electrical junction area from the effective photosensitive area, so as to achieve high bandwidth while ensuring the device's high responsivity, easy coupling characteristics and low-cost manufacturing potential. Summary of the Invention

[0008] This invention provides a GaAs-based low-capacitance, high-bandwidth PIN photodiode and its fabrication method, aiming to solve the technical problem that existing long-wavelength PIN-PDs cannot simultaneously achieve high bandwidth and high responsivity.

[0009] The present invention adopts the following technical solution:

[0010] A GaAs-based low-capacitance, high-bandwidth PIN photodiode includes a GaAs substrate, a deformable growth layer, and an InP-based PIN functional layer. The lattice constant of the deformable growth layer gradually changes along the growth direction to achieve a transition in the lattice constant from the GaAs substrate to the InP-based PIN functional layer. The InP-based PIN functional layer includes an n-type contact layer, a first intrinsic layer, an intrinsic absorption layer, and a window layer stacked sequentially. The first intrinsic layer has an ion-implanted modified region to form a high-resistivity region to reduce the effective electrical junction area of ​​the device.

[0011] Furthermore, the InP-based PIN functional layer also includes an intrinsic gradient layer disposed between the first intrinsic layer and the intrinsic absorption layer, and the ion implantation modified region extends into the intrinsic gradient layer and the intrinsic absorption layer.

[0012] Furthermore, the deformed growth layer is an InAlAs ternary alloy gradient layer or an InAlGaAs quaternary alloy gradient layer. By linearly controlling the In, Al and / or Ga components of the deformed growth layer, a synergistic gradient of the lattice constant and the bandgap width is achieved.

[0013] Furthermore, it also includes a dislocation filtering layer, which is disposed between the deformed growth layer and the InP-based PIN functional layer to prevent dislocations generated in the deformed growth layer from being transmitted to the InP-based PIN functional layer.

[0014] Furthermore, the dislocation filtering layer is an InAlAs / InGaAs superlattice layer, and the dislocation filtering function can be precisely controlled by adjusting the composition, sublayer thickness, and / or periodic parameters.

[0015] Furthermore, the ion implantation modified region is composed of H + or He + Formed by ion implantation.

[0016] Furthermore, the ion implantation modified regions are distributed in a grid-like, lattice-like, or ring-like pattern in the plane.

[0017] A method for fabricating a GaAs-based low-capacitance, high-bandwidth PIN photodiode, characterized by comprising the following steps:

[0018] Step S1: Provide a GaAs substrate;

[0019] Step S2: Grow a deformable growth layer on the GaAs substrate with a lattice constant that gradually changes along the growth direction;

[0020] Step S3: Grow an InP-based PIN functional layer on the deformed growth layer. The InP-based PIN functional layer includes an n-type contact layer, a first intrinsic layer, an intrinsic gradient layer, an intrinsic absorption layer, and a window layer stacked sequentially.

[0021] Step S4: Perform patterned selective ion implantation on the first intrinsic layer, the intrinsic gradient layer and the intrinsic absorption layer to form an ion implantation modified region.

[0022] Furthermore, step S4 includes the following sub-steps:

[0023] Step S41: Define an injection pattern on the surface of the InP-based PIN functional layer using photolithography;

[0024] Step S42: Using the implantation pattern as a mask, perform ion implantation to form the ion implantation modified region;

[0025] Step S43: Perform annealing.

[0026] Further, in step S2, a dislocation filtering layer is grown on the deformed growth layer; in step S3, the InP-based PIN functional layer is grown on the dislocation filtering layer.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] 1. This invention achieves physical decoupling and independent optimization of the effective electrical junction area and the effective photosensitive area by introducing an ion implantation modification region. This fundamentally solves the core contradiction of high-speed PIN-PD: on the one hand, by deliberately reducing the effective electrical junction area that determines the capacitance, the intrinsic junction capacitance of the device is significantly reduced, laying a physical foundation for obtaining high bandwidth; on the other hand, a large effective photosensitive area is maintained, thereby ensuring the high responsivity of the device and greatly reducing the packaging difficulty and alignment tolerance requirements for coupling with optical paths such as optical fibers, providing key design support for achieving low-cost, high-reliability mass production.

[0029] 2. This invention innovatively integrates a deformable growth layer with gradient properties on an inexpensive GaAs substrate and combines it with the subsequent growth of a high-quality InP-based PIN functional layer, constructing a low-cost, high-performance heterogeneous integrated material system. This deformable growth layer not only efficiently relaxes lattice mismatch stress and suppresses wafer warpage, but its synergistically gradient band structure also forms a natural band slope that facilitates the rapid directional transport of photogenerated carriers. This synergistic optimization of materials and band engineering effectively reduces carrier transit time and space charge effects, providing core material support for improving device response speed and linearity.

[0030] 3. This invention adopts an H-based approach. + or He + The ion-ring patterned implantation process incorporates an ion-implanted modification region in the first intrinsic layer. This effectively confines the region for generating and collecting photogenerated carriers to the central window in the lateral direction, suppressing diffusion and ensuring the effectiveness of the low-capacitance design. Furthermore, this ion-implanted region extends synchronously to the intrinsic gradient layer and intrinsic absorption layer above it, thereby forming a continuous and complete high-resistance isolation layer in the vertical direction. This eliminates vertical leakage and ensures the reliability of electrical isolation. Through multi-layer synergy, the physical realization of the photoelectric area decoupling design is ensured. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the extensional structure of Embodiment 1 and Embodiment 2 of the present invention.

[0032] Figure 2 This is a top view of the ion implantation device in Embodiments 1 and 2 of the present invention.

[0033] Figure 3 This is a schematic diagram of the lattice adaptation and bandgap variation of the InAlAs ternary alloy gradient layer in Embodiment 1 of the present invention.

[0034] Figure 4 This is a growth structure diagram of the InAlAs / InGaAs strained superlattice in Example 1 of this invention.

[0035] Figure 5 This is a schematic diagram of the lattice adaptation and bandgap variation of the InAlGaAs quaternary alloy gradient layer in Embodiment 2 of the present invention.

[0036] Figure 6 This is a growth structure diagram of the InAlAs / InGaAs unstrained superlattice in Example 2 of this invention.

[0037] In the figure: 1-GaAs substrate; 2-deformed growth layer; 3-dislocation filtering layer; 4-n-type contact layer; 5-first intrinsic layer; 6-intrinsic gradient layer; 7-intrinsic absorption layer; 8-window layer; 9-p-type contact layer. Detailed Implementation

[0038] Specific embodiments of the present invention will now be described with reference to the accompanying drawings. Many details are described below to provide a comprehensive understanding of the invention; however, those skilled in the art will be able to implement the invention without these details.

[0039] Reference Figure 1 The core concept of this invention lies in constructing an ideal crystal platform for epitaxial growth of InP-based PIN structures by integrating a high-quality deformable growth layer 2 and a dislocation filtering layer 3 on a low-cost, large-size GaAs substrate 1. Based on this, the core regions, such as the first intrinsic layer 5, are locally electrically modified using patterned ion implantation technology. This significantly reduces the effective electrical junction area while maintaining a large photosensitive surface to obtain high responsivity, thereby reducing capacitance and increasing bandwidth, fundamentally solving the contradictions in traditional designs.

[0040] Based on the above concept, the following two embodiments, combining two typical material systems and implantation schemes, will be described in detail. The device architecture of each embodiment is the same as the inventive concept; the main difference lies in the specific technical path for achieving lattice gradient, dislocation filtering, and ion implantation.

[0041] Example 1: Based on InAlAs ternary alloy gradient layer and H + Ion implantation scheme

[0042] Reference Figure 1 This embodiment provides a GaAs-based low-capacitance, high-bandwidth PIN photodiode, whose epitaxial structure mainly includes, from bottom to top: a GaAs substrate 1, a deformable growth layer 2, a dislocation filtering layer 3, and an InP-based PIN functional layer. The InP-based PIN functional layer includes, in sequence, an n-type contact layer 4, a first intrinsic layer 5, an intrinsic gradient layer 6, an intrinsic absorption layer 7, a window layer 8, and a p-type contact layer 9.

[0043] Reference Figures 1 to 3 The following section elaborates on the function, material design rationale, and beneficial effects of each epitaxial layer:

[0044] GaAs substrate 1: As the epitaxial growth foundation and mechanical support for the entire device, the core advantage of using GaAs substrate 1 lies in its significantly lower cost compared to traditional InP substrates, the ability to obtain larger wafers (such as 6 inches), and its superior mechanical strength and thermal conductivity. This provides fundamental conditions for significantly reducing chip manufacturing costs, improving production yield and capacity, and enhancing device heat dissipation.

[0045] Deformed Growth Layer 2: The deformed growth layer 2 is crucial for achieving heterogeneous integration from the GaAs substrate 1 to the InP-based PIN functional layer above. In this embodiment, it is preferably an InAlAs ternary alloy gradient layer. By linearly increasing the In composition while linearly decreasing the Al composition along the growth direction, the lattice constant is smoothly gradiented from matching GaAs (~5.65 Å) to matching InP (~5.87 Å). This design not only effectively relaxes the lattice mismatch stress of up to about 4%, but the natural band slope formed by its composition gradient also facilitates the directional transport of photogenerated carriers, laying a key crystallographic foundation for the subsequent growth of high-quality PIN structures.

[0046] Dislocation filtering layer 3: Located above the deformed growth layer 2, the dislocation filtering layer 3 primarily functions to capture and block the upward propagation of penetrating dislocations that may be generated during strain relaxation in the deformed growth layer 2. This embodiment preferably employs an InAlAs / InGaAs strained superlattice (composed of In...) that matches the InP lattice. 0.58 Al 0.42 As tensile strain layer and In x Ga 1-x This function is achieved through alternating stacks of compressive strain layers. The superlattice, through strain field interaction, can effectively bend and annihilate dislocations, ensuring that the upper functional layers achieve extremely high crystal quality. This is crucial for reducing dark current noise in the power PD and improving its reliability and stability.

[0047] n-type contact layer 4: The n-type contact layer 4 is grown on top of the dislocation filter layer 3 and is typically composed of highly doped n-type InAlAs material. Its function is to form a low-resistance n-type ohmic contact, serving as the cathode of the device, and providing a low-resistance path for the establishment of the electric field within the first intrinsic layer 5 under reverse bias. Thanks to the high-quality platform beneath, this layer enables epitaxy with low defect density, ensuring uniformity and stability of contact resistance and minimizing the device's series resistance.

[0048] First Intrinsic Layer 5: The first intrinsic layer 5 is the core design layer and innovative layer for achieving low capacitance performance. It is typically composed of a relatively thick layer of unintentionally doped InAlAs material, with a thickness designed to be 200-500 nm (commonly understood in the industry as a "large I-layer"). The core function of the first intrinsic layer 5 is to significantly expand the depletion region width of the device through its large thickness, thereby initially reducing the intrinsic junction capacitance from a structural design perspective. More importantly, this layer is the target layer for subsequent patterned ion implantation. The high-resistivity region formed by implantation can effectively reduce the effective electrical junction area laterally, thereby fundamentally achieving active and precise engineering control of capacitance, providing a physical basis for breaking the traditional trade-off between bandwidth and responsivity.

[0049] Intrinsic graded layer 6: Located between the first intrinsic layer 5 and the intrinsic absorber layer 7, intrinsic graded layer 6 is typically composed of InGaAlAs material with a graded bandgap and a thickness of 30-80 nm. Its function is to provide a smooth bandgap transition, eliminating the significant valence band gradient between the first intrinsic layer 5 (InAlAs) and the intrinsic absorber layer 7 (InGaAs). This effectively reduces the potential barrier for the transport of photogenerated holes to the p-region, suppresses carrier accumulation at the heterojunction, thereby improving the device's response speed and bandwidth, and optimizing high-frequency performance.

[0050] Intrinsic Absorption Layer 7: The intrinsic absorption layer 7 is the core region of the device's response to long-wavelength (e.g., 1310nm or 1550nm) optical signals, and is composed of intrinsic InGaAs material. In the high-speed device design of this invention, this layer is intentionally optimized to be thinner, typically 100-300nm (i.e., the "small i-layer" as commonly understood in the industry), aiming to minimize the transit time of photogenerated carriers, thereby reducing their limitation on the device's RC bandwidth. The intrinsic absorption layer 7 is grown on a high-quality intrinsic graded layer 6, ensuring extremely low defect density, thus achieving high internal quantum efficiency. This invention, through a complete lattice mismatch solution at the bottom layer, ensures that the intrinsic absorption layer 7 grown on the low-cost GaAs substrate 1 achieves dark current and responsivity performance comparable to that grown on a native InP substrate.

[0051] Window layer 8: Window layer 8 is grown on top of intrinsic absorber layer 7 and is typically composed of a wide-bandgap p-type InP material with a thickness of approximately 100-300 nm. The function of window layer 8 is to form a potential barrier for minority carriers (electrons) in intrinsic absorber layer 7, preventing them from diffusing to the surface and undergoing nonradiative recombination, thereby significantly reducing surface leakage current and improving the quantum efficiency and long-term reliability of the device. Simultaneously, window layer 8 also provides a suitable material interface for forming a good p-type ohmic contact.

[0052] p-type contact layer 9: Located on the top layer of the device, typically composed of heavily doped p-type contact layers. +The layer is composed of InGaAs material with a thickness of approximately 100-200 nm. The function of the p-type contact layer 9 is to form a low-resistance, low-contact-barrier ohmic contact with the p-type metal electrode, thereby efficiently drawing current out of the device. Based on the flat, uniform, and clean surface provided by the entire low-dislocation-density epitaxial structure below, this layer can achieve stable, uniform, and low-resistance metal-semiconductor contacts, ensuring the consistency and stability of device operation.

[0053] Reference Figures 1 to 4 The deformed growth layer 2 and the dislocation filter layer 3 are the design focus of this invention and are the core components for achieving high-quality heterogeneous integration of the GaAs substrate 1 and the InP-based PIN functional layer. The deformed growth layer 2, through a continuous gradual change in lattice constant, fundamentally solves the approximately 4% macroscopic lattice mismatch problem between GaAs and InP, constructing a virtual InP platform. The dislocation filter layer 3, on this basis, acts as a crucial crystal quality purifier, further eliminating microscopic defects and ensuring the crystal perfection of core functional regions such as the upper intrinsic layer 5 and intrinsic absorption layer 7, thus providing an ideal material basis for subsequent ion implantation modification processes. The structural design and working principle of the deformed growth layer 2 and the dislocation filter layer 3 are analyzed in detail below.

[0054] 1. Structural design and working principle of deformable growth layer 2

[0055] Reference Figure 3 The core design of the deformed growth layer 2 lies in achieving a linear and controllable gradual change of the lattice constant along the growth direction. The main technical approach is based on achieving continuous change of the lattice constant through precise control of the multi-element alloy composition. In this embodiment, the deformed growth layer 2 is an InAlAs ternary alloy gradient layer. By linearly controlling the In and Al components in the InAlAs ternary alloy gradient layer, a synergistic gradual change in the lattice constant and bandgap is achieved.

[0056] Reference Figure 3The design principle of the InAlAs ternary alloy graded layer is as follows: During growth, the flow rates of trimethylindium (TMIn) and trimethylaluminum (TMAl) are linearly adjusted using metal-organic chemical vapor deposition (MOCVD). This results in a linear increase in In content and a linear decrease in Al content along the growth direction, allowing the lattice constant of the InAlAs ternary alloy graded layer to smoothly and continuously transition from a value close to GaAs (~5.66 Å) at the bottom to a value matching InP (~5.87 Å) at the top. In this embodiment, the layer thickness is designed to be 1-3 μm, with the In content linearly increasing from 0.01 to 0.522 and the Al content linearly decreasing from 0.99 to 0.478. This linear gradient process allows the accumulated lattice mismatch strain to be fully relaxed within the layer by generating and confining a mismatched dislocation network, thereby forming a low dislocation density, nearly strain-free surface at the top.

[0057] Reference Figure 1 and Figure 3 This design not only achieves lattice matching but also brings about a synergistic gradient in the band structure. The band gap of InAlAs changes systematically from a wide band gap (~2.24 eV) to a narrow band gap (~1.54 eV) with increasing In composition, forming a natural band slope from the substrate to the active region of the device. The built-in quasi-electric field formed by this slope is beneficial for driving the photogenerated electrons generated in the intrinsic absorption layer 7 to be efficiently transported to the n-type contact layer 4 during device operation, thus providing a physical basis for reducing carrier transit time and improving response speed.

[0058] 2. Structural design and working principle of dislocation filter layer 3

[0059] Reference Figure 1 and Figure 4 Although the deformed growth layer 2 effectively relaxes most of the macroscopic strain, a small number of penetrating dislocations may still be generated during its relaxation process. The core function of the dislocation filtering layer 3 is to capture and block these residual dislocations from propagating upwards to the PIN core functional layers (especially the first intrinsic layer 5 and the intrinsic absorption layer 7), which are extremely sensitive to defects, thereby ensuring the crystal quality of the active region. This invention selects an InAlAs / InGaAs superlattice layer as the dislocation filtering layer 3. Through precise design of its composition, sublayer thickness, and period number, excellent dislocation filtering effect can be achieved.

[0060] Reference Figure 1 and Figure 3 To achieve optimal synergy with the InAlAs ternary alloy gradient layer and efficiently filter dislocations, the dislocation filtering layer 3 in this embodiment is preferably made of In... 0.58 Al 0.42 As tensile strain layer and In x Ga 1-xInAlAs / InGaAs strained superlattice composed of As compressive strain layers. This is achieved through gradual changes in sublayer thickness and In... x Ga 1-x As compositional gradient achieves synergy between "dynamic strain compensation" and "bandgap gradient", while ensuring overall superlattice lattice matching with InP base, thus meeting the dual requirements of carrier transport and defect filtering for high-performance devices.

[0061] Reference Figure 3 Specifically, the InAlAs / InGaAs strained superlattice comprises 10 periods, each with a total thickness of 10 nm; along the direction away from the GaAs substrate 1 (i.e., the growth direction), its structural parameters undergo precise gradients as follows: In x Ga 1-x The thickness of the As compressive strain layer smoothly increases from 3.6 nm in the first period to 8.3 nm in the tenth period; simultaneously, the In composition (x) of this layer linearly increases from 0.43 to 0.52, while the Ga composition (1-x) linearly decreases from 0.57 to 0.48. Correspondingly, the In... 0.58 Al 0.42 The thickness of the tensile strain layer decreases accordingly to ensure that the total thickness remains constant in each cycle.

[0062] Reference Figure 1 and Figure 3 The core advantage of this design lies in the fact that, through the synergistic gradual change of strain compensation (tensile and compressive strain) and structural parameters during the cycle, the average lattice constant of the entire dislocation filtering layer 3 can perfectly track and match the lattice constant of the top of the deformable growth layer 2 below, achieving optimal stress management. This spatially gradual distribution of a strong strain field can extremely efficiently bend, block, and annihilate penetrating dislocations, thereby achieving excellent defect filtering effects with fewer cycles and providing a near-perfect crystal surface for the subsequent growth of In-based PIN functional layers.

[0063] Reference Figure 1 and Figure 2 To effectively reduce the effective electrical junction area of ​​the device, this embodiment adopts an H-based... + The ion-implanting process employs a ring-patterned implantation technique, which creates an ion-implanted modified region within the first intrinsic layer 5. This ion-implanted region extends synchronously to the intrinsic gradient layer 6 and the intrinsic absorber layer 7 above it. The ion-implanted modified region is formed by introducing high-energy H₂. + The ions are formed by subsequent annealing processes. H +Ions in semiconductor lattices primarily exert two effects: first, they form electrically inactive passivating complexes with group III or V atoms in the material; second, they generate stable point defect clusters through lattice collisions. These two mechanisms together lead to a sharp decrease in carrier lifetime and a significant increase in resistivity in the injected region, thus forming a stable high-resistivity region. The establishment of this high-resistivity region is the physical basis for reconstructing the internal electric field distribution and current path of the device. This is based on a ring pattern and H... + The high-resistivity region design injected produces a synergistic modification effect on the first intrinsic layer 5, the intrinsic absorption layer 7, and the intrinsic gradient layer 6. The mechanism of action is explained as follows:

[0064] 1. Effect of ion implantation modified region on the first intrinsic layer 5

[0065] Reference Figure 1 and Figure 2 The annular high-resistivity region located in the first intrinsic layer 5 forms an electrical isolation barrier surrounding the central circular region laterally. This annular high-resistivity region precisely confines the effective conductive area of ​​the device to the central, un-injected circular region. When a reverse bias is applied to the device, the lateral expansion of the depletion electric field is effectively blocked by the annular high-resistivity region, significantly reducing the effective electrical junction area for establishing the electric field from the entire geometric area of ​​the device to the area of ​​the central circular region. According to the junction capacitance formula (C∝A), this structural design directly leads to a significant reduction in the intrinsic junction capacitance of the device, thus becoming the most critical and direct physical mechanism for improving its response bandwidth.

[0066] 2. Effect of ion implantation modified region on intrinsic absorber layer 7

[0067] Reference Figure 1 and Figure 2 Synchronous ion implantation of the intrinsic absorption layer 7 aims to optimize the transport path of photogenerated carriers, ensuring that the benefits of a small electrical area are fully realized during photoelectric conversion. If only the first intrinsic layer 5 is modified, the intrinsic absorption layer 7 above it will still generate carriers throughout the annular region under illumination. These carriers generated in the annular region may diffuse laterally into the collection region, forming additional current channels, effectively increasing the electrical area. (Through H...) + Ion implantation transforms the absorption layer of the annular region into a high recombination region, effectively confining the effective generation area of ​​photogenerated carriers to the central optical window from the source. This forces the vast majority of photogenerated carriers to be vertically transported within the window, effectively suppressing lateral diffusion, thus ensuring the effectiveness of the low capacitance design and improving collection efficiency at high frequencies.

[0068] 3. Effect of ion implantation modified region on intrinsic graded layer 6

[0069] Reference Figure 1 and Figure 2The synchronous implantation of the intrinsic graded layer 6 ensures the vertical continuity of the high-resistivity modification. The intrinsic graded layer 6 is located between the absorber layer and the first intrinsic layer 5. If it is not modified, a conductive path may be left between the high-resistivity regions of the two layers, compromising the integrity of the entire annular isolation structure. By allowing the ion-implanted modified region to extend through the intrinsic graded layer 6, a continuous and complete high-resistivity insulator can be formed throughout the entire depth from the absorber layer to the first intrinsic layer 5, completely eliminating potential vertical leakage paths and thus ensuring the reliability of the electrical isolation effect of the annular high-resistivity region.

[0070] 4. Reasons for using a ring pattern in the ion implantation modification region

[0071] This embodiment preferably uses a ring-shaped pattern, primarily due to its unique technical advantages: First, the ring structure forms a continuous, closed isolation zone, effectively isolating the central collection area from the peripheral area and achieving optimal capacitance reduction. Second, this pattern has a natural morphological match with the circular light spot pattern commonly used in optical fiber communication, which is beneficial for efficient light coupling and uniform absorption. Finally, compared to other complex patterns (such as dot lattices), the ring-shaped pattern is simpler and more robust in photolithography design and process control, which helps improve process repeatability and manufacturing yield. Therefore, the ring-shaped pattern is an ideal choice for achieving a balance between performance, reliability, and manufacturability.

[0072] In summary, this embodiment utilizes H + Ions and ring patterns are used to synergistically modify the first intrinsic layer 5, the intrinsic absorption layer 7, and the intrinsic gradient layer 6 in a three-dimensional manner. This design not only directly reduces the junction area electrically to improve bandwidth, but also systematically optimizes the generation and transport paths of photogenerated carriers, thus solving the traditional problem of balancing high bandwidth and high responsivity.

[0073] Reference Figures 1 to 4 This embodiment further provides a method for fabricating a GaAs-based low-capacitance, high-bandwidth PIN photodiode. The method first constructs a crystal platform on a GaAs substrate 1, suitable for high-quality InP-based epitaxy, through the synergistic growth of a deformable growth layer 2 and a dislocation filtering layer 3. Then, a complete InP-based PIN functional layer is grown on this platform. Finally, a unique patterned ion implantation process is used to locally modify key regions such as the first intrinsic layer 5 to reduce the effective electrical junction area. The key steps of this fabrication process are described in detail below:

[0074] Step S1: Provide GaAs substrate 1

[0075] A (100) oriented semi-insulating or n-type GaAs substrate 1 is provided. The substrate is then subjected to standard chemical cleaning with acetone, isopropanol and deionized water in sequence, followed by thermal deoxidation in a high-temperature hydrogen atmosphere to obtain a clean, atomically flat GaAs substrate 1 surface.

[0076] Step S2: Grow deformed growth layer 2 and dislocation filtering layer 3 on GaAs substrate 1.

[0077] Step S21: Grow an InAlAs ternary alloy gradient layer as a deformation growth layer 2

[0078] The treated GaAs substrate 1 was placed in a metal-organic chemical vapor deposition (MOCVD) chamber. After evacuating the system to a high vacuum, the substrate temperature was raised to approximately 600°C under a hydrogen atmosphere. Subsequently, the flow rates of trimethylindium (TMIn) and trimethylaluminum (TMAl) were linearly controlled by a programmed process: the flow rate of TMIn was linearly increased while the flow rate of TMAl was linearly decreased. This resulted in the growth of an InAlAs ternary alloy graded layer with an In composition linearly increasing from 0.01 to 0.522 and an Al composition linearly decreasing from 0.99 to 0.478 within a thickness of approximately 1.0–2.0 μm. This process smoothly transitioned the lattice constant from matching GaAs to matching InP.

[0079] Step S22: Grow an InAlAs / InGaAs strained superlattice layer as a dislocation filtering layer 3

[0080] On top of the InAlAs ternary alloy graded layer, an InAlAs / InGaAs strained superlattice layer is further grown as a dislocation filter layer 3. In this embodiment, an InAlAs / InGaAs strained superlattice layer is grown. 0.58 Al 0.42 As tensile strain layer and In x Ga 1-x A strained superlattice composed of alternating As compressive strain layers consists of 10 periods, each with a thickness of 10 nm. In... x Ga 1-x The thickness of the As compressive strain layer smoothly increases from 3.6 nm in the first period to 8.3 nm in the tenth period; simultaneously, the In composition (x) of this layer linearly increases from 0.43 to 0.52, while the Ga composition (1-x) linearly decreases from 0.57 to 0.48. Correspondingly, the In... 0.58 Al 0.42 The thickness of the tensile strain layer decreases accordingly to ensure that the total thickness remains constant in each cycle.

[0081] Step S3: Grow InP-based PIN functional layers using MOCVD process

[0082] On the high-quality crystal surface provided by dislocation filtering layer 3, InP-based PIN functional layers are sequentially grown using MOCVD process:

[0083] n-type contact layer 4: grown with Si-doped n + -InAlAs layer, with a thickness of approximately 300-500 nm and a doping concentration of approximately 1 × 10⁻⁶. 18 cm -3 .

[0084] First intrinsic layer 5: An unintentionally doped intrinsic InAlAs layer is grown as the first intrinsic layer 5 (large I layer), with a thickness of approximately 200-500 nm.

[0085] Intrinsic graded layer 6: An unintentionally doped InGaAlAs layer with a graded growth composition serves as intrinsic graded layer 6, with a thickness of approximately 30-80 nm, used to achieve a smooth bandgap transition.

[0086] Intrinsic absorption layer 7: An unintentionally doped intrinsic InGaAs layer is grown as intrinsic absorption layer 7 (small i layer), with a thickness of approximately 100-300 nm.

[0087] Window layer 8: A p-type InP layer is grown as window layer 8, with a thickness of approximately 100-300 nm.

[0088] p-type contact layer 9: The last heavily doped p-type contact layer was grown. + -The InGaAs layer serves as the p-type contact layer 9, with a thickness of approximately 100-200nm.

[0089] Step S4: Perform patterning H + Ion implantation forms a ring-shaped modified region.

[0090] After completing all epitaxial growth, the core modification step of this embodiment is performed, namely, through the annular patterned H... + Ion implantation forms a high-resistivity modified region:

[0091] Step S41, Pattern Definition: Precisely define a concentric ring-shaped photoresist injection pattern on the surface of the InP-based PIN functional layer to protect the central circular area.

[0092] Step S42, Ion Implantation: Using photoresist as a mask, perform H... + Ion implantation. In practice, the implantation energy and dose are precisely controlled by calculating the implantation depth and the required concentration. In this embodiment, the implantation energy is 50-400 keV, and the dose is 5 × 10⁻⁶. 13 Up to 5×10 15 cm -2The ion beam simultaneously bombards the unprotected annular region at the bottom of the local groove and the intrinsic absorption layer 7 and intrinsic gradient layer 6 exposed on the sidewalls of the local groove.

[0093] Step S43, Annealing: After implantation, remove the photoresist and perform rapid thermal annealing at 600-750℃ in a nitrogen atmosphere for 10-60 seconds to partially repair lattice damage and stabilize the electrical properties of the modified region. This forms a longitudinally penetrating ring-shaped ion-implanted modified region.

[0094] Step S5: Complete device fabrication

[0095] After ion implantation and annealing, standard back-end device processes are performed: the device mesa is defined using photolithography and etching; a passivation layer (such as SiN) is deposited. x The surface is passivated and local grooves are filled using SiO2; the passivation layer is photolithographically etched and etched to open electrode contact holes; ohmic contact metals on the p-side and n-side are fabricated respectively; finally, dicing, packaging and performance testing are performed to complete the fabrication of GaAs-based low-capacitance high-bandwidth PIN photodiode.

[0096] The InAlAs ternary alloy graded layer + strained superlattice + H used in this embodiment + The combination of annular injection techniques represents a technological path to pursue ultimate material quality and performance, specifically manifested as follows:

[0097] (1) Material quality and performance potential: The use of a purer InAlAs ternary alloy system for lattice gradient is beneficial to obtaining atomically sharp high-quality epitaxial interfaces. The strained superlattice generates a strong bending and pinning effect on penetrating dislocations through the alternating field of strong tensile strain and compressive strain, which can achieve the highest defect filtering efficiency with a thinner thickness, laying the most solid material foundation for the device to obtain extremely low dark current and noise.

[0098] (2) Capacitor control and bandwidth advantages: Based on the above high-quality platform, the annular H + Injection enables the most direct and effective reduction of the electrical area of ​​the first intrinsic layer 5. Mature H + The combination of injection process and annular patterning provides a reliable technical means to achieve the lowest intrinsic junction capacitance and the highest theoretical bandwidth potential of the device.

[0099] (3) High-end application adaptability: Although this scheme puts forward higher requirements for the linear control of composition and strain superlattice growth of MOCVD epitaxy, its advantages in material and electrical properties make it an advanced technology choice for fields with extreme requirements for device bandwidth, sensitivity and noise, such as high-speed backbone network communication and high-end optical sensing.

[0100] Example 2: Based on InAlGaAs quaternary alloy graded layer and He + Ion implantation scheme

[0101] Reference Figure 1 , Figure 2 , Figure 5 and Figure 6 This embodiment provides another specific implementation scheme for a GaAs-based low-capacitance, high-bandwidth PIN photodiode. It uses the core device architecture and inventive concept of Embodiment 1, with the main difference being: the deformed growth layer 2 adopts an InAlGaAs quaternary alloy gradient layer, the dislocation filtering layer 3 adopts a matching non-strained superlattice, and He is preferably used for ion implantation. + Ions. This embodiment focuses on optimizing process robustness, mass production yield, and long-term device reliability.

[0102] The following section focuses on a detailed description of the similarities and differences between this implementation and Example 1:

[0103] 1. Material design and growth strategy of deformable growth layer 2

[0104] Reference Figure 5 In this embodiment, the deformed growth layer 2 is an InAlGaAs quaternary alloy gradient layer. Its core design is to fix the composition of Al while linearly gradient the compositions of In and Ga, thereby achieving a smooth transition of the lattice constant from GaAs to InP.

[0105] Specifically, the Al composition of the InAlGaAs quaternary alloy graded layer was fixed at 0.47. Within a growth thickness of approximately 1.5–2.0 μm, the flow rates of trimethylindium (TMIn) and trimethylgallium (TMGa) were precisely controlled using MOCVD, causing the In composition to linearly increase from approximately 0.01 at the bottom to approximately 0.52 at the top, while the Ga composition linearly decreased from approximately 0.52 to approximately 0.01. Therefore, the material composition changed from the initial In... 0.01 Al 0.47 Ga 0.52 As (with a lattice similar to GaAs) gradually transitions to the final In. 0.52 Al 0.47 Ga 0.01 As (lattice-matched InP).

[0106] The strategy of fixing the Al composition offers significant process advantages: it simplifies growth control from the complex adjustment of coordinating the flow rates of three organometallic sources to primarily performing synchronous, inverse linear control of TMIn and TMGa. This simplification greatly reduces the difficulty of controlling composition and thickness uniformity on large-area epitaxial wafers (especially 6-inch or larger), thereby improving process repeatability, consistency, and yield in large-scale production, providing key technological support for low-cost manufacturing.

[0107] 2. Material design and compatibility optimization of dislocation filter layer 3

[0108] Reference Figure 6 To achieve optimal synergy with the quaternary gradient layer, the dislocation filtering layer 3 in this embodiment is preferably made of In 0.52 Al 0.48 As sublayer and In 0.53 Ga 0.47 An InAlAs / InGaAs unstrained superlattice composed of alternating As sublayers.

[0109] Specifically, the superlattice is designed with 13 periods, each 10 nm thick, for a total thickness of 130 nm. Both sublayers perfectly match the InP lattice constant. Along the growth direction, In... 0.52 Al 0.48 The thickness of the As sublayer decreases linearly from 8 nm in the first period to 2 nm in the thirteenth period; correspondingly, the In... 0.53 Ga 0.47 The thickness of the As sublayer increases linearly from 2 nm to 8 nm. This linear gradient design of the sublayer thickness allows the overall average lattice constant and stress state of the superlattice to be smoothly adapted to the top of the gradient layer below.

[0110] This unstrained superlattice bends and annihilates penetrating dislocations by abruptly changing the elastic modulus of the material at periodic interfaces. Its core advantage lies in achieving efficient dislocation filtering without introducing macroscopic tensile or compressive strain. This effectively avoids wafer warpage or reliability risks in subsequent processes that may result from strain accumulation, ensuring the flatness and long-term stability of the epitaxial wafer, making it particularly suitable for large-scale industrial manufacturing.

[0111] 3. He + Process selection and advantages of ion implantation

[0112] Reference Figure 2 In this embodiment, He is preferred in the ion implantation process. + Ions were implanted, and a ring pattern was also used. The process steps were basically the same as in Example 1 (windowing, photolithography, implantation, annealing), but the physical effects of implanted ions and the resulting properties were significantly different.

[0113] With H + Ions primarily introduce different electrical activities by forming passivation complexes; He + Ion implantation primarily creates high-resistivity regions by generating high-density, stable defect clusters such as vacancy-interstitial atom pairs in the crystal lattice. These defect clusters are permanent lattice damages with thermal stability far exceeding that of H+. + Injection may form complexes such as CH.

[0114] Therefore, He is adopted. + The annular modified region formed by ion implantation exhibits exceptional thermal stability and anti-aging properties. During subsequent long-term operation or high-temperature reliability testing, its high-resistivity characteristics show virtually no drift due to ion diffusion or complex decomposition. This fundamentally solves the problem of potential changes in the electrical properties of the implanted modified region over time or temperature, providing the device with superior long-term operational reliability and parameter consistency, making it particularly suitable for applications with stringent lifetime and stability requirements.

[0115] This embodiment uses an InAlGaAs quaternary graded layer + unstrained superlattice + He + The combination of annular injection techniques represents a technological path that pursues superior process robustness and ultimate reliability, specifically manifested as follows:

[0116] (1) Manufacturing friendliness: The design of InAlGaAs quaternary gradient layer to fix Al composition and the characteristics of non-strained superlattice without macroscopic stress greatly improve the controllability and yield of epitaxial process on large-size wafers.

[0117] (2) Reliability first: He + The lattice-damaged high-resistivity region formed by ion implantation possesses unparalleled thermal stability, ensuring high stability of device performance during long-term operation.

[0118] (3) Performance assurance: Although process robustness is the primary goal, this solution can still ensure that the device achieves the core high-performance indicators of low capacitance and high bandwidth through a high-quality material platform and equally effective ring capacitor reduction design, raising manufacturing feasibility and long-term reliability to a new level. It is an ideal solution for the needs of large-scale manufacturing and high-reliability applications in the telecommunications market.

[0119] The above are merely specific embodiments of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial modifications made to the present invention using the design concept shall be considered an infringement of the protection scope of the present invention.

Claims

1. A GaAs-based low-capacitance high-bandwidth PIN photodiode, characterized in that: comprising a GaAs substrate, a metamorphic growth layer, a dislocation filtering layer and an InP-based PIN functional layer; the lattice constant of the metamorphic growth layer gradually changes along the growth direction to realize the transition of the lattice constant from the GaAs substrate to the InP-based PIN functional layer; the metamorphic growth layer is an InAlAs ternary alloy graded layer or an InAlGaAs quaternary alloy graded layer, and the coordinated gradual change of the lattice constant and the band gap is realized by linear regulation of the In, Al and / or Ga components of the metamorphic growth layer; the dislocation filtering layer is arranged between the metamorphic growth layer and the InP-based PIN functional layer to block the transmission of dislocations generated by the metamorphic growth layer to the InP-based PIN functional layer; the InP-based PIN functional layer comprises an n-type contact layer, a first intrinsic layer, an intrinsic absorption layer and a window layer which are sequentially stacked, the first intrinsic layer is provided with an ion implantation modification region for forming a high resistance area to reduce the effective electrical junction area of the device; the InP-based PIN functional layer further comprises an intrinsic graded layer arranged between the first intrinsic layer and the intrinsic absorption layer, and the ion implantation modification region extends into the intrinsic graded layer and the intrinsic absorption layer. The dislocation filtering layer is an InAlAs / InGaAs superlattice layer, and the precise regulation of the dislocation filtering function is realized by component regulation, sublayer thickness regulation and / or period parameter regulation. The ion implantation modification region is distributed in a grid-like, lattice-like or ring-like pattern in the plane. The method comprises the following steps: Step S1, providing a GaAs substrate; 2. A GaAs-based low-capacitance high-bandwidth PIN photodiode as claimed in claim 1, characterized in that: Step S2, growing a metamorphic growth layer with a gradually changing lattice constant along the growth direction on the GaAs substrate, and growing a dislocation filtering layer on the metamorphic growth layer; 3. The GaAs-based low-capacitance, high-bandwidth PIN photodiode as described in claim 1, characterized in that: The ion implantation modification region is formed by H + or He + ion implantation.

4. The GaAs-based low-capacitance, high-bandwidth PIN photodiode as described in claim 1, characterized in that: Step S3, growing the InP-based PIN functional layer on the metamorphic growth layer and the dislocation filtering layer, the InP-based PIN functional layer comprising an n-type contact layer, a first intrinsic layer, an intrinsic graded layer, an intrinsic absorption layer and a window layer which are sequentially stacked; 5. A method for fabricating a GaAs-based low-capacitance high-bandwidth PIN photodiode, characterized in that: Step S4, performing selective ion implantation on the first intrinsic layer, the intrinsic graded layer and the intrinsic absorption layer to form an ion implantation modification region; this step comprises the following substeps: Step S41, defining an implantation pattern on the surface of the InP-based PIN functional layer by a photolithography process; Step S42, performing ion implantation with the implantation pattern as a mask to form the ion implantation modification region; Step S43, performing annealing treatment. ​ ​ ​ ​

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