Photovoltaic cell and method of manufacturing the same, photovoltaic module

Abstract

The present disclosure relates to the field of photovoltaics, and provides a photovoltaic cell, a manufacturing method thereof, and a photovoltaic module. The photovoltaic cell comprises: a substrate, one surface of the substrate being a polished surface, and the surface comprising first regions and second regions arranged alternately along a first direction; a passivation layer located on at least one of the first regions and the second regions; a first intrinsic layer located on the first regions, and a first doped layer located on a side of the first intrinsic layer away from the substrate; a second intrinsic layer located on the second regions, and a second doped layer located on a side of the second intrinsic layer away from the substrate; wherein the passivation layer is located between the first intrinsic layer and the substrate, and / or the passivation layer is located between the second intrinsic layer and the substrate. The present disclosure is at least advantageous in improving the collection efficiency of photogenerated carriers of the photovoltaic cell.

Description

Technical Field

[0001] This disclosure relates to the photovoltaic field, and in particular to a photovoltaic cell and its manufacturing method, and a photovoltaic module. Background Technology

[0002] Photovoltaic cells, as a sustainable and clean energy source, are being used more and more widely. A photovoltaic cell is a device that uses the photovoltaic principle to generate charge carriers, converting solar energy into electrical energy. Grid lines are typically used in photovoltaic cells to extract these charge carriers, thus efficiently utilizing the electrical energy. Currently, the mainstream types of photovoltaic cells include BC cells (BackContact), TOPCON (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated emitter and real cell), and heterojunction cells (Heterojunction with Intrinsic Thin-film, abbreviated as HIT or HJT), etc.

[0003] Among them, HBC cells (Heterojunction Back Contact) combine the excellent passivation performance of HJT cells with the characteristics of BC cells, such as no grid lines blocking the front side. They are considered to be a high-efficiency crystalline silicon photovoltaic cell option and have broad application prospects in the photovoltaic market.

[0004] However, in HBC cells, the morphology of each film layer can affect the functionality of each layer. Furthermore, the fabrication of HBC cells requires repeated use of mask technology, which greatly increases the difficulty of the process and the production cost, and also reduces the fabrication efficiency. This can lead to various factors affecting the photovoltaic cell's efficiency in collecting photogenerated carriers. Summary of the Invention

[0005] This disclosure provides a photovoltaic cell and its manufacturing method, as well as a photovoltaic module, which at least helps to improve the collection efficiency of photovoltaic cells for photogenerated carriers.

[0006] This disclosure provides a photovoltaic cell, comprising: a substrate, one surface of which is polished and includes a first region and a second region alternately arranged along a first direction; a passivation layer located on at least one of the first region and the second region; a first intrinsic layer and a first doped layer, the first intrinsic layer located on the first region and the first doped layer located on the side of the first intrinsic layer away from the substrate; a second intrinsic layer and a second doped layer, the second intrinsic layer located on the second region and the second doped layer located on the side of the second intrinsic layer away from the substrate, wherein the second doped layer and the first doped layer are doped with different types of doping elements; wherein the passivation layer is located between the first intrinsic layer and the substrate, and / or the passivation layer is located between the second intrinsic layer and the substrate.

[0007] Optionally, the passivation layer includes a first passivation layer located on the first region.

[0008] Optionally, the thickness of the first doped layer along the thickness direction of the substrate is 2 nm to 4 nm.

[0009] Optionally, the passivation layer includes a second passivation layer located on the second region.

[0010] Optionally, the passivation layer includes a second passivation layer and a first passivation layer located on the first region; wherein, along the thickness direction of the substrate, the ratio of the thickness of the second passivation layer to the thickness of the first passivation layer is less than or equal to 50%.

[0011] Optionally, the thickness of the second doped layer is 4 nm to 8 nm along the thickness direction of the substrate.

[0012] Optionally, along the thickness direction of the substrate, the thickness of the first intrinsic layer is less than the thickness of the second intrinsic layer.

[0013] Optionally, the passivation layer is intrinsic silicon oxide.

[0014] Optionally, the crystalline state distribution inside the first doped layer is a mixture of microcrystalline, nanocrystalline, and amorphous states; and / or, the crystalline state distribution inside the second doped layer is a mixture of microcrystalline, nanocrystalline, and amorphous states.

[0015] Optionally, the crystallinity of the first doped layer is 50% to 65%; and / or, the crystallinity of the second doped layer is 50% to 65%.

[0016] Optionally, the substrate includes two opposing surfaces along a second direction, one of the two surfaces including a first region and a second region, the first direction intersecting the second direction, the second direction being the thickness direction of the substrate; the substrate also includes a side surface connecting the two surfaces; the photovoltaic cell further includes: a side doped layer located in at least a portion of the side surface; the side doped layer includes a first part and a second part stacked along the first direction, the second part being located on the side of the first part away from the side surface; wherein, the crystallinity of the second part is lower than the crystallinity of the first part.

[0017] This disclosure also provides a method for manufacturing a photovoltaic cell, comprising: providing a substrate, one surface of which is a polished surface, and the surface including a first region and a second region alternately arranged along a first direction; forming an initial passivation layer on the polished surface; sequentially forming an initial intrinsic layer and an initial doped layer on the side of the initial passivation layer away from the substrate; forming a mask layer on the surface of the initial doped layer located in the first region or the second region away from the substrate; and performing patterning processing using the initial passivation layer as an etch barrier layer to remove the initial doped layer and the initial intrinsic layer not covered by the mask layer. The process involves forming an intrinsic layer and an initial passivation layer of at least a partial thickness, while preventing the polished surface from being etched, with the remaining initial passivation layer serving as a passivation layer; wherein the mask layer is located in the first region, the remaining initial passivation layer serves as a first intrinsic layer, the remaining initial doped layer serves as a first doped layer, and then a second intrinsic layer and a second doped layer are sequentially formed on the second region before the mask layer is removed; or, the mask layer is located in the second region, the remaining initial passivation layer serves as a second intrinsic layer, the remaining initial doped layer serves as a second doped layer, and then a first intrinsic layer and a first doped layer are sequentially formed on the first region before the mask layer is removed.

[0018] Optionally, the step of forming the initial passivation layer includes: placing the substrate in a reaction chamber, and introducing silane and carbon dioxide into the reaction chamber to deposit the initial passivation layer on the polished surface; wherein the ratio of the gas flow rate of the silane to the gas flow rate of the carbon dioxide is (1~3):1.

[0019] Optionally, the initial passivation layer is formed on the polished surface using a thermal oxidation process.

[0020] Optionally, the substrate includes a first surface and a second surface opposite to each other along a second direction, the second surface being the polished surface, the first direction intersecting the second direction, and the second direction being the thickness direction of the substrate; in the step of performing the patterning process, the first surface is further etched to make the first surface a textured surface.

[0021] In another aspect, this disclosure provides a photovoltaic module, comprising: a battery string, formed by connecting a plurality of photovoltaic cells as described in any one of the preceding claims, or formed by connecting a plurality of photovoltaic cells formed by a manufacturing method of photovoltaic cells as described in any one of the preceding claims; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film opposite to the battery string.

[0022] The technical solution provided in this disclosure has at least the following advantages:

[0023] The polished surface design improves the thickness uniformity of both the first and second intrinsic layers. Furthermore, compared to a textured surface, the polished surface design allows for a reduction in the thickness of at least one of the first and second intrinsic layers, which helps lower the tunneling resistivity of photogenerated carriers in the thinner first and / or second intrinsic layers, thereby improving the photovoltaic cell's collection efficiency for photogenerated carriers. In addition, by first setting a passivation layer on at least one of the first and second regions, followed by the first intrinsic layer and the first doped layer, and / or the second intrinsic layer and the second doped layer, the passivation effect of the passivation layer on the substrate can further reduce the thickness of the first and / or second intrinsic layers. In other words, the combined effect of the polished surface and the passivation layer helps to significantly reduce the thickness of the first and / or second intrinsic layers while ensuring good passivation of the substrate, thereby further reducing the tunneling resistivity of photogenerated carriers in the thinner first and / or second intrinsic layers, and further improving the photovoltaic cell's collection efficiency for photogenerated carriers. Moreover, reducing the thickness of the first intrinsic layer and / or the second intrinsic layer helps to reduce its parasitic absorption of light, and the design of the polished surface helps to enhance the reflection of long-wavelength light from the polished surface, both of which help to improve the light absorption and utilization rate of photovoltaic cells. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a first partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure;

[0026] Figure 2 This is a second partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure;

[0027] Figure 3 This is a third partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure;

[0028] Figure 4 This is a fourth partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure;

[0029] Figure 5 This is a fifth partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure;

[0030] Figure 6 A process flow diagram of a method for manufacturing a photovoltaic cell according to another embodiment of this disclosure;

[0031] Figure 7 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in another embodiment of the present disclosure after the formation of an initial passivation layer;

[0032] Figure 8 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in another embodiment of the present disclosure after the formation of a mask layer;

[0033] Figure 9 This is another partial cross-sectional schematic diagram of the photovoltaic cell manufacturing method provided in another embodiment of the present disclosure after the mask layer has been formed;

[0034] Figure 10 This is a partial cross-sectional schematic diagram after graphical processing in a method for manufacturing a photovoltaic cell according to another embodiment of this disclosure;

[0035] Figure 11 Another partial cross-sectional view after graphical processing in a method for manufacturing a photovoltaic cell according to another embodiment of this disclosure;

[0036] Figure 12 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method according to another embodiment of the present disclosure after the formation of an anti-reflection layer;

[0037] Figure 13 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method according to another embodiment of the present disclosure after the formation of a doped film;

[0038] Figure 14 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method according to another embodiment of the present disclosure after the formation of the second doped layer;

[0039] Figure 15 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in yet another embodiment of this disclosure;

[0040] Figure 16This is a partial cross-sectional schematic diagram of a photovoltaic module provided in yet another embodiment of the present disclosure.

[0041] Explanation of reference numerals in the attached figures:

[0042] 100, Substrate; 100a, Surface; 1001, First Surface; 1002, Second Surface; 100b, Side Surface; 110, First Region; 120, Second Region; 101, Passivation Layer; 111, First Passivation Layer; 121, Second Passivation Layer; 131, Initial Passivation Layer; 102, First Intrinsic Layer; 112, Initial Intrinsic Layer; 103, First Doped Layer; 113, Initial Doped Layer; 104, Second Intrinsic Layer; 14. Passivation film; 105. Second doped layer; 115. Doped film; 106. Side doped layer; 116. First part; 126. Second part; 107. Mask layer; 118. First transparent conductive layer; 128. Second transparent conductive layer; 119. First electrode; 129. Second electrode; 139. Third passivation layer; 149. Anti-reflective layer; 40. Photovoltaic cell; 41. Encapsulating film; 42. Cover plate; 43. Solder ribbon. Detailed Implementation

[0043] As can be seen from the background technology, the collection efficiency of photovoltaic cells for photogenerated carriers needs to be improved.

[0044] Analysis revealed that, to improve the absorption and utilization rate of light on the front side and for ease of fabrication, both sides of HBC cells generally have a textured morphology. Designing an intrinsic layer, such as amorphous silicon, on this textured morphology makes the intrinsic layer susceptible to the influence of the texture, leading to problems such as poor uniformity and insufficient passivation. This necessitates increasing the thickness of the intrinsic layer to improve its passivation effect. However, increasing the thickness of the intrinsic layer may result in higher contact resistance. Therefore, the textured morphology affects the passivation performance of the intrinsic layer, and the thickness of the intrinsic layer has a significant impact on both its passivation performance and transport resistance, ultimately adversely affecting the photovoltaic cell's efficiency in collecting photogenerated carriers.

[0045] This disclosure provides a photovoltaic cell and its manufacturing method, as well as a photovoltaic module. In the photovoltaic cell, the design of the polished surface is beneficial to improving the thickness uniformity of both the first intrinsic layer and the second intrinsic layer. Moreover, compared with the textured surface, the design based on the polished surface can appropriately reduce the thickness of at least one of the first intrinsic layer and the second intrinsic layer, which is beneficial to reducing the tunneling resistivity of photogenerated carriers in the thinner first intrinsic layer and / or second intrinsic layer, thereby improving the photovoltaic cell's collection efficiency of photogenerated carriers. Furthermore, by first setting a passivation layer on at least one of the first and second regions, followed by setting a first intrinsic layer and a first doped layer, and / or setting a second intrinsic layer and a second doped layer, the passivation effect of the passivation layer on the substrate can further reduce the thickness of the first intrinsic layer and / or the second intrinsic layer. In other words, the combined effect of the polished surface and the passivation layer helps to significantly reduce the thickness of the first intrinsic layer and / or the second intrinsic layer while ensuring a good passivation effect on the substrate. This further reduces the tunneling resistivity of photogenerated carriers in the thinner first intrinsic layer and / or the second intrinsic layer, thereby further improving the photovoltaic cell's collection efficiency of photogenerated carriers. Moreover, the reduction in the thickness of the first intrinsic layer and / or the second intrinsic layer helps to reduce its parasitic absorption of light, and the design of the polished surface helps to enhance the reflection of long-wavelength light, both of which contribute to improving the photovoltaic cell's light absorption and utilization rate.

[0046] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "a plurality of" means two or more, unless otherwise explicitly defined.

[0047] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0048] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0049] In the description of embodiments of this disclosure, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0050] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0051] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0052] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0053] In the description of embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Additionally, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0054] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0055] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0056] This disclosure provides a photovoltaic cell according to one embodiment. The photovoltaic cell provided by this disclosure will be described in detail below with reference to the accompanying drawings.

[0057] Reference Figures 1 to 3 The photovoltaic cell includes: a substrate 100, one surface 100a of the substrate 100 being a polished surface, and the surface 100a including a first region 110 and a second region 120 alternately arranged along a first direction X; a passivation layer 101 located on at least one of the first region 110 and the second region 120; a first intrinsic layer 102 and a first doped layer 103, the first intrinsic layer 102 being located on the first region 110 and the first doped layer 103 being located on the side of the first intrinsic layer 102 away from the substrate 100; a second intrinsic layer 104 and a second doped layer 105, the second intrinsic layer 104 being located on the second region 120 and the second doped layer 105 being located on the side of the second intrinsic layer 104 away from the substrate 100, the second doped layer 105 and the first doped layer 103 being doped with different types of doping elements; wherein, the passivation layer 101 is located between the first intrinsic layer 102 and the substrate 100, and / or, the passivation layer 101 is located between the second intrinsic layer 104 and the substrate 100.

[0058] in, Figure 1 This is a first partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure; Figure 2 This is a second partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure; Figure 3 This is a third partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure.

[0059] It should be noted that when a surface 100a of the substrate 100 is described as a polished surface, it means that this surface 100a includes multiple platform structures or pyramidal base structures. Compared to a surface that includes multiple pyramidal structures, i.e., a surface with a textured surface, the polished surface 100a has a flatter surface morphology. This is beneficial for improving the uniformity of the passivation layer 101, intrinsic layer, and / or doped layer formed on this surface 100a, resulting in a relatively flat morphology for the passivation layer 101, intrinsic layer, and / or doped layer formed on the polished surface. The platform structures or pyramidal base structures of the polished surface can be considered as the base portion of a pyramidal structure; that is, the polished surface includes multiple square pyramidal base surfaces.

[0060] In some cases, the polished surface can be the surface formed after the substrate 100 has been texturized to form a pyramid structure, and then polished to remove the apex of the pyramid structure during the polishing process. In other words, the polished surface includes the remaining structure after the apex of the pyramid structure has been removed; that is, the polished surface includes the remaining slightly raised platform structure or the base structure.

[0061] It is worth noting that the surface 100a used to set the first intrinsic layer 102 and the second intrinsic layer 104 is designed as a polished surface. This facilitates the improvement of the thickness uniformity of the first intrinsic layer 102 and the second intrinsic layer 104 by means of the polished surface. That is, along the second direction Y, the thickness of different regions in the first intrinsic layer 102 is almost the same, and the thickness of different regions in the second intrinsic layer 104 is also almost the same. This is beneficial to improving the passivation effect of the first intrinsic layer 102 on the substrate 100 and improving the passivation effect of the second intrinsic layer 104 on the substrate 100. Furthermore, due to the assistance of the polished surface, the relatively thin first intrinsic layer 102 and second intrinsic layer 104 can provide a good passivation effect on the substrate 100. In other words, compared to the textured surface, the design based on the polished surface can appropriately reduce the thickness of at least one of the first intrinsic layer 102 and the second intrinsic layer 104. The reduction in the thickness of the first intrinsic layer 102 and / or the second intrinsic layer 104 is beneficial to reducing the tunneling resistivity of photogenerated carriers in the thinner first intrinsic layer 102 and / or the second intrinsic layer 104, thereby improving the collection efficiency of photovoltaic cells for photogenerated carriers.

[0062] Furthermore, a passivation layer 101 is first disposed on at least one of the first region 110 and the second region 120, followed by a first intrinsic layer 102 and a first doped layer 103 and / or a second intrinsic layer 104 and a second doped layer 105. By utilizing the passivation effect of the passivation layer 101 on the substrate 100, the thickness of the first intrinsic layer 102 and / or the second intrinsic layer 104 can be further reduced, thereby further reducing the tunneling resistivity of photogenerated carriers in the thinner first intrinsic layer 102 and / or the second intrinsic layer 104, so as to further improve the collection efficiency of photovoltaic cells for photogenerated carriers.

[0063] It is worth emphasizing that the combined effect of the polished surface and the passivation layer 101 helps to significantly reduce the thickness of the first intrinsic layer 102 and / or the second intrinsic layer 104 while ensuring a good passivation effect on the substrate 100. This reduces the tunneling resistivity of photogenerated carriers in the thinner first intrinsic layer 102 and / or second intrinsic layer 104, thereby further improving the photovoltaic cell's collection efficiency for photogenerated carriers. Moreover, the reduction in the thickness of the first intrinsic layer 102 and / or the second intrinsic layer 104 helps to reduce its parasitic absorption of light, and the design of the polished surface helps to enhance the reflection of long-wavelength light, both of which contribute to improving the photovoltaic cell's light absorption and utilization rate.

[0064] In some cases, for ease of describing the arrangement of the passivation layer 101, the intrinsic layer and the doped layer on the substrate 100, the substrate 100 is divided into a first region 110 and a second region 120 with reference to the surface 100a of the substrate 100. The intrinsic layer includes a first intrinsic layer 102 and a second intrinsic layer 104, the doped layer includes a first doped layer 103 and a second doped layer 105, and the passivation layer 101 includes at least one of the first passivation layer and the second passivation layer described later.

[0065] Specifically, the first region 110 can be considered as the region where the first intrinsic layer 102 and the first doped layer 103 are placed on the surface 100a of the substrate 100; the second region 120 can be considered as the region where the second intrinsic layer 104 and the second doped layer 105 are placed on the surface 100a of the substrate 100. In other words, the first region 110 can be considered as the region within the substrate 100 directly opposite to the first intrinsic layer 102 and the first doped layer 103 along the second direction Y, or it can be understood as the region where the orthogonal projections of the first intrinsic layer 102 and the first doped layer 103 are located on the substrate 100; the second region 120 can be considered as the region within the substrate 100 directly opposite to the second intrinsic layer 104 and the second doped layer 105 along the second direction Y, or it can be understood as the region where the orthogonal projections of the second intrinsic layer 104 and the second doped layer 105 are located on the substrate 100.

[0066] The photovoltaic cell provided in one embodiment of this disclosure will be described in more detail below with reference to the accompanying drawings.

[0067] In some embodiments, reference Figures 1 to 3 The first doped layer 103 is doped with a p-type dopant, and the second doped layer 105 is doped with an n-type dopant; in other embodiments, refer to Figures 1 to 3 The first doped layer 103 is doped with an N-type dopant element, and the second doped layer 105 is doped with a P-type dopant element.

[0068] In some cases, the N-type dopant can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As); the P-type dopant can be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

[0069] In some embodiments, reference Figures 1 to 3 The substrate 100 can be made of an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material can be monocrystalline, polycrystalline, amorphous, or microcrystalline (a state simultaneously possessing both monocrystalline and amorphous states is called microcrystalline). For example, silicon can be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In other embodiments, reference continues... Figures 1 to 3 The substrate 100 can also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallium arsenide, perovskite, cadmium telluride, and copper indium selenide. The following description uses silicon as the material for substrate 100 as an example.

[0070] The following describes in detail the arrangement relationship between the passivation layer 101, the first intrinsic layer 102, and the second intrinsic layer 104 through three embodiments.

[0071] In some embodiments, reference Figure 1 The passivation layer 101 may include a first passivation layer 111 located on the first region 110. In this way, not only can the polished surface promote the thickness uniformity of the first passivation layer 111 and thus improve its passivation effect, but both the first passivation layer 111 and the first intrinsic layer 102 can passivate the substrate 100. Therefore, with the combined effect of the polished surface and the first passivation layer 111, the thickness of the first intrinsic layer 102 can be effectively reduced, for example, to a thickness smaller than that of the second intrinsic layer 104 located on the second region 120 where no passivation layer is provided, so as to reduce the tunneling resistivity of photogenerated carriers in the thinner first intrinsic layer 102.

[0072] In some cases, the first doped layer 103 is doped with a p-type dopant, and the second doped layer 105 is doped with an n-type dopant. The photogenerated carriers transported via the first intrinsic layer 102 and the first doped layer 103 are holes, while the photogenerated carriers transported via the second intrinsic layer 104 and the second doped layer 105 are electrons. Generally, the resistance encountered by electrons during transport in the second intrinsic layer 104 and the second doped layer 105 is less than the resistance encountered by holes during transport in the first intrinsic layer 102 and the first doped layer 103. Therefore, even if the thickness of the first intrinsic layer 102 and the thickness of the second intrinsic layer 104 are reduced by the same amount, for example, by 1 nm, the reduction in resistance to hole transport in the first intrinsic layer 102 will be greater than the reduction in resistance to electron transport in the second intrinsic layer 104.

[0073] Based on this, a first passivation layer 111 is provided between the first intrinsic layer 102 and the substrate 100. This can effectively reduce the thickness of the first intrinsic layer 102 while ensuring a good passivation effect on the portion of the substrate 100 located in the first region 110. This significantly reduces the obstruction to hole transport in the first intrinsic layer 102 and the first doped layer 103, thereby significantly reducing the hole tunneling resistivity.

[0074] In some examples, continue to refer to Figure 1 Along the thickness direction of the substrate 100, i.e., in the second direction Y, the ratio of the thickness of the first intrinsic layer 102 to the thickness of the second intrinsic layer 104 can be 1 / 4 to 2 / 3, for example, 1 / 3, 5 / 12, 1 / 2, 7 / 12, or 2 / 3. It is worth noting that, with the combined effect of the polished surface and the first passivation layer 111, the thickness of the first intrinsic layer 102 can be reduced by at least 1 / 3 compared to the thickness of the second intrinsic layer 104 located on the second region 120 where no passivation layer is provided. This can significantly reduce the hole tunneling resistivity, and at the same time, the first passivation layer 111 and the first intrinsic layer 102 ensure a good passivation effect on the substrate 100 and reduce the parasitic absorption of light by the first intrinsic layer 102.

[0075] In one example, continue to refer to Figure 1 Along the thickness direction of the substrate 100, i.e., in the second direction Y, the thickness of the first intrinsic layer 102, which is disposed between the substrate 100 and the first passivation layer 111, can be 2nm to 4nm. For example, it can be 2nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm, 2.6nm, 2.7nm, 2.8nm, 2.9nm, 3nm, 3.1nm, 3.2nm, 3.3nm, 3.4nm, 3.5nm, 3.6nm, 3.7nm, 3.8nm, 3.9nm, or 4nm, etc.

[0076] In one example, continue to refer to Figure 1 Along the thickness direction of the substrate 100, i.e., in the second direction Y, the thickness of the second intrinsic layer 104 located on the second region 120 where no passivation layer is provided can be 6nm to 8nm, for example, it can be 6nm, 6.1nm, 6.2nm, 6.3nm, 6.4nm, 6.5nm, 6.6nm, 6.7nm, 6.8nm, 6.9nm, 7nm, 7.1nm, 7.2nm, 7.3nm, 7.4nm, 7.5nm, 7.6nm, 7.7nm, 7.8nm, 7.9nm or 8nm, etc.

[0077] In other embodiments, reference is made to... Figure 2 The passivation layer 101 may include not only the first passivation layer 111 located on the first region 110, but also the second passivation layer 121 located on the second region 120. In other words, the passivation layer 101 includes the second passivation layer 121 and the first passivation layer 111 located on the first region 110. Thus, while ensuring good passivation effect on the substrate 100 located in both the first region 110 and the second region 120, not only can the thickness of the first intrinsic layer 102 be effectively reduced by the combined effect of the polished surface and the first passivation layer 111, but the thickness of the second intrinsic layer 104 can also be effectively reduced by the combined effect of the polished surface and the second passivation layer 121. This is beneficial for reducing the tunneling resistivity of photogenerated carriers in the first intrinsic layer 102 and the second intrinsic layer 104, as well as reducing the parasitic absorption of light by the first intrinsic layer 102 and the second intrinsic layer 104.

[0078] It is worth noting that the first passivation layer 111 and the second passivation layer 121 can be formed in the same step, that is, the second passivation layer 121 is formed during the formation of the first passivation layer 111. Due to the influence of the fabrication process, the thickness of the second passivation layer 121 will be smaller than the thickness of the first passivation layer 111.

[0079] In some cases, continue to refer to Figure 2 Along the thickness direction of the substrate 100, i.e. the second direction Y, the ratio of the thickness of the second passivation layer 121 to the thickness of the first passivation layer 111 can be less than or equal to 50%, for example, it can be 50%, 49%, 48%, 47%, 46%, 45%, 44%, 43%, 42%, 41%, 40%, 39%, 38%, 37%, 36%, 35%, 34%, 33%, 32%, 31% or 30%, etc.

[0080] In one example, continue to refer to Figure 2Along the second direction Y, the thickness of the first passivation layer 111 can be 1nm to 2nm, for example, it can be 1nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm or 2nm, etc.

[0081] In one example, continue to refer to Figure 2 Along the second direction Y, the thickness of the second passivation layer 121 can be less than or equal to 1 nm, for example, it can be 1 nm, 0.95 nm, 0.9 nm, 0.85 nm, 0.8 nm, 0.75 nm, 0.7 nm, 0.65 nm, 0.6 nm, 0.55 nm, 0.5 nm, 0.45 nm, 0.4 nm, 0.35 nm or 0.3 nm, etc.

[0082] In some cases, continue to refer to Figure 2 Since the thickness of the first passivation layer 111 is greater than the thickness of the second passivation layer 121, the passivation effect of the first passivation layer 111 on the substrate 100 is better than that of the second passivation layer 121. Based on this, the reduction in the thickness of the first intrinsic layer 102 can be greater than the reduction in the thickness of the second intrinsic layer 104; that is, the thickness of the first intrinsic layer 102 can also be less than the thickness of the second intrinsic layer 104. Furthermore, due to the combined effect of the first passivation layer 111 and the second passivation layer 121, the difference in thickness between the first intrinsic layer 102 and the second intrinsic layer 104 can be reduced, for example, making the thickness of the first intrinsic layer 102 equal to the thickness of the second intrinsic layer 104.

[0083] In some examples, continue to refer to Figure 2 Along the second direction Y, the ratio of the thickness of the first intrinsic layer 102 to the thickness of the second intrinsic layer 104 can be 2 / 7 to 1, for example, it can be 2 / 7, 3 / 7, 4 / 7, 5 / 7, 6 / 7 or 1, etc. In this way, the reduction in the thickness of the first intrinsic layer 102 can be greater than the reduction in the thickness of the second intrinsic layer 104, which is beneficial to significantly reduce the hole tunneling resistivity, and can retain a relatively thick second intrinsic layer 104 to ensure a good passivation effect on the substrate 100 while reducing the electron tunneling resistivity.

[0084] In one example, continue to refer to Figure 2 Along the second direction Y, the thickness of the first intrinsic layer 102 can be 2nm~4nm.

[0085] In one example, continue to refer to Figure 2Along the second direction Y, the thickness of the second intrinsic layer 104 can be 4nm to 7nm, for example, it can be 4nm, 4.1nm, 4.2nm, 4.3nm, 4.4nm, 4.5nm, 4.6nm, 4.7nm, 4.8nm, 4.9nm, 5nm, 5.1nm, 5.2nm, 5.3nm, 5.4nm, 5.5nm, 5.6nm, 5.7nm, 5.8nm, 5.9nm, 6nm, 6.1nm, 6.2nm, 6.3nm, 6.4nm, 6.5nm, 6.6nm, 6.7nm, 6.8nm, 6.9nm, or 7nm, etc.

[0086] In some other embodiments, reference is made to Figure 3 The passivation layer 101 may include a second passivation layer 121 located on the second region 120. Thus, not only can the polished surface promote the thickness uniformity of the second passivation layer 121, thereby improving its passivation effect, but both the second passivation layer 121 and the second intrinsic layer 104 can passivate the substrate 100. Therefore, by means of the combined action of the polished surface and the second passivation layer 121, while ensuring a good passivation effect on the portion of the substrate 100 located in the second region 120, the thickness of the second intrinsic layer 104 can be effectively reduced, for example, to a thickness smaller than that of the first intrinsic layer 102 located on the first region 110 where no passivation layer is provided. This reduces the tunneling resistivity of photogenerated carriers in the thinner second intrinsic layer 104, thereby reducing the electron tunneling resistivity and reducing the parasitic absorption of light by the second intrinsic layer 104.

[0087] In some cases, the first doped layer 103 is doped with a P-type dopant, and the second doped layer 105 is doped with an N-type dopant. The photogenerated carriers transported through the first intrinsic layer 102 and the first doped layer 103 are holes, while the photogenerated carriers transported through the second intrinsic layer 104 and the second doped layer 105 are electrons. Generally, the tunneling resistivity of electrons in the second intrinsic layer 104 is lower than that of holes. Therefore, the reduction in the thickness of the second intrinsic layer 104 has a more limited effect on the reduction in the tunneling resistivity of electrons than the reduction in the thickness of the first intrinsic layer 102. Consequently, a thicker second intrinsic layer 104 is preferred to improve the passivation effect on the substrate 100.

[0088] In some examples, reference Figure 3Along the second direction Y, the ratio of the thickness of the second intrinsic layer 104 to the thickness of the first intrinsic layer 102 can be 1 / 2 to 7 / 8, for example, 1 / 2, 5 / 8, 3 / 4, or 7 / 8. It is worth noting that, with the combined effect of the polished surface and the second passivation layer 121, the thickness of the second intrinsic layer 104 can be reduced by at least 1 / 8 compared to the thickness of the first intrinsic layer 102 located on the first region 110 where no passivation layer is provided. This allows for a reduction in electron tunneling resistivity while simultaneously enhancing the passivation effect on the substrate 100 through the thicker second intrinsic layer 104.

[0089] In one example, refer to Figure 3 Along the second direction Y, the thickness of the first intrinsic layer 102 located on the first region 110 where no passivation layer is provided can be 6nm~8nm.

[0090] In one example, refer to Figure 3 Along the second direction Y, the thickness of the second intrinsic layer 104 on the second region 120, which has a second passivation layer 121 disposed between it and the substrate 100, can be 4nm to 7nm.

[0091] In the various embodiments described above, in conjunction with reference to the reference Figures 1 to 3 Without considering whether a passivation layer is provided between the second intrinsic layer 104 and the substrate 100, the thickness of the second intrinsic layer 104 can be 4nm to 8nm along the thickness direction of the substrate 100, i.e., in the second direction Y. For example, it can be 4nm, 4.1nm, 4.2nm, 4.3nm, 4.4nm, 4.5nm, 4.6nm, 4.7nm, 4.8nm, 4.9nm, 5nm, 5.1nm, 5.2nm, 5.3nm, etc. nm, 5.4nm, 5.5nm, 5.6nm, 5.7nm, 5.8nm, 5.9nm, 6nm, 6.1nm, 6.2nm, 6.3nm, 6.4nm, 6.5nm, 6.6nm, 6 .7nm, 6.8nm, 6.9nm, 7nm, 7.1nm, 7.2nm, 7.3nm, 7.4nm, 7.5nm, 7.6nm, 7.7nm, 7.8nm, 7.9nm or 8nm, etc.

[0092] In some embodiments, reference Figure 1 or Figure 2Along the thickness direction of the substrate 100, i.e., in the second direction Y, the thickness of the first intrinsic layer 102 can be less than the thickness of the second intrinsic layer 104. It is worth noting that, based on the presence of a first passivation layer 111 between the substrate 100 and the first intrinsic layer 102, regardless of whether a second passivation layer is provided between the substrate 100 and the second intrinsic layer 104, the thickness of the first intrinsic layer 102 can be designed to be less than the thickness of the second intrinsic layer 104 to effectively reduce the thickness of the first intrinsic layer 102, thereby significantly reducing the tunneling resistivity of holes in the first intrinsic layer 102. In contrast, reducing the thickness of the second intrinsic layer 104 has a less significant impact on reducing the electron tunneling resistivity; therefore, a thicker second intrinsic layer 104 can be used to enhance the passivation effect on the substrate 100. In other words, the thicknesses of the first intrinsic layer 102 and the second intrinsic layer 104 can be designed from different angles, both ultimately contributing to improving the photovoltaic cell's collection efficiency of photogenerated carriers.

[0093] In some embodiments, reference Figures 1 to 3 The passivation layer 101 can be intrinsic silicon oxide. It is worth noting that, for the same thickness, intrinsic silicon oxide provides superior passivation of the substrate 100 compared to other forms of silicon oxide. Therefore, designing the passivation layer 101 as intrinsic silicon oxide helps to further reduce the thickness of the first intrinsic layer 102 and / or the second intrinsic layer 104, thereby further reducing the tunneling resistivity of photogenerated carriers while ensuring that the passivation effect on the substrate 100 is not reduced.

[0094] In some embodiments, reference Figures 1 to 3 The crystalline state distribution inside the first doped layer 103 is a mixture of microcrystalline, nanocrystalline and amorphous states.

[0095] In some embodiments, reference Figures 1 to 3 The crystalline state distribution inside the second doped layer 105 is a mixture of microcrystalline, nanocrystalline, and amorphous states. It should be noted that the crystalline state distribution inside the first doped layer 103 and the second doped layer 105 can be the same or different.

[0096] In some cases, the first doped layer 103 and the second doped layer 105 can both be at least one of microcrystalline silicon, nanocrystalline silicon, and amorphous silicon. Both microcrystalline silicon and nanocrystalline silicon are small-sized grains. The difference between microcrystalline silicon and nanocrystalline silicon is that the grain size of microcrystalline silicon is between tens and hundreds of nanometers; the grain size of nanocrystalline silicon is typically less than 30 nanometers, mostly between 5 and 20 nanometers.

[0097] In some cases, due to the influence of the fabrication process of the first doped layer 103, the portion of the first doped layer 103 near the substrate 100 generally exhibits an amorphous state. Subsequently, as it gradually crystallizes and grows, the portion of the first doped layer 103 away from the substrate 100 gradually transforms from an amorphous state to a microcrystalline or nanocrystalline state. Similarly, the portion of the second doped layer 105 near the substrate 100 mainly exhibits an amorphous state. Subsequently, as it gradually crystallizes and grows, the portion of the second doped layer 105 away from the substrate 100 gradually transforms from an amorphous state to a microcrystalline or nanocrystalline state.

[0098] In some cases, refer to Figures 1 to 3 The crystallinity of the first doped layer 103 can be 50% to 65%, for example, it can be 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, 59%, 60%, 61%, 62%, 63%, 64% or 65%, etc.

[0099] In some cases, refer to Figures 1 to 3 The crystallinity of the second doped layer 105 can be 50% to 65%, for example, it can be 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, 59%, 60%, 61%, 62%, 63%, 64% or 65%, etc.

[0100] It should be noted that the crystallinity of the first doped layer 103 and the crystallinity of the second doped layer 105 can both be obtained by Raman spectroscopy. In Raman spectroscopy, the crystalline and amorphous portions of the first doped layer 103 or the second doped layer 105 will exhibit spectral peaks of different intensities. By observing the intensity of the spectral peaks in different regions of the first doped layer 103 or the second doped layer 105, the crystallinity of the first doped layer 103 or the second doped layer 105 can be estimated.

[0101] In some embodiments, reference Figures 1 to 3Along the second direction Y, the thickness of both the first doped layer 103 and the second doped layer 105 can be 22nm~27nm, for example, 22nm, 22.1nm, 22.2nm, 22.3nm, 22.4nm, 22.5nm, 22.6nm, 22.7nm, 22.8nm, 22.9nm, 23nm, 23.1nm, 23.2nm, 23.3nm, 23.4nm, 23.5nm, 23.6nm, 23.7nm, 23.8nm, 23.9nm, 24nm, 24.1nm, 24.2nm, 24.3nm, 24.4nm, 24.5nm, 24.6nm, 24.7nm, 24.8nm, 24.9nm, 25nm, 25.1nm, 25.2nm, 25.3nm, 25.4nm, 25.5nm, 25.6nm, 25.7nm, 25.8nm, 25.9nm, 26nm, 26.1nm, 26.2nm, 26.3nm, 26.4nm, 26.5nm, 26.6nm, 26.7nm, 26.8nm, 26.9nm, or 27nm, etc.

[0102] In some embodiments, reference Figure 4 , Figure 4 This is a fourth partial cross-sectional view of a photovoltaic cell provided in an embodiment of the present disclosure. The substrate 100 may include two opposing surfaces 100a along a second direction Y. One of the two surfaces 100a includes a first region 110 and a second region 120. The first direction X intersects the second direction Y, which is the thickness direction of the substrate 100. The substrate 100 may also include a side surface 100b connecting the two surfaces 100a. The photovoltaic cell may further include a side doped layer 106 located in at least a portion of the side surface 100b. The side doped layer 106 may include a first portion 116 and a second portion 126 stacked along the first direction X. The second portion 126 is located on the side of the first portion 116 away from the side surface 100b. The crystallinity of the second portion 126 is lower than that of the first portion 116. The crystallinity of the side doped layer 106 can also be obtained by Raman spectroscopy.

[0103] It is worth noting that the crystallinity of the second part 126 is lower than that of the first part 116. Therefore, the greater the disorder in the atomic structure of the second part 126, which is further away from the side 100b, the wider its optical bandgap becomes compared to that of the first part 116. Thus, as light incident on the side 100b passes sequentially through the second part 126 and the first part 116, the wider-bandgap second part 126 first absorbs the high-energy short-wavelength light, allowing the lower-energy long-wavelength light to pass through to the first part 116. The narrower-bandgap first part 116 then absorbs the transmitted long-wavelength light, thereby achieving segmented absorption of the solar spectrum and reducing energy loss caused by the bandgap limitation of a single material.

[0104] It should be noted that the side doped layer 106 can be the second doped layer that is deposited around the side 100b during the preparation of the second doped layer 105. Due to the difference in process position, the internal morphology of the second doped layer formed by the surrounding deposition is not the same as that of the second doped layer 105 formed on the surface 100a. Therefore, the second doped layer deposited around the side 100b is regarded as the side doped layer 106.

[0105] In practical applications, if the fabrication process also involves plating around the passivation layer, the first intrinsic layer, the first doped layer, and / or the second intrinsic layer, then during the fabrication of the passivation layer, the passivation layer plating around the side can be retained or removed; during the fabrication of the first intrinsic layer, the first intrinsic layer plating around the side can be retained or removed; during the fabrication of the first doped layer, the first doped layer plating around the side can also be retained or removed; and during the fabrication of the second intrinsic layer, the second intrinsic layer plating around the side can also be retained or removed.

[0106] In some embodiments, reference Figure 5 , Figure 5 This is a fifth partial cross-sectional view of a photovoltaic cell provided in an embodiment of the present disclosure. The photovoltaic cell may further include: a first transparent conductive layer 118 located on the side of the first doped layer 103 away from the substrate 100; and a second transparent conductive layer 128 located on the side of the second doped layer 105 away from the substrate 100.

[0107] In some embodiments, continue to refer to Figure 5 The photovoltaic cell may further include: a first electrode 119 located on the side of the first transparent conductive layer 118 away from the substrate 100; and a second electrode 129 located on the side of the second transparent conductive layer 128 away from the substrate 100.

[0108] In some embodiments, continue to refer to Figure 5The substrate 100 may include a first surface 1001 and a second surface 1002 opposite to each other along the second direction Y. The second surface 1002 is a polished surface. The first intrinsic layer 102 and the second intrinsic layer 104 are both located on the second surface 1002. The photovoltaic cell may also include: a third passivation layer 139 located on the first surface 1001; and an anti-reflection layer 149 located on the side of the third passivation layer 139 away from the substrate 100.

[0109] In some cases, refer to Figures 1 to 5 The first surface 1001 can be a velvety surface.

[0110] In summary, the polished surface design is beneficial to improving the thickness uniformity of both the first intrinsic layer 102 and the second intrinsic layer 104. Moreover, compared to the textured surface, the polished surface design can appropriately reduce the thickness of at least one of the first intrinsic layer 102 and the second intrinsic layer 104, which is beneficial to reducing the tunneling resistivity of photogenerated carriers in the thinner first intrinsic layer 102 and / or second intrinsic layer 104, thereby improving the collection efficiency of photovoltaic cells for photogenerated carriers. Furthermore, a passivation layer 101 is first disposed on at least one of the first region 110 and the second region 120, followed by a first intrinsic layer 102 and a first doped layer 103 and / or a second intrinsic layer 104 and a second doped layer 105. With the passivation effect of the passivation layer 101 on the substrate 100, the thickness of the first intrinsic layer 102 and / or the second intrinsic layer 104 can be further reduced. In other words, the combined effect of the polished surface and the passivation layer 101 is beneficial to significantly reduce the thickness of the first intrinsic layer 102 and / or the second intrinsic layer 104 while ensuring a good passivation effect on the substrate 100. This further reduces the tunneling resistivity of photogenerated carriers in the thinner first intrinsic layer 102 and / or the second intrinsic layer 104, thereby further improving the collection efficiency of photovoltaic cells for photogenerated carriers. Moreover, reducing the thickness of the first intrinsic layer 102 and / or the second intrinsic layer 104 helps to reduce their parasitic absorption of light, and the design of the polished surface helps to enhance the reflection of long-wavelength light from the polished surface, both of which help to improve the light absorption and utilization rate of photovoltaic cells.

[0111] Another embodiment of this disclosure provides a method for manufacturing a photovoltaic cell, used to form the photovoltaic cell provided in the foregoing embodiments. The method for manufacturing a photovoltaic cell according to another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0112] Reference Figures 1 to 14 , Figure 6 This is a process flow diagram of a method for manufacturing a photovoltaic cell according to another embodiment of the present disclosure. The method for manufacturing a photovoltaic cell includes at least the following steps:

[0113] S1: Reference Figure 7 , Figure 7 This is a partial cross-sectional view of a photovoltaic cell manufacturing method provided in another embodiment of the present disclosure after the formation of an initial passivation layer. A substrate 100 is provided, and a surface 100a of the substrate 100 is a polished surface. The surface 100a includes a first region 110 and a second region 120 arranged alternately along a first direction X.

[0114] S2: Continue to refer to Figure 7 An initial passivation layer 131 is formed on the polished surface.

[0115] S3: Reference Figure 8 or Figure 9 An initial intrinsic layer 112 and an initial doped layer 113 are sequentially formed on the side of the initial passivation layer 131 away from the substrate 100.

[0116] S4: Continue to refer to Figure 8 or Figure 9 A mask layer 107 is formed on the surface of the initial doped layer 113 located in the first region 110 or the second region 120 away from the substrate 100.

[0117] in, Figure 8 This is a partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in another embodiment of the present disclosure after the formation of a mask layer; Figure 9 This is another partial cross-sectional view of a photovoltaic cell manufacturing method provided in another embodiment of the present disclosure after the mask layer has been formed.

[0118] S5: Refer to Figure 8 and Figure 10 References Figure 8 and Figure 11 Or refer to Figure 9 and Figure 3 Patterning is performed using the initial passivation layer 131 as an etching barrier layer to remove the initial doped layer 113, the initial intrinsic layer 112, and the initial passivation layer 131 with at least a partial thickness that are not covered by the mask layer 107, while avoiding etching of the polished surface. The remaining initial passivation layer 131 is the passivation layer 101.

[0119] In some cases, in conjunction with reference Figure 8 and Figure 10 Or refer to Figure 8 and Figure 11 The mask layer 107 is located in the first region 110, the remaining initial intrinsic layer 112 is the first intrinsic layer 102, and the remaining initial doped layer 113 is the first doped layer 103; in conjunction with the reference Figure 10 and Figure 1 or in conjunction with references Figure 11 and Figure 2Then, a second intrinsic layer 104 and a second doped layer 105 are formed sequentially on the second region 120, and the mask layer 107 is removed.

[0120] Or, in other cases, in conjunction with references Figure 9 and Figure 3 The mask layer 107 is located in the second region 120, the remaining initial intrinsic layer 112 is the second intrinsic layer 104, the remaining initial doped layer 113 is the second doped layer 105, and then the first intrinsic layer 102 and the first doped layer 103 are formed sequentially on the first region 110 and the mask layer 107 is removed.

[0121] It should be noted that, Figure 10 This is a partial cross-sectional schematic diagram after graphical processing in a method for manufacturing a photovoltaic cell according to another embodiment of this disclosure; Figure 11 This is another partial cross-sectional view after graphical processing in a method for manufacturing a photovoltaic cell according to another embodiment of this disclosure. Furthermore, the following... Figure 8 The mask layer 107 shown is formed on the first region 110 as an example. A detailed explanation will be given of the formation of the second intrinsic layer 104 and the second doped layer 105, followed by the removal of the mask layer 107. In practical applications, Figure 9 The mask layer 107 shown is formed on the second region 120, and the corresponding formation is as follows: Figure 3 In the steps of forming the first intrinsic layer 102 and the first doped layer 103 and removing the mask layer 107, the method of forming the first intrinsic layer and the first doped layer can be similar to the method of forming the second intrinsic layer 104 and the second doped layer 105 described later. The difference is that the thickness of the first intrinsic layer and the second intrinsic layer formed is different, or the thickness of the first doped layer and the second doped layer formed or the type of doping element are different. Therefore, the same or corresponding parts will not be described again later.

[0122] It is worth noting that an initial passivation layer 131 can be formed on the entire surface of the polished surface first. When patterning the initial intrinsic layer 112 and the initial doped layer 113, whether the patterning process is used to form the first intrinsic layer 102 and the first doped layer 103 or the second intrinsic layer 104 and the second doped layer 105, the mask layer 107 can be used as a protective layer, and the initial passivation layer 131, which is not covered by the mask layer 107, can be used as an etching barrier layer to prevent the polished surface from being etched in the patterning process. This ensures that the first intrinsic layer 102 and the second intrinsic layer 104 are formed on the polished surface, and the passivation layer 101 is formed simultaneously. This allows for the formation of a passivation layer 101 between the first intrinsic layer 102 and the substrate 100 and / or between the second intrinsic layer 104 and the substrate 100 without additional fabrication steps. This simplifies the photovoltaic cell fabrication process by reducing the thickness of the first intrinsic layer 102 and / or the second intrinsic layer 104 through the combination of the polished surface and the passivation layer 101.

[0123] It is worth emphasizing that the design of forming an initial passivation layer 131 on the entire polished surface can not only effectively protect the polished surface not covered by the mask layer 107 during subsequent patterning processing, but also simultaneously form a passivation layer 101 that helps to reduce the thickness of the first intrinsic layer 102 and / or the second intrinsic layer 104. Compared with the technical solution of using additional mask technology to ensure that the morphology of the entire polished surface is not damaged, the photovoltaic cell manufacturing method provided in another embodiment of this disclosure not only eliminates the need for additional mask preparation processes to protect the polished surface during patterning processing, but also additionally forms a passivation layer 101 that is beneficial to the collection efficiency of photogenerated carriers in the photovoltaic cell. This not only simplifies the photovoltaic cell manufacturing process, but also facilitates the formation of a photovoltaic cell with better photoelectric conversion performance.

[0124] The following will describe in more detail, with reference to the accompanying drawings, the retention of the remaining initial passivation layer 131 after the graphical processing in step S5 of the photovoltaic cell manufacturing method provided in another embodiment of the present disclosure.

[0125] In some embodiments, in conjunction with reference Figure 8 and Figure 10The mask layer 107 is located in the first region 110. Further, in step S5, during the patterning process, not only are the initial doped layer 113 and initial intrinsic layer 112, which are not covered by the mask layer 107 and are located in the second region 120, removed, but also the entire thickness of the initial passivation layer 131 located in the second region 120 is removed. In other words, after the patterning process in step S5, the remaining initial passivation layer 131 is located only in the first region 110; that is, the remaining initial passivation layer 131 serving as passivation layer 101 is the first passivation layer 111 located in the first region 110.

[0126] In other embodiments, in conjunction with reference to Figure 8 and Figure 11 The mask layer 107 is located in the first region 110. Further, in step S5, during the patterning process, after removing the initial doped layer 113 and the initial intrinsic layer 112 located in the second region 120 (which are not covered by the mask layer 107), only a portion of the initial passivation layer 131 located in the second region 120 is removed. In other words, after the patterning process in step S5, the remaining initial passivation layer 131 is located not only in the first region 110 but also in the second region 120, and the remaining initial passivation layer 131 in the second region 120 is the film layer retained after the patterning process. Based on this, the final passivation layer 101 can include not only the first passivation layer 111 located in the first region 110 but also the second passivation layer 121 located in the second region 120.

[0127] In some cases, refer to Figure 11 or Figure 2 Along the thickness direction of the substrate 100, i.e., in the second direction Y, the thickness of the second passivation layer 121 can be less than the thickness of the first passivation layer 111. For example, the ratio of the thickness of the second passivation layer 121 to the thickness of the first passivation layer 111 can be less than or equal to 50%.

[0128] In yet other embodiments, in conjunction with reference to the reference Figure 9 and Figure 3 The mask layer 107 is located in the second region 120. Further, in the patterning process of step S5, not only are the initial doped layer 113 and the initial intrinsic layer 112, which are not covered by the mask layer 107 and are located in the first region 110, removed, but also the entire thickness of the initial passivation layer 131 located in the first region 110 is removed. In other words, after the patterning process in step S5, the remaining initial passivation layer 131 is located only in the second region 120; that is, the remaining initial passivation layer 131 serving as passivation layer 101 is the second passivation layer 121 located in the second region 120.

[0129] The following will describe in more detail the formation process of the initial passivation layer 131 in a photovoltaic cell manufacturing method provided by another embodiment of the present disclosure, with reference to the accompanying drawings.

[0130] In some embodiments, reference Figure 7 The initial passivation layer 131 can be intrinsic silicon oxide.

[0131] In some cases, when the material of the substrate 100 includes silicon, in the patterning step S5, a texturing solution can be used to etch the areas not covered by the mask layer 107. Generally, the reaction rate of the texturing solution with silicon is much greater than the reaction rate of the texturing solution with intrinsic silicon oxide. Based on this, the initial passivation layer 131 can be used as an etching barrier layer to prevent the polished surface from being etched in step S5.

[0132] The following example illustrates the formation process of the initial passivation layer 131 using the preparation of intrinsic silicon oxide as an example.

[0133] In some embodiments, reference Figure 7 The step of forming the initial passivation layer 131 may include: placing the substrate 100 in a reaction chamber, and introducing silane and carbon dioxide into the reaction chamber to deposit the initial passivation layer 131 on the polished surface; wherein the ratio of the gas flow rate of silane to the gas flow rate of carbon dioxide may be (1~3):1, for example, it may be 1:1, 1.5:1, 2:1, 2.5:1 or 3:1, etc.

[0134] It is worth noting that controlling the ratio of silane gas flow rate to carbon dioxide gas flow rate to (1~3):1 is more conducive to forming intrinsic silicon oxide with better density and passivation effect, i.e., the initial passivation layer 131. For example, the stoichiometric ratio of silicon to oxygen in the initial passivation layer 131 can be close to 1:2 or 1:2. The density or passivation effect of the initial passivation layer 131 is evaluated by testing the refractive index or porosity of the prepared initial passivation layer 131.

[0135] In some cases, when silane and carbon dioxide are introduced into the reaction chamber, the gas pressure in the reaction chamber can be controlled to be 0.2 Torr to 0.6 Torr, for example, 0.2 Torr, 0.25 Torr, 0.3 Torr, 0.35 Torr, 0.4 Torr, 0.45 Torr, 0.5 Torr, 0.55 Torr, or 0.6 Torr. This is beneficial for forming an initial passivation layer 131 with better uniformity and density under a low-pressure preparation environment.

[0136] In some cases, when silane and carbon dioxide are introduced into the reaction chamber, the coating power corresponding to the reaction chamber is controlled to be 100W~300W, for example, it can be 100W, 150W, 200W, 250W or 300W.

[0137] In some cases, when silane and carbon dioxide are introduced into the reaction chamber, the flow rate of the introduced carbon dioxide can be controlled to be 200 sccm to 500 sccm, for example, 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, 450 sccm or 500 sccm, etc.; the flow rate of the introduced silane can be controlled to be 400 sccm to 800 sccm, for example, 400 sccm, 450 sccm, 500 sccm, 550 sccm, 600 sccm, 650 sccm, 700 sccm, 750 sccm or 800 sccm, etc.

[0138] In some cases, when silane and carbon dioxide are introduced into the reaction chamber, the temperature inside the reaction chamber can be controlled between 160°C and 200°C, for example, it can be 160°C, 165°C, 170°C, 175°C, 180°C, 185°C, 190°C, 195°C or 200°C.

[0139] In some cases, the thickness of the initial passivation layer 131 along the second direction Y can be 1nm to 2nm, for example, it can be 1nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm or 2nm, etc.

[0140] In other embodiments, reference is made to... Figure 7 Alternatively, a thermal oxidation process can be used to form an initial passivation layer 131 on the polished surface. In this case, the material of the substrate 100 includes silicon. The substrate 100 is placed in an oxygen-rich atmosphere, and by increasing the ambient temperature, the substrate 100 is oxidized to form the initial passivation layer 131. The uniformity and density of the initial passivation layer 131 formed under this environment also meet the requirements.

[0141] In some embodiments, in conjunction with reference Figure 8 and Figure 10 References Figure 8 and Figure 11 or in conjunction with references Figure 9 and Figure 3 The substrate 100 may include a first surface 1001 and a second surface 1002 that are opposite to each other along the second direction Y. The second surface 1002 is a polished surface. The first direction X intersects with the second direction Y, and the second direction Y is the thickness direction of the substrate 100. In the step of patterning, the first surface 1001 is also etched so that the first surface 1001 is a textured surface.

[0142] It is worth noting that during the patterning process in step S5, the texturing process of the first surface 1001 and the patterning process of the second surface 1002 can be carried out simultaneously. Moreover, under the effect of the etching barrier of the initial passivation layer 131, the second surface 1002, which is the polished surface, can be avoided from being damaged. Thus, by taking advantage of the huge difference between the etching rate of the substrate 100 and the etching rate of the initial passivation layer 131 during the patterning process, the state of texturing one side and polishing the other side can be achieved at the same time. This is beneficial to further simplify the manufacturing process of photovoltaic cells and improve the photoelectric conversion efficiency of photovoltaic cells.

[0143] In some cases, refer to Figure 5 The manufacturing method of photovoltaic cells may further include: forming a third passivation layer 139 on a textured first surface 1001; and forming an antireflection layer 149 on the side of the third passivation layer 139 away from the substrate 100. It should be noted that the formation steps of the third passivation layer 139 and the antireflection layer 149 can be performed within the specified timeframes. Figure 10 or Figure 11 The formation of the first intrinsic layer 102 and the first doped layer 103, as shown, can be performed afterward, or it can be done subsequently based on... Figure 10 or Figure 11 The process is carried out after the formation of the second intrinsic layer and the second doped layer in the semi-finished battery shown.

[0144] In some embodiments, in conjunction with reference Figure 10 , Figures 12 to 14 With the mask layer 107 located in the first region 110, it is formed first. Figure 10 The first intrinsic layer 102 and the first doped layer 103 shown are examples, and the method for subsequently forming the third passivation layer, the antireflection layer, the second intrinsic layer and the second doped layer will be described in detail.

[0145] Reference Figure 10 and Figure 12 , Figure 12 This is a partial cross-sectional view of a photovoltaic cell manufacturing method provided in another embodiment of the present disclosure after the formation of an anti-reflection layer. A third passivation layer 139 is formed on a first surface 1001, and an anti-reflection layer 149 is formed on the side of the third passivation layer 139 away from the substrate 100.

[0146] Reference Figure 12 and Figure 13 , Figure 13 This is a partial cross-sectional view of a photovoltaic cell manufacturing method provided in another embodiment of the present disclosure after the formation of a doped film. A passivation film 114 is formed on the second surface 1002 after the formation of the first intrinsic layer 102, the first doped layer 103 and the mask layer 107. The passivation film 114 is located on both the first region 110 and the second region 120. A doped film 115 is formed on the side of the passivation film 114 away from the substrate 100.

[0147] Reference Figure 13 and Figure 14 , Figure 14 This is a partial cross-sectional view of a photovoltaic cell manufacturing method according to another embodiment of the present disclosure after the formation of the second doped layer. The passivation film 114 and the doped film 115 are patterned to remove the passivation film 114 and the doped film 115 located on the first region 110. Under the protection of the mask layer 107 on the first region 110, the first intrinsic layer 102 and the first doped layer 103 will not be etched in this patterning step, and the remaining passivation film 114 on the second region 120 is the second intrinsic layer 104, and the remaining doped film 115 on the second region 120 is the second doped layer 105. Further, after the formation of the second intrinsic layer 104 and the second doped layer 105, the mask layer 107 on the first region 110 is removed.

[0148] Reference Figure 14 and Figure 5 The manufacturing method of a photovoltaic cell may further include: forming a first transparent conductive layer 118 and a second transparent conductive layer 128, wherein the first transparent conductive layer 118 is located on the side of the first doped layer 103 away from the substrate 100, and the second transparent conductive layer 128 is located on the side of the second doped layer 105 away from the substrate 100; forming a first electrode 119 and a second electrode 129, wherein the first electrode 119 is located on the side of the first transparent conductive layer 118 away from the substrate 100, and the second electrode 129 is located on the side of the second transparent conductive layer 128 away from the substrate 100.

[0149] The following is a specific embodiment of a method for manufacturing a photovoltaic cell provided in another embodiment of this disclosure. Specifically, the photovoltaic cell is prepared through the following steps:

[0150] (1) Provide an N-type silicon wafer, such as an N-type monocrystalline silicon wafer, with a thickness of 90μm~130μm. Perform double-sided cleaning and double-sided polishing on the N-type silicon wafer to remove organic impurities from the surface of the N-type silicon wafer and form a double-sided polished structure, i.e., the substrate.

[0151] (2) Using PECVD (Plasma Enhanced Chemical Vapor Deposition) process, intrinsic silicon oxide, intrinsic amorphous silicon and boron-doped microcrystalline silicon are deposited on the back side of the N-type silicon wafer, or intrinsic silicon oxide, intrinsic amorphous silicon and boron-doped nanocrystalline silicon are deposited on the back side of the N-type silicon wafer to form the P region.

[0152] The process of depositing intrinsic silicon oxide, i.e. forming the initial passivation layer, includes: introducing carbon dioxide and silane, with the ratio of silane gas flow rate to carbon dioxide gas flow rate being (1~3):1, the gas pressure in the reaction chamber being 0.2 Torr~0.6 Torr, the thickness of the intrinsic silicon oxide being controlled at 1nm~2nm, the coating power corresponding to the reaction chamber being 100W~300W, the gas flow rate of introduced carbon dioxide being 200sccm~500sccm, the gas flow rate of introduced silane being 400sccm~800sccm, and the temperature in the reaction chamber being 160℃~200℃.

[0153] The process of depositing intrinsic amorphous silicon, i.e. forming the initial intrinsic layer, includes: introducing hydrogen and silane, with the ratio of hydrogen gas flow rate to silane gas flow rate being (1~4):1, the gas pressure in the reaction chamber being 0.4 Torr~0.6 Torr, the thickness of the intrinsic amorphous silicon being controlled at 2nm~4nm, the corresponding deposition power in the reaction chamber being 300W~400W, the hydrogen gas flow rate being 1000sccm~5000sccm, the silane gas flow rate being 500sccm~2000sccm, and the temperature in the reaction chamber being 180℃~210℃.

[0154] The process of forming the initial doped layer by plating boron-doped microcrystalline silicon or boron-doped nanocrystalline silicon includes: introducing hydrogen, silane, carbon dioxide, and borane. The ratio of the gas flow rate of hydrogen to that of silane can be (280~350):1. The gas pressure in the reaction chamber is 3 Torr~4 Torr. The thickness of the boron-doped microcrystalline silicon or boron-doped nanocrystalline silicon is controlled at 22nm~27nm. The coating power corresponding to the reaction chamber is 5000W~7000W. The gas flow rate of hydrogen is 10000sccm~24000sccm, the gas flow rate of silane is 50sccm~100sccm, the gas flow rate of carbon dioxide is 10sccm~40sccm, the gas flow rate of borane is 20sccm~100sccm, and the temperature in the reaction chamber is 140℃~180℃.

[0155] (3) Forming an initial mask layer, wherein the material of the initial mask layer may include at least one of silicon nitride, silicon oxynitride, silicon oxide, or amorphous silicon.

[0156] (4) The initial mask layer is patterned by laser, and the initial mask layer is locally etched by laser to form a mask layer on the surface of the initial doped layer in the first region or the second region away from the substrate. The laser can be an ultraviolet laser or a green laser, and the laser pulse is less than 50 ns.

[0157] (5) The semi-finished battery formed after step (4) is patterned. Specifically, the semi-finished battery is placed in a texturing tank and texturized with an alkaline sodium hydroxide solution to form a pyramidal textured structure on the front side. The areas of the semi-finished battery that are not laser-treated, i.e., the areas forming the mask layer, are protected from alkaline corrosion by the mask layer. During texturing, the laser-treated areas of the semi-finished battery are etched by alkaline corrosion of microcrystalline and amorphous silicon, and finally the etching stops after reaching silicon oxide. The battery structure with a textured front side and a polished back side is achieved by utilizing the difference in reaction rates between alkali and silicon and silicon oxide. The alkaline concentration of the sodium hydroxide solution is 40%~45%, and the patterning time is 300s~500s.

[0158] (6) Deposit a third passivation layer and an antireflection layer on the front side of the N-type silicon wafer. Specifically, intrinsic amorphous silicon and silicon nitride are deposited on the front side using a PECVD process.

[0159] The process of depositing intrinsic amorphous silicon, i.e. forming the third passivation layer, includes: introducing hydrogen and silane, with the ratio of hydrogen gas flow rate to silane gas flow rate being (1~3):1, the gas pressure in the reaction chamber being 0.4 Torr~0.6 Torr, the thickness of the intrinsic amorphous silicon being controlled at 6nm~8nm, the coating power corresponding to the reaction chamber being 100W~400W, the hydrogen gas flow rate being 1000sccm~5000sccm, the silane gas flow rate being 500sccm~1000sccm, and the temperature in the reaction chamber being 180℃~210℃.

[0160] The process of depositing silicon nitride, i.e. forming an antireflective layer, includes: introducing ammonia gas and silane, with the ammonia gas flow rate being 5000 sccm~8000 sccm and the silane gas flow rate being 2000 sccm~4000 sccm, the temperature in the reaction chamber being 150℃~220℃, the corresponding deposition power in the reaction chamber being 2000W~50500W, the gas pressure in the reaction chamber being 1 Torr~1.5 Torr, the silicon nitride deposition process duration being 500s~700s, and the silicon nitride thickness being controlled at 75nm~90nm.

[0161] (7) The back of the semi-finished battery formed after step (6) is plated with intrinsic amorphous silicon and phosphorus-doped microcrystalline silicon, or with intrinsic amorphous silicon and phosphorus-doped nanocrystalline silicon, to form an N-region.

[0162] The process of depositing intrinsic amorphous silicon, i.e. forming a passivation film, includes: introducing hydrogen gas and silane, with the ratio of hydrogen gas flow rate to silane gas flow rate being (1~2):1; the gas pressure in the reaction chamber being 0.4 Torr~0.6 Torr; the thickness of the intrinsic amorphous silicon being controlled at 6nm~8nm; the deposition power corresponding to the reaction chamber being 100W~400W; the flow rate of the introduced hydrogen gas being 1000sccm~2000sccm; the flow rate of the introduced silane gas being 500sccm~1000sccm; and the temperature in the reaction chamber being 180℃~210℃.

[0163] The process of forming a doped film by plating phosphorus-doped microcrystalline silicon or phosphorus-doped nanocrystalline silicon includes: introducing hydrogen and silane, or carbon dioxide and phosphine into the back side, with the ratio of hydrogen gas flow rate to silane gas flow rate being (250~320):1; the gas pressure in the reaction chamber being 4 Torr~6 Torr; the thickness of the intrinsic amorphous silicon being controlled at 22nm~27nm; the plating power corresponding to the reaction chamber being 3000W~6000W; the gas flow rate of the introduced hydrogen being 10000sccm~18000sccm; the gas flow rate of the introduced silane being 50sccm~80sccm; the gas flow rate of the introduced carbon dioxide being 30sccm~80sccm; the gas flow rate of the introduced phosphine being 200sccm~500sccm; and the temperature in the reaction chamber being 170℃~200℃.

[0164] (8) Laser etching is used to etch the P-region, followed by cleaning. Specifically, an ultraviolet laser or a green laser is used with a laser pulse of less than 50 ns to remove the passivation film and doped film located in the P-region; then, hydrofluoric acid is used to clean and remove the mask layer on the P-region and the passivation film and doped film remaining after laser etching.

[0165] (9) An initial transparent conductive layer is formed on the back side of the semi-finished battery formed after step (8). Specifically, the initial transparent conductive layer is prepared by PVD (Physical Vapor Deposition) or RPD (Reactive Plasma Deposition) process. The material of the initial transparent conductive layer may include at least one of VTTO (Indium Tin Oxide) or ITO (Vanadium-doped Tin Oxide).

[0166] (10) Backside laser isolation: Using an ultraviolet laser or a green laser, laser grooving is performed on the edge of the N region near the P region to divide the remaining initial transparent conductive layer into a first transparent conductive layer and a second transparent conductive layer, and to isolate the first doped layer and the second doped layer. The laser pulse is less than 50 ns. Furthermore, the laser parameters can be controlled to avoid laser damage to the first intrinsic layer and the second intrinsic layer.

[0167] (11) Screen printing and metallization processes are performed sequentially to form the first electrode and the second electrode. Specifically, the metallization process can be low-temperature curing at 210°C to finally form an ohmic contact between the first electrode and the first transparent conductive layer, and an ohmic contact between the second electrode and the second transparent conductive layer.

[0168] Another embodiment of this disclosure provides a photovoltaic module, including a plurality of photovoltaic cells provided in the foregoing embodiments, or including a plurality of photovoltaic cells formed by the manufacturing method of the photovoltaic cells provided in the foregoing embodiments. The photovoltaic module provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0169] Reference Figures 1 to 5 ,as well as Figure 15 and Figure 16 The photovoltaic module may include: a battery string, which is formed by connecting multiple photovoltaic cells 40 provided in the foregoing embodiments, or by connecting multiple photovoltaic cells 40 formed by the manufacturing method of photovoltaic cells provided in the foregoing embodiments; an encapsulating film 41 for covering the surface of the battery string; and a cover plate 42 for covering the surface of the encapsulating film 41 facing away from the battery string.

[0170] in, Figure 15 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in yet another embodiment of this disclosure; Figure 16 This is a partial cross-sectional schematic diagram of a photovoltaic module provided in yet another embodiment of the present disclosure.

[0171] In some embodiments, the photovoltaic cell 40 is a BC cell, which includes, but is not limited to, IBC cells (Interdigitated Back Contact), HBC cells (Heterojunction Back Contact), TBC cells (TOPCon Back Contact), or HTBC cells (Hybrid Passivated Back Contact).

[0172] It should be noted that multiple photovoltaic cells 40 can be electrically connected to each other via solder strips 43. Figure 15 and Figure 16 The illustration only shows one positional relationship between the photovoltaic cells 40, where the sides of each photovoltaic cell 40 with the first electrode 119 and the second electrode 129 are arranged facing the same side, so that the solder ribbon 43 connects the same side of two adjacent photovoltaic cells 40 respectively. In other embodiments, the photovoltaic cells may also be arranged such that the sides of two adjacent photovoltaic cells with electrodes are located on different sides, in which case the solder ribbon connects the different sides of two adjacent photovoltaic cells.

[0173] In some embodiments, the photovoltaic cells 40 are electrically connected in the form of a single cell or multiple segments to form multiple cell strings, and the multiple cell strings are electrically connected in series and / or parallel. The photovoltaic cells 40 can be a single cell or a sliced ​​cell, where a sliced ​​cell refers to a cell formed by cutting a complete single cell.

[0174] In some embodiments, the encapsulating film 41 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the photovoltaic cell 40, and the second encapsulating layer covers the other of the front or back sides of the photovoltaic cell 40. Specifically, at least one of the first or second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. Alternatively, at least one of the first or second encapsulating layer can also be an EP film, an EPE film, or a PVP film. Here, EP film refers to a co-extruded film composed of stacked EVA film and POE film; EPE film refers to a co-extruded film formed by sequentially stacking EVA film + POE film + EVA film; and PVP film refers to a co-extruded film formed by stacking POE film + EVA film + POE film. Co-extruded films can be prepared by sequentially extruding one or more raw materials onto another pre-made film during the film processing, or by bonding different types of pre-made films together.

[0175] In some cases, the first encapsulation layer and the second encapsulation layer still have a boundary line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0176] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 42 facing the encapsulating film 41 can be an uneven surface or a textured surface containing multiple raised structures, thereby increasing the utilization rate of incident light. The cover plate 42 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer, and the second cover plate being opposite to the second encapsulation layer.

[0177] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A photovoltaic cell, characterized in that, include: The substrate includes two opposing surfaces along a second direction, one of the two surfaces being a polished surface and including a first region and a second region alternately arranged along a first direction, the first direction intersecting the second direction, the second direction being the thickness direction of the substrate; A passivation layer is located on at least one of the first region and the second region; A first intrinsic layer and a first doped layer, wherein the first intrinsic layer is located on the first region and the first doped layer is located on the side of the first intrinsic layer away from the substrate; The second intrinsic layer and the second doped layer are located on the second region and the second doped layer is located on the side of the second intrinsic layer away from the substrate. The second doped layer and the first doped layer are doped with different types of doping elements. Wherein, the passivation layer is located between the first intrinsic layer and the substrate, and / or, the passivation layer is located between the second intrinsic layer and the substrate; A side-doped layer is located in at least a portion of the side surface; the side-doped layer includes a first part and a second part stacked along the first direction, the second part being located on the side of the first part away from the side surface; wherein the crystallinity of the second part is lower than that of the first part.

2. The photovoltaic cell according to claim 1, characterized in that, The passivation layer includes a first passivation layer located on the first region.

3. The photovoltaic cell according to claim 2, characterized in that, Along the thickness direction of the substrate, the thickness of the first intrinsic layer is 2nm~4nm.

4. The photovoltaic cell according to claim 1 or 2, characterized in that, The passivation layer includes a second passivation layer located on the second region.

5. The photovoltaic cell according to claim 4, characterized in that, The passivation layer includes a second passivation layer and a first passivation layer located on the first region; wherein, along the thickness direction of the substrate, the ratio of the thickness of the second passivation layer to the thickness of the first passivation layer is less than or equal to 50%.

6. The photovoltaic cell according to claim 1, characterized in that, Along the thickness direction of the substrate, the thickness of the second intrinsic layer is 4 nm to 8 nm.

7. The photovoltaic cell according to claim 1, characterized in that, Along the thickness direction of the substrate, the thickness of the first intrinsic layer is less than the thickness of the second intrinsic layer.

8. The photovoltaic cell according to claim 1, characterized in that, The passivation layer is intrinsic silicon oxide.

9. The photovoltaic cell according to claim 1, characterized in that, The crystalline state distribution inside the first doped layer is a mixture of microcrystalline, nanocrystalline, and amorphous states; and / or, the crystalline state distribution inside the second doped layer is a mixture of microcrystalline, nanocrystalline, and amorphous states.

10. The photovoltaic cell according to claim 9, characterized in that, The crystallinity of the first doped layer is 50% to 65%; and / or the crystallinity of the second doped layer is 50% to 65%.

11. A method for manufacturing a photovoltaic cell, characterized in that, include: A substrate is provided, one surface of which is a polished surface, and the surface includes a first region and a second region that are alternately arranged along a first direction; An initial passivation layer is formed on the polished surface; An initial intrinsic layer and an initial doped layer are sequentially formed on the side of the initial passivation layer away from the substrate; A mask layer is formed on the surface of the initial doped layer located in the first region or the second region away from the substrate; Patterning is performed using the initial passivation layer as an etching barrier layer to remove the initial doped layer, the initial intrinsic layer, and at least a portion of the initial passivation layer that are not covered by the mask layer, while preventing the polished surface from being etched. The remaining initial passivation layer is then used as a passivation layer. Wherein, the mask layer is located in the first region, the remaining initial intrinsic layer is the first intrinsic layer, the remaining initial doped layer is the first doped layer, and then a second intrinsic layer and a second doped layer are sequentially formed on the second region and the mask layer is removed; or, the mask layer is located in the second region, the remaining initial intrinsic layer is the second intrinsic layer, the remaining initial doped layer is the second doped layer, and then a first intrinsic layer and a first doped layer are sequentially formed on the first region and the mask layer is removed.

12. The method for manufacturing a photovoltaic cell according to claim 11, characterized in that, The step of forming the initial passivation layer includes: placing the substrate in a reaction chamber, and introducing silane and carbon dioxide into the reaction chamber to deposit the initial passivation layer on the polished surface; The ratio of the gas flow rate of silane to the gas flow rate of carbon dioxide is (1~3):

1.

13. The method for manufacturing a photovoltaic cell according to claim 11, characterized in that, The initial passivation layer is formed on the polished surface using a thermal oxidation process.

14. The method for manufacturing a photovoltaic cell according to claim 11, characterized in that, The substrate includes a first surface and a second surface opposite to each other along a second direction, the second surface being the polished surface, the first direction intersecting the second direction, and the second direction being the thickness direction of the substrate; In the step of performing the graphic processing, the first surface is also etched to make the first surface have a textured surface.

15. A photovoltaic module, characterized in that, include: A battery string is formed by connecting multiple photovoltaic cells as described in any one of claims 1 to 10, or by connecting multiple photovoltaic cells formed by the manufacturing method of photovoltaic cells as described in any one of claims 11 to 14; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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