A method for hybrid bonding chemical mechanical polishing and semiconductor wafer

Abstract

The chemical mechanical polishing method for hybrid bonding of the present application firstly performs first polishing on the surface of the wafer on the first polishing disc until the copper layer on the surface of the medium layer of the wafer is removed. Then the copper pillar in the medium layer of the wafer is secondly polished on the first polishing disc, the surface of the copper pillar is controlled to be lower than the surface of the medium layer, and the first height difference d1 between the surface of the copper pillar and the surface of the medium layer is between 500 angstrom and 1500 angstrom. Finally, the medium layer of the wafer is thirdly polished on the second polishing disc, the surface of the copper pillar in the medium layer is controlled to be lower than the surface of the medium layer, the second height difference d2 between the surface of the copper pillar and the surface of the medium layer is between 30 angstrom and 50 angstrom, and the ratio of the second polishing time t2 of the second polishing to the third polishing time t3 of the third polishing is between 1:1 and 1.5:1. The chemical mechanical polishing method for hybrid bonding of the present application can effectively control the recess degree of the copper pillar relative to the medium layer by optimizing the over-polishing time of the first polishing disc and the polishing time of the second polishing disc, and the recess degree of the copper pillar relative to the medium layer is controlled within the nanometer level.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a chemical mechanical polishing method for hybrid bonding and a semiconductor wafer. Background Technology

[0002] In modern semiconductor manufacturing, Cu-Cu hybrid bonding technology is widely used due to its superior electrical and mechanical properties. This technology achieves efficient interconnection between chips by directly bonding copper layers to each other, forming a high-density interconnect structure. However, high-quality bonding interfaces are crucial for the success of this bonding technology. The flatness and uniformity of the bonding interface directly affect the bonding strength and signal transmission integrity, thus determining the overall performance and reliability of the chip. To achieve high-quality bonding interfaces, both the copper and dielectric layers must undergo highly planarization. Chemical mechanical polishing (CMP), as an advanced surface treatment process, plays a vital role in this process. CMP removes excess material and achieves surface planarization through a combination of chemical reactions and mechanical action. In Cu-Cu hybrid bonding, the planarization of the copper and dielectric layers is particularly important. Planarization of the copper layer ensures good contact between the copper pillars during bonding, while planarization of the dielectric layer helps reduce unevenness and void formation at the bonding interface. By precisely controlling various parameters in the CMP process, such as the composition of the polishing slurry, the pressure and rotation speed of the polishing head, high-quality planarization of the copper layer and dielectric layer can be achieved.

[0003] However, during CMP (Continuous Metal Processing), there is a significant difference in removal rates between the copper pillars and the dielectric layer. The copper removal rate is typically higher than that of the dielectric layer, leading to a tendency for copper surfaces to become concave during polishing, while the dielectric layer may experience erosion. Copper concavity refers to the excessive removal of the copper surface relative to the dielectric layer during polishing, creating a recessed area below the dielectric layer surface. This concavity not only affects the flatness of the bonding interface but can also lead to voids in subsequent bonding processes. These voids reduce bond strength, affecting the integrity and reliability of signal transmission, thus negatively impacting the overall performance of the chip.

[0004] Traditional CMP processes have limitations in controlling copper pitting. While the surface finish of copper can be improved by adjusting polishing parameters (such as the composition of the polishing slurry, the pressure and rotation speed of the polishing head), it is difficult to effectively control the size of copper pits while maintaining a smooth surface. This is especially true in Cu-Cu mixed bonding, where the flatness requirements of the bonding interface are extremely stringent; even the slightest unevenness can lead to bonding failure. Therefore, traditional CMP processes often struggle to achieve the required precision and consistency when dealing with differences in removal rates between copper pillars and dielectric layers. Summary of the Invention

[0005] In view of the problems existing in the prior art described above, this application provides a chemical mechanical polishing method and semiconductor wafer for hybrid bonding, which can effectively control the size of the copper pillars in Cu-Cu hybrid bonding, thereby improving the bonding yield and bonding strength.

[0006] To achieve the above and other related objectives, the present invention provides a chemical mechanical polishing method for hybrid bonding, comprising the following steps:

[0007] The surface of the wafer is first polished on the first polishing pad until the copper layer on the surface of the dielectric layer of the wafer is removed;

[0008] The copper pillars in the dielectric layer of the wafer are polished a second time on the first polishing pad, and the surface of the copper pillars is controlled to be lower than the surface of the dielectric layer, and the first height difference d1 between the surface of the copper pillars and the surface of the dielectric layer is between 500 Å and 1500 Å.

[0009] The dielectric layer of the wafer is polished a third time on the second polishing pad. The surface of the copper pillar in the dielectric layer is controlled to be lower than the surface of the dielectric layer, and the second height difference d2 between the surface of the copper pillar and the surface of the dielectric layer is between 30 Å and 50 Å. The ratio of the second polishing time t2 for the second polishing to the third polishing time t3 for the third polishing is between 1:1 and 1.5:1.

[0010] Optionally, the dielectric layer is TEOS or SiCN.

[0011] Optionally, the first height difference d1 between the copper pillar surface and the dielectric layer surface is between 800 Å and 1200 Å, and the second height difference d2 between the copper pillar surface and the dielectric layer surface is between 40 Å and 50 Å.

[0012] Optionally, the grinding rate of the wafer surface on the first polishing pad and the grinding rate of the copper pillars in the dielectric layer of the wafer on the first polishing pad are both between 7000 Å / min and 9000 Å / min; the grinding rate of the dielectric layer of the wafer on the second polishing pad is between 500 Å / min and 1500 Å / min.

[0013] Optionally, the flow rate of the polishing fluid is between 250 ml / min and 300 ml / min during the first, second, and third polishing processes.

[0014] Optionally, the ratio of the removal rate of the dielectric layer to the removal rate of the copper pillar on the second polishing pad is between 1.5:1 and 2.5:1.

[0015] Optionally, the first polishing disc corresponds to the first polishing head, and the second polishing disc corresponds to the second polishing head. The pressure of the first polishing head and the second polishing head are both 1 Psi - 3 Psi, and the rotation speed is both 75 r / min ~ 100 r / min.

[0016] Optionally, the second polishing time t2 is between 90 s and 150 s, and the third polishing time t3 is between 60 s and 150 s.

[0017] Optionally, the first polishing pad uses a hard polishing pad, and the second polishing pad uses a soft polishing pad. The polishing fluid used in both the first and second polishing pads is SiO2 abrasive, and the particle diameter of the SiO2 abrasive is between 40 nm and 100 nm.

[0018] In another aspect, the present invention provides a semiconductor wafer obtained by applying the chemical mechanical polishing method for hybrid bonding described above.

[0019] As described above, the chemical mechanical polishing method for hybrid bonding provided by the present invention has at least the following beneficial technical effects:

[0020] The chemical mechanical polishing method for hybrid bonding of the present invention first polishes the surface of the wafer on a first polishing pad until the copper layer on the surface of the dielectric layer of the wafer is removed. Then, a second polishing is performed on the copper pillars in the dielectric layer of the wafer on the first polishing pad, controlling the surface of the copper pillars to be lower than the surface of the dielectric layer and the first height difference d1 between the copper pillar surface and the dielectric layer surface to be between 500 Å and 1500 Å. Finally, a third polishing is performed on the dielectric layer of the wafer on a second polishing pad, controlling the surface of the copper pillars in the dielectric layer to be lower than the surface of the dielectric layer and the second height difference d2 between the copper pillar surface and the dielectric layer surface to be between 30 Å and 50 Å. The ratio of the second polishing time t2 for the second polishing to the third polishing time t3 for the third polishing is between 1:1 and 1.5:1.

[0021] The chemical mechanical polishing method for hybrid bonding of the present invention effectively controls the degree of concavity of the copper pillars relative to the dielectric layer by optimizing the overpolishing time of the first polishing pad and the polishing time of the second polishing pad, keeping the concavity within the nanometer range. Furthermore, it reduces and precisely controls the concavity of the copper pillars, significantly increasing the contact area of ​​hybrid bonding, reducing void formation, and thus improving bonding yield and bonding strength. In addition, by adjusting the combination of overpolishing time and polishing time, this method can flexibly adapt to different chip designs and bonding requirements, exhibiting high process flexibility. Attached Figure Description

[0022] Figure 1 The flowchart shown is a chemical mechanical polishing method for hybrid bonding provided in an embodiment of the present invention.

[0023] Figure 2 The diagram shown is a schematic diagram of a wafer before the first polishing provided in an embodiment of the present invention.

[0024] Figure 3 The diagram shows a wafer after the first polishing, as provided in an embodiment of the present invention.

[0025] Figure 4 The diagram shows a wafer after a second polishing, as provided in an embodiment of the present invention.

[0026] Figure 5 The diagram shows a wafer after a third polishing, as provided in an embodiment of the present invention.

[0027] Figure Labels

[0028] 1. Dielectric layer; 2. Substrate; 3. Copper pillar; 4. Copper layer. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0031] Example 1

[0032] This embodiment provides a chemical mechanical polishing method for mixed bonding, referring to... Figures 1 to 5 This includes the following steps:

[0033] S100: The surface of the wafer is first polished on the first polishing pad until the copper layer on the surface of the dielectric layer of the wafer is removed;

[0034] Reference Figure 2 and Figure 3In semiconductor manufacturing, a copper layer 4 is typically coated on the surface of the dielectric layer 1 of a wafer. If the copper layer 4 is not completely removed during hybrid bonding, voids may appear at the bonding interface. These voids reduce bonding strength, affecting the integrity and reliability of signal transmission. Furthermore, the presence of the copper layer 4 leads to insufficient flatness at the bonding interface, further reducing bonding strength. Insufficient bonding strength increases the risk of chip failure during use. Therefore, in this step, the wafer surface is first polished on a first polishing pad until the copper layer 4 on the surface of the dielectric layer 1 is removed. The purpose of this step is to remove excess copper layer 4 from the wafer surface, fully exposing the copper pillars 3, preparing for subsequent fine polishing. The first polishing pad uses a hard polishing pad, and the polishing fluid used is SiO2 abrasive with a particle diameter between 40 nm and 100 nm. This particle size range effectively removes the copper layer 4 while avoiding excessive damage to the dielectric layer 1. In this embodiment, the dielectric layer 1 is TEOS (tetraethoxysilane) or SiCN (silicon carbonitride). The first polishing pad corresponds to a first polishing head, which has a pressure of 1 Psi-3 Psi and a rotation speed of 75 r / min to 100 r / min. The grinding rate on the wafer surface on the first polishing pad is between 7000 Å / min and 9000 Å / min. This rate range effectively removes the copper layer while avoiding surface damage caused by over-polishing. During the first polishing, the flow rate of the polishing slurry is between 250 ml / min and 300 ml / min. This flow rate range ensures uniform distribution of the polishing slurry and improves the polishing effect. In an optional embodiment of this example, the grinding rate on the wafer surface on the first polishing pad is 8000 Å / min. This rate exhibits good polishing effect in practical applications and can effectively balance the removal rate and surface quality.

[0035] S200: The copper pillars in the dielectric layer of the wafer are polished a second time on the first polishing pad, and the surface of the copper pillars is controlled to be lower than the surface of the dielectric layer and the first height difference d1 between the surface of the copper pillars and the surface of the dielectric layer is between 500 Å and 1500 Å.

[0036] Specifically, refer to Figure 4The copper pillars 3 in the dielectric layer 1 of the wafer are then further polished on the first polishing pad. The surface of the copper pillars 3 is controlled to be lower than the surface of the dielectric layer 1, and the first height difference d1 between the surfaces of the copper pillars 3 and the dielectric layer 1 is between 500 Å and 1500 Å. This polishing pad is equipped with a hard polishing pad. This step, by controlling the overpolishing time, creates a certain depression on the surface of the copper pillars 3 relative to the surface of the dielectric layer 1, thus initially controlling the degree of depression of the copper pillars 3. In this embodiment, the first polishing pad corresponds to a first polishing head, with a pressure of 1 Psi - 3 Psi and a rotation speed of 75 r / min to 100 r / min. This rotation speed range ensures the uniformity and efficiency of the polishing process while avoiding surface damage caused by excessive rotation speed. The second polishing time t2 for the second polishing is between 90 s and 150 s. By precisely controlling the polishing time, the degree of depression of the copper pillars 3 relative to the surface of the dielectric layer 1 can be effectively controlled, initially forming the desired depression of the copper pillars 3 relative to the dielectric layer 1. The first height difference d1 between the surface of the copper pillar 3 and the surface of the dielectric layer 1 is between 800 Å and 1200 Å. In an optional embodiment of this example, the first height difference d1 between the surface of the copper pillar 3 and the surface of the dielectric layer 1 is 1000 Å. The grinding rate of the copper pillar 3 in the dielectric layer 1 of the wafer on the first polishing pad is between 7000 Å / min and 9000 Å / min. In an optional embodiment of this example, the grinding rate of the copper pillar 3 in the dielectric layer 1 of the wafer on the first polishing pad is 8000 Å / min. During the second polishing, the flow rate of the polishing fluid is between 250 ml / min and 300 ml / min. This flow rate range ensures uniform distribution of the polishing fluid and improves the polishing effect. Specifically, the polishing process involves first placing the wafer on the first polishing pad to ensure close contact between the wafer surface and the hard polishing pad. Then, the pressure of the first polishing head is adjusted to 1 Psi to 3 Psi to ensure the uniformity and efficiency of the polishing process. The rotation speed of the first polishing head was adjusted to 75 r / min to 100 r / min to ensure the uniformity and efficiency of the polishing process. Next, the polishing slurry supply system was started, ensuring the flow rate of the polishing slurry was between 250 ml / min and 300 ml / min. The polishing slurry used SiO2 abrasive with a particle diameter between 40 nm and 100 nm. Then, the second polishing process began, controlling the polishing time t2 to be between 90 s and 150 s. Through real-time monitoring and adjustment, the first height difference d1 between the surface of the copper pillar 3 and the surface of the dielectric layer 1 was ensured to be between 500 Å and 1500 Å, and the grinding rate was ensured to be between 7000 Å / min and 9000 Å / min. During the polishing process, the height difference d1 between the surface of the copper pillar 3 and the surface of the dielectric layer 1 was monitored in real time to ensure it remained within the predetermined range. Based on the monitoring results, the polishing time t2 and the flow rate of the polishing slurry were adjusted as needed to ensure the uniformity and efficiency of the polishing process. The polishing process was stopped after the predetermined polishing time t2 was reached.Clean the wafer surface to remove residual polishing fluid and copper particles. Finally, check the height difference d1 between the surface of copper pillar 3 and the surface of dielectric layer 1 to ensure it is within the predetermined range.

[0037] S300: The dielectric layer of the wafer is polished for the third time on the second polishing pad, wherein the surface of the copper pillar in the dielectric layer is lower than the surface of the dielectric layer and the second height difference d2 between the surface of the copper pillar and the surface of the dielectric layer is between 30 Å and 50 Å, and the ratio of the second polishing time t2 for the second polishing to the third polishing time t3 for the third polishing is between 1:1 and 1.5:1.

[0038] Specifically, refer to Figure 5 A third polishing process is performed on the dielectric layer 1 of the wafer on a second polishing pad. The surface of the copper pillars 3 in the dielectric layer 1 is controlled to be lower than the surface of the dielectric layer 1, and the second height difference d2 between the surface of the copper pillars 3 and the surface of the dielectric layer 1 is controlled to be between 30 Å and 50 Å. This step further precisely controls the degree of indentation of the copper pillars 3 by adjusting the composition of the polishing slurry and the polishing time, ensuring that the final indentation of the copper pillars 3 is within an acceptable range. A soft polishing pad is used on the second polishing pad to reduce damage to the dielectric layer 1. The polishing slurry used on the second polishing pad is SiO2 abrasive, and the particle diameter of the SiO2 abrasive is between 40 nm and 100 nm. In this embodiment, the second polishing pad corresponds to a second polishing head, with a pressure of 1 Psi - 3 Psi and a rotation speed of 75 r / min to 100 r / min. The third polishing time t3 is between 60 s and 150 s. By precisely controlling the polishing time, the degree of indentation of the surface of the copper pillars 3 relative to the surface of the dielectric layer 1 can be further precisely controlled. The ratio of the second polishing time t2 for the second polishing to the third polishing time t3 for the third polishing is between 1:1 and 1.5:1. This time ratio ensures precise control over the degree of indentation of the copper pillar 3 during the second and third polishing processes. The grinding rate of the dielectric layer 1 of the wafer on the second polishing pad is between 500 Å / min and 1500 Å / min. In an optional embodiment of this example, the grinding rate of the dielectric layer 1 of the wafer on the second polishing pad is 1000 Å / min. The ratio of the removal rate of the dielectric layer 1 to the removal rate of the copper pillar 3 on the second polishing pad is between 1.5:1 and 2.5:1. During the third polishing, the flow rate of the polishing fluid is between 250 ml / min and 300 ml / min. In an optional embodiment of this example, the second height difference d2 between the surface of the copper pillar 3 and the surface of the dielectric layer 1 is 42 Å, the second polishing time t2 for the second polishing is 90 s, and the third polishing time t2 for the third polishing is 60 s.

[0039] The chemical mechanical polishing (CMP) method for hybrid bonding of this invention optimizes the over-polishing time of the first polishing pad and the polishing time of the second polishing pad. This method effectively controls the degree of concavity of the copper pillar 3 relative to the dielectric layer 1, keeping the concavity within the nanometer range. Furthermore, it reduces and precisely controls the concavity of the copper pillar 3, significantly increasing the contact area of ​​hybrid bonding, reducing void formation, and thus improving bonding yield and bonding strength. In addition, by adjusting the combination of over-polishing time and polishing time, this method can flexibly adapt to different chip designs and bonding requirements, exhibiting high process flexibility. This CMP method for hybrid bonding is based on existing dual-pad CMP equipment, is easy to implement on a production line, and requires no additional hardware investment.

[0040] Example 2

[0041] This embodiment provides a semiconductor wafer obtained using the chemical mechanical polishing method for hybrid bonding described in Embodiment 1. (Refer to...) Figure 5 The semiconductor wafer includes a substrate 2, a dielectric layer 1, and copper pillars 3 embedded in the dielectric layer 1. After chemical mechanical polishing, a precisely controlled second height difference d2 is formed between the surface of the copper pillars 3 and the surface of the dielectric layer 1. The second height difference d2 is controlled within the range of 30 Å to 50 Å, achieving nanometer-level interface flatness. Because the depression of the copper pillars 3 is precisely controlled within the aforementioned extremely small range, the bonding interface of this semiconductor wafer has extremely high flatness and uniformity. This enables the wafer to achieve the maximum effective contact area when performing Cu-Cu hybrid bonding with another wafer, significantly reducing voids and defects at the bonding interface, thereby improving the yield and reliability of Cu-Cu hybrid bonding.

[0042] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A chemical mechanical polishing method for mixed bonding, characterized in that, Includes the following steps: The surface of the wafer is first polished on the first polishing pad until the copper layer on the surface of the dielectric layer of the wafer is removed; The copper pillars in the dielectric layer of the wafer are polished a second time on the first polishing pad, and the surface of the copper pillars is controlled to be lower than the surface of the dielectric layer, and the first height difference d1 between the surface of the copper pillars and the surface of the dielectric layer is between 500 Å and 1500 Å. The dielectric layer of the wafer is polished a third time on the second polishing pad, wherein the surface of the copper pillar in the dielectric layer is lower than the surface of the dielectric layer and the second height difference d2 between the surface of the copper pillar and the surface of the dielectric layer is between 30 Å and 50 Å, and the ratio of the second polishing time t2 for the second polishing to the third polishing time t3 for the third polishing is between 1:1 and 1.5:

1.

2. The chemical mechanical polishing method for hybrid bonding according to claim 1, characterized in that, The dielectric layer is TEOS or SiCN.

3. The chemical mechanical polishing method for hybrid bonding according to claim 2, characterized in that, The first height difference d1 between the surface of the copper pillar and the surface of the dielectric layer is between 800 Å and 1200 Å, and the second height difference d2 between the surface of the copper pillar and the surface of the dielectric layer is between 40 Å and 50 Å.

4. The chemical mechanical polishing method for hybrid bonding according to claim 1, characterized in that, The grinding rate of the wafer surface on the first polishing pad and the grinding rate of the copper pillars in the dielectric layer of the wafer on the first polishing pad are both between 7000 Å / min and 9000 Å / min; the grinding rate of the dielectric layer of the wafer on the second polishing pad is between 500 Å / min and 1500 Å / min.

5. The chemical mechanical polishing method for hybrid bonding according to claim 1, characterized in that, During the first polishing, the second polishing, and the third polishing, the flow rate of the polishing fluid is between 250 ml / min and 300 ml / min.

6. The chemical mechanical polishing method for hybrid bonding according to claim 1, characterized in that, The ratio of the removal rate of the dielectric layer to the removal rate of the copper pillar on the second polishing pad is between 1.5:1 and 2.5:

1.

7. The chemical mechanical polishing method for hybrid bonding according to claim 1, characterized in that, The first polishing disc corresponds to a first polishing head, and the second polishing disc corresponds to a second polishing head. The pressure of the first polishing head and the second polishing head are both 1 Psi - 3 Psi, and the rotation speed is both 75 r / min ~ 100 r / min.

8. The chemical mechanical polishing method for hybrid bonding according to claim 1, characterized in that, The second polishing time t2 is between 90 s and 150 s, and the third polishing time t3 is between 60 s and 150 s.

9. The chemical mechanical polishing method for hybrid bonding according to claim 1, characterized in that, The first polishing pad uses a hard polishing pad, and the second polishing pad uses a soft polishing pad. The polishing liquid used in both the first and second polishing pads is SiO2 abrasive, and the particle diameter of the SiO2 abrasive is between 40 nm and 100 nm.

10. A semiconductor wafer, characterized in that, Obtained by applying the chemical mechanical polishing method for hybrid bonding as described in any one of claims 1 to 9.

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