Charging pile national standard protocol control guidance switching method

Abstract

The invention discloses a charging pile national standard protocol control guidance switching method, which comprises a control guidance switching circuit, and the control guidance switching circuit comprises a first output circuit, a second output circuit, a third switching circuit, a CC detection circuit and a vehicle end CC signal input circuit. The first output circuit and the second output circuit are connected in parallel on a third switching circuit, and the third switching circuit accesses a signal into a vehicle end CC signal input circuit and transmits the signal into a CC detection circuit for signal detection. According to the invention, the first output circuit or the second output circuit is connected into the vehicle end CC signal input circuit through the third switching signal, and the output signals of the first output circuit and the second output circuit are respectively switched by using the first switching signal or the second switching signal, so that switching and intercommunication of three protocols are realized.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of protocol switching, and particularly relates to a charging pile national standard protocol control guide switching method. BACKGROUND

[0002] With the rapid development of the electric vehicle industry, the supporting charging facilities are also continuously improved. After years of development, the charging protocol of the national standard charging pile has developed from the charging protocol published in 2015, namely, the 2015 national standard charging protocol, to the 2015+ national standard charging protocol and the ChaoJi charging protocol, and the three charging protocols are not compatible with each other, which causes the existing charging facilities to be unable to achieve unified charging standards. SUMMARY

[0003] The application aims to provide a charging pile national standard protocol control guide switching method, which can realize the intercommunication of the three standards and perfectly solve the problem of incompatible charging of the three charging protocols on the market.

[0004] The application provides the following technical scheme: a charging pile national standard protocol control guide switching method, comprising a control guide switching circuit, wherein the control guide switching circuit comprises a first output circuit, a second output circuit, a third switching circuit, a CC detection circuit and a vehicle end CC signal input circuit, the first output circuit and the second output circuit are connected in parallel on the third switching circuit, the third switching circuit is connected to the vehicle end CC signal input circuit to input signals into the CC detection circuit for signal detection.

[0005] The first output circuit is a 2015+ national standard charging protocol output circuit, comprising a first switching circuit, a pull-up resistor and two 2015+ national standard protocol resistors.

[0006] The second output circuit is a ChaoJi national standard charging protocol output circuit, comprising a second switching circuit, a pull-up resistor, a 2015 national standard protocol resistor and a ChaoJi national standard protocol resistor, the second switching circuit is connected in parallel on the ChaoJi national standard protocol resistor, when the second switching circuit is disconnected, a ChaoJi charging protocol signal is output, and when the second switching circuit is closed, a 2015 national standard charging protocol signal is output.

[0007] The third switching circuit is a double-pole double-throw switch control circuit, the first output circuit and the second output circuit are connected to the input end of the double-pole double-throw switch control circuit, and the output end of the double-pole double-throw switch control circuit is connected to the CC detection circuit.

[0008] Further, the first output circuit comprises a first switching circuit composed of a triode and a PMOS tube, a current-limiting resistor, a pull-down resistor, a pull-up resistor, a filter capacitor and two 2015+ national standard protocol resistors.

[0009] The first output circuit is controlled by a first switching signal. Two 2015+ national standard protocol resistors are connected. The other end of the 2015+ national standard protocol resistor is connected to the third switching circuit. The current-limiting resistor is connected to the side of the transistor. The upper end of the transistor is connected to a pull-up resistor and a PMOS transistor, and the lower end is connected to a pull-down resistor and a filter capacitor. The other end of the pull-down resistor is connected to the other end of the current-limiting resistor. The other end of the filter capacitor is connected to the upper end of the transistor and the PMOS transistor. The two ends of the PMOS transistor are connected to the two ends of the 2015+ national standard protocol resistor.

[0010] Furthermore, the second output circuit includes a switching circuit composed of transistors and PMOS transistors, a current limiting resistor, a pull-down resistor, a pull-up resistor, a filter capacitor, a 2015 national standard protocol resistor, and a ChaoJi national standard protocol resistor.

[0011] The second output circuit is controlled by the second switching signal. The 2015 / ChaoJi national standard protocol resistor and the ChaoJi national standard protocol resistor are connected. The other end of the ChaoJi national standard protocol resistor is connected to the third switching circuit. The current limiting resistor is connected to the side of the transistor. The upper end of the transistor is connected to a pull-up resistor and a PMOS transistor, and the lower end is connected to a pull-down resistor and a filter capacitor. The other end of the pull-down resistor is connected to the other end of the current limiting resistor. The other end of the filter capacitor is connected to the upper end of the transistor and the PMOS transistor. The two ends of the PMOS transistor are connected to the two ends of the ChaoJi national standard protocol resistor.

[0012] Furthermore, the third switching circuit includes a double-pole double-throw relay, a current-limiting resistor, a pull-down resistor, a filter capacitor, an NMOS transistor, and a relay coil freewheeling diode;

[0013] The current-limiting resistor is connected to the gate (G) terminal of the NMOS transistor. A pull-down resistor and a filter capacitor are connected to the source (S) terminal of the NMOS transistor. The other end of the pull-down resistor is connected to the gate (G) terminal of the NMOS transistor. The other end of the filter capacitor is connected to the drain (D) terminal of the NMOS transistor. A relay coil freewheeling diode and a double-pole double-throw relay are also connected to the drain (D) terminal of the NMOS transistor.

[0014] Furthermore, the double-pole double-throw relay includes two output terminals connected to the CC signal input, two input terminals connected to the first output circuit, and two input terminals connected to the second output circuit.

[0015] Furthermore, the first switching signal, the second switching signal, and the third switching signal are all controlled by the MCU chip.

[0016] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: the first switching signal controls the normal or abnormal charging state of the first output circuit and outputs the 2015+ charging protocol signal at the same time; the second switching signal controls the output of the 2015 charging protocol signal and the ChaoJi charging protocol signal of the second output circuit; and finally, the third switching signal controls the activation or reset of the relay to transmit the signal to the vehicle-end CC signal input circuit, and the CC detection circuit detects the signal, thereby switching the three protocols. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0018] Figure 1 This is an application block diagram for switching national standard protocols provided by the present invention;

[0019] Figure 2 This is a block diagram of the first output circuit of the present invention;

[0020] Figure 3 This is a block diagram of the second output circuit of the present invention;

[0021] Figure 4 This is a block diagram of the third switching circuit of the present invention;

[0022] Figure 5 This is a schematic diagram of a national standard protocol control and guidance switching circuit for charging piles according to the present invention.

[0023] In the diagram: 100 is the first output circuit; 200 is the second output circuit; 300 is the third switching circuit; 1 is the first switching signal; 2 is the second switching signal; 3 is the third switching signal; R4, R10, and R8 are current-limiting resistors; R5, R12, and R11 are pull-down resistors; Q2 and Q5 are NPN transistors; Q1 and Q4 are PMOS transistors; Q3 is an NMOS transistor; C1, C2, and C3 are filter capacitors; R1 and R6 are pull-up resistors; R2 and R3 are 2015+ national standard protocol resistors; R7 is a 2015 / ChaoJi national standard protocol resistor; R9 is a ChaoJi national standard protocol resistor; K1 is a double-pole double-throw relay; D1 is a freewheeling diode. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Please see Figures 1 to 4 The present invention provides a technical solution: a national standard protocol control and guidance switching method for charging piles, including a control and guidance switching circuit. The control and guidance switching circuit includes a first output circuit 100, a second output circuit 200, a third switching circuit 300, a CC detection circuit, and a vehicle-end CC signal input circuit. The first output circuit 100 and the second output circuit 200 are connected in parallel on the third switching circuit 300. The third switching circuit 300 inputs the signal to the vehicle-end CC signal input circuit and sends the signal to the CC detection circuit for signal detection.

[0026] like Figure 2 As shown, the first output circuit 100 is a 2015+ national standard charging protocol output circuit, including a first switching circuit, a pull-up resistor and a 2015+ national standard protocol resistor. The first switching circuit is controlled by the first switching signal 1 so that the first output circuit 100 outputs a 2015+ international protocol signal.

[0027] like Figure 3 As shown, the second output circuit 200 is a ChaoJi national standard charging protocol output circuit, including a second switch circuit, a pull-up resistor, a 2015 national standard protocol resistor and a ChaoJi national standard protocol resistor. The second switch circuit is connected in parallel with the ChaoJi national standard protocol resistor. When the second switch circuit is open, it outputs a ChaoJi charging protocol signal, and when it is closed, it outputs a 2015 national standard charging protocol signal.

[0028] like Figure 4 As shown, the third switching circuit 300 is a double-pole double-throw switch control circuit. The first output circuit and the second output circuit are both connected to the input terminal of the double-pole double-throw switch control circuit. The output terminal of the double-pole double-throw switch control circuit is connected to the CC detection circuit. The double-pole double-throw switch control circuit is adjusted by the third switching signal 3, and the first output circuit 100 or the second output circuit 200 is connected to the CC signal input circuit to detect the signal.

[0029] like Figure 5 As shown, the first output circuit includes a first switching circuit composed of transistor Q2 and PMOS transistor Q1, current limiting resistor R4, pull-down resistor R5, pull-up resistor R1, filter capacitor C1, 2015+ national standard protocol resistor R2 and 2015+ national standard protocol resistor R3.

[0030] The first output circuit 100 is controlled by the first switching signal 1. Resistors R2 and R3 (2015+ GB / T 1) are connected. The other end of resistor R3 is connected to the third switching circuit 300. A current-limiting resistor R4 is connected to the side of transistor Q2. The upper end of transistor Q2 is connected to pull-up resistor R1 and PMOS transistor Q1, while the lower end is connected to pull-down resistor R5 and filter capacitor C1. The other end of pull-down resistor R5 is connected to the other end of current-limiting resistor R4. The other end of filter capacitor C1 is connected to the upper end of transistor Q2 and PMOS transistor Q1. The two ends of PMOS transistor Q1 are connected to resistor R2 (2015+ GB / T 1). When the first switching signal 1 is high, NPN transistor Q2 is in amplification mode, and the gate (G) terminal of PMOS transistor Q1 drops from high level to low level due to the pull-up resistor R1. The voltage across the gate (GS) terminals is less than zero and lower than the gate threshold voltage, so PMOS transistor Q1 is turned on. At this time, the circuit is on, the charging pile is working normally, and it outputs a normal operation signal of the 2015+ national standard protocol. When the first switching signal 1 is low, NPN transistor Q2 is in cutoff mode. Since the gate (G) terminal of PMOS transistor Q1 is high level due to the pull-up resistor R1, the gate (GS) terminals of PMOS transistor Q1 are at the same level and are in disconnected mode. The charging pile enters an abnormal state and outputs an abnormal operation signal of the 2015+ national standard protocol.

[0031] The second output circuit includes a switching circuit composed of transistor Q5 and PMOS transistor Q4, current limiting resistor R10, pull-down resistor R12, pull-up resistor R6, filter capacitor C3, 2015 national standard protocol resistor R7 and ChaoJi national standard protocol resistor R9.

[0032] The second output circuit 200 is controlled by the second switching signal 2. Resistors R7 and R9 are connected. The other end of resistor R9 is connected to the third switching circuit 300. A current-limiting resistor R10 is connected to the side of transistor Q5. The upper end of transistor Q5 is connected to a pull-up resistor R6 and a PMOS transistor Q4, while the lower end is connected to a pull-down resistor R12 and a filter capacitor C3. The other end of pull-down resistor R12 is connected to the other end of current-limiting resistor R10. The other end of filter capacitor C3 is connected to the upper end of transistor Q5 and the PMOS transistor Q4. When MOSFET Q4 is connected, and the two ends of PMOS transistor Q4 are connected to the two ends of ChaoJi national standard protocol resistor R9, when the second switching signal 2 is high, NPN transistor Q5 is in the amplification state, and the gate terminal of PMOS transistor Q4, which was pulled up by pull-up resistor R6, drops from a high level to a low level. The voltage across GS is less than zero and lower than the gate threshold voltage, so PMOS transistor Q4 is turned on. When the second switching signal 2 is low, NPN transistor Q5 is in the cutoff state, and the gate terminal of PMOS transistor Q4, which was pulled up by pull-up resistor R6, is at a high level. The voltage across GS of PMOS transistor Q4 is the same, so it is in the off state.

[0033] The third switching circuit includes a double-pole double-throw relay K1, a current-limiting resistor R8, a pull-down resistor R11, a filter capacitor C2, an NMOS transistor Q3, and a relay coil freewheeling diode D1.

[0034] A current-limiting resistor R8 is connected to the gate (G) terminal of NMOS transistor Q3. A pull-down resistor R11 and a filter capacitor C2 are connected to the source (S) terminal of NMOS transistor Q3. The other end of the pull-down resistor R11 is connected to the gate (G) terminal of NMOS transistor Q3, and the other end of the filter capacitor C2 is connected to the drain (D) terminal of NMOS transistor Q3. A relay coil freewheeling diode D1 and a double-pole double-throw relay K1 are also connected to the drain (D) terminal of NMOS transistor Q3. When the third switching signal 3 is high, the voltage at the gate (GS) terminal is high and higher than the gate voltage, the NMOS transistor is turned on, the relay is energized, and contacts 8 and 9 are connected to contacts 4 and 5. When the third switching signal 3 is low, the NMOS transistor is turned off, the relay is in the reset state, and contacts 9 and 10 are connected to contacts 3 and 4.

[0035] The double-pole double-throw relay K1 includes two output terminals connected to the CC signal input, two input terminals connected to the first output circuit 100, and two input terminals connected to the second output circuit 200.

[0036] The first switching signal 1, the second switching signal 2, and the third switching signal 3 are all controlled by the MCU chip.

[0037] Switching process: When the first switching signal 1 is high, NPN transistor Q2 is in amplification mode, and the gate terminal of PMOS transistor Q1 drops from the high level of pull-up resistor R1 to the low level. The voltage across the gate and GS terminals is less than zero and lower than the gate threshold voltage, so PMOS transistor Q1 is turned on. When the third switching signal 3 is high, the voltage across the gate and GS terminals is high and higher than the gate voltage, so NMOS transistor is turned on, relay is energized, and contacts 8 and 9 are connected to contacts 4 and 5. At this time, the 2015+ charging protocol normal operation status signal is output.

[0038] When the first switching signal 1 is low, NPN transistor Q2 is in the off state. The gate of PMOS transistor Q1 is high due to the pull-up resistor R1, and the gate and gate of PMOS transistor are in the same state and are disconnected. When the third switching signal 3 is high, the voltage at the gate and gate is high and higher than the gate voltage, the NMOS transistor is turned on, the relay is energized, and contacts 8 and 9 are connected with contacts 4 and 5. At this time, the 2015+ charging protocol abnormal working status signal is output.

[0039] When the second switching signal 2 is high, NPN transistor Q5 is in amplification mode, and the gate (G) terminal of PMOS transistor Q4, pulled up by pull-up resistor R6, drops from a high level to a low level. The voltage across gate and gate (GS) is less than zero and lower than the gate threshold voltage, so PMOS transistor Q4 is turned on. When the third switching signal 3 is low, NMOS transistor is turned off, relay is in reset mode, and contacts 9 and 10 are connected to contacts 3 and 4. At this time, the 2015 charging protocol signal is output.

[0040] When the second switching signal 2 is low, the NPN transistor Q5 is in the off state, and the gate terminal of the PMOS transistor Q4 is pulled up to a high level by the pull-up resistor R6. The gate and gate terminals of the PMOS transistor are at the same level and are in the off state. When the third switching signal 3 is low, the MOS transistor is disconnected, the relay is in the reset state, and contacts 9 and 10 are connected to 3 and 4. At this time, the ChaoJi charging protocol signal is output.

[0041] In summary, the present invention provides a national standard protocol control guidance switching method for charging piles, which realizes the switching of national standard protocol control guidance through a first output circuit 100, a second output circuit 200, and a third switching circuit 300, thereby meeting the uniformity of national charging pile standard design.

[0042] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for control and guidance switching of a national standard protocol for charging piles, comprising a control and guidance switching circuit, characterized in that: The control guidance switching circuit includes a first output circuit (100), a second output circuit (200), a third switching circuit (300), a CC detection circuit, and a vehicle-end CC signal input circuit. The first output circuit (100) and the second output circuit (200) are connected in parallel on the third switching circuit (300). The third switching circuit (300) inputs the signal into the vehicle-end CC signal input circuit and sends the signal into the CC detection circuit for signal detection. The first output circuit (100) is a 2015+ national standard charging protocol output circuit, including a first switch circuit, a pull-up resistor and a 2015+ national standard protocol resistor; The second output circuit (200) is a ChaoJi national standard charging protocol output circuit, including a second switch circuit, a pull-up resistor, a 2015 national standard protocol resistor and a ChaoJi national standard protocol resistor. The second switch circuit is connected in parallel with the ChaoJi national standard protocol resistor. When the second switch circuit is open, it outputs the ChaoJi charging protocol signal. When it is closed, it outputs the 2015 national standard charging protocol signal. The third switching circuit (300) is a double-pole double-throw switch control circuit. The first output circuit and the second output circuit are both connected to the input terminal of the double-pole double-throw switch control circuit. The output terminal of the double-pole double-throw switch control circuit is connected to the CC detection circuit.

2. The charging pile full compliance with national standard protocol control and guidance switching method according to claim 1, characterized in that: The first output circuit includes a first switching circuit composed of a transistor (Q2) and a PMOS transistor (Q1), a current limiting resistor (R4), a pull-down resistor (R5), a pull-up resistor (R1), a filter capacitor (C1), a 2015+ national standard protocol resistor (R2), and a 2015+ national standard protocol resistor (R3). The first output circuit (100) is controlled by the first switching signal (1). The 2015+ GB standard protocol resistor (R2) and the 2015+ GB standard protocol resistor (R3) are connected. The other end of the 2015+ GB standard protocol resistor (R3) is connected to the third switching circuit (300). The current limiting resistor (R4) is connected to the side of the transistor (Q2). The upper end of the transistor (Q2) is connected to the pull-up resistor (R1) and the PMOS transistor (Q1). The lower end is connected to the pull-down resistor (R5) and the filter capacitor (C1). The other end of the pull-down resistor (R5) is connected to the other end of the current limiting resistor (R4). The other end of the filter capacitor (C1) is connected to the upper end of the transistor (Q2) and the PMOS transistor (Q1). The two ends of the PMOS transistor (Q1) are connected to the two ends of the 2015+ GB standard protocol resistor (R3).

3. The charging pile full compliance with national standard protocol control and guidance switching method according to claim 1, characterized in that: The second output circuit includes a switching circuit composed of a transistor (Q5) and a PMOS transistor (Q4), a current limiting resistor (R10), a pull-down resistor (R12), a pull-up resistor (R6), a filter capacitor (C3), a 2015 national standard protocol resistor (R7), and a ChaoJi national standard protocol resistor (R9). The second output circuit (200) is controlled by the second switching signal (2). The 2015 / ChaoJi national standard protocol resistor (R7) and the ChaoJi national standard protocol resistor (R9) are connected. The other end of the ChaoJi national standard protocol resistor (R9) is connected to the third switching circuit (300). The current limiting resistor (R10) is connected to the side of the transistor (Q5). The upper end of the transistor (Q5) is connected to the pull-up resistor (R6) and the PMOS transistor (Q4), and the lower end is connected to the pull-down resistor (R12) and the filter capacitor (C3). The other end of the pull-down resistor (R12) is connected to the other end of the current limiting resistor (R10). The other end of the filter capacitor (C3) is connected to the upper end of the transistor (Q5) and the PMOS transistor (Q4). The two ends of the PMOS transistor (Q4) are connected to the two ends of the ChaoJi national standard protocol resistor (R9).

4. The charging pile full compliance with national standard protocol control and guidance switching method according to claim 1, characterized in that: The third switching circuit includes a double-pole double-throw relay (K1), a current-limiting resistor (R8), a pull-down resistor (R11), a filter capacitor (C2), an NMOS transistor (Q3), and a relay coil freewheeling diode (D1). The current-limiting resistor (R8) is connected to the gate (G) terminal of the NMOS transistor (Q3). A pull-down resistor (R11) and a filter capacitor (C2) are connected to the source (S) terminal of the NMOS transistor (Q3). The other end of the pull-down resistor (R11) is connected to the gate (G) terminal of the NMOS transistor (Q3). The other end of the filter capacitor (C2) is connected to the drain (D) terminal of the NMOS transistor (Q3). A relay coil freewheeling diode (D1) and a double-pole double-throw relay (K1) are also connected to the drain (D) terminal of the NMOS transistor (Q3).

5. The charging pile full compliance with national standard protocol control and guidance switching method according to claim 4, characterized in that: The double-pole double-throw relay (K1) includes two output terminals connected to the CC signal input, two input terminals connected to the first output circuit (100), and two input terminals connected to the second output circuit (200).

6. A method for controlling and guiding the switching of a charging pile that fully complies with national standard protocols, as described in any one of claims 2 to 4, characterized in that: The first switching signal (1), the second switching signal (2) and the third switching signal (3) are all controlled by the MCU chip.

Images