Topography-aware optical proximity correction method, device, storage medium and electronic equipment

Abstract

The application discloses a topography-aware optical proximity correction method and device, a storage medium and an electronic device. The topography-aware optical proximity correction method comprises the following steps: obtaining an original design layout; performing CMP simulation on the original design layout to generate wafer topography data; constructing a coupled optical model based on an EUV three-dimensional mask model and the wafer topography data; decomposing the layout of the design layout according to multi-graphic patterning process rules to obtain at least two mask layout; and performing collaborative topography-aware optical proximity correction on the at least two mask layout by using the coupled optical model to obtain at least two corrected mask layout; wherein when the current mask layout is corrected, the optical proximity environment used includes historical mask correction results generated based on the coupled optical model. The application can improve the imaging accuracy of advanced process nodes.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a shape-sensing optical proximity effect correction method, apparatus, storage medium, and electronic device. Background Technology

[0002] As integrated circuit manufacturing processes continue to advance to 3 nanometers and below, extreme ultraviolet (EUV) lithography has become a core method for achieving critical layer patterning. However, EUV lithography uses absorber masks with three-dimensional structures, and the resulting shadowing effect causes angle-dependent attenuation and phase shift of the incident light, leading to positional deviations and changes in critical dimensions. Meanwhile, after processes such as chemical mechanical polishing (CMP), the wafer surface is not an ideal plane but exhibits nanometer-scale local morphological undulations. These undulations are equivalent to spatial defocusing, further distorting the image. Furthermore, to overcome the limitations of single-exposure resolution, multiple patterning processes are widely adopted, decomposing a single design pattern onto multiple masks for sequential exposure. This results in complex optical interactions between patterns on different masks.

[0003] Currently, the Topography-aware Optical Proximity Correction (TOPC) method has been used to address the defocusing effect caused by wafer topography variations. It integrates wafer thickness distribution data obtained from CMP simulations to spatially modulate the defocusing parameters in the lithography imaging model, thereby pre-compensating for imaging deviations caused by topography changes.

[0004] However, the current TOPC method employs a fragmented and non-cooperative correction paradigm, which neither couples the EUV 3D mask shadow effect with wafer local topography defocusing, nor models the optical interactions between masks in multiple patterning, resulting in systematic integrated imaging errors at advanced process nodes. Summary of the Invention

[0005] This application provides a shape-sensing optical proximity effect correction method, apparatus, storage medium, and electronic device, which can improve the imaging accuracy of advanced process nodes.

[0006] In a first aspect, embodiments of this application provide a method for correcting the optical proximity effect of shape perception, including:

[0007] Obtain the original design layout;

[0008] CMP simulation was performed on the original design layout to generate wafer topography data;

[0009] A coupled optical model is constructed based on the EUV three-dimensional mask model and the wafer topography data;

[0010] The design layout is decomposed according to multiple graphical process rules to obtain at least two mask layouts.

[0011] The coupled optical model is used to perform cooperative topography-aware optical proximity effect correction on at least two mask patterns to obtain at least two corrected mask patterns; wherein, when correcting the current mask pattern, the optical proximity environment used includes historical mask correction results generated based on the coupled optical model.

[0012] In the topography-aware optical proximity effect correction method provided in this application embodiment, the construction of a coupled optical model based on the EUV three-dimensional mask model and the wafer topography data includes:

[0013] The wafer morphology data is mapped to a spatially varying defocus distribution;

[0014] The defocus distribution and the shadow effect characterized by the EUV three-dimensional mask model are integrated into the lithographic imaging model to form a coupled optical model.

[0015] In the morphology-sensing optical proximity effect correction method provided in this application embodiment, mapping the wafer morphology data into a spatially varying defocus distribution includes:

[0016] Based on the wafer morphology data, the resist thickness in each region of the wafer surface is determined;

[0017] Based on the relationship between the resist thickness and the defocusing amount, a corresponding defocusing amount value is assigned to each region;

[0018] Based on the defocus value, defocus marker layer data for optical simulation is generated to form a spatially varying defocus distribution.

[0019] In the shape-aware optical proximity effect correction method provided in this application embodiment, the step of using the coupled optical model to perform cooperative shape-aware optical proximity effect correction on at least two mask patterns to obtain at least two corrected mask patterns includes:

[0020] The first mask pattern is updated by performing topography-aware optical proximity correction.

[0021] Based on the coupled optical model, the updated first mask pattern is simulated as the first printed pattern under the wafer topography data;

[0022] The first printed pattern is incorporated into the optical proximity environment, and the second mask pattern is corrected for the optical proximity effect by shape perception in order to update the second mask pattern.

[0023] The shape-sensing optical proximity effect correction method provided in this application embodiment further includes:

[0024] Determine whether the updated first mask layout and the second mask layout converge;

[0025] If not, then based on the updated second mask layout, the updated first mask layout is optimized in reverse until the updated first mask layout and the second mask layout converge.

[0026] In the shape-aware optical proximity effect correction method provided in this application embodiment, the step of reverse-optimizing the updated first mask pattern based on the updated second mask pattern until the updated first mask pattern and the second mask pattern converge includes:

[0027] Based on the coupled optical model, the updated second mask pattern is simulated as a second printed pattern under the wafer topography data;

[0028] The second printed pattern is incorporated into the optical proximity environment, and the step of performing shape-aware optical proximity effect correction on the first mask pattern to update the first mask pattern is performed until the updated first mask pattern and the second mask pattern converge.

[0029] In the shape-sensing optical proximity effect correction method provided in this application embodiment, the EUV three-dimensional mask model is a simplified analytical shadow model.

[0030] Secondly, embodiments of this application provide a shape-sensing optical proximity effect correction device, comprising:

[0031] The acquisition unit is used to acquire the original design layout;

[0032] The simulation unit is used to perform CMP simulation on the original design layout and generate wafer topography data.

[0033] The construction unit is used to construct a coupled optical model based on the EUV three-dimensional mask model and the wafer topography data;

[0034] The decomposition unit is used to decompose the design layout according to multiple graphical process rules to obtain at least two mask layouts.

[0035] The correction unit is used to perform cooperative topography-aware optical proximity effect correction on at least two of the mask patterns using the coupled optical model to obtain at least two corrected mask patterns; wherein, when correcting the current mask pattern, the optical proximity environment used includes historical mask correction results generated based on the coupled optical model.

[0036] Thirdly, this application provides a storage medium storing a plurality of instructions adapted for loading by a processor to execute the shape-sensing optical proximity effect correction method described in any of the preceding claims.

[0037] Fourthly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the shape-sensing optical proximity effect correction method described in any of the preceding claims.

[0038] In summary, the topography-aware optical proximity effect correction method provided in this application includes: acquiring the original design layout; performing CMP simulation on the original design layout to generate wafer topography data; constructing a coupled optical model based on the EUV 3D mask model and the wafer topography data; performing layout decomposition on the design layout according to multiple graphical process rules to obtain at least two mask layouts; and using the coupled optical model to perform collaborative topography-aware optical proximity effect correction on the at least two mask layouts to obtain at least two corrected mask layouts. Wherein, when correcting the current mask layout, the optical proximity environment used includes historical mask correction results generated based on the coupled optical model. This application embodiment can improve the imaging accuracy of advanced process nodes. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram illustrating an application scenario of the shape-sensing optical proximity effect correction method provided in the embodiments of this application.

[0041] Figure 2 This is a schematic flowchart of the shape-sensing optical proximity effect correction method provided in the embodiments of this application.

[0042] Figure 3 This is a schematic diagram of the shape-sensing optical proximity effect correction device provided in the embodiments of this application.

[0043] Figure 4 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0044] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0045] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0046] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0047] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustration and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0048] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0049] Current TOPC methods employ a fragmented and non-cooperative correction paradigm, failing to couple the EUV 3D mask shadowing effect with wafer local topography defocusing, and failing to model the optical interactions between masks in multiple patterning, resulting in systematic integrated imaging errors at advanced process nodes.

[0050] Based on this, embodiments of this application provide a method, apparatus, storage medium, and electronic device for correcting the optical proximity effect of shape perception. Specifically, the shape perception optical proximity effect correction apparatus can be integrated into an electronic device, which can be a server or a terminal, etc. The terminal can include mobile phones, wearable smart devices, tablet computers, laptops, and personal computers (PCs), etc., and other computers and auxiliary devices. The server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0051] For example, such as Figure 1 As shown, the electronic device can acquire the original design layout; perform CMP simulation on the original design layout to generate wafer topography data; construct a coupled optical model based on the EUV 3D mask model and wafer topography data; decompose the design layout according to multiple graphical process rules to obtain at least two mask layouts; use the coupled optical model to perform collaborative topography-aware optical proximity effect correction on at least two mask layouts to obtain at least two corrected mask layouts; wherein, when correcting the current mask layout, the optical proximity environment used includes historical mask correction results generated based on the coupled optical model.

[0052] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0053] Please see Figure 2 , Figure 2 This is a schematic flowchart of the shape-sensing optical proximity effect correction method provided in this application embodiment. The specific flow of the shape-sensing optical proximity effect correction method can be as follows:

[0054] 101. Obtain the original design layout.

[0055] The original design layout is a two-dimensional planar graphic data file that defines the physical structure of one or more layers of an integrated circuit. It fully describes the geometry, dimensions, and relative positions of all functional units in the chip, including transistors, interconnects, and vias. In the semiconductor industry, original design layouts typically use industry-standard data formats such as GDSII or OASIS.

[0056] In some embodiments, the original design layout can be read from local or network storage devices, such as directly connected hard drives, network-attached storage, or storage area networks, from layout files pre-generated and stored by the design department. In some embodiments, the original design layout can be retrieved from a design database, for example, through an application programming interface or database query command, from an integrated circuit design database.

[0057] 102. Perform CMP simulation on the original design layout to generate wafer topography data.

[0058] The purpose of CMP simulation on the original design layout is to predict and quantify the changes in wafer surface morphology caused by the CMP process. Since the polishing rate during CMP is closely related to the local pattern density, dense and sparse areas will experience different amounts of material removal, resulting in non-uniform micro-undulations on the wafer surface related to the original design layout. This morphology change can be directly translated into spatially variable defocus in subsequent photolithography processes, and is one of the key factors affecting imaging accuracy. Therefore, CMP simulation of the original design layout is a prerequisite for achieving accurate morphology-aware optical proximity effect correction.

[0059] CMP simulation can be performed using a CMP process simulation tool, which consists of one or more calibrated CMP process models. These CMP process models can be based on physical mechanisms (such as models considering pressure distribution, polishing pad deformation, and slurry dynamics), or they can be empirical models or machine learning models built upon extensive experimental data.

[0060] Specifically, the original design layout and its specific process parameters (such as polishing pressure, time, slurry characteristics, etc.) can be input into a CMP process simulation tool. This tool can calculate the effective polishing rate of a local area based on layout characteristics such as pattern density, line width, and spacing. Then, based on a selected physical or mathematical model, it simulates the dynamic material removal process of the entire CMP process. After the simulation is complete, the CMP process simulation tool outputs a two-dimensional data array or height map, i.e., wafer morphology data. Each numerical point in this wafer morphology data represents the remaining film thickness after CMP at the corresponding coordinate point on the wafer surface, or the height deviation value (in nanometers) relative to the global ideal reference plane.

[0061] 103. Construct a coupled optical model based on EUV 3D mask model and wafer topography data.

[0062] The coupled optical model is a "topography-shadow-defocus" coupled optical model, which has the ability to simultaneously predict the light intensity distribution of EUV 3D mask imaging at any local topography point.

[0063] Specifically, step 103 may include the following steps:

[0064] 1031. Map wafer morphology data to spatially varying defocus distribution.

[0065] First, based on the wafer morphology data and the specific process flow (such as resist coating process parameters), the resist thickness in different areas of the wafer surface during exposure can be calculated. It is understandable that height deviations in the wafer morphology data will directly lead to localized variations in the resist thickness.

[0066] Then, based on photolithography imaging theory (such as analysis through scalar or vector imaging models) and / or process experimental data, a correspondence function or lookup table is established to define the defocus amount relative to the optimal focal plane for a given resist thickness. It should be noted that this correspondence may be non-linear and depends on the type and optical properties of the resist.

[0067] Finally, this correspondence can be used to calculate a specific defocus value for each point in the simulation mesh on the wafer surface. Integrating the defocus values ​​of all points generates a defocus marker layer. This defocus marker layer can be used as a spatial variable in subsequent optical simulations to precisely modulate the imaging conditions of each local area, thereby accurately simulating the non-uniform defocus state caused by the CMP process.

[0068] That is, step 1031 can specifically be: determining the resist thickness of each region on the wafer surface based on the wafer morphology data; assigning a corresponding defocus amount value to each region based on the correspondence between the resist thickness and the defocus amount; and generating defocus mark layer data for optical simulation based on the defocus amount value to form a spatially varying defocus amount distribution.

[0069] 1032. The defocus distribution and the shadow effect characterized by the EUV three-dimensional mask model are integrated into the lithographic imaging model to form a coupled optical model.

[0070] This EUV 3D mask model describes the angle-dependent transmittance variation and phase delay, or "shadowing effect," produced when incident EUV light (wavelength 13.5 nm) passes through an absorber structure with specific height and sidewall angles. This EUV 3D mask model can be based on a complex database (lookup table) pre-calculated using rigorous electromagnetic field simulations (such as finite-difference time-domain (FDTD) or rigorous coupled-wave analysis (RCWA), or it can be a simplified analytical shadowing model used to balance computational efficiency and accuracy. Essentially, it elevates the mask from a simple two-dimensional binary transmission object to an object with a three-dimensional electromagnetic response.

[0071] This lithographic imaging model is a fundamental one. Such models are typically based on partially coherent imaging theories (such as the Hopkins formula). By integrating the defocus distribution with the shadowing effect characterized by the EUV 3D mask model, the resulting coupled optical model can simultaneously calculate the diffraction spectrum of the 3D mask and the local defocus conditions at various points in space during imaging simulation. This allows for accurate prediction of the light intensity distribution under the combined influence of the actual wafer morphology and EUV mask physics.

[0072] 104. Decompose the design layout according to the multiple graphical process rules to obtain at least two mask layouts.

[0073] By decomposing the original design pattern according to multiple patterning process rules and distributing it onto multiple independent mask patterns, it can be ensured that these mask patterns can accurately reproduce the original design intent on the wafer through multiple exposure and etching steps.

[0074] Among them, the multi-graphic process rules can be decomposition rules, color allocation rules, spacing constraints, etc. of self-aligned dual-graphic SADP or self-aligned quadruple-graphic SAQP.

[0075] Specifically, a decomposition algorithm (such as a coloring algorithm) can be used to analyze the original design layout, and the dense graphics that were originally on the same layer can be distributed to at least two mask layouts according to the principle of not being adjacent to each other or meeting specific spacing requirements.

[0076] For example, for a dual graphical decomposition, a first mask pattern (the set of patterns corresponding to color A) and a second mask pattern (the set of patterns corresponding to color B) can be generated.

[0077] 105. At least two mask patterns are corrected for the optical proximity effect by using a coupled optical model to obtain at least two corrected mask patterns; wherein, when correcting the current mask pattern, the optical proximity environment used includes the historical mask correction results generated based on the coupled optical model.

[0078] Here, "historical mask" refers to all mask layouts that have completed TOPC in the current round of collaborative correction before the current mask layout. The historical mask correction result refers to the printed pattern generated by simulation using a coupled optical model based on the completed TOPC mask layout.

[0079] The following describes the specific process of performing collaborative topography-sensing optical proximity effect correction when the original design layout is decomposed into five mask layouts (hereinafter referred to as M1, M2, M3, M4, and M5).

[0080] First, an initial TOPC is performed on M1. Since there are currently no other corrected mask patterns affecting the imaging, TOPC can be performed directly on M1. The goal of the correction is to make the printed pattern of M1 under the current topology as close as possible to its ideal target pattern. After correction, an updated mask pattern M1' is obtained. Then, using a coupled optical model, a rigorous photolithographic simulation is performed on the corrected mask pattern M1' to predict its printed pattern P1 under real wafer topology conditions. This printed pattern P1 can accurately reflect the final imaging topology of M1' on the wafer, including all deformations caused by topology and shading effects.

[0081] Subsequently, P1 is incorporated into the optical proximity environment, and TOPC is performed on the mask pattern M2. At this point, when calculating the imaging quality of any pattern on M2, the TOPC engine considers not only the wafer morphology and EUV shading, but also precisely calculates the optical interactions (such as light intensity superposition and interference) between the pattern and the printed pattern P1. After correction, the mask pattern M2' is obtained. Next, the printed pattern of the simulated mask pattern M2' is denoted as P_12 (i.e., the superposition of the simulated patterns P1 and M2').

[0082] Then, following the same "correction-simulation-environment transfer" logic, subsequent masks can be processed sequentially: Incorporate the printed pattern P_12 into the optical proximity environment, perform TOPC on the mask layout M3 to obtain M3'. Simulate M3' to obtain P_123. Incorporate P_123 into the optical proximity environment, perform TOPC on the mask layout M4 to obtain M4'. Simulate M4' to obtain P_1234. Incorporate P_1234 into the optical proximity environment, perform TOPC on the mask layout M5 to obtain M5'. This completes the first round of collaborative TOPC for all five masks.

[0083] In some embodiments, global iterative optimization can be performed to achieve higher integration accuracy. The results of the first round of collaborative correction (M1' to M5') are used as initial values. The printed patterns of four mask patterns are fixed within the optical proximity environment, and the remaining mask pattern is optimized. For example, M2'-M5' are first fixed, and P_2345 (i.e., the four printed patterns obtained from the simulation of M2'-M5') is included within the optical proximity environment. M1' is then optimized in reverse to obtain M1''. This process is repeated for all mask patterns, performing multiple rounds of optional local or global iterations until the change in each mask pattern is less than a preset threshold, or the critical dimension (CD) error of the integrated pattern converges to a satisfactory level.

[0084] Therefore, when decomposing the original design layout into two mask layouts (the first mask layout and the second mask layout), the step "using a coupled optical model to perform synergistic topography-aware optical proximity effect correction on at least two mask layouts to obtain at least two corrected mask layouts" can specifically be as follows: perform topography-aware optical proximity effect correction on the first mask layout to update the first mask layout; based on the coupled optical model, simulate the first printed pattern of the updated first mask layout under wafer topography data; incorporate the first printed pattern into the optical proximity environment, and perform topography-aware optical proximity effect correction on the second mask layout to update the second mask layout.

[0085] Then, it can be determined whether the updated first mask pattern and the second mask pattern have converged; if not, the updated first mask pattern is optimized in reverse based on the updated second mask pattern until the updated first mask pattern and the second mask pattern converge; if so, the updated first mask pattern and the second mask pattern can be output.

[0086] Specifically, the step "based on the updated second mask pattern, reverse optimize the updated first mask pattern until the updated first mask pattern and the second mask pattern converge" can be: based on the coupled optical model, simulate the second printed pattern of the updated second mask pattern under the wafer topography data; incorporate the second printed pattern into the optical proximity environment, and return to perform the step of performing topography-aware optical proximity effect correction on the first mask pattern to update the first mask pattern, until the updated first mask pattern and the second mask pattern converge.

[0087] Through the embodiments of this application, an optical environment that increasingly approximates the final actual exposure scenario can be gradually constructed for each mask pattern's TOPC. For example, for the fifth mask M5, its TOPC process already includes all the optical proximity effects of the first four mask patterns. This effectively solves the problems of integrated pattern distortion, critical dimension deviation, and narrowing process window caused by the neglect of interactions between mask patterns in traditional TOPC.

[0088] Experimental data shows that, in the test case of the 3nm technology node, the TOPC method provided in this embodiment improves the critical dimension uniformity (CDU) of the final integrated pattern by about 35% and expands the overlap process window by about 25% compared with the traditional TOPC method, significantly improving the consistency of manufacturing yield and circuit performance.

[0089] In summary, the topography-aware optical proximity effect correction method provided in this application includes: acquiring the original design layout; performing CMP simulation on the original design layout to generate wafer topography data; constructing a coupled optical model based on the EUV 3D mask model and wafer topography data; decomposing the design layout according to multiple graphical process rules to obtain at least two mask layouts; and using the coupled optical model to perform collaborative topography-aware optical proximity effect correction on the at least two mask layouts to obtain at least two corrected mask layouts. When correcting the current mask layout, the optical proximity environment used includes historical mask correction results generated based on the coupled optical model. This application, by constructing a "topography-shadow-defocus" coupled optical model that integrates the EUV 3D mask shadow effect and the wafer's local topography, replaces the traditional approximate model based on an ideal 2D mask and a single defocus, achieving a more accurate description of imaging physics. Meanwhile, a collaborative correction mechanism is adopted to use the imaging results of the preceding mask pattern as the optical proximity environment of the subsequent mask pattern TOPC in multiple patterning processes. This compensates for the cumulative optical interactions between mask patterns, thereby improving the TOPC from independent optimization of each mask pattern to global optimization of multiple mask patterns. This effectively reduces pattern stitching errors and critical dimension deviations, and maintains imaging stability within a wider process window, significantly improving the imaging accuracy and manufacturing yield of advanced process nodes at 3nm and below.

[0090] To facilitate better implementation of the shape-sensing optical proximity effect correction method provided in this application embodiment, this application embodiment also provides a shape-sensing optical proximity effect correction device. The meanings of the terms used are the same as in the shape-sensing optical proximity effect correction method described above, and specific implementation details can be found in the description of the method embodiment.

[0091] Please see Figure 3 , Figure 3 This is a schematic diagram of the topography-sensing optical proximity effect correction device provided in an embodiment of this application. The topography-sensing optical proximity effect correction device may include an acquisition unit 201, a simulation unit 202, a construction unit 203, a decomposition unit 204, and a correction unit 205.

[0092] Acquisition unit 201 is used to acquire the original design layout;

[0093] Simulation unit 202 is used to perform CMP simulation on the original design layout and generate wafer topography data;

[0094] Building unit 203 is used to build a coupled optical model based on EUV 3D mask model and wafer topography data;

[0095] Decomposition unit 204 is used to decompose the design layout according to multiple graphical process rules to obtain at least two mask layouts.

[0096] The correction unit 205 is used to perform cooperative topography-aware optical proximity effect correction on at least two mask patterns using a coupled optical model to obtain at least two corrected mask patterns; wherein, when correcting the current mask pattern, the optical proximity environment used includes historical mask correction results generated based on the coupled optical model.

[0097] For specific implementation methods of each of the above units, please refer to the embodiments of the above-described shape-sensing optical proximity effect correction method, which will not be repeated here.

[0098] In summary, the topography-aware optical proximity effect correction device provided in this application embodiment can acquire the original design layout through the acquisition unit 201; perform CMP simulation on the original design layout by the simulation unit 202 to generate wafer topography data; construct a coupled optical model based on the EUV 3D mask model and wafer topography data by the construction unit 203; decompose the design layout by the decomposition unit 204 according to multiple graphical process rules to obtain at least two mask layouts; and correct the at least two mask layouts by the correction unit 205 using the coupled optical model to perform collaborative topography-aware optical proximity effect correction on the at least two mask layouts to obtain at least two corrected mask layouts. When correcting the current mask layout, the optical proximity environment used includes historical mask correction results generated based on the coupled optical model. This application embodiment can improve the imaging accuracy of advanced process nodes.

[0099] This application also provides an electronic device that may integrate the shape-sensing optical proximity effect correction device of this application, such as... Figure 4 As shown, it illustrates a structural schematic diagram of the electronic device involved in the embodiments of this application, specifically:

[0100] The electronic device may include components such as a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media. Those skilled in the art will understand that... Figure 4 The electronic device structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein:

[0101] The processor 301 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs stored in the memory 302 and / or this application, and by calling data stored in the memory 302, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operation of the storage medium, user interface, and application programs, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 301.

[0102] The memory 302 can be used to store software programs and this application. The processor 301 executes various functional applications and data processing by running the software programs and this application stored in the memory 302. The memory 302 may mainly include a program storage area and a data storage area. The program storage area may store applications required for operating the storage medium and at least one function; the data storage area may store data created based on the use of the electronic device. In addition, the memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0103] Although not shown, the electronic device may also include a display unit, an input unit, and a power supply, etc., which will not be described in detail here. Specifically, in this embodiment, the processor 301 in the electronic device loads the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 runs the application programs stored in the memory 302 to realize various functions, as follows:

[0104] Obtain the original design layout;

[0105] Perform CMP simulation on the original design layout to generate wafer topography data;

[0106] A coupled optical model was constructed based on EUV 3D mask model and wafer topography data;

[0107] The design layout is decomposed according to multiple graphical process rules to obtain at least two mask layouts.

[0108] At least two mask patterns are corrected for the optical proximity effect by using a coupled optical model to obtain at least two corrected mask patterns. The optical proximity environment used when correcting the current mask pattern includes historical mask correction results generated based on the coupled optical model.

[0109] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0110] Therefore, embodiments of this application provide a storage medium storing a plurality of instructions that can be loaded by a processor to execute steps in any of the methods provided in embodiments of this application. For example, the instructions can execute the following steps:

[0111] Obtain the original design layout;

[0112] Perform CMP simulation on the original design layout to generate wafer topography data;

[0113] A coupled optical model was constructed based on EUV 3D mask model and wafer topography data;

[0114] The design layout is decomposed according to multiple graphical process rules to obtain at least two mask layouts.

[0115] At least two mask patterns are corrected for the optical proximity effect by using a coupled optical model to obtain at least two corrected mask patterns. The optical proximity environment used when correcting the current mask pattern includes historical mask correction results generated based on the coupled optical model.

[0116] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.

[0117] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0118] Since the instructions stored in the storage medium can execute the steps of any method provided in the embodiments of this application, the beneficial effects that any method provided in the embodiments of this application can achieve can be realized. For details, please refer to the previous embodiments, which will not be repeated here.

[0119] The foregoing has provided a detailed description of the shape-sensing optical proximity effect correction method, apparatus, storage medium, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for correcting optical proximity effect in shape perception, characterized in that, include: Obtain the original design layout; CMP simulation was performed on the original design layout to generate wafer topography data; The wafer morphology data is mapped to a spatially varying defocus distribution; The defocus distribution and the shadow effect characterized by the EUV three-dimensional mask model are integrated into the photolithography imaging model to form a coupled optical model. The design layout is decomposed according to multiple graphical process rules to obtain at least two mask layouts; The coupled optical model is used to perform cooperative topography-aware optical proximity effect correction on at least two of the mask patterns to obtain at least two corrected mask patterns; wherein, when correcting the current mask pattern, the optical proximity environment used includes historical mask correction results generated based on the coupled optical model.

2. The shape-perceived optical proximity effect correction method as described in claim 1, characterized in that, The step of mapping the wafer topography data into a spatially varying defocus distribution includes: Based on the wafer morphology data, the resist thickness in each region of the wafer surface is determined; Based on the relationship between the resist thickness and the defocusing amount, a corresponding defocusing amount value is assigned to each region; Based on the defocus value, defocus marker layer data for optical simulation is generated to form a spatially varying defocus distribution.

3. The shape-perceived optical proximity effect correction method as described in claim 1, characterized in that, The process of using the coupled optical model to perform cooperative topography-aware optical proximity effect correction on at least two mask patterns to obtain at least two corrected mask patterns includes: The first mask pattern is updated by performing topography-aware optical proximity correction. Based on the coupled optical model, the updated first mask pattern is simulated as the first printed pattern under the wafer topography data; The first printed pattern is incorporated into the optical proximity environment, and the second mask pattern is corrected for the optical proximity effect by shape perception in order to update the second mask pattern.

4. The shape-perceived optical proximity effect correction method as described in claim 3, characterized in that, Also includes: Determine whether the updated first mask layout and the second mask layout converge; If not, then based on the updated second mask layout, the updated first mask layout is optimized in reverse until the updated first mask layout and the second mask layout converge.

5. The shape-perceived optical proximity effect correction method as described in claim 4, characterized in that, The step of reverse-optimizing the updated first mask pattern based on the updated second mask pattern until the updated first mask pattern and the second mask pattern converge includes: Based on the coupled optical model, the updated second mask pattern is simulated as a second printed pattern under the wafer topography data; The second printed pattern is incorporated into the optical proximity environment, and the step of performing shape-aware optical proximity effect correction on the first mask pattern to update the first mask pattern is performed until the updated first mask pattern and the second mask pattern converge.

6. The shape-perceived optical proximity effect correction method as described in claim 1, characterized in that, The EUV 3D mask model is a simplified analytical shadow model.

7. A shape-sensing optical proximity effect correction device, characterized in that, include: The acquisition unit is used to acquire the original design layout; The simulation unit is used to perform CMP simulation on the original design layout to generate wafer topography data. The construction unit is used to map the wafer topography data into a spatially varying defocus distribution; and to integrate the defocus distribution and the shadow effect characterized by the EUV three-dimensional mask model into the lithography imaging model to form a coupled optical model. The decomposition unit is used to decompose the design layout according to multiple graphical process rules to obtain at least two mask layouts. The correction unit is used to perform cooperative topography-aware optical proximity effect correction on at least two of the mask patterns using the coupled optical model to obtain at least two corrected mask patterns; wherein, when correcting the current mask pattern, the optical proximity environment used includes historical mask correction results generated based on the coupled optical model.

8. A storage medium, characterized in that, The storage medium stores multiple instructions, which are adapted for loading by a processor to execute the shape-sensing optical proximity effect correction method according to any one of claims 1-6.

9. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the shape-sensing optical proximity effect correction method as described in any one of claims 1-6.

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