Memory system, electronic device, and operating method of electronic device

Abstract

The invention relates to a storage system, an electronic device, and an operation method of the electronic device. An electronic device includes a controller and a power source. The controller stores a table including gate signal frequencies for a plurality of operations and a number of power transistors, and outputs a power control signal including one or both of the gate signal frequencies for the operations and the number of power transistors for the operations based on the table and an operation request to perform the operations. The power supply includes a plurality of power transistors that receive gate signals. The power supply generates one or more gate signals input to one or more power transistors among the plurality of power transistors based on a power control signal, and generates a load supply voltage based on a system supply voltage based on conduction of the one or more power transistors.

Description

[0001] Cross Reference to Related Applications

[0002] This application is based on and claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2024-0102703, filed on August 1, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] Devices, apparatuses, and methods consistent with the present disclosure relate to an electronic device, and more particularly, to a storage system for providing optimized power for each operation, an electronic device, and an operating method of an electronic device. BACKGROUND

[0004] An electronic device can operate based on power supplied from the outside. For example, the electronic device can convert an external voltage supplied from the outside into an internal voltage required for internal components, and then use the converted internal voltage. When the external voltage is converted into the internal voltage, power loss can occur due to voltage switching or equivalent resistance. Accordingly, as a ratio of power of the internal voltage with respect to power of the external voltage, i.e., power efficiency, increases, power consumption can decrease.

[0005] Different operations performed by an electronic device can require different amounts of power. Even for operations supplied with the same internal voltage, a relationship between a load current and power efficiency can vary. Accordingly, a load current at which maximum power efficiency occurs for a specific operation can also vary depending on the operation. Accordingly, there are techniques to optimize power efficiency based on an operation that consumes the maximum amount of power, but the limitations of these techniques are that, in operations other than the operation that consumes the maximum amount of power, power efficiency decreases. SUMMARY

[0006] One aspect is to provide a storage system, an electronic device, and an operating method of an electronic device in which a frequency of a power supply and a number of power transistors in the power supply are set for each operation to provide optimized power.

[0007] According to an aspect of one or more embodiments, there is provided an electronic device including: a controller configured to store a table including a gate signal frequency and a number of power transistors for a plurality of operations, and output a power control signal including at least one of the gate signal frequency for an operation or the number of power transistors for the operation based on the table and an operation request to perform the operation; and a power supply including a plurality of power transistors receiving a plurality of gate signals, the power supply configured to generate at least one gate signal input to at least one power transistor among the plurality of power transistors based on the power control signal, and generate a load supply voltage based on a system supply voltage based on a turn-on of the at least one power transistor.

[0008] According to another aspect of one or more embodiments, there is provided an electronic device including: a controller configured to receive an operation request to perform an operation, and output a power control signal indicating the operation in response to the operation request; and a power supply including a plurality of power transistors receiving a plurality of gate signals, the power supply configured to store a table including a gate signal frequency and a number of power transistors for a plurality of operations, generate at least one gate signal input to at least one power transistor among the plurality of power transistors based on the power control signal and the table, and generate a load supply voltage based on a system supply voltage based on a turn-on of the at least one power transistor.

[0009] According to still another aspect of one or more embodiments, there is provided a storage system including: a host configured to store a table including a gate signal frequency and a number of power transistors for each of a plurality of operations, generate an operation request to perform an operation, generate one of a first power control signal and a second power control signal, wherein the first power control signal indicates the operation, the second power control signal includes the gate signal frequency and the number of power transistors for the operation indicated by the first power control signal, and generate a system supply voltage; and a storage device configured to store the table, receive the operation request, one of the first power control signal or the second power control signal, and the system supply voltage, control a turn-on operation of a plurality of power transistors based on one of the first power control signal or the second power control signal, convert the system supply voltage to a load supply voltage based on the plurality of power transistors turned on, and perform the operation.

[0010] According to still another aspect of one or more embodiments, a method of operating an electronic device is provided, the method including generating target operation information indicating a target operation; setting a target gate signal frequency for the target operation of the target operation information and a target number of power transistors for the target operation of the target operation information based on a table including a gate signal frequency and a number of power transistors for each operation; providing a gate signal having the target gate signal frequency to the target number of power transistors among a plurality of power transistors in a power supply; and generating a load supply voltage based on a system supply voltage based on turn-on of the target number of power transistors. BRIEF DESCRIPTION OF DRAWINGS

[0011] Various embodiments will be understood more fully from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 and Figure 2 is a block diagram of an electronic device according to various embodiments;

[0013] Figure 3 is a graph illustrating an example of a first table according to various embodiments;

[0014] Figure 4 is a graph illustrating an example of a second table according to various embodiments;

[0015] Figure 5 is a graph illustrating setting of a frequency and / or a number of power transistors to be activated based on an interface according to various embodiments;

[0016] Figure 6 and Figure 7 is a graph illustrating a power supply according to various embodiments;

[0017] Figure 8 is a timing diagram illustrating a load current and a plurality of gate signals according to a number of power transistors to be activated according to various embodiments;

[0018] Figure 9 is a timing diagram illustrating a load current and a plurality of gate signals according to a frequency of a gate signal according to various embodiments;

[0019] Figure 10 is a graph illustrating an example of power efficiency according to a number of power transistors to be activated according to various embodiments;

[0020] Figure 11 is a graph illustrating an example of power efficiency according to a frequency of a gate signal according to various embodiments;

[0021] Figure 12 is a graph illustrating an example of power efficiency according to an operation according to various embodiments;

[0022] Figure 13 is a block diagram of an electronic device according to various embodiments;

[0023] Figure 14 is a graph illustrating setting a frequency and / or a number of power transistors to be activated based on pin connection according to various embodiments;

[0024] Figure 15 and Figure 16 is a block diagram of an electronic device according to various embodiments;

[0025] Figure 17 is a block diagram of an electronic system according to various embodiments;

[0026] Figures 18 to 21 is a block diagram of a storage system according to various embodiments; and

[0027] Figure 22 is a flowchart illustrating a method of operating an electronic device according to various embodiments. DETAILED DESCRIPTION

[0028] As described above, an electronic device can operate based on power supplied from the outside. For example, the electronic device can convert an external voltage supplied from the outside into an internal voltage required for internal components, and then use the converted internal voltage. In this regard, the electronic device can include a voltage supply for converting the external voltage into the internal voltage. For example, a power supply for generating an internal voltage lower than the external voltage can be provided as a buck converter performing a buck converting operation. When the external voltage is converted into the internal voltage, power loss can occur due to voltage switching or an equivalent resistance inside the voltage supply. Accordingly, as a ratio of power of the internal voltage with respect to power of the external voltage, i.e., power efficiency, increases, power consumption can decrease.

[0029] Since different operations performed by an electronic device can require different amounts of power, the relationship between a load current and power efficiency can vary even for operations that are supplied with the same internal voltage. Accordingly, a load current at which maximum power efficiency occurs for a certain operation can also vary according to the operation. Thus, there are related technologies that optimize power efficiency based on an operation that consumes the maximum amount of power, but these related technologies have the disadvantage that power efficiency decreases in operations other than the operation that consumes the maximum amount of power.

[0030] As described above, one aspect is to provide a storage system, an electronic device, and a method of operating an electronic device in which a frequency of a power supply and a number of power transistors in the power supply are set for each operation to provide optimized power.

[0031] Hereinafter, various embodiments are described in detail with reference to the accompanying drawings. As used in this specification, the phrase "at least one of A, B or C" in its various aspects includes "only A," "only B," "only C," "A and B," "A and C," "B and C," and "A, B and C."

[0032] As used herein, the expressions "first," "second," and so on can modify various components regardless of order and / or importance and are used to distinguish one component from another component only and do not limit the components. For example, a "first" user device and a "second" user device can represent different user devices regardless of order or importance. For example, without departing from the scope of the present disclosure, a "first" component can be referred to as a "second" component, and similarly, a "second" component can be referred to as a "first" component.

[0033] When a component (e.g., a first component) is described as being "operatively or communicatively coupled" / "operatively or communicatively coupled to" or "connected to" another component (e.g., a second component), it should be understood that the component can be directly coupled to the other component or can be connected to the other component through another component (e.g., a third component). On the other hand, when a component (e.g., a first component) is described as being "directly coupled" or "directly connected" to another component (e.g., a second component), it should be understood that there is no other component (e.g., a third component) between the component and the other component.

[0034] Figure 1 and Figure 2 are block diagrams of electronic devices 100 and 200 according to various embodiments.

[0035] Referring to Figure 1 , the electronic device 100 can be provided in a smart phone, a tablet personal computer, a mobile phone, an electronic book reader, a desktop personal computer, a laptop personal computer, a netbook computer, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a mobile medical device, a camera, a wearable device, or a home appliance, etc.

[0036] The electronic device 100 can include a central processing unit (CPU) 110, a controller 120, a power supply 130, a plurality of channels 140, and a plurality of elements 150. The plurality of channels 140 can include a first channel 140_1, a second channel 140_2,..., to an n-th channel 140_n. The plurality of elements 150 can include a first element 150_1, a second element 150_2,..., to an n-th element 150_n.

[0037] The CPU 110 can control all operations of the electronic device 100. In an embodiment, the CPU 110 can provide an operation request REQ to the controller 120. The operation request REQ can include an instruction to request the controller 120 to perform an operation.

[0038] The controller 120 can receive the operation request REQ and perform an operation of the operation request REQ. In an embodiment, the controller 120 can be configured to perform control logic of various devices such as a baseboard management controller (BMC), a storage controller, and / or a memory controller.

[0039] In an embodiment, the controller 120 can store a table 121. The table 121 can include a frequency and / or a size of a power transistor for each of various operations that can be provided in the operation request REQ. In some embodiments, the various operations can include a background operation performed in an idle state of the electronic device 100 and / or a foreground operation performed in an active state of the electronic device 100. In some embodiments, the frequency in the table 121 can include an operating frequency of a gate signal generated by the power supply 130. In some embodiments, the size of the power transistor in the table 121 can represent a number of power transistors to be activated among a plurality of power transistors (PTRs) 131 in the power supply 130. The activated power transistor(s) can represent a transistor that can be turned on in response to an on level of the gate signal. The deactivated power transistor(s) can represent a transistor that has been turned off.

[0040] The controller 120 can output a power control signal PCSIG based on the table 121 and the operation request REQ. The power control signal PCSIG can include a signal for controlling a power supply operation of the power supply 130. In some embodiments, the power control signal PCSIG can include a frequency among the frequencies in the table 121 corresponding to the operation of the operation request REQ. In some embodiments, the power control signal PCSIG can include a number of transistors among the numbers of transistors in the table 121 corresponding to the operation of the operation request REQ (e.g., a number of power transistors to be activated). In some embodiments, the power control signal PCSIG can include a frequency and a number of power transistors among the frequencies and the numbers of power transistors in the table 121 corresponding to the operation of the operation request REQ.

[0041] In an embodiment, the controller 120 and the power supply 130 can communicate with each other via an interface. For example, the interface can be provided in various ways, for example, an interface conforming to a Joint Electron Device Engineering Council (JEDEC) standard (such as an internal integrated circuit (I2C), double data rate (DDR4), DDR5, low power DDR (LPDDR4), and / or LPDDR5), an interface conforming to a standard (such as a non-volatile memory express (NVMe), NVMe management interface (MI), and / or NVMe over fabrics (NVMeof)), and / or an interface (such as an advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached (SAS), peripheral component interconnect (PCI), PCI express (PCIe), NVMe, IEEE 1394, universal serial bus (USB), secure digital (SD) card, multimedia card (MMC), eMMC, universal flash memory (UFS), embedded UFS (eUFS), and / or compact flash (CF) card). However, embodiments are not limited to the above-described examples. The controller 120 can transmit a command to the power supply 130 via the interface, and the power supply 130 can transmit a response to the command to the controller 120.

[0042] The power supply 130 can supply a plurality of load supply voltages VO1, VO2,..., and VOn to a plurality of elements 150 via a plurality of channels 140. In an embodiment, the power supply 130 can convert (or switch) a system supply voltage VSYS supplied from a power source (for example, a battery, an external power source, etc.) to the plurality of load supply voltages VO1, VO2,..., and VOn. In an embodiment, the power supply 130 can include a plurality of power transistors (PTRs) 131, and the power supply 130 can switch the system supply voltage VSYS to the plurality of load supply voltages VO1, VO2,..., and VOn based on turning on of at least one power transistor among the plurality of power transistors 131. Each of the plurality of power transistors 131 of the power supply 130 can be turned on or turned off based on a gate signal having a specific frequency.

[0043] In an embodiment, when the power source is a battery in the electronic device 100, the system supply voltage VSYS can be referred to as an internal supply voltage of the electronic device 100. When the power source is an external power source of the electronic device 100, the system supply voltage VSYS can be referred to as an external supply voltage of the electronic device 100.

[0044] When the power supply 130 converts the system supply voltage VSYS into a plurality of load supply voltages VO1, VO2,..., and VOn, a power loss according to the system supply voltage VSYS can occur due to conductor loss caused by the turned-on power transistor. A power loss according to the system supply voltage VSYS can occur due to switching loss caused by the activated power transistor. Accordingly, the efficiency of power consumption in the system increases as the ratio of system power to external supply power, i.e., power efficiency, is maintained at a high level.

[0045] In an embodiment, the power supply 130 can receive a power control signal PCSIG from the controller 120 via an interface. The power supply 130 can generate at least one toggled gate signal based on the frequency of the power control signal PCSIG and / or the number of power transistors to be activated. The toggled gate signal can include a signal input to the power transistors to be activated among the plurality of power transistors 131. Based on the turn-on of the at least one power transistor to be activated, the power supply 130 can generate a plurality of load supply voltages VO1, VO2,..., and VOn based on the system supply voltage VSYS. The plurality of load supply voltages VO1, VO2,..., and VOn can be supplied to the plurality of elements 150. The voltage levels of the plurality of load supply voltages VO1, VO2,..., and VOn can be determined according to the operation (i.e., the type of operation) of the operation request REQ and / or according to the elements connected to the corresponding channels. The power supply 130 can transmit a setup completion signal SDSIG to the controller 120 via the interface. The setup completion signal SDSIG is a response signal or ACK (e.g., ACK is an abbreviation of acknowledgement) to the power control signal PCSIG.

[0046] In an embodiment, the power supply 130 and the plurality of elements 150 can be connected to each other via a plurality of channels 140. The number of the plurality of channels 140 can be n. The number n can be a natural number greater than or equal to 2. In some embodiments, one element 150 can be connected to one channel. That is, in some embodiments, the plurality of channels 140 and the plurality of elements 150 can be provided in a one-to-one relationship.

[0047] The plurality of elements 150 can include functional units that receive load supply voltages to perform various functions in the electronic device 100. The plurality of elements 150 can receive different load supply voltages. In some embodiments, the plurality of elements 150 can include the CPU 110, the controller 120, a memory, etc. Some of the plurality of elements 150 can be disposed in the same hardware. For example, a first element 150_1 and a second element 150_2 can be in the controller 120, and an n-th element 150_n can be in a memory (e.g., a flash memory, etc.). However, embodiments are not limited to the above-described example.

[0048] Referring to Figure 2 , similar to the electronic device 100, the electronic device 200 can include a CPU 210, a controller 220, a power supply 230, a plurality of channels 240, and a plurality of elements 250. The plurality of channels 240 can include a first channel 240_1, a second channel 240_2,..., and an n-th channel 240-n. The plurality of elements 250 can include a first element 250_1, a second element 250_2,..., and an n-th element 250_n. In describing the CPU 210, the controller 220, the power supply 230, the plurality of channels 240, and the plurality of elements 250 illustrated in FIG. 2, descriptions that are repeated with those given above with reference to FIG. 1 are omitted for the sake of brevity. Figure 2 Figure 1

[0049] In an embodiment, the controller 220 can transmit a power control signal PCSIG indicating an operation of the operation request REQ to the power supply 230 via the interface. In an embodiment, the power control signal PCSIG can include a value corresponding to an operation mode of the operation. Although not illustrated in FIG. 2, in some embodiments, the power control signal PCSIG can include a value corresponding to a number of power transistors to be activated for the operation of the operation request REQ. Figure 2 Figure 2 In an embodiment, the controller 220 of the electronic device 200 can further store a table 121 illustrated in FIG. 1. Figure 1

[0050] In an embodiment, the power supply 230 of the electronic device 200 can store a table 232. In some embodiments, the table 232 can be the same as the table 121 discussed above with reference to FIG. 1. The power supply 230 can set a frequency and / or a number of power transistors to be activated corresponding to the operation of the operation request REQ in the table 232 based on the power control signal PCSIG. The power supply 230 can generate at least one gate signal that toggles back and forth based on the set frequency and / or the set number of power transistors to be activated. Based on the turn-on of the at least one power transistor to be activated, the power supply 230 can generate a plurality of load supply voltages VO1, VO2,..., and Vo based on the system supply voltage Vsys. The power supply 230 can transmit a setting completion signal SDSIG to the controller 220 via the interface. Figure 2 Figure 1

[0051] According to the above-described embodiments, the operation frequency (e.g., the frequency of the gate signal) and / or the number of power transistors to be activated of the power supply 130 and 230 are set for each operation, and thus, advantageously, the power consumption of the electronic devices 100 and 200 can be reduced and optimized, and the total cost of ownership (TCO) of a user using the electronic devices 100 and 200 can be reduced.

[0052] Figure 3 is a diagram illustrating an example of a first table according to various embodiments.​​​​​​

[0053] Referring to Figure 3 A first table can be provided in Table 121 and / or Table 232. In an embodiment, the first table can include a frequency and a number of power transistors to be activated corresponding to each of a plurality of foreground operations FGOs. In other words, for each of the plurality of foreground operations FGOs, Table 121 and / or Table 232 can include a frequency and a number of power transistors to be activated for the foreground operation FGO. The frequency can include a frequency of a gate signal. Since a load is different for each of the plurality of foreground operations FGOs, a load current can be different for each foreground operation even though a generated load supply voltage is the same. The plurality of foreground operations FGOs can include various operations of a storage device, various operations of a memory (or a memory device), or access methods or computing operations of other devices (e.g., a network interface card (NIC), a network adapter, an AI accelerator, etc.). For example, the plurality of foreground operations FGOs can include a sequential read SEQ read, a random read RAN read, a mixed operation MIX OP, a random write RAN write, and / or a sequential write SEQ write. In an embodiment, the mixed operation MIX OP can denote an operation including a read operation and a write operation. The sequential read SEQ read, the random read RAN read, the mixed operation MIX OP, the random write RAN write, and the sequential write SEQ write can correspond to a first to a fifth operation mode value OP_mode1, OP_mode2, OP_mode3, OP_mode4, and OP_mode5, respectively, as illustrated in Table 121 and / or Table 232. For example, if a signal (e.g., a power control signal PCSIG) includes the first operation mode value OP_mode1, the signal can indicate the sequential read SEQ read. However, embodiments are not limited to the above-described example. Figure 3

[0054] For each of the sequential read SEQ read, the random read RAN read, the mixed operation MIX OP, the random write RAN write, and the sequential write SEQ write, a frequency of a gate signal and a number (hereinafter, referred to as a "number" for convenience of description) of power transistors to be activated can be set. For example, in some embodiments, the frequency and the number of power transistors for the sequential read SEQ read can be "F11" and "N11", respectively. The frequency and the number of power transistors for the random read RAN read can be "F12" and "N12", respectively. The frequency and the number of power transistors for the mixed operation MIX OP can be "F13" and "N13", respectively. The frequency and the number of power transistors for the random write RAN write can be "F14" and "N14", respectively. The frequency and the number of power transistors for the sequential write SEQ write can be "F15" and "N15", respectively.

[0055] ​In some embodiments, the load for the sequential read SEQ read can be the smallest and the load for the sequential write SEQ write can be the largest among the sequential read SEQ read, the random read RAN read, the mixed operation MIX OP, the random write RAN write, and the sequential write SEQ write. Thus, among the frequencies “F11”, “F12”, “F13”, “F14”, and “F15” and the quantities “N11”, “N12”, “N13”, “N14”, and “N15”, the frequency “F15” and the quantity “N15” for the sequential write SEQ write can be the largest, and the frequency “F11” and the quantity “N11” for the sequential read SEQ read can be the smallest. For example, the amplitudes can increase in the order of “F11”, “F12”, “F13”, “F14”, and “F15”, and the sizes (i.e., the number of power transistors) can increase in the order of “N11”, “N12”, “N13”, “N14”, and “N15”. For example, the amplitudes of “F11”, “F12”, and “F13” increase in this order, and “F14” and “F15” can be greater than or equal to “F13”. The quantities of “N11”, “N12”, and “N13” increase in this order. For example, “N11” can be smaller than “N12”, and “N12” can be smaller than “N13”. “N14” and “N15” can be greater than or equal to “N13”.

[0056] In some embodiments, the frequency “F13” and the quantity “N13” can be determined according to the ratio of each of the read operation and the write operation in the mixed operation MIX OP. For example, as the ratio of the read operation in the mixed operation MIX OP becomes greater than the ratio of the write operation, the frequency “F13” and the quantity “N13” can become closer to the frequency “F12” and the quantity “N12”. For example, as the ratio of the write operation in the mixed operation MIX OP becomes greater than the ratio of the read operation, the frequency “F13” and the quantity “N13” can become closer to the frequency “F14” and the quantity “N14”. However, embodiments are not limited to the above example. In some embodiments, the frequency “F13” and the quantity “N13” for the mixed operation MIX OP can be greater than the frequency “F14” and the quantity “N14”.

[0057] Figure 4 FIG. 1 is a diagram illustrating an example of a first table according to various embodiments.

[0058] Reference Figure 4A second table can be provided in Table 121 and / or Table 232. In embodiments, the second table can include a frequency and a number of power transistors corresponding to each of the plurality of background operations BGOs. In other words, for each of the plurality of background operations BGOs, Table 121 and / or Table 232 can include a frequency and a number of power transistors to activate for the background operation BGO. Since the load is different for each of the plurality of background operations BGOs, the load current can be different for each background operation even though the generated load supply voltage is the same. The plurality of background operations BGOs can include, for example, background operations of a storage device and / or background operations of a volatile memory device. The background operations of a storage device can include, for example, wear leveling, read reclaim, and / or garbage collection. The background operations of a volatile memory (e.g., dynamic random access memory (DRAM)) can include, for example, self-refresh. Wear leveling of a storage device involves a technique for preventing over- deterioration of a particular memory block by ensuring that memory blocks in a non-volatile memory (e.g., NAND flash memory) are used uniformly, and wear leveling can be performed by a firmware technique that balances erase counts of physical blocks. Read reclaim involves a technique for guaranteeing read performance by moving data stored in a memory block to another memory block before an uncorrectable error occurs in the data stored in the memory block. Garbage collection involves a technique for ensuring available capacity in a non-volatile memory by copying valid data from a memory block to a new memory block and then erasing the existing memory block. Self-refresh involves a technique for preventing natural leakage and loss of data stored in a memory cell of a DRAM by rewriting the data stored in the memory cell (e.g., a potential difference of a charged capacitor in the memory cell) at regular intervals. In some embodiments, wear leveling, read reclaim, or garbage collection of a storage device can include a read operation, a write operation, or an erase operation of a non-volatile memory (e.g., NAND flash). For example, with reference to Figure 4 The plurality of background operations BGOs of the second table can include a background NAND read BKGRD NAND read, a background NAND write BKGRD NAND write, and a background NAND erase BKGRD NAND erase. However, embodiments are not limited to the above example.

[0059] For each of the background NAND read BKGRD NAND read, the background NAND write BKGRD NAND write, and the background NAND erase BKGRD NAND erase, the number of frequency and power transistors can be set. For example, the number of frequency and power transistors for the background NAND read BKGRD NAND read can be “F21” and “N21”, respectively. The number of frequency and power transistors for the background NAND write BKGRD NAND write can be “F22” and “N22”, respectively. The number of frequency and power transistors for the background NAND erase BKGRD NAND erase can be “F23” and “N23”, respectively.

[0060] Figure 5 is a diagram illustrating setting of a frequency and / or the number of power transistors to be activated based on an interface according to some embodiments.

[0061] Referring to Figure 5 In operation S510, the controller 520 can check a type of an operation. For example, the controller 520 can check a type of an operation requested by the CPU 110 using an operation request REQ transmitted by the CPU 110.

[0062] In operation S520, the controller 520 can transmit a power control signal to the power supply 530. In an embodiment, the controller 520 can transmit a first power control signal to the power supply 530 via an interface in response to a first operation request received from an external source (e.g., the CPU 110). In an embodiment, the first power control signal can include a frequency and / or the number of power transistors for a first operation of the first operation request. For example, when the interface between the controller 520 and the power supply 530 performs communication in an I2C method, the controller 520 can transmit serial data (SDA) to the power supply 530 in synchronization with a serial clock (SCL) signal. A data specification of the SDA transmitted by the controller 520 can include a start field, an address field, a write command field, a data field, and a stop field. In this case, a frequency and / or the number of power transistors of a gate signal can be provided in the data field. In an embodiment, the first power control signal can indicate the first operation of the first operation request. That is, the first power control signal can include an operation mode value for the first operation. For example, when the interface between the controller 520 and the power supply 530 is the I2C method, the data field of the SDA transmitted by the controller 520 can include the operation mode value.

[0063] In operation S530, the power supply 530 can set the frequency of the gate signal and / or the number of power transistors based on the power control signal. In an embodiment, the power supply 530 can set the frequency of the gate signal and / or the number of power transistors provided in the first power control signal. For example, the power supply 530 can receive SDA from the controller 520 in synchronization with SCL. In response to a write command of SDA, the power supply 530 can write or set the frequency of the gate signal and / or the number of power transistors provided in the data field to an internal register or the like. In an embodiment, the power supply 530 can store the table 232 and set the frequency of the gate signal and / or the number of power transistors based on the operation mode value in the first power control signal.

[0064] In operation S540, the power supply 530 can transmit a setting completion signal to the controller 520. In an embodiment, the power supply 530 can transmit the first response signal regarding the first power control signal to the controller 520 via the interface. The setting completion signal can be provided as a signal specified in a standard for a separate communication interface, or can be newly formed for the power control signal.

[0065] In operation S550, the controller 520 can determine whether the setting is completed. For example, the controller 520 can determine whether the setting is completed based on reception of the setting completion signal from the power supply 530.

[0066] When the controller 520 determines that the setting is completed (S550, Yes), the controller 520 can perform an operation according to an operation request in operation S560. For example, when the controller 520 receives the setting completion signal from the power supply 530, the controller 520 can perform an operation according to an operation request in operation S560.

[0067] When the controller 520 determines that the setting is not completed (S550, No), operation S520 can be performed. For example, when the controller 520 does not receive the setting completion signal from the power supply 530 for a certain period of time, or when the controller 520 receives a signal (e.g., NAK (an acronym for Negative Acknowledgement)) other than the setting completion signal from the power supply 530, operation S520 can be performed.

[0068] Figure 6 and Figure 7 is a diagram illustrating a step-down converter according to various embodiments.

[0069] Referring to Figure 1 , Figure 2 and Figure 6 , in some embodiments, the power supply 130 can include a plurality of step-down converters connected to a plurality of channels 140. Figure 6An example of a step-down converter 600 connected to one channel is shown. One of the step-down converters in the power supply 130 can generate one load supply voltage VO via one channel. The plurality of step-down converters can convert the system supply voltage VSYS to a plurality of load supply voltages VO1, VO2, …, and VOn by controlling the on operation of each of the plurality of power transistors 131 according to the frequency and the number of power transistors for the operation of the operation request REQ. The plurality of step-down converters can supply the plurality of load supply voltages VO1, VO2, …, and VOn to the plurality of elements 150 via the plurality of channels 140.

[0070] The plurality of channels 140 connected to the power supply 130 can include inductors and capacitors. Referring to Figure 6 For example, one channel connected to the step-down converter 600 can include an inductor LO and a capacitor CO. The inductor LO can be connected to a second node N2 and a fourth node N4. The second node N2 can be referred to as an output node corresponding to one channel connected to the power supply 130. The load supply voltage VO can be applied to the fourth node N4. The capacitor CO can be connected between the fourth node N4 and a second supply voltage VSS. An LC filter (e.g., a low pass filter (LPF)) can be formed by the inductor LO and the capacitor CO. The inductor LO and the capacitor CO can remove high frequency components occurring at the output terminal, allowing only direct current components to pass through and be delivered to the output terminal. The inductor LO stores energy generated by a load current IL that is the inductor current, and releases the stored energy. The load current IL that is the inductor current can flow due to the step-down conversion operation of the step-down converter 600.

[0071] In an embodiment, the step-down converter 600 can include a plurality of upper power transistors 610, a plurality of lower power transistors 620, an on-timer 630, and a power controller 640.

[0072] The plurality of upper power transistors 610 can be connected in series with the plurality of lower power transistors 620 between a first node N1 and a third node N3. A first supply voltage VDD can be applied to the first node N1. The first supply voltage VDD can be generated based on the system supply voltage VSYS. In an embodiment, the voltage level of the first supply voltage VDD can be less than or equal to the voltage level of the system supply voltage VSYS. A second supply voltage VSS can be applied to the third node N3. The second supply voltage VSS can have a voltage level lower than the voltage level of the first supply voltage VDD. In an embodiment, the second supply voltage VSS can have a ground voltage of a ground.

[0073] The number of each of the plurality of upper power transistors 610 and the plurality of lower power transistors 620 can be k. The number k can be a natural number greater than or equal to 2. In an embodiment, the number of each of the plurality of upper power transistors 610 and the plurality of lower power transistors 620 can correspond to the number of the plurality of operations that can be supported by the electronic device 100. For example, k can be set to a value greater than or equal to the number of the plurality of operations. When k is greater than the number of the plurality of operations, the power transistors exceeding the number of the plurality of operations can be spare transistors. In some embodiments, the plurality of upper power transistors 610 can be formed as P-type transistors, and the plurality of lower power transistors 620 can be formed as N-type transistors. In this case, the first electrodes of the plurality of upper power transistors 610 and the third electrodes of the plurality of lower power transistors 620 can be sources, and the second electrodes of the plurality of upper power transistors 610 and the fourth electrodes of the plurality of lower power transistors 620 can be drains. At least one of the plurality of upper power transistors 610 can be activated. At least one of the plurality of lower power transistors 620 can be activated. When the activated upper power transistor is turned on, the activated lower power transistor can be turned off. When the activated lower power transistor is turned on, the activated upper power transistor can be turned off. That is, the activated upper power transistor and the activated lower power transistor can be alternately turned on. As the number of the turned-on power transistors increases, the resistance value of the equivalent resistance of the turned-on power transistors decreases. As the number of the turned-on power transistors decreases, the resistance value of the equivalent resistance of the turned-on power transistors increases.

[0074] The plurality of upper power transistors 610 can be connected in parallel with each other between the first node N1 and the second node N2. Each of the plurality of upper power transistors 610 can include a gate for receiving an upper gate signal, a first electrode connected to a line to which the first supply voltage VDD is applied, and a second electrode connected to an output node (e.g., the second node N2). The gate electrode of the first upper power transistor HPTR1 can receive a first upper gate signal HGS1. The gate electrode of the second upper power transistor HPTR2 can receive a second upper gate signal HGS2. Similarly, the gate electrode of the kth upper power transistor HPTRk can receive a kth upper gate signal HGSk. The plurality of upper power transistors 610 can be turned on in response to the turn-on levels of the first upper gate signal HGS1 to the kth upper gate signal HGSk (or referred to as the plurality of upper gate signals HGS1 to HGSk). The first node N1 and the second node N2 are electrically connected to each other through the turned-on upper power transistors, and the first current can flow through the turned-on upper power transistors.

[0075] The plurality of lower power transistors 620 can be connected in parallel to each other between the second node N2 and the third node N3. Each of the plurality of lower power transistors 620 can include a gate electrode for receiving a lower gate signal, a third electrode connected to the third node N3, and a fourth electrode connected to the second node N2. The gate electrode of the first lower power transistor LPTR1 can receive a first lower gate signal LGS1. The gate electrode of the second lower power transistor LPTR2 can receive a second lower gate signal LGS2. Similarly, the gate electrode of the kth lower power transistor LPTRk can receive a kth lower gate signal LGSk. The plurality of lower power transistors 620 can be turned on in response to the on level of the first lower gate signal LGS1 to the kth lower gate signal LGSk (or referred to as the plurality of lower gate signals LGS1 to LGSk). The second node N2 and the third node N3 are electrically connected to each other through the turned-on lower power transistors, and a second current can flow through the turned-on lower power transistors.

[0076] The on timing timer 630 can receive a power control signal FPCSIG including a frequency of a gate signal. The on timing timer 630 can adjust an on time based on the frequency of the gate signal included in the power control signal FPCSIG. The on time can represent a time period during which the plurality of upper gate signals HGS1 to HGSk and the plurality of lower gate signals LGS1 to LGSk maintain an on level. The off time can represent a time period during which the plurality of upper gate signals HGS1 to HGSk and the plurality of lower gate signals LGS1 to LGSk maintain an off level. The on timing timer 630 can generate an on time signal OTSIG including the on time. The on time signal OTSIG can be provided to the power controller 640.

[0077] In an embodiment, as the frequency of the gate signal indicated by the power control signal FPCSIG increases, the on time can decrease. As the frequency of the gate signal indicated by the power control signal FPCSIG decreases, the on time can increase.

[0078] The power controller 640 can receive at least one of the on time signal OTSIG or a power control signal NPCSIG including a number of power transistors to be activated. The number of transistors included in the power control signal NPCSIG can indicate each of the number of activated upper power transistors and the number of activated lower power transistors. For example, when the number of transistors included in the power control signal NPCSIG is i (where i is an integer of 1 to k), each of the number of activated upper power transistors and the number of activated lower power transistors is i. For example, assuming that the number of transistors i is 2, then two of the upper power transistors will be activated, and two of the lower power transistors will be activated.

[0079] The power controller 640 can output at least one upper gate signal and at least one lower gate signal that are toggled back and forth between an on level and an off level based on the number of transistors included in the power control signal NPCSIG (e.g., the number of power transistors to be activated). For example, when the number of transistors included in the power control signal NPCSIG is 1, a first upper gate signal HGS1 and a first lower gate signal LGS1 can be toggled back and forth. For example, when the number of transistors included in the power control signal NPCSIG is 2, a second upper gate signal HGS2 and a second lower gate signal LGS2 can be toggled back and forth in addition to the first upper gate signal HGS1 and the first lower gate signal LGS1. Similarly, when the number of transistors included in the power control signal NPCSIG is i, first through ith upper gate signals and first through ith lower gate signals can be toggled back and forth.

[0080] The power controller 640 can adjust the frequencies of the plurality of upper gate signals HGS1 through HGSk and the plurality of lower gate signals LGS1 through LGSk based on the on time included in the on time signal OTSIG. The time periods during which the plurality of upper gate signals HGS1 through HGSk and the plurality of lower gate signals LGS1 through LGSk maintain the on level can be adjusted, and thus, the frequencies of the plurality of upper gate signals HGS1 through HGSk and the plurality of lower gate signals LGS1 through LGSk can be changed. In some embodiments, the power controller 640 can control the off times of the plurality of upper gate signals HGS1 through HGSk and the plurality of lower gate signals LGS1 through LGSk.

[0081] Figure 7 An example of a buck converter 700 connected to one lane is shown. Referring to Figure 1 、 Figure 2 and Figure 7 As described above with reference to Figure 6 , one buck converter 700 can be connected to one lane and can include a plurality of upper power transistors 710, a plurality of lower power transistors 720, an on timer 730, and a power controller 740. The plurality of upper power transistors 710, the plurality of lower power transistors 720, and the on timer 730 are as described above with reference to Figure 6 . The buck converter 700 can further include a first current sensor 750 and a second current sensor 760.

[0082] The first current sensor 750 can be connected to both terminals of the plurality of upper power transistors 710. When at least one of the upper power transistors 710 is turned on, the first current sensor 750 can sense a first current and output a first current sense signal CSS1 including a value of the sensed first current.

[0083] The second current sensor 760 can be connected to both terminals of the plurality of lower power transistors 720. When at least one of the plurality of lower power transistors 720 is turned on, the second current sensor 760 can sense a second current and output a second current sense signal CSS2 including a value of the sensed second current.

[0084] In some embodiments, the first current sensor 750 and the second current sensor 760 can be provided as components separate from the power controller 740. In some embodiments, the first current sensor 750 and the second current sensor 760 can be disposed inside the power controller 740 as components included in the power controller 740.

[0085] Since the components of the step-down converter 700 are electrically connected to each other to form a circuit path, the first current and the second current can correspond to the load current IL. Accordingly, sensing the first current and the second current can be equivalent to sensing the load current IL.

[0086] In embodiments, the power controller 740 can change the number of the upper gate signals and the number of the lower gate signals that are toggled back and forth based on changes in the first current sense signal CSS1 and the second current sense signal CSS2. In some embodiments, the power controller 740 can change the frequencies of the plurality of upper gate signals HGS1 to HGSk and the plurality of lower gate signals LGS1 to LGSk based on changes in the first current sense signal CSS1 and the second current sense signal CSS2. In some embodiments, when the value of the sensed load current IL increases, the power controller 740 can increase the frequencies of the plurality of upper gate signals HGS1 to HGSk and the plurality of lower gate signals LGS1 to LGSk and / or can increase the number of the plurality of upper power transistors 710 and the plurality of lower power transistors 720 that are activated. When the value of the sensed load current IL decreases, the power controller 740 can decrease the frequencies of the plurality of upper gate signals HGS1 to HGSk and the plurality of lower gate signals LGS1 to LGSk and / or can decrease the number of the plurality of upper power transistors 710 and the plurality of lower power transistors 720 that are activated.

[0087] Figure 8 is a timing diagram illustrating a load current and a plurality of gate signals according to the number of power transistors to be activated according to some embodiments.

[0088] Reference Figure 8In an embodiment, when the number PTR size (hereinafter, simply referred to as the number PTR size) of power transistors to be activated is 1, one upper power transistor to be activated and one lower power transistor to be activated can exist. For example, when the number PTR size is 1, the first upper power transistor HPTR1 and the first lower power transistor LPTR1 can be activated. The first upper gate signal HGS1 and the first lower gate signal LGS1 can be toggled. When the logic level of the first upper gate signal HGS1 and the logic level of the first lower gate signal LGS1 are at a logic low level, the first upper power transistor HPTR1 can be turned on and the first lower power transistor LPTR1 can be turned off. In this case, the load current IL can increase. When the logic level of the first upper gate signal HGS1 and the logic level of the first lower gate signal LGS1 are at a logic high level, the first upper power transistor HPTR1 can be turned off and the first lower power transistor LPTR1 can be turned on. In this case, the load current IL can decrease.

[0089] In an embodiment, when the number PTR size is 2, the first upper power transistor HPTR1 and the second upper power transistor HPTR2 can be activated, and the first lower power transistor LPTR1 and the second lower power transistor LPTR2 can be activated. The first upper gate signal HGS1 and the second upper gate signal HGS2 can be toggled, and the first lower gate signal LGS1 and the second lower gate signal LGS2 can be toggled. The increase / decrease trend of the load current IL can be the same as that when the number PTR size is 1.

[0090] In an embodiment, when the number PTR size is 3, the first to third upper power transistors HPTR1 to HPTR3 and the first to third lower power transistors LPTR1 to LPTR3 can be activated, and the first to third upper power transistors HPTR1 to HPTR3 and the first to third lower power transistors LPTR1 to LPTR3 can be toggled. The increase / decrease trend of the load current IL can be the same as described above.

[0091] In an embodiment, as the number PTR size decreases, the number of upper gate signals and lower gate signals to be toggled can decrease. As the number PTR size increases, the number of upper gate signals and lower gate signals to be toggled can increase. In an embodiment, when the number PTR size is k, a plurality of upper gate signals HGS1 to HGSk and a plurality of lower gate signals LGS1 to LGSk can be toggled.

[0092] In operation in which a relatively small load and load current IL occur, switching loss can mainly affect power efficiency. In this case, in an embodiment, the number PTR size can be reduced to increase the resistance value of the equivalent resistance, thereby reducing switching loss. As described above, there is an effect of improving the efficiency of power consumed in operation in which a relatively small load occurs.

[0093] In operation in which a relatively large load and load current IL occur, conduction loss can mainly affect power efficiency. In this case, in an embodiment, the number PTR size can be increased to reduce the resistance value of the equivalent resistance, thereby reducing conduction loss. As described above, there is an effect of improving the efficiency of power consumed in operation in which a relatively large load occurs.

[0094] Figure 9 is a timing chart illustrating a load current and a plurality of gate signals according to the frequency of the gate signal according to some embodiments.

[0095] Referring to Figure 6 , Figure 7 and Figure 9 , as the frequency FREQ in the power control signal FPCSIG increases, the frequency of the upper gate signal HGS and the lower gate signal LGS switched back and forth can also increase. "F1", "F2", or "F3" can be examples indicating the value of the frequency FREQ. It is assumed that "F1" is the smallest, "F2" is greater than "F1" and smaller than "F3", and "F3" is the largest.

[0096] In an embodiment, as the frequency FREQ increases in the order of "F1", "F2", and "F3", the period during which the upper gate signal HGS and the lower gate signal LGS switched back and forth maintain the on level gradually decreases, and the frequency of the upper gate signal HGS and the lower gate signal LGS switched back and forth can increase. As the period during which the upper gate signal HGS and the lower gate signal LGS switched back and forth maintain the on level changes, the increase / decrease trend of the load current IL can also change.

[0097] In operation in which a relatively small load occurs, an embodiment can reduce switching loss by reducing the frequency FREQ. As described above, there is an effect of improving power efficiency in operation in which a relatively small load occurs.

[0098] In operation in which a relatively large load occurs, an embodiment can reduce conduction loss by increasing the frequency FREQ. As described above, there is an effect of improving power efficiency in operation in which a relatively large load occurs.

[0099] Figure 10 is a graph illustrating an example of power efficiency according to the number of power transistors to be activated according to some embodiments.

[0100] refer to Figure 10 The graph showing the relationship between power efficiency (PWR) and load current (IL) varies depending on the number of power transistors to be activated. The load current (IL) at maximum power efficiency also varies depending on the number of power transistors to be activated. (Reference) Figure 10 For example, the number of power transistors to be activated can increase in size in the following order: a first number PTR size 1, a second number PTR size 2, a third number PTR size 3, and a fourth number PTR size 4. That is, the first number PTR size 1 can be the smallest, and the fourth number PTR size 4 can be the largest. The load current IL that produces the maximum power efficiency among the first to fourth numbers PTR size 1, PTR size 2, PTR size 3, and PTR size 4 can be the first to fourth load currents IL11, IL12, IL13, and IL14. The magnitude of the load current can increase in the following order: the first load current IL11, the second load current IL2, the third load current IL3, and the fourth load current IL14. However, the embodiments are not limited to the above examples. The embodiment EMBDS can increase the number of power transistors to be activated when the load and load current IL increase, and can decrease the number of power transistors to be activated when the load and load current IL decrease. The embodiment EMBDS can provide maximum power efficiency for each operation by setting the number of power transistors to be activated in response to an operation request.

[0101] Figure 11 This is a graph illustrating an example of power efficiency based on the frequency of the gate signal according to some embodiments.

[0102] refer to Figure 11The graph showing the relationship between the power efficiency PWR efficiency and the load current IL can vary depending on the frequency of the gate signal. In each frequency graph, there can be a section of the graph that has a higher power efficiency PWR efficiency depending on the load current IL. For example, the amplitudes of the frequencies can increase in the following order: the first frequency FSW1, the second frequency FSW2, the third frequency FSW3, the fourth frequency FSW4, and the fifth frequency FSW5. That is, the first frequency FSW1 can be the smallest, and the fifth frequency FSW5 can be the largest. The first to fourth load currents IL21, IL22, IL23, IL24 can represent the load current IL when the amplitude relationship of the power efficiency PWR efficiency changes. For example, the fourth load current IL24 can represent the load current IL when the power efficiency PWR efficiency of the fifth frequency FSW5 in the graph is higher than the power efficiency PWR efficiency of the fourth frequency FSW4 in the graph. The section in which the load current IL is greater than the fourth load current IL24 can represent a section in which a relatively large load occurs, that is, an interval in which a heavy load occurs. The section in which the load current IL is less than the fourth load current IL24 can represent a section in which a relatively small load occurs, that is, a section in which a light load occurs. The embodiment EMBDS can increase the frequency of the gate signal as the load and the load current IL increase, and can decrease the frequency of the gate signal as the load and the load current IL decrease. The embodiment EMBDS can provide the maximum power efficiency for each operation by setting the frequency of the gate signal in response to an operation request.

[0103] Figure 12 is a graph showing an example of the power efficiency according to operations according to some embodiments.

[0104] Referring to Figure 12 , the graph showing the relationship between the power efficiency PWR efficiency and the load current IL can vary depending on the operation. The load current IL showing the maximum efficiency for a plurality of operations can also be different from each other, and can be represented as the first to fourth load currents IL31, IL32, IL33, and IL34. The first to fourth load currents IL31, IL32, IL33, and IL34 can correspond to the first to fourth load currents IL11, IL12, IL13, and IL14 of Figure 10 and / or the first to fourth load currents IL21, IL22, IL23, and IL24 of Figure 11 . The embodiment EMBDS can provide the maximum power efficiency for each operation by setting the frequency and / or the number of the gate signal (for example, the number of power transistors to be activated) according to the operation in response to an operation request.

[0105] Figure 13 is a block diagram of an electronic device 1300 according to an embodiment.

[0106] Referring to Figure 13 Like the electronic devices 100 and 200, the electronic device 1300 can include a CPU 1310, a controller 1320, a power supply 1330, first to nth channels 1340_1 to 1340_n, and first to nth elements 1350_1 to 1350_n. In describing the CPU 1310, the controller 1320, the power supply 1330, the first to nth channels 1340_1 to 1340_n, and the first to nth elements 1350_1 to 1350_n illustrated in FIG. 13, descriptions that are repeated with those given above with reference to FIGS. 1 to 12 are omitted for the sake of brevity. Figure 13 Figure 1 Figure 2

[0107] The controller 1320 can receive an operation request REQ from the CPU 1310. The controller 1320 can transmit a power control signal PCSIG[m:0] indicating an operation of the operation request REQ to the power supply 1330.

[0108] Each of the controller 1320 and the power supply 1330 can be provided with at least one pin. For example, the controller 1320 can have a plurality of first pins PN1, and the power supply 1330 can have a plurality of second pins PN2. The controller 1320 can be communicatively connected to the power supply 1330 by physically connecting the plurality of first pins PN1 to the plurality of second pins PN2. In an embodiment, the plurality of first pins PN1 and the plurality of second pins PN2 can be provided as general-purpose input / output (GPIO), dedicated pins, or input / output (IO), etc. However, embodiments are not limited to the above-described embodiment.

[0109] ​​​The power control signal PCSIG[m:0] can include signals transmitted via the plurality of first pins PN1 and the plurality of second pins PN2. The power control signal PCSIG[m:0] can include a plurality of bits. For example, the power control signal PCSIG[m:0] can include m+1 bits. However, embodiments are not limited to the above example. The number m can be a natural number greater than or equal to 1. One bit of the power control signal PCSIG[m:0] can be output via one first pin and transmitted to the power supply 1330 via one second pin. The number of bits in the power control signal PCSIG[m:0] can be greater than or equal to the number of connection pins. When the number of each of the first pins PN1 and the second pins PN2 is 3, the number of bits of the power control signal PCSIG[m:0] can be 3, and m can be 2. The number of bits of the power control signal PCSIG[m:0], the plurality of first pins PN1, and the plurality of second pins PN2 can express all of a plurality of operations. For example, in the case where the number of the plurality of operations is 4, the number of the plurality of first pins PN1 and the number of the plurality of second pins PN2 can be 2 or more, and m can be 1. In this case, the power control signal PCSIG[1:0] can include "00", "01", "10", or "11". The values "00", "01", "10", or "11" can represent the operation mode values of each of the four operations.

[0110] The power supply 1330 can include a plurality of power transistors PTR 1331, and can store a table 1332. In embodiments, the table 1332 can include a first table of Figure 3 In some embodiments, the table 1332 can further include a second table of Figure 4

[0111] Based on the power control signal PCSIG[m:0] and the table 1332, the power supply 1330 can generate at least one gate signal that is input to at least one power transistor to be activated among the plurality of power transistors 1331. The power supply 1330 can set the frequency of the gate signal and / or the number of power transistors corresponding to the operation mode value of the power control signal PCSIG[m:0] based on the table stored therein.

[0112] Based on the conduction of the at least one power transistor, the power supply 1330 can generate a plurality of load supply voltages VO1, VO2,..., and VOn based on the system supply voltage VSYS.

[0113] According to the above-described embodiments, power consumption of the electronic device 1300 can be reduced and optimized, and TCO of a user can be reduced.

[0114] Figure 14 ​is a diagram illustrating setting of a frequency and / or a number of power transistors to be activated based on pin connections according to some embodiments.

[0115] Referring to Figure 14 , operation S1410 is the same as operation S510, and a repeated description thereof is omitted for the sake of brevity. In operation S1420, the controller 1420 can transmit a power control signal to the power supply 1430. For example, in some embodiments, the controller 1420 can transmit a first power control signal to the power supply 1430 via a plurality of first pins PN1 in response to a first operation request of the CPU 1310. In some embodiments, similar to the power control signal PCSIG[m:0] of Figure 13 , the first power control signal can include an operation mode value.

[0116] In operation S1430, based on the power control signal, the power supply 1430 can set a frequency and / or a number (e.g., a number of power transistors to be activated) of gate signals corresponding to the operation mode value in the table stored therein.

[0117] In operation S1440, the controller 1420 can perform an operation according to the operation request. Referring to Figure 13 , for example, the controller 1320 can have a plurality of first pins PN1 for transmitting the power control signal PCSIG[m:0], and the power supply 1330 can have a plurality of second pins PN2 connected to the plurality of first pins PN1 and receiving the power control signal PCSIG[m:0]. After transmitting the power control signal PCSIG[m:0] to the power supply 1330, the controller 1320 can perform an operation by generating a command for indicating that the operation is performed.

[0118] Figure 15 and Figure 16 are block diagrams of electronic devices 1500 and 1600 according to some embodiments.

[0119] Referring to Figure 15 , similar to the electronic devices 100, 200, and 1300, the electronic device 1500 can include a CPU 1510, a controller 1520, a power supply 1530, first to nth channels 1540_1 to 1540_n, and first to nth elements 1550_1 to 1550_n. In describing the CPU 1510, the controller 1520, the power supply 1530, the first to nth channels 1540_1 to 1540_n, and the first to nth elements 1550_1 to 1550_n shown in Figure 15 , a repeated description thereof is omitted for the sake of brevity. Referring to Figure 1 , the controller 1520 can transmit a power control signal to the power supply 1530. For example, in some embodiments, the controller 1520 can transmit a first power control signal to the power supply 1530 via a plurality of first pins PN1 in response to a first operation request of the CPU 1510. In some embodiments, similar to the power control signal PCSIG[m:0] ofFigure 2 and Figure 13 The description given above is repeated.

[0120] In an embodiment, the CPU 1510 can store a table 1511, such as the above-described tables 121, 232, and 1332. The CPU 1510 can communicate with the power supply 1530 via an interface. In some embodiments, the interface can include an I2C interface or the like. The CPU 1510 can transmit a power control signal PCSIG to the power supply 1530 based on the table 1511. In an embodiment, the power control signal PCSIG can include a number (e.g., a number of power transistors to be activated) and / or a frequency of a gate signal. In an embodiment, the power control signal PCSIG can include an operation mode value. The CPU 1510 can set the frequency of the gate signal and / or the number of power transistors corresponding to the operation mode value of the power control signal PCSIG based on the table stored therein.

[0121] In an embodiment, the power supply 1530 can transmit a setting completion signal SDSIG to the CPU 1510 via the interface.

[0122] Referring to Figure 16 Like the electronic devices 100, 200, 1300, and 1500, the electronic device 1600 can include a CPU 1610, a controller 1620, a power supply 1630, first to nth channels 1640_1 to 1640_n, and first to nth elements 1650_1 to 1650_n. In the description Figure 16 The descriptions given above with respect to the CPU 1610, the controller 1620, the power supply 1630, the first to nth channels 1640_1 to 1640_n, and the first to nth elements 1650_1 to 1650_n are repeated. Figure 1 , Figure 2 , Figure 13 and Figure 15 The descriptions given above are repeated.

[0123] In an embodiment, the CPU 1610 can transmit a power control signal PCSIG[m:0] indicating an operation of the operation request REQ to the power supply 1630. To this end, each of the CPU 1610 and the power supply 1630 can have at least one pin. For example, the CPU 1610 can have a plurality of first pins PN1, and the power supply 1630 can have a plurality of second pins PN2. The plurality of first pins PN1 and the plurality of second pins PN2 can be provided as GPIOs, dedicated pins, or IOs, etc. The power control signal PCSIG[m:0] can be transmitted from the plurality of first pins PN1 to the plurality of second pins PN2. A bit value of the power control signal PCSIG[m:0] can represent an operation mode value.

[0124] The power supply 1630 can include a plurality of power transistors PTR 1631. The power supply 1630 can store a table 1632, such as the above-described tables 121, 232, 1332, and 1511. The power supply 1630 can set a frequency of a gate signal and / or a number of power transistors corresponding to the operation mode value of the power control signal PCSIG[m:0] based on the table stored therein.

[0125] According to the above-described embodiments, power consumption of the electronic devices 1500 and 1600 can be reduced and optimized, and TCO of a user can be reduced.

[0126] Figure 17 is a block diagram of an electronic system 1700 according to some embodiments.

[0127] Reference Figure 17 , the electronic system 1700 can be a system including one or more electronic devices. The electronic system 1700 can include a CPU 1710, a BMC 1720, a power supply 1730, a DRAM 1740, and a plurality of devices 1751, 1752, and 1753. In describing the CPU 1710, the BMC 1720, the power supply 1730, the DRAM 1740, and the plurality of devices 1751, 1752, and 1753, descriptions repeated with the above-described descriptions given with reference to Figure 1 、 Figure 2 、 Figure 13 、 Figure 15 and Figure 16 are omitted for the sake of brevity.

[0128] In some embodiments, the CPU 1710 can correspond to the CPU 1510 of Figure 15 , and can generate a power control signal PCSIG based on a table stored therein. In an embodiment, as described above with reference to Figure 1The power control signal PCSIG may include the frequency of the gate signal and the number of power transistors to be activated for the current operation to be performed. In an embodiment, as referenced above... Figure 2 The power control signal PCSIG may include an operating mode value corresponding to the current operation to be performed. The CPU 1710 and the power supply 1730 can communicate with each other via an interface, and the power supply 1730 can send an ACK signal, a NAK signal, or a setup completion signal SDSIG to the CPU 1710.

[0129] In some embodiments, CPU 1710 may correspond to Figure 16 The CPU 1510 generates a power control signal PCSIG[m:0]. The CPU 1710 can be communicatively connected to the power supply 1730 via at least one pin. The CPU 1710 can send the power control signal PCSIG[m:0] to the power supply 1730 via at least one pin. The power supply 1730 can set the frequency of the gate signal and / or the number of power transistors corresponding to the operating mode value of the power control signal PCSIG[m:0] based on a table stored therein.

[0130] In some embodiments, BMC 1720 may correspond to Figure 1 Controller 120 Figure 2 Controller 220 and / or Figure 5 The controller 520. According to an embodiment, the BMC 1720 can generate a power control signal PCSIG based on an operation request REQ received from the CPU 1710 and a table stored therein. In an embodiment, as referenced above... Figure 1 The power control signal PCSIG may include the frequency of the gate signal and the number of power transistors to be activated. In an embodiment, as referenced above... Figure 2 The power control signal PCSIG may include an operating mode value. The BMC 1720 and the power supply 1730 can communicate with each other via an interface, and the power supply 1730 can send an ACK signal, a NAK signal, or a setup complete signal SDSIG to the BMC 1720.

[0131] In some embodiments, BMC 1720 may correspond to Figure 13 Controller 1320 and Figure 14each of the controllers 1420. The BMC 1720 according to the embodiment can generate the power control signal PCSIG[m:0] based on the operation request REQ received from the CPU 1710. The BMC 1720 can be communicatively connected to the power supply 1730 via at least one pin. The power supply 1730 can set the frequency of the gate signal and / or the number of power transistors corresponding to the operation mode value of the power control signal PCSIG[m:0] based on a table stored therein.

[0132] In some embodiments, the power supply 1730 can sense the load current flowing through the power supply rail in order to monitor the power consumption of each power supply rail, as described above with reference to Figure 7

[0133] In some embodiments, the elements that receive the load supply voltage from the power supply 1730 via the plurality of channels can include, for example, the CPU 1710, the BMC 1720, the DRAM 1740, and the plurality of devices 1751, 1752, and 1753. The plurality of devices 1751, 1752, and 1753 can include, for example, a graphics card, a sound card, a storage device, a USB device, a NIC, etc.

[0134] According to the above-described embodiments, the power consumption of the electronic system 1700 can be reduced and optimized, and the TCO of the user can be reduced.

[0135] Figures 18 to 21 are block diagrams of storage systems 1800, 1900, 2000, and 2100 according to some embodiments. The above-described embodiments can be applied to Figures 18 to 21 the storage systems 1800, 1900, 2000, and 2100 illustrated.

[0136] Referring to Figure 18 , the storage system 1800 can include a host 1810 and a storage device 1820.

[0137] The host 1810 can manage operations such as storing data in the storage device 1820 and reading data from the storage device 1820. In an embodiment, the operations requested by the host 1810 to the storage device 1820 can include sequential read, sequential write, mixed operation, random read, and / or random write. In an embodiment, the host 1810 can include the above-described CPU. The host 1810 according to the embodiment can further include the BMC 1720 or the DRAM 1740, a power supply, etc. Figure 17

[0138] ​​In an embodiment, the host 1810 can provide an operation request REQ and a power control signal PCSIG to the storage controller 1821. The storage controller 1821 can provide the power control signal PCSIG to a power management integrated circuit (PMIC) 1822.

[0139] The storage device 1820 can include a storage medium for storing data in response to a request from the host 1810. For example, the storage device 1820 can include at least one of a solid state drive (SSD), an embedded memory, or a removable external memory. When the storage device 1820 includes the SSD, the storage device 1820 can include a device conforming to an NVMe standard. When the storage device 1820 includes the embedded memory or the external memory, the storage device 1820 can include a device conforming to a UFS or eMMC standard. The host 1810 and the storage device 1820 can each generate and transmit a packet according to a standard protocol adopted.

[0140] The storage device 1820 can include the storage controller 1821, the PMIC 1822, the volatile memory 1823, and the non-volatile memory 1824. The storage device 1820 can include at least one voltage regulator in addition to the PMIC 1822.

[0141] The storage controller 1821 can include a host interface, a memory interface, a CPU, a flash translation layer (FTL), a packet manager, a buffer memory, an error correction code (ECC) engine, and / or an advanced encryption standard (AES) engine.

[0142] The PMIC 1822 can perform the operations of the power supply described above. The PMIC 1822 can supply a plurality of load supply voltages to each of the storage controller 1821, the volatile memory 1823, and the non-volatile memory 1824 via a plurality of channels. For example, the PMIC 1822 can supply a first load supply voltage VO1s to the storage controller 1821 via some of the plurality of channels. For example, the PMIC 1822 can supply a second load supply voltage VO2s to the volatile memory 1823 via some of the plurality of channels. For example, the PMIC 1822 can supply a third load supply voltage VO3s to the non-volatile memory 1824 via some of the plurality of channels. The PMIC 1822 can include a plurality of power transistors PTR 1825.

[0143] The volatile memory 1823 can store data when power is supplied to the storage device 1820.

[0144] The non-volatile memory 1824 can store data regardless of power. When the non-volatile memory 1824 includes a flash memory, the flash memory can include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. In some embodiments, the storage device 1820 can include other types of non-volatile memory. For example, in some embodiments, the storage device 1820 can include magnetic random access memory (MRAM), spin transfer torque MRAM, conductive-bridge RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM, and / or other types of memory.

[0145] Referring to Figure 19 , the storage system 1900 can include a host 1910 and a storage device 1920. The storage device 1920 can include a storage controller 1921, a PMIC 1922, a volatile memory 1923, and a non-volatile memory 1924. Repetitive description as given above with reference to Figure 18 is omitted for the sake of brevity.

[0146] In an embodiment, the host 1910 can provide an operation request REQ to the storage controller 1921 and supply a system supply voltage VSYS to the PMIC 1922.

[0147] The storage controller 1921 can transmit a command for instructing an operation to be performed to the volatile memory 1923 and / or the non-volatile memory 1924 based on the operation request REQ.

[0148] In an embodiment, the storage controller 1921 can store a table 1925. The table 1925 can include a first table of Figure 3 . The table 1925 can further include a second table of Figure 4 . The storage controller 1921 can correspond to the controller 120 of Figure 1 and the controller 520 of Figure 5 . The storage controller 1921 can generate at least one power control signal PCSIG based on the operation request REQ received from the host 1910 and the table 1925. In an embodiment, the at least one power control signal PCSIG can include a first power control signal including a frequency of a gate signal and / or a second power control signal including a number of power transistors to be activated. The storage controller 1921 and the PMIC 1922 can communicate with each other via an interface, and the PMIC 1922 can transmit an ACK signal, a NAK signal, or a set completion signal SDSIG to the storage controller 1921.

[0149] In an embodiment, when the storage device 1920 is in the idle state, the storage controller 1921 can transmit, in the idle state, a fourth power control signal including a frequency of the gate signal and a number of power transistors for the background operation to the PMIC 1922. In some embodiments, the storage controller 1921 can transmit a command to the volatile memory 1923 and / or the non-volatile memory 1924 to instruct that the background operation is performed. For example, in the idle state, the storage controller 1921 can transmit a command (a read command, a write command, etc.) to the non-volatile memory 1924 to perform a garbage collection operation.

[0150] In an embodiment, the PMIC 1922 can set at least one power transistor to be activated based on the second power control signal, and generate at least one gate signal that is toggled back and forth.

[0151] In an embodiment, in the idle state, the PMIC 1922 can generate at least one gate signal that is toggled back and forth based on the fourth power control signal.

[0152] Reference Figure 20 , the storage system 2000 can include a host 2010 and a storage device 2020. For the sake of brevity, the repetitive description as given above is omitted.

[0153] In an embodiment, the storage controller 2021 can correspond to the controller 220 of Figure 2 and the controller 520 of Figure 5 . The storage controller 2021 can generate at least one power control signal PCSIG based on an operation request REQ received from the host 2010 and an internal algorithm. The power control signal PCSIG according to an embodiment can include an operation mode value as described above with reference to Figure 2 . The storage controller 2021 can communicate with the PMIC 2022 via an interface.

[0154] In an embodiment, the storage controller 2021 can correspond to the controller 1320 of Figure 13 and the controller 1420 of Figure 14 . The storage controller 2021 can generate a power control signal PCSIG including an operation mode value based on an operation request REQ received from the host 2010 and an internal algorithm. The storage controller 2021 can be communicatively connected to the PMIC 2022 via at least one pin.

[0155] In an embodiment, when the storage device 2020 is in the idle state, the storage controller 2021 can transmit a third power control signal representing a background operation to the PMIC 2022 in the idle state. In addition, the storage controller 2021 can transmit a command for instructing that the background operation is performed to the volatile memory 2023 and / or the non-volatile memory 2024.

[0156] In an embodiment, the PMIC 2022 can store a table 2025. The table 2025 can include a first table of Figure 3 The table 2025 can further include a second table of Figure 4 .

[0157] In an embodiment, the PMIC 2022 can set at least one power transistor to be activated based on the first power control signal and the table 2025, and generate at least one gate signal that is toggled back and forth.

[0158] In an embodiment, in the idle state, the PMIC 2022 can generate at least one gate signal that is toggled back and forth based on the third power control signal and the table 2025.

[0159] Referring to Figure 21 , the storage system 2100 can include a host 2110 and a storage device 2120. For the sake of brevity, the repetitive description as given above is omitted.

[0160] In an embodiment, the host 2110 can store a table 2111. The table 2111 can include a first table of Figure 3 The table 2111 can further include a second table of Figure 4 .

[0161] In an embodiment, the host 2110 can provide at least one power control signal PCSIG to the PMIC 2122 based on an operation request REQ and the table 2111. The host 2110 can include a BMC 1720 of Figure 17 In an embodiment, the at least one power control signal PCSIG can include a first power control signal including a frequency of a gate signal and / or a second power control signal including a number of power transistors to be activated. The host 2110 and the PMIC 2122 can communicate with each other via an interface, or can be communicatively connected to each other via at least one pin.

[0162] Although Figure 21The table is not shown, but according to some embodiments, the PMIC 2122 can store a table, such as the table 2111, the host 2110 can provide the PMIC 2122 with a power control signal PCSIG including an operating mode value, and the PMIC 2122 can set the frequency of the gate signal and / or the number of power transistors based on the operating mode value and the table.

[0163] According to the above embodiments, the power consumption of the storage systems 1800, 1900, 2000, and 2100 can be reduced and optimized, and the TCO of the user can be reduced.

[0164] Figure 22 is a flowchart illustrating a method of operating an electronic device according to some embodiments.

[0165] Referring to Figure 22 Operation S2210 is to generate target operation information indicating a target operation. Referring to Figure 1 For example, the CPU 110 can generate the target operation information and transmit the target operation information to the controller 120.

[0166] Operation S2220 is to set a target frequency and a target number corresponding to the target operation of the target operation information. For example, the target frequency and the target number can be set based on a table. As described above, the table can include the frequency of the gate signal for each operation and the number of power transistors to be turned on. The target frequency can include a specific frequency of the gate signal. The target number can include a specific number of upper power transistors and lower power transistors to be activated.

[0167] Operation S2230 is to provide the gate signal having the target frequency to the target number of power transistors among the plurality of power transistors in the power supply. For example, the upper gate signal and the lower gate signal input to the upper power transistors and the lower power transistors to be activated can be switched back and forth.

[0168] Operation S2240 is to generate a load supply voltage based on the system supply voltage based on the turning on of the target number of power transistors.

[0169] In some embodiments, the table can include a first frequency group and a first number group corresponding to a plurality of foreground operations. The frequency group can include one or more values having the frequency of the gate signal as a parameter. The number group can include one or more values having the number of upper power transistors and lower power transistors as a parameter.

[0170] In an embodiment, the foreground operations can include sequential read, sequential write, random read, and random write. The first frequency group can include a first frequency of the gate signal set for the random read, a second frequency of the gate signal set for the sequential read, a third frequency of the gate signal set for the random write, and a fourth frequency of the gate signal set for the sequential write. The first number group can include a first number of the power transistor set for the random read, a second number of the power transistor set for the sequential read, a third number of the power transistor set for the random write, and a fourth number of the power transistor set for the sequential write.

[0171] In an embodiment, in the table, the first frequency can be the smallest, and the fourth frequency can be the largest. In the table, the first number can be the smallest, and the fourth number can be the largest.

[0172] In an embodiment, the table can further include a second frequency group and a second number group corresponding to a plurality of background operations.

[0173] In an embodiment, the method of operating the electronic device can further include monitoring a load current corresponding to a load supply voltage, and changing the target number of the power transistor and the target frequency of the gate signal based on a monitoring result. The embodiments described above are the same as the embodiments described above with reference to Figure 7 In an embodiment, the method of operating the electronic device can further include monitoring a load current corresponding to a load supply voltage, and changing the target number of the power transistor and the target frequency of the gate signal based on a monitoring result. The embodiments described above are the same as the embodiments described above with reference to

[0174] In an embodiment, changing the target number of the power transistor and the target frequency of the gate signal based on the monitoring result can include increasing the target number of the power transistor and the target frequency of the gate signal based on a first monitoring result that a first load current that is increasing has been monitored, and decreasing the target number of the power transistor and the target frequency of the gate signal based on a second monitoring result that a second load current that is decreasing has been monitored. The embodiments described above are the same as the embodiments described above with reference to Figure 7 In an embodiment, changing the target number of the power transistor and the target frequency of the gate signal based on the monitoring result can include increasing the target number of the power transistor and the target frequency of the gate signal based on a first monitoring result that a first load current that is increasing has been monitored, and decreasing the target number of the power transistor and the target frequency of the gate signal based on a second monitoring result that a second load current that is decreasing has been monitored. The embodiments described above are the same as the embodiments described above with reference to

[0175] While various embodiments have been particularly shown and described with reference to the accompanying drawings, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An electronic device, comprising: The controller is configured to: A storage table, the table including the gate signal frequency and the number of power transistors for multiple operations, and Based on the table and the operation request to perform the operation, a power control signal is output, the power control signal including at least one of a gate signal frequency for the operation or a number of power transistors for the operation; and A power supply, comprising a plurality of power transistors receiving a plurality of gate signals, is configured to: Based on the power control signal, at least one gate signal is generated and input to at least one power transistor among the plurality of power transistors, and Based on the conduction of the at least one power transistor, a load supply voltage is generated based on the system supply voltage.

2. The electronic device of claim 1, wherein the power control signal includes a first power control signal and a second power control signal, the first power control signal including the gate signal frequency, and the second power control signal including the number of power transistors, and The power source includes: Multiple power transistors, each power transistor including a gate configured to receive a gate signal, a first electrode connected to a first node receiving a first supply voltage, and a second electrode connected to a second node; Multiple power transistors, each power transistor including a gate configured to receive a power gate signal, a third electrode connected to a third node receiving a second supply voltage, and a fourth electrode connected to the second node; On-time timer, the on-time timer being configured as follows: Receive the first power control signal, Based on the frequency of the gate signal indicated by the first power control signal, the on-time is adjusted, the on-time indicating the period during which the plurality of gate signals maintain an on-level; as well as Generate a conduction time signal based on the conduction time; and A power controller, configured to: Receive at least one of the conduction time signal or the second power control signal. In response to the second power control signal, based on the number of power transistors indicated by the second power control signal, at least one upper gate signal and at least one lower gate signal are output that switch back and forth between the on-level and off-level. and In response to the on-time signal, the frequencies of at least one upper gate signal provided to the plurality of upper power transistors and at least one lower gate signal provided to the plurality of lower power transistors are adjusted based on the on-time.

3. The electronic device according to claim 2, wherein, The power supply also includes: A first current sensor, configured to sense a first current flowing through the plurality of power transistors and configured to output a first current sensing signal including a value of the first current; and A second current sensor, configured to sense a second current flowing through the plurality of lower-power transistors and configured to output a second current sensing signal including the value of the second current, and The power controller is configured to change at least one of the following based on the first current sensing signal and the second current sensing signal: the frequency of each of the at least one upper gate signal and the at least one lower gate signal that are switched back and forth, or the number of the plurality of upper power transistors and the plurality of lower power transistors.

4. The electronic device of claim 3, wherein the first current and the second current correspond to the load current output from the second node, and The power controller is configured to: As the value of the load current increases, the frequency of each of the at least one upper gate signal and the at least one lower gate signal that switch back and forth, and the number of the plurality of upper power transistors and the plurality of lower power transistors are increased. When the value of the load current decreases, the frequency of each of the at least one upper gate signal and the at least one lower gate signal that switch back and forth, and the number of the plurality of upper power transistors and the plurality of lower power transistors are reduced.

5. The electronic device according to claim 1, wherein: The multiple operations include sequential read, sequential write, random read, and random write, and The table includes a first gate signal frequency and a first number of power transistors for the random read, a second gate signal frequency and a second number of power transistors for the sequential read, a third gate signal frequency and a third number of power transistors for the random write, and a fourth gate signal frequency and a fourth number of power transistors for the sequential write.

6. The electronic device of claim 5, wherein in the table, the first gate signal frequency has a minimum value and the fourth gate signal frequency has a maximum value, and The first number of power transistors has a minimum value, and the fourth number of power transistors has a maximum value.

7. The electronic device according to claim 1, wherein, The controller is configured to send a first power control signal to the power supply via an interface in response to a first operation request received from an external source. The power supply is configured to send a first response signal regarding the first power control signal to the controller via the interface.

8. The electronic device of claim 1, wherein the power supply further comprises a plurality of buck converters configured to convert the system supply voltage into a plurality of load supply voltages by controlling the on-state operation of each of the plurality of power transistors according to the gate signal frequency and the number of power transistors, and configured to output the plurality of load supply voltages via a plurality of channels.

9. An electronic device, comprising: The controller is configured to: Receive operation requests to perform operations, and In response to the operation request, a power control signal indicating the operation is output; and A power supply, comprising a plurality of power transistors receiving a plurality of gate signals, is configured to: A storage table, comprising the gate signal frequencies and the number of power transistors for multiple operations, Based on the power control signal and the table, at least one gate signal is generated and input to at least one power transistor among the plurality of power transistors. Based on the conduction of the at least one power transistor, a load supply voltage is generated based on the system supply voltage.

10. The electronic device of claim 9, wherein the power control signal comprises a first power control signal and a second power control signal, the first power control signal comprising the gate signal frequency corresponding to the operation in the table, and the second power control signal comprising the number of power transistors corresponding to the operation in the table, and The power supply also includes: Multiple power transistors, each power transistor including a gate configured to receive a gate signal, a first electrode connected to a first node receiving a first supply voltage, and a second electrode connected to a second node; Multiple power transistors, each power transistor including a gate configured to receive a power gate signal, a third electrode connected to a third node receiving a second supply voltage, and a fourth electrode connected to the second node; On-time timer, the on-time timer being configured as follows: Receive the first power control signal, Based on the frequency of the gate signal indicated by the first power control signal, the on-time is adjusted, the on-time indicating the period during which the plurality of gate signals maintain an on-level; Generate an on-time signal including the on-time; and A power controller, configured to: Receive at least one of the conduction time signal or the second power control signal. In response to the second power control signal, based on the number of power transistors indicated by the second power control signal, at least one upper gate signal and at least one lower gate signal are output that switch back and forth between the on-level and off-level. and In response to the on-time signal, the frequencies of at least one upper gate signal provided to the plurality of upper power transistors and at least one lower gate signal provided to the plurality of lower power transistors are adjusted based on the on-time.

11. The electronic device according to claim 10, wherein, The power supply also includes: A first current sensor, configured to sense a first current flowing through the plurality of power transistors and configured to output a first current sensing signal including a value of the first current; and A second current sensor, configured to sense a second current flowing through the plurality of lower-power transistors and configured to output a second current sensing signal including the value of the second current, and The power controller is configured to change at least one of the following based on the first current sensing signal and the second current sensing signal: the frequency of each of the at least one upper gate signal and the at least one lower gate signal that are switched back and forth, or the number of the plurality of upper power transistors and the plurality of lower power transistors.

12. The electronic device according to claim 9, wherein: The multiple operations include sequential read, sequential write, random read, and random write, and The table includes a first gate signal frequency and a first number of power transistors for the random read, a second gate signal frequency and a second number of power transistors for the sequential read, a third gate signal frequency and a third number of power transistors for the random write, and a fourth gate signal frequency and a fourth number of power transistors for the sequential write.

13. The electronic device of claim 12, wherein in the table, the first gate signal frequency has a minimum value and the fourth gate signal frequency has a maximum value, and In the table, the first number of power transistors has a minimum value and the fourth number of power transistors has a maximum value.

14. The electronic device of claim 9, wherein the controller is configured to, in response to a first operation request requesting the execution of a first operation, send a first power control signal indicative of the first operation to the power supply via an interface, and The power supply is configured to send a first response signal regarding the first power control signal to the controller via the interface.

15. The electronic device according to claim 9, wherein, The controller includes at least one first pin for transmitting the power control signal. The power supply includes at least one second pin, which is connected to the at least one first pin and receives the power control signal. The controller is configured to generate a command to perform the operation after the power control signal is sent to the power source.

16. A storage system, comprising: The host, which is configured as follows: The storage table includes the gate signal frequency and the number of power transistors for each of the plurality of operations. Generate an operation request to perform the operation. Generate one of a first power control signal and a second power control signal, the first power control signal indicating the operation, and the second power control signal including a gate signal frequency and the number of power transistors for the operation indicated by the first power control signal. Generate system power supply voltage; and Storage device, the storage device being configured to: Store the table, The system receives the operation request, one of the first power control signal or the second power control signal, and the system supply voltage. Based on either the first power control signal or the second power control signal, the conduction operation of a plurality of power transistors is controlled. Based on the multiple power transistors that are turned on, the system supply voltage is converted into the load supply voltage, and Perform the operation described above.

17. The storage system of claim 16, wherein the storage device receives the first power control signal, and in, The storage device includes: Memory; A storage controller configured to send a command to the memory to perform the operation based on the operation request; and Power management integrated circuit (PMIC), the PMIC including the plurality of power transistors, the PMIC being configured to: Based on the first power control signal and the table, at least one gate signal is generated and input to at least one power transistor among the plurality of power transistors. The load supply voltage is generated based on the conduction of the at least one power transistor.

18. The storage system of claim 17, wherein the table includes a plurality of first gate signal frequencies and a plurality of first numbers of power transistors for each of a plurality of foreground operations, and a plurality of second numbers of second gate signal frequencies and power transistors for each of a plurality of background operations. The storage controller in the idle state is configured as follows: Send a third power control signal to the PMIC instructing background operation, and Send a second command to the memory to execute the background operation, and The PMIC is configured to generate the at least one gate signal based on the third power control signal and the table.

19. The storage system of claim 16, wherein the storage device receives the second power control signal, and in, The storage device includes: Memory; A storage controller configured to store the table and configured to send a first command to the storage to perform the operation based on the operation request; and Power management integrated circuit (PMIC), the PMIC including the plurality of power transistors, the PMIC being configured to: Based on the second power control signal, at least one gate signal is generated and input to at least one power transistor among the plurality of power transistors, and The load supply voltage is generated based on the conduction of the at least one power transistor.

20. The storage system of claim 19, wherein the table includes a plurality of first gate signal frequencies and a plurality of first numbers of power transistors for each of a plurality of foreground operations, and a plurality of second numbers of second gate signal frequencies and power transistors for each of a plurality of background operations. The storage controller in the idle state is configured as follows: A fourth power control signal is sent to the PMIC, the fourth power control signal including a second gate signal frequency for background operation and a second number of power transistors, and Send a second command to the memory to execute the background operation, and The PMIC in the idle state is configured to generate the at least one gate signal based on the fourth power control signal.

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