Voltage monitor and off-chip driver of memory device

Abstract

The present disclosure provides a voltage monitor for a memory device, and an off-chip driver (OCD), which is provided for the memory device. The voltage monitor includes a first voltage divider, a bridge switch, an OCD, and a control circuit. The first voltage divider receives an internal voltage in the memory device and divides the internal voltage to generate a sensing signal on a sensing node. The bridge switch is coupled between the sensing node and the connection pad. The OCD includes a pull-up circuit and a pull-down circuit. The control circuit is coupled to the bridge switch and the OCD. In the test mode, the control circuit conducts the bridge switch. In the test mode, the control circuit provides a bias voltage to the OCD, so that a first current value of a first leakage current flowing through the pull-up circuit is matched with a second current value of a second leakage current flowing through the pull-down circuit.

Description

Technical Field

[0001] This disclosure relates to a voltage monitor and off-chip driver (OCD) for a memory device. Background Technology

[0002] Figure 1 This diagram illustrates the off-chip driver and switches. Typically, memory devices require a set resistor value to determine at least one operating parameter. This set resistor value is provided by the off-chip driver (OCD) 11 via an external matching resistor provided by the DQPAD connection pad.

[0003] To reduce the number of connection pads in the memory device, the memory device monitors a sensing signal SSEN corresponding to the internal voltage within the memory device via connection pad DQPAD. In test mode, switch 12 is turned on. The pull-up switch MP and pull-down switch MN of OCD 11 are turned off in response to enable signals PUPEN and PDNEN. Therefore, the memory device can monitor its internal voltage via connection pad DQPAD. However, pull-up switch MP and pull-down switch MN each have a relatively low absolute value of their critical voltage. This may result in a sub-critical leakage current corresponding to either pull-up switch MP or pull-down switch MN. In test mode, leakage current is generated flowing through at least one of pull-up switch MP and pull-down switch MN to connection pad DQPAD. Therefore, the sensing signal SSEN on connection pad DQPAD is inaccurate.

[0004] Therefore, improving the accuracy of the sensing signal SSEN located on the DQPAD connection pad is one of the key research and development focuses for those skilled in the art. Summary of the Invention

[0005] This disclosure provides a voltage monitor for a memory device including a connection pad and an off-chip driver (OCD). In test mode, the voltage monitor can balance leakage current in the OCD to improve the accuracy of the sensing signal located on the connection pad corresponding to the internal voltage in the memory device.

[0006] In one embodiment disclosed herein, a voltage monitor for a memory device includes a first voltage divider, a bridge switch, an OCD, and control circuitry. The first voltage divider is coupled to a sensing node. The first voltage divider receives an internal voltage in the memory device and divides the internal voltage to generate a sensing signal at the sensing node. A first terminal of the bridge switch is coupled to the sensing node. A second terminal of the bridge switch is coupled to a connection pad. The OCD includes a pull-up circuit and a pull-down circuit. The pull-up circuit is coupled between a high reference voltage and a connection pad. The pull-down circuit is coupled between a connection pad and a low reference voltage. Control circuitry is coupled to the bridge switch and the OCD. In a test mode, the control circuitry turns on the bridge switch. In the test mode, the control circuitry provides a bias voltage to the OCD such that a first current value of a first leakage current flowing through the pull-up circuit matches a second current value of a second leakage current flowing through the pull-down circuit.

[0007] In one embodiment disclosed herein, the OCD includes a connection pad, a pull-up circuit, a pull-down circuit, and a control circuit. The connection pad outputs a sense signal corresponding to an internal voltage in the memory device. The pull-up circuit includes a control switch and a pull-up switch. A first terminal of the control switch is coupled to a high reference voltage. The pull-up switch is coupled between a second terminal of the control switch and the connection pad. The pull-down circuit is coupled between the connection pad and a low reference voltage. The control circuit is coupled to the pull-up circuit. When the memory device is in test mode, the control circuit disconnects the control switch and provides a bias voltage to the second terminal of the control switch to adjust the current flowing through the pull-up circuit.

[0008] In one embodiment disclosed herein, the OCD includes a connection pad, a pull-up circuit, a pull-down circuit, and a control circuit. The connection pad outputs a sense signal corresponding to an internal voltage in the memory device. The pull-up circuit is coupled between a high reference voltage and the connection pad. The pull-down circuit includes a control switch and a pull-down switch. A first terminal of the control switch is coupled to a low reference voltage. The pull-down switch is coupled between a second terminal of the control switch and the connection pad. The control circuit is coupled to the pull-down circuit. When the memory device is in test mode, the control circuit disconnects the control switch and provides a bias voltage to the second terminal of the control switch to adjust the current flowing through the pull-down circuit.

[0009] Based on the above, in test mode, the control circuit turns on the bridge switch and provides a bias voltage to the OCD, so that the first current value of the first leakage current flowing through the pull-up circuit matches the second current value of the second leakage current flowing through the pull-down circuit. Therefore, in test mode, the first leakage current and the second leakage current on the connection pad are balanced. In this way, the sensing signal on the connection pad is not disturbed by either the first or second leakage current in test mode. The voltage monitor can improve the accuracy of the sensing signal located on the connection pad in test mode.

[0010] To make the above easier to understand, several embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings are included to provide a further understanding of this disclosure and form part of this specification. These drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0012] Figure 1 A schematic diagram illustrating an external chip driver and a switch;

[0013] Figure 2 A schematic diagram illustrating a voltage monitor according to an embodiment of the present disclosure;

[0014] Figure 3 A schematic diagram illustrating a voltage monitor according to an embodiment of the present disclosure;

[0015] Figure 4 A schematic diagram illustrating a voltage monitor according to an embodiment of the present disclosure;

[0016] Figure 5 A schematic diagram illustrating a multi-source circuit according to an embodiment of the present disclosure;

[0017] Figure 6 A schematic diagram illustrating an off-chip driver (OCD) according to an embodiment of the present disclosure.

[0018] Explanation of icon numbers

[0019] 100, 200, 300: Voltage monitor

[0020] 110, 310, 3431: Voltage divider

[0021] 12: Switch

[0022] 120, 320: Bridge switch

[0023] 11, 130, 230, 430: External driver for chips, OCD

[0024] 131, 231, 331, 431: Pull-up circuits

[0025] 132, 232, 332, 432: Pull-down circuits

[0026] 140, 240, 340, 443: Control circuit

[0027] 341: Level shifter

[0028] 342: Logic Circuits

[0029] 343: Multi-source circuits

[0030] 3432: Selection Circuit

[0031] 3433: Voltage Regulator

[0032] AG: with the door

[0033] CP: Capacitor

[0034] DQPAD: Connecting Pad

[0035] ILN: Second Leakage Current

[0036] ILP: First Leakage Current

[0037] MN: Pull-down switch

[0038] MP: Pull-up switch

[0039] M_en: Enable signal

[0040] ND: Sensing Node

[0041] OPA: Operational Amplifier

[0042] PUPEN, PDNEN: Enable signals

[0043] R1, R2: Voltage dividing resistors

[0044] Ra~Rd: Resistor

[0045] SC1, SC2: Control signals

[0046] SEL <n:1>Selection signal

[0047] SMD: Mode Signal

[0048] SSEN: Sensing signal

[0049] SWB: Bias Switch

[0050] SWCN, SWCP: Control switches

[0051] TP: Transistor

[0052] Va~Vd: Reference voltage values

[0053] VB: Bias Voltage

[0054] VCCP: High Voltage Level

[0055] VDDQ: High Reference Voltage

[0056] VINT: Internal voltage

[0057] Vk: Selected voltage value

[0058] VSSQ: Low reference voltage Detailed Implementation

[0059] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for the purpose of clarity and ease of understanding, the various drawings of this disclosure show a portion of an electronic device, and some elements in the various drawings may not be drawn to scale. Furthermore, the number and dimensions of each device shown in the drawings are merely illustrative and not intended to limit the scope of this disclosure.

[0060] Certain terms are used throughout the description and the following claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may refer to the same element under different names. This document is not intended to distinguish between elements with different names but the same function. In the following description and claims, the terms "comprising," "including," and "having" are used in an open-ended manner and should therefore be interpreted as "including, but not limited to...". Therefore, when the terms "comprising," "including," and / or "having" are used in the description of this disclosure, the presence of corresponding features, areas, steps, operations, and / or elements is indicated, but not limited to, the presence of one or more corresponding features, areas, steps, operations, and / or elements.

[0061] It should be understood that when a component is referred to as "coupled to," "connected to," or "conducted to" another component, it may be directly connected to the other component and establish a direct electrical connection, or there may be an intermediate component in between to pass the electrical connection (indirect electrical connection). Conversely, when a component is referred to as "directly coupled to," "directly connected to," or "directly connected to" another component, there is no intermediate component in between.

[0062] Please refer to Figure 2 , Figure 2 This illustration shows a schematic diagram of a voltage monitor according to an embodiment of the present disclosure. In this embodiment, the voltage monitor 100 of a memory device includes a voltage divider 110, a bridge switch 120, an off-chip driver (OCD) 130, and control circuitry 140. The voltage divider 110 is coupled to a sensing node ND. The voltage divider 110 receives the internal voltage VINT of the memory device and divides the internal voltage VINT to generate a sensing signal SSEN on the sensing node ND. The sensing signal SSEN can be a sense voltage or a sense current. For example, the memory device can be dynamic random access memory (DRAM). The internal voltage VINT can be one of the internal reference voltages VDD, VSS, VREFDQ, high reference voltage VDDQ, and low reference voltage VSSQ of the memory device, but the present disclosure is not limited thereto.

[0063] In this embodiment, the first terminal of the bridging switch 120 is coupled to the sensing node ND. The second terminal of the bridging switch 120 is coupled to the connection pad DQPAD.

[0064] In this embodiment, the OCD 130 includes a pull-up circuit 131 and a pull-down circuit 132. The pull-up circuit 131 is coupled between the high reference voltage VDDQ and the connection pad DQPAD. The pull-down circuit 132 is coupled between the connection pad DQPAD and the low reference voltage VSSQ.

[0065] In this embodiment, control circuit 140 is coupled to bridge switch 120 and OCD 130. In test mode, control circuit 140 turns on bridge switch 120. In test mode, control circuit 140 provides bias voltage VB to OCD 130 to match a first current value of the first leakage current ILP flowing through pull-up circuit 131 with a second current value of the second leakage current ILN flowing through pull-down circuit 132.

[0066] Generally, pull-up circuit 131 and pull-down circuit 132 are disabled in test mode. However, each transistor in pull-up circuit 131 and pull-down circuit 132 has a relatively low absolute critical voltage. Therefore, a first leakage current ILP and a second leakage current ILN may be generated in test mode. The voltage value of the sensing signal SSEN on the connection pad DQPAD increases with the increase of the first leakage current ILP. The voltage value of the sensing signal SSEN on the connection pad DQPAD decreases with the increase of the second leakage current ILN. Therefore, the voltage value of the sensing signal SSEN on the connection pad DQPAD is affected by the first leakage current ILP and / or the second leakage current ILN.

[0067] It is worth mentioning that, in this embodiment, in test mode, control circuit 140 uses control signal SC1 to turn on bridge switch 120 and provide bias voltage VB to OCD 130. The first current value of the first leakage current ILP flowing through pull-up circuit 131 matches the second current value of the second leakage current ILN flowing through pull-down circuit 132 (i.e., ILP - ILN ≈ 0). The first current value of the first leakage current ILP flowing through pull-up circuit 131 is substantially equal to or similar to the second current value of the second leakage current ILN flowing through pull-down circuit 132. Therefore, in test mode, the first leakage current ILP and the second leakage current ILN on connection pad DQPAD are balanced. Thus, in test mode, the sensing signal SSEN on connection pad DQPAD is not affected by the first leakage current ILP and the second leakage current ILN. Voltage monitor 100 can improve the accuracy of the sensing signal SSEN located on connection pad DQPAD in test mode.

[0068] In this embodiment, the bridge switch 120 is turned off in normal mode and stops providing bias voltage VB in the range between the low reference voltage VSSQ and the high reference voltage VDDQ. The OCD 130 operates in normal mode. For example, the OCD 130 provides an external matching resistor value via the connection pad DQPAD in normal mode.

[0069] In this embodiment, in the test mode, the control circuit 140 provides a bias voltage VB to the pull-up circuit 131 to adjust the first current value of the first leakage current ILP, but this disclosure is not limited thereto. In some embodiments, in the test mode, the control circuit 140 provides a bias voltage VB to the pull-down circuit 132 to adjust the second current value of the second leakage current ILN.

[0070] Please refer to Figure 3 , Figure 3 This diagram illustrates a voltage monitor according to an embodiment of the present disclosure. In this embodiment, the voltage monitor 200 includes a voltage divider 110, a bridge switch 120, an OCD 230, and a control circuit 240. The connection and operation of the voltage divider 110 and the bridge switch 120 are described in... Figure 2 The embodiments have been clearly explained, so they will not be repeated here.

[0071] In this embodiment, the OCD 230 includes a pull-up circuit 231 and a pull-down circuit 232. The pull-up circuit 231 includes a control switch SWCP and a pull-up switch MP. The pull-down circuit 232 includes a pull-down switch MN. A first terminal of the control switch SWCP is coupled to a high reference voltage VDDQ. The pull-up switch MP is coupled between a second terminal of the control switch SWCP and a connection pad DQPAD. The pull-down switch MN is coupled between the connection pad DQPAD and a low reference voltage VSSQ. The connection pad DQPAD outputs a sensing signal SSEN corresponding to the internal voltage VINT in the memory device.

[0072] During the first period of the test mode, control circuit 240 turns on control switch SWCP, turns off pull-up switch MP and pull-down switch MN, and determines the absolute difference between a first current value of the first leakage current ILP flowing through pull-up circuit 131 and a second current value of the second leakage current ILN flowing through pull-down circuit 132 based on the sensing signal SSEN located on connection pad DQPAD. During the first period of the test mode, when the sensing signal SSEN on connection pad DQPAD is always equal to the voltage of the high reference voltage VDDQ or the low reference voltage VSSQ, control circuit 240 determines that the absolute difference between the first current value and the second current value is higher than a threshold value. This means that the first leakage current ILP and the second leakage current ILN are unbalanced. For example, the threshold value is "0" or 0.01 mA, but this disclosure is not limited to this. Therefore, during the second period of the test mode, control circuit 240 turns off control switch SWCP, pull-up switch MP and pull-down switch MN, and provides bias voltage VB to the second terminal of control switch SWCP.

[0073] When the absolute difference between the first current value and the second current value is less than or equal to a critical value, it means that the first leakage current ILP and the second leakage current ILN are balanced. Therefore, the control circuit 240 operates during the first period.

[0074] For example, each of the control switch SWCP and the pull-up switch MP can be implemented by a p-type transistor, but this disclosure is not limited thereto. The pull-down switch MN can be implemented by an n-type transistor, but this disclosure is not limited thereto. The control terminal of the pull-up switch MP receives an enable signal PUPEN. The control terminal of the pull-down switch MN receives an enable signal PDNEN. In test mode, the control circuit 240 uses the control signal SC2 to turn on the control switch SWCP, uses the enable signal PUPEN with a high logic level to turn off the pull-up switch MP, and uses the enable signal PDNEN with a low logic level to turn off the pull-down switch MN. When the absolute difference between the first current value and the second current value is higher than a threshold value, the control circuit 240 uses the control signal SC2 to turn off the control switch SWCP, the pull-up switch MP, and the pull-down switch MN, and provides a bias voltage VB to the second terminal of the control switch SWCP.

[0075] The second leakage current ILN is generated based on the difference between the voltage of the sensing signal SSEN and the voltage of the low reference voltage VSSQ. The first leakage current ILP is generated based on the difference between the voltage of the bias voltage VB and the voltage of the sensing signal SSEN. It should be noted that the control circuit 240 can adjust the first leakage current ILP using the bias voltage VB based on the second leakage current ILN, thereby matching the first leakage current ILP with the second leakage current ILN.

[0076] In some embodiments, the control circuit 240 is configured in the OCD 230. In other words, the OCD 230 also includes the control circuit 240.

[0077] Please refer to Figure 4 , Figure 4 This diagram illustrates a voltage monitor according to an embodiment of the present disclosure. In this embodiment, the voltage monitor 300 includes a voltage divider 310, a bridge switch 320, an OCD 330, and a control circuit 340. The voltage divider 310 includes voltage-dividing resistors R1 and R2. Voltage-dividing resistor R1 is coupled between the internal voltage Vint and the sensing node ND. Voltage-dividing resistor R2 is coupled between the sensing node ND and the background voltage VBB. The voltage divider 310 divides the internal voltage Vint according to the resistance values ​​of the voltage-dividing resistors R1 and R2 to generate a sensing signal SSEN.

[0078] In this embodiment, the bridging switch 320 is coupled between the sensing node ND and the connection pad DQPAD. The bridging switch 320 can be implemented using an n-type transistor, but this disclosure is not limited thereto.

[0079] In this embodiment, the OCD 330 includes a pull-up circuit 331 and a pull-down circuit 332. The pull-up circuit 331 includes a control switch SWCP and a pull-up switch MP. The pull-down circuit includes a pull-down switch MN. A first terminal of the control switch SWCP is coupled to a high reference voltage VDDQ. The pull-up switch MP is coupled between a second terminal of the control switch SWCP and a connection pad DQPAD. The pull-down switch MN is coupled between the connection pad DQPAD and a low reference voltage VSSQ. In this embodiment, the control switch SWCP can be implemented using a p-type transistor, but this disclosure is not limited thereto.

[0080] In this embodiment, the control circuit 340 includes a level shifter 341, a logic circuit 342, and a bias switch SWB. The level shifter 341 is coupled to the control terminal of the bridge switch 320. The level shifter 341 receives the mode signal SMD and reacts to the mode signal SMD to generate a control signal SC1. In test mode, the mode signal SMD has a first logic level, and the control signal SC1 has a first voltage level. In normal mode, the mode signal SMD has a second logic level, and the control signal SC1 has a second voltage level.

[0081] For example, in test mode, the mode signal SMD has a high logic level. Level shifter 341 shifts the voltage value of the mode signal SMD to generate a control signal SC1 with a high voltage level VCCP (i.e., the first voltage level). Bridge switch 320 responds to the control signal SC1 with the first voltage level being turned on. Control switch SWCP responds to the control signal SC1 with the first voltage level being turned off.

[0082] For example, in normal mode, the mode signal SMD has a low logic level. Level shifter 341 shifts the voltage value of the mode signal SMD to generate a control signal SC1 with a low voltage level (i.e., a second voltage level). Bridge switch 320 is turned off in response to the control signal SC1 with the second voltage level. Control switch SWCP is turned on in response to the control signal SC1 with the second voltage level.

[0083] In some embodiments, the level shifter 341 may be implemented by a source follower, a buffer, or a converter, but this disclosure is not limited thereto.

[0084] In this embodiment, logic circuit 342 is coupled to level shifter 341. Logic circuit 342 generates control signal SC2 in response to control signal SC1 and enable signal M_en. In this embodiment, logic circuit 342 performs an AND logic operation on control signal SC1 and enable signal M_en to generate control signal SC2. For example, logic circuit 342 includes AND gate AG, but this disclosure is not limited thereto. The first input of AND gate AG receives enable signal M_en. The second input of AND gate AG receives control signal SC1. The output of AND gate AG outputs control signal SC2.

[0085] The first terminal of the bias switch SWB receives the bias voltage VB. The second terminal of the bias switch SWB is coupled to the second terminal of the control switch SWCP. The control terminal of the bias switch SWB receives the control signal SC2. In this embodiment, in test mode, the bias switch SWB responds to the control signal SC2 being turned on and transmits the bias voltage VB to the second terminal of the control switch SWCP. The bias switch SWB can be implemented using an n-type transistor, but this disclosure is not limited thereto.

[0086] During the first period of the test mode, the control circuit 340 provides an enable signal M_en with a low logic level. The control signal SC2 has a low logic level or a second voltage level. Therefore, the control switch SWCP is turned on. The bias switch SWB is turned off. The pull-up switch MP is turned off in response to the enable signal PUPEN with a high logic level. The pull-down switch MN is turned off in response to the enable signal PDNEN with a low logic level. The control circuit 340 determines the absolute difference between a first current value of the first leakage current ILP and a second current value of the second leakage current ILN.

[0087] During the first period of the test mode, if the sensing signal SSEN at the connection pad DQPAD is consistently equal to either the high reference voltage VDDQ or the low reference voltage VSSQ, the control circuit 340 determines that the absolute difference between the first current value and the second current value is higher than a threshold value. In the second period following the first period, the control circuit 340 provides an enable signal M_en with a high logic level. The control signal SC2 has a high logic level or the first voltage level. Therefore, the control switch SWCP is turned off. The bias switch SWB is turned on to transfer the bias voltage VB to the second terminal of the control switch SWCP.

[0088] In this embodiment, the control circuit 340 further includes a multi-source circuit 343. The multi-source circuit 343 is coupled to the first terminal of the bias switch SWB. The multi-source circuit 343 responds to the selection signal SEL. <n:1>The bias voltage VB is adjusted accordingly. The multi-source circuit 343 generates a reference voltage value based on the high reference voltage VDDQ and the low reference voltage VSSQ. The multi-source circuit 343 responds to the selection signal SEL. <n:1>Select the selected voltage value and apply a bias voltage VB in response to the selected voltage value, which is provided in the range between the low reference voltage VSSQ and the high reference voltage VDDQ.

[0089] Please refer to Figure 4 as well as Figure 5 , Figure 5 This illustration shows a schematic diagram of a multi-source circuit according to an embodiment of the present disclosure. In this embodiment, the multi-source circuit 343 includes a voltage divider 3431, a selection circuit 3432, and a voltage regulator 3433. The second voltage divider 3431 is coupled between a high reference voltage VDDQ and a low reference voltage VSSQ. The voltage divider 3431 generates reference voltage values ​​Va to Vd. For example, the voltage divider 3431 includes resistors Ra to Rd. Resistors Ra to Rd are connected in series between the high reference voltage VDDQ and the low reference voltage VSSQ. The reference voltage value Va is generated at the node of resistors Ra and Rb. The reference voltage value Vb is generated at the node of resistors Rb and Rc. The reference voltage value Vc is generated at the node of resistors Rc and Rd. The reference voltage value Vd is generated at the low reference voltage VSSQ. For example, the resistance values ​​of resistors Ra to Rd are the same, but the present disclosure is not limited thereto. The low reference voltage VSSQ is 0 volts, but this disclosure is not limited to this. Reference voltage Va is equal to 0.75 × VDDQ. Reference voltage Vb is equal to 0.5 × VDDQ. Reference voltage Vc is equal to 0.25 × VDDQ. Reference voltage Vd is equal to VSSQ.

[0090] In this embodiment, the selection circuit 3432 is coupled to the voltage divider 3431. The selection circuit 3432 responds to the selection signal SEL. <n:1>The selected voltage value Vk is chosen, and a bias voltage VB is provided in response to the selected voltage value Vk. In this embodiment, the selection circuit 3432 responds to the selection signal SEL. <n:1>Select the selected voltage value Vk from the reference voltage values ​​Va~Vd.

[0091] In this embodiment, the selection circuit 3432 can be implemented by a switching network or a multiplexer (MUX), but this disclosure is not limited thereto. Selection signal SEL <n:1>It can be a numeric code with at least two digits, but this disclosure is not limited to this.

[0092] The number of resistors in voltage divider 3431 can be adjusted based on actual design or requirements. The number of resistors in voltage divider 3431 in this disclosure is not limited to this. Therefore, the number of reference voltage values ​​provided by voltage divider 3431 can be adjusted. The number of reference voltage values ​​in voltage divider 3431 in this disclosure is also not limited to this. The selected voltage value Vk is a voltage value within the voltage range between the high reference voltage VDDQ and the low reference voltage VSSQ.

[0093] In this embodiment, voltage regulator 3433 is coupled to the first terminal of selection circuit 3432 and bias switch SWB. Voltage regulator 3433 responds to the selected voltage value Vk by providing bias voltage VB. In other words, voltage regulator 3433 sets the selected voltage value Vk as the bias voltage VB.

[0094] In this embodiment, the voltage regulator 3433 includes an operational amplifier (OPA) and a transistor (TP). The first input terminal of the OPA receives a selected voltage value Vk. The first terminal of the transistor (TP) receives an input reference voltage (for example, a high voltage level VCCP, but this disclosure is not limited thereto). The second terminal of the transistor (TP) is coupled to the second input terminal of the OPA. The second terminal of the transistor (TP) is used for the output bias voltage VB. The control terminal of the transistor (TP) is coupled to the output terminal of the OPA.

[0095] In this embodiment, the transistor TP can be implemented using a p-type transistor, but this disclosure is not limited thereto. The first input terminal of the operational amplifier OPA is a non-inverting input terminal. The second input terminal of the operational amplifier OPA is an inverting input terminal. Therefore, the voltage regulator 3433 is a negative-feedback unit gain buffer or a low-dropout regulator (LDO) with drive capability.

[0096] For example, the input reference voltage (for example, the high voltage level VCCP) is in the range of 2.6 to 3.0 volts. The high reference voltage VDDQ is in the range of 1.0 to 1.4 volts. During the second period of the test mode, the control circuit 340 provides an enable signal M_en with a high logic level. This second period is also called the "multi-source mode". During the second period, if the control switch SWCP is completely disconnected, the first current value of the first leakage current ILP is very low. The first current value of the first leakage current ILP is lower than the first current value of the second leakage current ILN. Therefore, the first leakage current ILP and the second leakage current ILN are still unbalanced (i.e., ILP - ILN < 0). The multi-source circuit 343 can increase the selected voltage value Vk to increase the voltage value of the bias voltage VB. The first current value of the first leakage current ILP is increased to match the first current value of the second leakage current ILN. Therefore, the first leakage current ILP and the second leakage current ILN are balanced (i.e., ILP - ILN ≈ 0). In this way, the sensing signal SSEN on the connection pad DQPAD is not affected by the first leakage current ILP and the second leakage current ILN.

[0097] For example, during the second period of the test mode, if the control switch SWCP is not open, the first current value of the first leakage current ILP is higher than the first current value of the second leakage current ILN. Therefore, the first leakage current ILP and the second leakage current ILN are still unbalanced (i.e., ILP - ILN > 0). The multi-source circuit 343 can reduce the selected voltage value Vk to reduce the bias voltage VB. The first current value of the first leakage current ILP is reduced to match the first current value of the second leakage current ILN. Therefore, the first leakage current ILP and the second leakage current ILN are balanced (i.e., ILP - ILN ≈ 0). In this way, the sensing signal SSEN on the connection pad DQPAD is not affected by the first leakage current ILP and the second leakage current ILN.

[0098] Please refer to Figure 6 , Figure 6 This illustration shows an off-chip driver (OCD) according to an embodiment of the present disclosure. In this embodiment, the OCD 430 includes a connection pad DQPAD, a pull-up circuit 431, a pull-down circuit 432, and a control circuit 443. The connection pad DQPAD outputs a sensing signal SSEN corresponding to the internal voltage VINT in the memory device. The pull-up circuit 431 is coupled between a high reference voltage VDDQ and the connection pad DQPAD. The pull-down circuit 432 includes a control switch SWCN and a pull-down switch MN. A first terminal of the control switch SWCN is coupled to a low reference voltage VSSQ. The pull-down switch MN is coupled between a second terminal of the control switch SWCN and the connection pad DQPAD. The control circuit 443 is coupled to the pull-down circuit 432. When the memory device is in test mode, the control circuit 443 disconnects the control switch SWCN and provides a bias voltage VB to the second terminal of the control switch SWCN to adjust the current flowing through the pull-down circuit 432.

[0099] In this embodiment, the control circuit 443 determines the absolute difference between a first current value of the first leakage current ILP and a second current value of the second leakage current ILN. During the first period of the test mode, if the sensing signal SSEN on the connection pad DQPAD is always equal to the voltage of the high reference voltage VDDQ or the low reference voltage VSSQ, the control circuit 443 determines that the absolute difference between the first current value and the second current value is higher than a threshold. Therefore, the control circuit 443 uses the control signal SC2 to disconnect the control switch SWCN and transmit the bias voltage VB to the second terminal of the control switch SWCP to reduce the absolute difference between the first current value of the first leakage current ILP and the second current value of the second leakage current ILN. In this embodiment, the control circuit 443 uses the control signal SC1 to control the bridge switch (for example...). Figure 2 Bridge switch 120 in Figure 3 Bridge switch 120 or Figure 4 (Bridge switch 320 in the middle).

[0100] In this embodiment, the control circuit 443 includes a multi-source circuit (e.g., multi-source circuit 343). The multi-source circuit is coupled to the second terminal of the control switch SWCN. The multi-source circuit provides a bias voltage VB in the range between the low reference voltage VSSQ and the high reference voltage VDDQ.

[0101] In some embodiments, the control circuit 443 may be configured external to the OCD 430.

[0102] In summary, in test mode, the control circuit turns on the bridge switch and provides bias to the OCD so that the first current value of the first leakage current flowing through the pull-up circuit matches the second current value of the second leakage current flowing through the pull-down circuit. Therefore, in test mode, the first and second leakage currents on the connection pads are balanced. Thus, the sensing signal on the connection pads is not disturbed by either the first or second leakage current in test mode. A voltage monitor can improve the accuracy of the sensing signal on the connection pads in test mode.

[0103] Various modifications and variations can be made to the disclosed embodiments by those skilled in the art without departing from the scope or spirit of this disclosure. Based on the foregoing, this disclosure is intended to cover modifications and variations falling within the scope of the following claims and their equivalents.

Claims

1. A voltage monitor for a memory device, characterized in that, The voltage monitor includes: A first voltage divider is coupled to the sensing node and configured to receive an internal voltage in a memory device and divide the internal voltage to generate a sensing signal at the sensing node. A bridging switch, wherein a first end of the bridging switch is coupled to the sensing node, and a second end of the bridging switch is coupled to a connecting pad; External drivers for the chip include: A pull-up circuit is coupled between the high reference voltage and the connection pad; and A pull-down circuit is coupled between the connection pad and the low reference voltage; and The control circuit, coupled to the bridge switch and the external chip driver, wherein in test mode: The control circuit turns on the bridge switch, and The control circuit provides a bias to the external driver of the chip so that a first current value of the first leakage current flowing through the pull-up circuit matches a second current value of the second leakage current flowing through the pull-down circuit.

2. The voltage monitor according to claim 1, characterized in that, In normal mode, the control circuit disconnects the bridge switch and stops providing the bias voltage.

3. The voltage monitor according to claim 1, characterized in that: The pull-up circuit includes: A control switch, the first terminal of which is coupled to the high reference voltage; and A pull-up switch is coupled between the second terminal of the control switch and the connecting pad, and The pull-down circuit includes: A pull-down switch is coupled between the connection pad and the low reference voltage.

4. The voltage monitor according to claim 3, characterized in that, In the test mode, the control circuit turns on the control switch, turns off the pull-up switch and the pull-down switch, and determines the absolute difference between the first current value and the second current value based on the sensing signal located on the connection pad.

5. The voltage monitor according to claim 4, characterized in that, When the sensing signal on the connection pad is always equal to the voltage of the high reference voltage or the low reference voltage, the control circuit determines that the absolute difference between the first current value and the second current value is higher than a critical value, disconnects the control switch, the pull-up switch and the pull-down switch, and provides the bias voltage to the second terminal of the control switch.

6. The voltage monitor according to claim 3, characterized in that, The control circuit includes: A level shifter, coupled to the control terminal of the bridge switch, is configured to receive a mode signal and generate a first control signal in response to the mode signal; A logic circuit, coupled to the level shifter and configured to generate a second control signal in response to the first control signal and the enable signal; and A bias switch, wherein a first terminal of the bias switch receives the bias voltage, a second terminal of the bias switch is coupled to a second terminal of the control switch, and a control terminal of the bias switch receives the second control signal.

7. The voltage monitor according to claim 6, characterized in that, In the test mode, the bias switch responds to the second control signal being turned on and transmits the bias voltage to the second terminal of the control switch.

8. The voltage monitor according to claim 6, characterized in that, The logic circuit includes: The AND gate receives the enable signal at its first input terminal, the first control signal at its second input terminal, and the second control signal at its output terminal.

9. The voltage monitor according to claim 6, characterized in that, The control circuit also includes: A multi-source circuit is coupled to the first terminal of the bias switch and configured to adjust the bias voltage value in response to a selection signal.

10. The voltage monitor according to claim 9, characterized in that, The multi-source circuit includes: A second voltage divider, coupled between a high reference voltage and a low reference voltage, is configured to generate multiple reference voltage values; and A selection circuit, coupled to the second voltage divider, is configured to respond to the selection signal to select one of the plurality of reference voltage values ​​as the selected voltage value.

11. The voltage monitor according to claim 10, characterized in that, The multi-source circuit also includes: A voltage regulator, coupled to the first terminal of the selection circuit and the bias switch, is configured to provide the bias voltage in response to the selected voltage value.

12. The voltage monitor according to claim 11, characterized in that, The voltage regulator includes: An operational amplifier, wherein the first input terminal of the operational amplifier receives the selected voltage value; and A transistor, wherein a first terminal of the transistor receives an input reference voltage, a second terminal of the transistor is coupled to a second input terminal of the operational amplifier, and a control terminal of the transistor is coupled to an output terminal of the operational amplifier.

13. The voltage monitor according to claim 6, characterized in that: In the test mode, the mode signal has a first logic level, and the first control signal has a first voltage level; as well as In normal mode, the mode signal has a second logic level, and the first control signal has a second voltage level.

14. The voltage monitor according to claim 13, characterized in that: In the test mode, the bridge switch has the first voltage level in response to the first control signal being turned on, and In the normal mode, the bridge switch is disconnected in response to the first control signal having the second voltage level.

15. An external driver for a memory device, comprising: A connection pad is configured to output a sensing signal corresponding to the internal voltage in the memory device; Pull-up circuit, including: A control switch, wherein a first terminal of the control switch is coupled to a high reference voltage; and A pull-up switch is coupled between the second end of the control switch and the connecting pad; A pull-down circuit is coupled between the connection pad and the low reference voltage; and The control circuit is coupled to the pull-up circuit. When the memory device is in test mode, the control circuit disconnects the control switch and provides a bias voltage to the second terminal of the control switch to adjust the first current flowing through the pull-up circuit.

16. The external driver according to claim 15, characterized in that, The control circuit includes: A multi-source circuit is coupled to the second terminal of the control switch and configured to provide the bias voltage within the range between the low reference voltage and the high reference voltage.

17. An external driver for a memory device, comprising: A connection pad is configured to output a sensing signal corresponding to the internal voltage in the memory device; A pull-up circuit is coupled between the high reference voltage and the connection pad; Pull-down circuit, including: A control switch, the first terminal of which is coupled to a low reference voltage; and A pull-down switch is coupled between the second terminal of the control switch and the connecting pad; and The control circuit is coupled to the pull-down circuit. When the memory device is in test mode, the control circuit disconnects the control switch and provides a bias voltage to the second terminal of the control switch to adjust the current flowing through the pull-down circuit.

18. The external driver according to claim 17, characterized in that, The control circuit includes: A multi-source circuit is coupled to the second terminal of the control switch and configured to provide the bias voltage within the range between the low reference voltage and the high reference voltage.

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