A silicon carbide MOSFET device with super-junction structure
By optimizing the arrangement of P-pillars and N-pillars and the selective semi-enclosed structure, the contradiction between the on-resistance and blocking voltage of silicon carbide devices in high-voltage applications was resolved, improving the reliability and resistance to single-event burn-out, and realizing high-performance silicon carbide MOSFET devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-05
- Publication Date
- 2026-03-27
AI Technical Summary
In high-voltage applications, traditional silicon carbide devices face a difficult-to-reconcile contradiction between on-resistance and blocking voltage. The introduction of superjunction structures leads to enhanced electric field and reliability issues, especially insufficient resistance to single-particle burn-out.
By optimizing the arrangement of P-pillars and N-pillars, placing the P-pillars below the trench, and combining this with a selective semi-enclosed structure, the heavily doped P-pillar region is short-circuited to the source, thus optimizing the charge balance state of the superjunction pillar region and reducing the electric field strength and Miller capacitance.
While maintaining a high blocking voltage, it significantly reduces on-resistance, improves device switching speed and single-event burn-out resistance, and enhances device reliability and performance.
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Figure CN121463492B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to the technical field of semiconductor power devices, and particularly relates to a silicon carbide MOSFET device with a super-junction structure. BACKGROUND
[0002] As a core component of an electric energy conversion system, the performance of a power semiconductor device directly determines the energy conversion efficiency, system size and cost. In recent years, the third-generation wide-bandgap semiconductor represented by silicon carbide (SiC) has gradually become a research hotspot in the field of power devices due to its excellent material properties. Compared with traditional silicon (Si) materials, silicon carbide has a higher critical breakdown field, a wider bandgap and a higher thermal conductivity. These characteristics enable silicon carbide devices to work in a higher voltage, higher frequency and higher temperature environment while achieving lower power loss.
[0003] However, as the power electronic system continues to improve the requirements for power density and efficiency, the inherent contradiction between the on-resistance (Rds(on)) and the blocking voltage (BV) of the traditional silicon carbide device has led to its performance failing to meet the current application requirements. In particular, in the medium and high voltage application fields such as new energy vehicle traction inverters, photovoltaic, energy storage, smart grids, rail transit and the like, how to further reduce the on-state loss of the device while maintaining the high blocking voltage of the device has become a key challenge for technological development.
[0004] At present, by introducing a super-junction structure into the traditional silicon carbide device, P columns and N columns arranged alternately in the drift region can be completely depleted in the blocking state, forming an approximately rectangular electric field distribution, which significantly improves the voltage resistance of the device. At the same time, in the on-state, the current can flow through the highly doped N column region, thereby reducing the on-resistance of the device and breaking through the theoretical limit of silicon carbide material. However, the introduction of the super-junction structure also brings related reliability problems to the silicon carbide device. On the one hand, for a trench silicon carbide MOSFET, the introduction of the super-junction structure will bring a horizontal electric field in the bulk, which, when superimposed with the vertical electric field, will enhance the electric field at the corners and bottom of the trench, thereby being detrimental to the long-term reliability of the gate oxide and the device. On the other hand, the introduction of the super-junction structure will generate a high electric field at the interface of the bulk column region, which is not conducive to the single event burnout resistance of the device. When the incident particle energy in the cosmic space is extremely high, it will penetrate the entire silicon carbide super-junction device, generating a large number of electron-hole pairs on the incident path. The high electric field at the column region interface will cause more holes to accelerate through the P bulk region to the source, which will easily trigger the conduction of the parasitic triode of the device. The excessively high current will cause the temperature of the sensitive region of the device to rise, and the device will burn out. SUMMARY
[0005] The purpose of the present application is to provide a silicon carbide MOSFET device with a super-junction structure, which realizes further optimization of the charge balance state of the super-junction column region, improves the figure of merit (FOM) between the breakdown voltage and the on-resistance of the device, reduces the electric field strength at the interface of the super-junction column region, and improves the single-particle burnout resistance of the device.
[0006] To achieve the above-mentioned purpose, the present application provides the following technical solutions.
[0007] A silicon carbide MOSFET device with a super-junction structure includes an N-type substrate and a super-junction structure. A drain electrode is deposited below the N-type substrate. The super-junction structure includes a heavily doped N-type epitaxial layer grown above the N-type substrate. A heavily doped P-column region is formed in the center of the heavily doped N-type epitaxial layer. A gate trench oxide is provided above the heavily doped P-column region. A P-body region is formed on both sides of the gate trench oxide. An N+ source region is formed above the P-body region. P+ contact regions are formed on both sides of the N+ source region. A polysilicon gate is formed inside the gate trench oxide. An oxide dielectric layer is formed above the polysilicon gate. The P+ contact regions and the N+ source region are short-circuited by a source electrode. The source electrode is fully wrapped around the oxide dielectric layer. The top of the heavily doped P-column region is short-circuited by a source electrode through a selective P-type half-pack structure to convert part of the gate-drain capacitance to drain-source capacitance and reduce the Miller capacitance of the device.
[0008] As a further scheme of the present application, the heavily doped P-column region is formed by multiple epitaxy and multiple ion implantation or trench filling.
[0009] As a further scheme of the present application, by arranging the heavily doped P-column region at the bottom of the trench gate, the electric field strength at the bottom of the device trench can be effectively suppressed, and the device cell size can be reduced to the extreme small, and the device on-resistance can be significantly reduced while maintaining high blocking voltage. By short-circuiting the heavily doped P-column region and the source electrode through a selective half-pack structure, most of the gate-drain capacitance of the device is converted to drain-source capacitance, the Miller capacitance of the device is reduced, the switching speed of the device is improved, and the switching loss of the device is reduced.
[0010] As a further scheme of the present application, the width of the heavily doped P-column region is consistent with the width of the trench gate in the gate trench oxide.
[0011] As a further scheme of the present application: the heavily doped P pillar region includes a first heavily doped P pillar region, a second heavily doped P pillar region, a third heavily doped P pillar region, a fourth heavily doped P pillar region and a fifth heavily doped P pillar region, the first heavily doped P pillar region is grown above the N-type substrate, the second heavily doped P pillar region is formed above the first heavily doped P pillar region, the third heavily doped P pillar region is formed above the second heavily doped P pillar region, the fourth heavily doped P pillar region is formed above the third heavily doped P pillar region, the fifth heavily doped P pillar region is formed above the fourth heavily doped P pillar region, and the gate trench oxide is located above the fifth heavily doped P pillar region.
[0012] As a further scheme of the present application: the heavily doped N-type epitaxial layer is formed by multiple epitaxy, and the epitaxial resistivity is uniform.
[0013] As a further scheme of the present application: the heavily doped N-type epitaxial layer includes multiple epitaxial layers, and the first heavily doped P pillar region, the second heavily doped P pillar region, the third heavily doped P pillar region, the fourth heavily doped P pillar region and the fifth heavily doped P pillar region are respectively formed by ion implantation on the epitaxial layers.
[0014] As a further scheme of the present application: the widths of the first heavily doped P pillar region, the second heavily doped P pillar region, the third heavily doped P pillar region and the fourth heavily doped P pillar region are the same as the width of the gate trench oxide, and the width of the fifth heavily doped P pillar region is the sum of the widths of the gate trench oxide and the selective P-type half-enclosure structure.
[0015] As a further scheme of the present application: the ion implantation doses of the first heavily doped P pillar region, the second heavily doped P pillar region, the third heavily doped P pillar region, the fourth heavily doped P pillar region and the fifth heavily doped P pillar region decrease in turn.
[0016] As a further scheme of the present application: the ion implantation doses of the first heavily doped P pillar region, the second heavily doped P pillar region, the third heavily doped P pillar region, the fourth heavily doped P pillar region and the fifth heavily doped P pillar region decrease from top to bottom, and finally a heavily doped P pillar region with uniform doping distribution is formed.
[0017] As a further scheme of the present application: the heavily doped N-type epitaxial layer includes a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a fourth epitaxial layer, a fifth epitaxial layer and a sixth epitaxial layer, the first epitaxial layer is formed above the N-type substrate, the second epitaxial layer is formed above the first epitaxial layer, the third epitaxial layer is formed above the second epitaxial layer, the fourth epitaxial layer is formed above the third epitaxial layer, and the fifth epitaxial layer is formed above the fourth epitaxial layer.
[0018] As a further scheme of the present application: the first heavily doped P column region is located in the center of the first epitaxial layer, the second heavily doped P column region is located in the center of the second epitaxial layer, the third heavily doped P column region is located in the center of the third epitaxial layer, the fourth heavily doped P column region is located in the center of the fourth epitaxial layer, the fifth heavily doped P column region is located in the center of the fifth epitaxial layer, and the lower end of the gate trench oxide is located in the center of the sixth epitaxial layer; the doping concentration of the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, the fourth epitaxial layer and the fifth epitaxial layer decreases in turn; and the ion implantation dose of the first heavily doped P column region, the second heavily doped P column region, the third heavily doped P column region, the fourth heavily doped P column region and the fifth heavily doped P column region increases in turn.
[0019] As a further scheme of the present application: the sixth epitaxial layer is formed above the fifth epitaxial layer, and the sixth epitaxial layer is used to form a top cell region to reduce the on-resistance of the device; the first heavily doped P column region, the second heavily doped P column region, the third heavily doped P column region and the fourth heavily doped P column region are short-circuited with the source electrode through a selective P-type half-enclosure structure; by optimizing the charge balance state of the super junction column region, the electric field strength of the junction interface of the super junction column region is reduced, and the single event burnout resistance of the device is improved.
[0020] Compared with the prior art, the present application has the following beneficial effects:
[0021] 1. The present application optimizes the arrangement mode of P columns and N columns, and arranges the P columns below the trench, which effectively shields the influence of the super junction introduced lateral electric field and the superposition of the device longitudinal electric field on the trench corner and bottom, suppresses the electric field of the trench corner and bottom to a low level, improves the gate oxide reliability of the device, and on the other hand, the device cell size can be made extremely small under the existing process capability, while maintaining high blocking voltage of the device, the on-resistance of the device is significantly reduced.
[0022] 2. The present application sets the heavily doped P column region at the bottom of the trench to be short-circuited with the source electrode through a selective half-enclosure structure, which can further improve the effective on-resistance area of the device, reduce the on-resistance of the device, and optimize the figure of merit FOM of the device; on the other hand, the half-enclosure short-circuit region short-circuits the heavily doped P column region with the source electrode, which can more effectively suppress the electric field strength of the trench corner and bottom, and convert most of the gate leakage capacitance (i.e. Miller capacitance) of the device into drain-source capacitance, improve the switching speed of the device, reduce the switching loss of the device, and improve the reliability of the device.
[0023] 3. The present application optimizes the charge balance state of the super junction column region, improves the figure of merit FOM between the breakdown voltage and the on-resistance of the device, improves the performance of the device, and reduces the electric field strength of the junction interface of the super junction column region, and improves the single event burnout resistance of the device.
[0024] 4, The present application is directed to the deficiencies of silicon carbide super-junction MOSFET in device performance, structure design and reliability, and innovatively proposes a high-performance and high-reliability silicon carbide MOSFET device with a super-junction structure, which provides a feasible technical path for the commercial application of silicon carbide super-junction devices. BRIEF DESCRIPTION OF DRAWINGS
[0025] Figure 1A It is a cell structure schematic diagram of a silicon carbide MOSFET device with a super-junction structure according to the embodiment 1 of the present application;
[0026] Figure 1B It is a selective semi-pack P-type short connection area structure schematic diagram of a silicon carbide MOSFET device with a super-junction structure according to the embodiment 1 of the present application;
[0027] Figure 2 It is an electric field intensity distribution diagram of the trench bottom gate oxide layer of the device according to the embodiment 1 of the present application in the blocking state;
[0028] Figure 3A It is a cell structure schematic diagram of a silicon carbide MOSFET device with a super-junction structure according to the embodiment 2 of the present application;
[0029] Figure 3B It is a selective semi-pack P-type short connection area structure schematic diagram of a silicon carbide MOSFET device with a super-junction structure according to the embodiment 2 of the present application;
[0030] Figure 4 It is a heavily doped P-pillar area doping concentration distribution diagram of the device according to the embodiments 1 and 2 of the present application;
[0031] Figure 5A It is a cell structure schematic diagram of a high-performance and high single-particle burnout resistance ability silicon carbide MOSFET device with a super-junction structure according to the embodiment 3 of the present application;
[0032] Figure 5B It is a selective semi-pack P-type short connection area structure schematic diagram of a high-performance and high single-particle burnout resistance ability silicon carbide MOSFET device with a super-junction structure according to the embodiment 3 of the present application;
[0033] Figure 6 It is an electric field intensity distribution diagram of the pillar area interface of the device according to the embodiments 1 and 3 of the present application in the blocking state.
[0034] In the figure: 101, N-type substrate; 102, heavily doped N-type epitaxial layer; 1021, first epitaxial layer; 1022, second epitaxial layer; 1023, third epitaxial layer; 1024, fourth epitaxial layer; 1025, fifth epitaxial layer; 1026, sixth epitaxial layer; 103, heavily doped P column region; 1031, first heavily doped P column region; 1032, second heavily doped P column region; 1033, third heavily doped P column region; 1034, fourth heavily doped P column region; 1035, fifth heavily doped P column region; 104, P-body region; 105, N+ source region; 106, P+ contact region; 107, selective P-type half-encapsulation structure; 108, gate trench oxide; 109, polysilicon gate; 110, oxide dielectric layer; 111, source electrode; 112, drain electrode. DETAILED DESCRIPTION
[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.
[0036] Embodiment 1
[0037] Please refer to Figure 1A , Figure 1B , Figure 2 , Figure 4 and Figure 6 In this embodiment, a silicon carbide MOSFET device with super-junction structure includes an N-type substrate 101, a heavily doped N-type epitaxial layer 102, a heavily doped P column region 103, a P-body region 104, an N+ source region 105, a P+ contact region 106, a selective P-type half-encapsulation structure 107, a gate trench oxide 108, a polysilicon gate 109, an oxide dielectric layer 110, a source electrode 111 and a drain electrode 112.
[0038] The N-type substrate 101 is provided with a super junction structure, which includes a heavily doped N-type epitaxial layer 102 formed above the N-type substrate 101, a heavily doped P-column region 103 formed in the center of the heavily doped N-type epitaxial layer 102, a gate trench oxide 108 formed above the heavily doped P-column region 103, a polysilicon gate 109 formed in the gate trench oxide 108, an oxide dielectric layer 110 formed above the polysilicon gate 109, a P-body region 104 formed on both sides of the gate trench oxide 108, an N+ source region 105 formed above the P-body region 104, a P+ contact region 106 formed on both sides of the N+ source region 105, the P+ contact region 106 and the N+ source region 105 being short-circuited by a source electrode 111, the source electrode 111 being fully surrounded by the oxide dielectric layer 110, a drain electrode 112 being formed below the N-type substrate 101, and the top of the heavily doped P-column region 103 being short-circuited with a selective P-type half-enclosure structure 107 by the source electrode 111.
[0039] Preferably, the heavily doped P-column region 103 is formed by multiple epitaxy and multiple ion implantation or trench filling.
[0040] Preferably, the width of the heavily doped P-column region 103 is consistent with the width of the trench gate in the gate trench oxide 108.
[0041] In the embodiment, by arranging the heavily doped P-column region at the bottom of the trench gate, the electric field intensity at the bottom of the device trench can be effectively suppressed, and the device cell size can be reduced to the extreme small, so that the device on-resistance can be significantly reduced while maintaining high blocking voltage; by short-circuiting the heavily doped P-column region with the source electrode through the selective half-enclosure structure, most of the gate-drain capacitance of the device can be converted into drain-source capacitance, so that the device Miller capacitance can be reduced, the device switching speed can be improved, and the device switching loss can be reduced.
[0042] Embodiment 2:
[0043] The super junction structure in the silicon carbide device provided in Embodiment 1 can be formed by multiple epitaxy and ion implantation or trench filling. However, for the multiple epitaxy and ion implantation process, the high-temperature process of the subsequent multiple epitaxy is repeatedly superimposed on the epitaxy of the previous ion implantation, which causes the uneven distribution of the doping of the finally formed super junction column region, thereby affecting the device performance. In order to solve the above problems, as shown in Figure 3A 、 Figure 3B and Figure 4As shown, the present application provides a second silicon carbide super junction device structure, which improves the figure of merit FOM between the device breakdown voltage and on-resistance, and improves the device performance. The device structure comprises an N-type substrate 101, a super junction structure disposed above the N-type substrate 101, the super junction structure comprising a heavily doped N-type epitaxial layer 102 formed above the N-type substrate 101, a heavily doped P-column region 103 formed in the center of the heavily doped N-type epitaxial layer 102, a gate trench oxide 108 formed above the heavily doped P-column region 103, a polysilicon gate 109 formed in the gate trench oxide 108, an oxide dielectric layer 110 formed above the polysilicon gate 109, a P-body region 104 formed on both sides of the gate trench oxide 108, an N+ source region 105 formed above the P-body region 104, a P+ contact region 106 formed on both sides of the N+ source region 105, the P+ contact region 106 and the N+ source region 105 being short-circuited by a source electrode 111, the source electrode 111 fully surrounding and wrapping the oxide dielectric layer 110, a drain electrode 112 formed below the N-type substrate 101, and the top of the heavily doped P-column region 103 being short-circuited with a selective P-type half-pack structure 107 by the source electrode 111.
[0044] Preferably, the heavily doped P-column region 103 is formed by multiple epitaxy and multiple ion implantation or trench filling.
[0045] Preferably, the width of the heavily doped P-column region 103 is consistent with the width of the trench gate in the gate trench oxide 108.
[0046] Preferably, the heavily doped P-column region 103 comprises a first heavily doped P-column region 1031, a second heavily doped P-column region 1032, a third heavily doped P-column region 1033, a fourth heavily doped P-column region 1034, and a fifth heavily doped P-column region 1035, the first heavily doped P-column region 1031 being grown above the N-type substrate 101, the second heavily doped P-column region 1032 being formed above the first heavily doped P-column region 1031, the third heavily doped P-column region 1033 being formed above the second heavily doped P-column region 1032, the fourth heavily doped P-column region 1034 being formed above the third heavily doped P-column region 1033, the fifth heavily doped P-column region 1035 being formed above the fourth heavily doped P-column region 1034, the gate trench oxide 108 being located above the fifth heavily doped P-column region 1035, and the heavily doped N-type epitaxial layer 102 being formed by multiple epitaxy with consistent epitaxial resistivity.
[0047] Preferably, the heavily doped N-type epitaxial layer 202 comprises multiple epitaxial layers, and the first heavily doped P-column region 1031, the second heavily doped P-column region 1032, the third heavily doped P-column region 1033, the fourth heavily doped P-column region 1034, and the fifth heavily doped P-column region 1035 are formed by ion implantation on the epitaxial layers.
[0048] Preferably, the width of the first, second, third and fourth heavily doped P pillar regions 1031, 1032, 1033 and 1034 is the same as the width of the gate trench oxide 108, and the width of the fifth heavily doped P pillar region 1035 is the sum of the width of the gate trench oxide 108 and the width of the selective P-type half-encapsulation structure 107.
[0049] The embodiment can achieve a better trade-off between breakdown voltage and on-resistance through multiple epitaxy and ion implantation processes, and has the characteristics of small parasitic capacitance, low switching loss and high reliability, thereby providing a feasible technical path for commercial application of silicon carbide super-junction devices. Similarly, the structure can also add a bottom auxiliary layer above the N-type substrate 201 of the device to form a semi-super junction structure, thereby reducing the difficulty and cost of device manufacturing processes and further improving the reliability of the device.
[0050] Preferably, the ion implantation dose of the first, second, third, fourth and fifth heavily doped P pillar regions 1031, 1032, 1033, 1034 and 1035 decreases in turn.
[0051] Preferably, the ion implantation dose of the first, second, third, fourth and fifth heavily doped P pillar regions 1031, 1032, 1033, 1034 and 1035 decreases from top to bottom, so as to finally form a heavily doped P pillar region 103 with uniform doping distribution.
[0052] Embodiment 3:
[0053] The silicon carbide super-junction MOSFET can generate a high electric field at the interface of the body-in pillar region, which is not conducive to the single-particle burnout resistance of the device. In order to solve the above problem, the present application provides a third silicon carbide super-junction device structure, please refer to Figure 5A- Figure 6 .
[0054] In this embodiment, the silicon carbide super-junction device structure includes an N-type substrate 101, a super-junction structure is arranged above the N-type substrate 101, the super-junction structure includes a heavily doped N-type epitaxial layer 102 formed above the N-type substrate 101, a heavily doped P-column region 103 is formed in the center of the heavily doped N-type epitaxial layer 102, a gate trench oxide 108 is formed above the heavily doped P-column region 103, a polysilicon gate 109 is formed in the inside of the gate trench oxide 108, an oxide dielectric layer 110 is formed above the polysilicon gate 109, a P-body region 104 is formed on both sides of the gate trench oxide 108, an N+ source region 105 is formed above the P-body region 104, a P+ contact region 106 is formed on both sides of the N+ source region 105, the P+ contact region 106 and the N+ source region 105 are short-circuited by a source electrode 111, the source electrode 111 completely surrounds and wraps the oxide dielectric layer 110 in the inside, a drain electrode 112 is formed below the N-type substrate 101, the top of the heavily doped P-column region 103 is short-circuited with a selective P-type half-pack structure 107 through the source electrode 111, the heavily doped P-column region 103 is formed by multiple epitaxy and multiple ion implantation or slot filling, the source electrode is a semiconductor power device, the width of the heavily doped P-column region 103 is consistent with the width of the trench gate in the gate trench oxide 108, the heavily doped P-column region 103 includes a first heavily doped P-column region 1031, a second heavily doped P-column region 1032, a third heavily doped P-column region 1033, a fourth heavily doped P-column region 1034 and a fifth heavily doped P-column region 1035, the first heavily doped P-column region 1031 is grown above the N-type substrate 101, the second heavily doped P-column region 1032 is formed above the first heavily doped P-column region 1031, the third heavily doped P-column region 1033 is formed above the second heavily doped P-column region 1032, the fourth heavily doped P-column region 1034 is formed above the third heavily doped P-column region 1033, the fifth heavily doped P-column region 1035 is formed above the fourth heavily doped P-column region 1034, the gate trench oxide 108 is located above the fifth heavily doped P-column region 1035, the heavily doped N-type epitaxial layer 102 is formed by multiple epitaxy, and the epitaxial resistivity is consistent, the heavily doped N-type epitaxial layer 202 includes multiple epitaxial layers formed by epitaxy, the first heavily doped P-column region 1031, the second heavily doped P-column region 1032, the third heavily doped P-column region 1033, the fourth heavily doped P-column region 1034 and the fifth heavily doped P-column region 1035 are respectively formed by ion implantation on the epitaxial layer, the width of the first heavily doped P-column region 1031, the second heavily doped P-column region 1032, the third heavily doped P-column region 1033 and the fourth heavily doped P-column region 1034 is the same as the width of the gate trench oxide 108, the width of the fifth heavily doped P-column region 1035 is the sum of the width of the gate trench oxide 108 and the width of the selective P-type half-pack structure 107.
[0055] The embodiment can achieve a better trade-off of breakdown voltage and on-state resistance in multiple epitaxy and ion implantation processes, while having small parasitic capacitance, low switching loss and high reliability, thereby providing a feasible technical path for commercial application of silicon carbide super-junction devices. Similarly, the structure can also add a bottom auxiliary layer on the N-type substrate 201 to form a semi-super junction structure, thereby reducing the difficulty and cost of device manufacturing process and further improving the reliability of the device.
[0056] Preferably, the ion implantation doses of the first, second, third, fourth and fifth heavily doped P pillar regions 1031, 1032, 1033, 1034 and 1035 decrease in turn.
[0057] Preferably, the heavily doped N-type epitaxial layer 102 includes a first epitaxial layer 1021, a second epitaxial layer 1022, a third epitaxial layer 1023, a fourth epitaxial layer 1024, a fifth epitaxial layer 1025 and a sixth epitaxial layer 1026, the first epitaxial layer 1021 is formed above the N-type substrate 101, the second epitaxial layer 1022 is formed above the first epitaxial layer 1021, the third epitaxial layer 1023 is formed above the second epitaxial layer 1022, the fourth epitaxial layer 1024 is formed above the third epitaxial layer 1023, the fifth epitaxial layer 1025 is formed above the fourth epitaxial layer 1024, the first heavily doped P pillar region 1031 is located in the center of the first epitaxial layer 1021, the second heavily doped P pillar region 1032 is located in the center of the second epitaxial layer 1022, the third heavily doped P pillar region 1033 is located in the center of the third epitaxial layer 1023, the fourth heavily doped P pillar region 1034 is located in the center of the fourth epitaxial layer 1024, the fifth heavily doped P pillar region 1035 is located in the center of the fifth epitaxial layer 1025, the lower end of the gate trench oxide 108 is located in the center of the sixth epitaxial layer 1026, the sixth epitaxial layer 1026 is formed above the fifth epitaxial layer 1025, the sixth epitaxial layer 1026 is used to form a top cell region to reduce the on-state resistance of the device, the first, second, third and fourth heavily doped P pillar regions 1031, 1032, 1033 and 1034 are short-circuited with the source electrode 111 through the selective P-type half-pack structure 107, the doping concentrations of the first, second, third, fourth and fifth epitaxial layers 1021, 1022, 1023, 1024 and 1025 decrease in turn, and the ion implantation doses of the first, second, third, fourth and fifth heavily doped P pillar regions 1031, 1032, 1033, 1034 and 1035 increase in turn.
[0058] By optimizing the charge balance state of the super-junction column region, the electric field strength of the junction between the column regions in the device is reduced, the anti-single particle burnout capability of the device is improved, and meanwhile the device has the characteristics of high breakdown voltage, small on-resistance, small parasitic capacitance, low switching loss and high reliability, which provides a feasible technical path for the commercial application of the silicon carbide super-junction device. Similarly, the structure can also add a bottom auxiliary layer above the N-type substrate 101 of the device to form a semi-super junction structure, so as to reduce the difficulty and cost of the device manufacturing process and further improve the reliability of the device. By optimizing the charge balance state of the super-junction column region, the electric field strength of the junction between the column regions in the device is reduced, the anti-single particle burnout capability of the device is improved.
[0059] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can make equivalent replacement or change according to the technical scheme and inventive concept of the present application within the technical range disclosed by the present application, which should be covered within the protection scope of the present application.
Claims
1. A silicon carbide MOSFET device with a superjunction structure, characterized in that, include: An N-type substrate (101) is formed on which a drain electrode (112) is deposited. A superjunction structure is provided, comprising a heavily doped N-type epitaxial layer (102) grown on top of an N-type substrate (101), a heavily doped P-pillar region (103) formed in the center of the heavily doped N-type epitaxial layer (102), a gate trench oxide (108) disposed above the heavily doped P-pillar region (103), P-body regions (104) formed on both sides of the gate trench oxide (108), an N+ source region (105) formed above the P-body region (104), P+ contact regions (106) formed on both sides of the N+ source region (105), and a polysilicon gate (109) formed inside the gate trench oxide (108). An oxide dielectric layer (110) is formed above the polysilicon gate (109). The P+ contact region (106) and the N+ source region (105) are shorted by a source electrode (111). The interior of the source electrode (111) is fully enclosed and connected to the oxide dielectric layer (110). The top of the heavily doped P pillar region (103) is shorted to the selective P-type semi-enclosed structure (107) by the source electrode (111) to convert part of the gate-drain capacitance into drain-source capacitance and reduce the device Miller capacitance.
2. The silicon carbide MOSFET device with a superjunction structure according to claim 1, characterized in that: The heavily doped P-pillar region (103) is formed by multiple epitaxial growths and multiple ion implantations or trench fillings.
3. The silicon carbide MOSFET device with a superjunction structure according to claim 2, characterized in that: The width of the heavily doped P-pillar region (103) is the same as the trench gate width of the gate trench oxide (108) to suppress the electric field strength at the bottom of the trench of the MOSFET device.
4. The silicon carbide MOSFET device with a superjunction structure according to claim 1, characterized in that: The heavily doped P-pillar region (103) includes a first heavily doped P-pillar region (1031), a second heavily doped P-pillar region (1032), a third heavily doped P-pillar region (1033), a fourth heavily doped P-pillar region (1034), and a fifth heavily doped P-pillar region (1035). The first heavily doped P-pillar region (1031) is grown on top of the N-type substrate (101). The second heavily doped P-pillar region (1032) is formed on top of the first heavily doped P-pillar region (1031). The third heavily doped P-pillar region (1033) is formed on top of the second heavily doped P-pillar region (1032). The fourth heavily doped P-pillar region (1034) is formed on top of the third heavily doped P-pillar region (1033). The fifth heavily doped P-pillar region (1035) is formed on top of the fourth heavily doped P-pillar region (1034). The gate trench oxide (108) is located on top of the fifth heavily doped P-pillar region (1035).
5. The silicon carbide MOSFET device with a superjunction structure according to claim 3, characterized in that: The heavily doped N-type epitaxial layer (102) includes an epitaxial layer formed by multiple epitaxys. The first heavily doped P-pillar region (1031), the second heavily doped P-pillar region (1032), the third heavily doped P-pillar region (1033), the fourth heavily doped P-pillar region (1034) and the fifth heavily doped P-pillar region (1035) are formed by ion implantation on the epitaxial layer, respectively.
6. The silicon carbide MOSFET device with a superjunction structure according to claim 5, characterized in that: The widths of the first doped P-pillar region (1031), the second doped P-pillar region (1032), the third doped P-pillar region (1033), and the fourth doped P-pillar region (1034) are the same as the width of the gate trench oxide (108), and the width of the fifth doped P-pillar region (1035) is the sum of the widths of the gate trench oxide (108) and the selective P-type half-enclosed structure (107).
7. The silicon carbide MOSFET device with a superjunction structure according to claim 6, characterized in that: The ion implantation doses of the first-doped P-pillar region (1031), the second-doped P-pillar region (1032), the third-doped P-pillar region (1033), the fourth-doped P-pillar region (1034), and the fifth-doped P-pillar region (1035) decrease sequentially.
8. The silicon carbide MOSFET device with a superjunction structure according to claim 6, characterized in that: The heavily doped N-type epitaxial layer (102) includes a first epitaxial layer (1021), a second epitaxial layer (1022), a third epitaxial layer (1023), a fourth epitaxial layer (1024), a fifth epitaxial layer (1025), and a sixth epitaxial layer (1026). The first epitaxial layer (1021) is formed above the N-type substrate (101), the second epitaxial layer (1022) is formed above the first epitaxial layer (1021), the third epitaxial layer (1023) is formed above the second epitaxial layer (1022), the fourth epitaxial layer (1024) is formed above the third epitaxial layer (1023), and the fifth epitaxial layer (1025) is formed above the fourth epitaxial layer (1024).
9. The silicon carbide MOSFET device with a superjunction structure according to claim 8, characterized in that: The first doped P-pillar region (1031) is located in the center of the first epitaxial layer (1021), the second doped P-pillar region (1032) is located in the center of the second epitaxial layer (1022), the third doped P-pillar region (1033) is located in the center of the third epitaxial layer (1023), the fourth doped P-pillar region (1034) is located in the center of the fourth epitaxial layer (1024), the fifth doped P-pillar region (1035) is located in the center of the fifth epitaxial layer (1025), and the lower end of the gate trench oxide (108) is located at the center of the first doped P-pillar region (1031). At the center of the sixth epitaxial layer (1026), the doping concentrations of the first epitaxial layer (1021), the second epitaxial layer (1022), the third epitaxial layer (1023), the fourth epitaxial layer (1024), and the fifth epitaxial layer (1025) decrease sequentially, while the ion implantation doses of the first heavily doped P-pillar region (1031), the second heavily doped P-pillar region (1032), the third heavily doped P-pillar region (1033), the fourth heavily doped P-pillar region (1034), and the fifth heavily doped P-pillar region (1035) increase sequentially.
10. The silicon carbide MOSFET device with a superjunction structure according to claim 9, characterized in that: The sixth epitaxial layer (1026) is formed above the fifth epitaxial layer (1025). The sixth epitaxial layer (1026) is used to form the top cell region to reduce the on-resistance of the device. The first heavily doped P-pillar region (1031), the second heavily doped P-pillar region (1032), the third heavily doped P-pillar region (1033), and the fourth heavily doped P-pillar region (1034) are shorted to the source electrode (111) through a selective P-type half-enclosed structure (107).
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