Film deposition method for wafer surface

Abstract

The invention provides a method for depositing a thin film on the surface of a wafer. The method at least comprises the following steps: S1, providing a wafer subjected to dry etching treatment; s2, performing rapid thermal annealing treatment on the wafer to repair surface damage caused by dry etching; and S3, depositing a dielectric film on the surface of the wafer subjected to the rapid thermal annealing treatment through a plasma enhanced chemical vapor deposition process. According to the collaborative film deposition method, silicon wafer surface damage caused by dry etching is eliminated, precise control over the film thickness and optimization of the fitting degree of the measurement result can be achieved, the reliability of the film measurement result is improved, the method is combined with efficient annealing of RTP and low-temperature deposition of PECVD, and the reliability of the film measurement result is improved. Cooperative regulation and control of the film thickness, the crystallinity, the interface quality and the measurement fitting degree are achieved, and the method has great significance in promoting miniaturization of semiconductor devices.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a thin film deposition method for wafer surface. BACKGROUND

[0002] In the manufacturing process of semiconductor chips, various micro patterns and structures are needed to be made on the substrate material such as wafer to form various elements and interconnection lines of integrated circuits. Dry etching is a general technical means for pattern transfer due to its good anisotropy and high resolution. Through dry etching, the circuit pattern determined by photolithography is transferred from photoresist to the underlying semiconductor material or metal layer, thereby realizing the function of chip design.

[0003] However, in the etching process, due to the non-uniformity of etching rate in the wafer, the thickness of the thin film after etching is also non-uniform. The general process steps include first removing most of the thin film by main etching, and then removing the remaining part by over-etching. In this process, the substrate material inevitably suffers slight thickness loss, and dry etching forms a damage layer with high roughness and unstable morphology on the substrate surface. The mainstream measurement method of dielectric thin film is optical measurement. The thickness data is obtained by fitting analysis of the actual test spectrum data and the theoretical spectrum model, therefore, the irregular damage layer and the deteriorated interface will introduce optical signal noise, which reduces the reliability of the data obtained in the fitting analysis. This makes the process monitoring and thickness control extremely difficult, and seriously interferes with the accuracy of thin film optical measurement.

[0004] Therefore, it is necessary to provide a thin film deposition method capable of accurately controlling and / or measuring the thickness of the thin film on the wafer surface. SUMMARY

[0005] In view of the defects and deficiencies in the prior art, the present application provides a thin film deposition method for wafer surface to solve at least one or more of the above technical problems.

[0006] The present application provides a thin film deposition method for wafer surface, which at least comprises the following steps: S1: providing a wafer processed by dry etching; S2: performing rapid thermal annealing treatment on the wafer to repair the surface damage caused by dry etching; S3: depositing a dielectric thin film on the wafer surface after the rapid thermal annealing treatment by a plasma enhanced chemical vapor deposition process. The technical solution provides a fundamental process solution to solve the problems of surface damage after dry etching and inaccurate thin film measurement, and through the sequential combination of RTP repair and PECVD deposition, a thin film with stable properties and more dense uniformity is obtained, and the performance and measurement accuracy of the thin film are synergistically improved.

[0007] In an optional embodiment, step S2 comprises: S201: control the heating rate to heat the wafer to an oxidation temperature; S202: at the oxidation temperature, oxygen is introduced into the reaction chamber to cause the surface of the wafer to undergo an oxidation reaction to generate an oxide layer. This step not only repairs the damage to the semiconductor layer, but also grows a layer of high-quality dense oxide layer, providing a more ideal substrate for subsequent processes.

[0008] In an optional embodiment, the heating rate of the rapid thermal annealing treatment is 50-150℃ / s, the oxidation temperature is 800-1000℃, and the oxidation reaction time is 10-60s. Effective RTP repair effect can be obtained within this process parameter range.

[0009] In an optional embodiment, the material of the oxide layer is silicon dioxide. RTP is performed on a silicon wafer, and silicon dioxide is generated on the surface of the silicon wafer after the reaction of oxygen and silicon.

[0010] In an optional embodiment, the thickness of the oxide layer is 10-50Å. The repair layer within this thickness range can balance between effective repair and not affecting device design.

[0011] In an optional embodiment, step S3 comprises: S301: measuring the thickness of the oxide layer generated on the wafer surface; S302: according to the difference between the measured thickness of the oxide layer and the target thickness, depositing a dielectric thin film with a supplementary thickness by the plasma enhanced chemical vapor deposition process, so that the total thickness of the oxide layer and the dielectric thin film reaches the target thickness. This step measures the thickness of the oxide layer generated by RTP first, and then deposits PECVD based on it to supplement the remaining thickness, achieving precise control of the final thin film thickness.

[0012] In an optional embodiment, the process temperature of the plasma enhanced chemical vapor deposition process is 380-420℃, and different deposition times are selected according to the target thickness. Low-temperature deposition can avoid re-heating damage to the repaired lattice.

[0013] In an optional embodiment, the material of the dielectric thin film is silicon dioxide, silicon nitride or silicon oxynitride.

[0014] In an optional embodiment, the thickness of the dielectric film is less than 200 angstroms. The technical solution of the present application is particularly suitable for thin film processes with a film thickness of less than 200 angstroms.

[0015] In an optional embodiment, the rapid thermal annealing process and the plasma enhanced chemical vapor deposition process are continuously performed in situ in the same reaction chamber. This can prevent the device from being exposed to introduced interface contamination or oxidation, and can save wafer transfer time and improve process efficiency.

[0016] Compared with the prior art, the wafer surface thin film deposition method provided by the present application has the following beneficial effects: The wafer surface thin film deposition method provided by the present application can not only eliminate the damage to the silicon wafer surface caused by dry etching, but also achieve precise control of the thickness of the thin film, and optimize the fitting degree of the measurement result, thereby significantly improving the reliability of the thin film measurement result. The method combines the high-efficiency annealing capability of RTP (rapid thermal annealing) and the low-temperature deposition characteristics of PECVD (plasma enhanced chemical vapor deposition), and cooperatively optimizes the thickness, crystallinity, interface quality and measurement fitting degree of the thin film, which is of great significance for promoting the feature size reduction of semiconductor devices. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A wafer surface thin film deposition method flowchart is provided in the present application. DETAILED DESCRIPTION

[0018] In the prior art, dry etching (Dry-Etch) is an etching process performed in an atmosphere or a vacuum, which usually uses ions or chemicals in a gas to remove part of the material surface. This technology is crucial in semiconductor manufacturing, as it can achieve high precision and high resolution pattern transfer.

[0019] Rapid thermal annealing (RTP) is a technology that can heat the wafer to a high temperature in a short time, which can be used to improve the crystal structure of the thin film, eliminate defects, etc.

[0020] PECVD (Plasma Enhanced Chemical Vapor Deposition) refers to a plasma enhanced chemical vapor deposition method. PECVD uses microwaves or radio frequency to ionize a gas containing thin film component atoms to form a local plasma. The plasma has strong chemical activity and can easily react to deposit the desired thin film on the substrate.

[0021] When etching a film, the etching rate and film thickness within the wafer are not completely uniform, and generally, a main etching step is used to remove most of the film, and a over-etching step is used to remove the remaining film. The selectivity between the substrate material and the etched film is high enough to avoid losing too much substrate material, and the selectivity between the substrate material and the etched film can be improved by using different etching conditions for the main etching and the over-etching, but the substrate material will inevitably have a slight thickness loss. The mainstream measurement method of dielectric film is optical measurement, and the thickness data is obtained by fitting the actual test spectrum data with the theoretical spectrum model. The slight loss of the substrate, the deposition of the thin film (<200 Å), and the subsequent measurement will be disturbed, resulting in limited measurement fitting and reducing the reliability of the data.

[0022] To overcome the above technical problems, the present application provides a wafer surface film deposition method. The technical solutions of the present application are described in detail below through examples. Those skilled in the art can easily understand other advantages and effects of the present application through the disclosure of the present application. The present application can also be implemented or applied through other different specific embodiments, and each detail in the present application can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0023] Reference is made to Figure 1 The wafer surface film deposition method provided by the present embodiment is described in detail below.

[0024] S1: providing a wafer subjected to dry etching treatment.

[0025] Specifically, taking a commonly used 8-inch silicon wafer as an example, first, the silicon wafer is subjected to patterned photolithography and dry etching, and part of the silicon substrate surface is exposed. At this time, the exposed part of the silicon substrate surface has a slight thickness loss caused by etching and is accompanied by various surface structure defects.

[0026] S2: performing rapid thermal annealing treatment on the wafer to repair the surface damage caused by dry etching.

[0027] Specifically, since the wafer surface after dry etching has lattice damage, dangling bonds and contaminants, direct deposition of PECVD film will cause an increase in interface defects, a decrease in film quality, and serious interference with the accuracy of optical measurement signals. Therefore, RTP treatment is performed before deposition, which can repair lattice defects through high-temperature annealing, thereby forming a surface flat and chemically stable interface.

[0028] S201: first, control the heating rate to heat the wafer to an oxidation temperature.

[0029] Specifically, the silicon wafer is heated under the protection of inert gas, and the heating rate is 50-150 °C / s until the preset oxidation temperature of 800-1000 °C is reached. The rapid heating rate of 50-150 °C / s can make the silicon wafer quickly pass through the low temperature interval and reach the target reaction temperature, which helps to inhibit the diffusion of impurities during the heating process, thereby more conducive to the formation of high-quality interface. As an example, the heating rate can be 60 °C / s, 90 °C / s, 110 °C / s or 140 °C / s. Further, the heating rate is 80-120 °C / s. The oxidation temperature interval of 800-1000 °C can provide sufficient energy for silicon atoms and oxygen atoms to react and grow a dense SiO2 oxide layer. As an example, the oxidation temperature can be 820 °C, 850 °C, 900 °C, 920 °C or 950 °C. Further, the oxidation temperature is 850-950 °C.

[0030] S202: Then, oxygen is introduced into the reaction chamber at the oxidation temperature, so that the surface of the wafer undergoes an oxidation reaction to generate an oxide layer.

[0031] Specifically, the oxidation reaction step not only repairs the damage to the semiconductor layer structure, but also grows a high-quality, dense oxide layer. This oxide layer, as part of the thin film stack, has stable and known thickness and optical constants, such as refractive index n and extinction coefficient k, providing a more ideal growth substrate for subsequent PECVD processes. The present embodiment uses a silicon wafer for RTP, so the material layer generated on the surface of the silicon wafer after the reaction of oxygen and silicon is a silicon dioxide layer.

[0032] In an optional embodiment, the oxidation reaction time is 10-60 s, which can obtain effective RTP repair effect and generate an oxide film layer with a suitable thickness, reducing the impact of high temperature on other sensitive areas of the device. As an example, the oxidation reaction time can be 12 s, 20 s, 30 s, 40 s or 50 s. Further, the oxidation reaction time is 20-40 s.

[0033] In an optional embodiment, the thickness of the silicon dioxide layer generated on the surface of the silicon wafer is 10-50 Å. An oxide layer with this thickness is sufficient to effectively cover and eliminate the surface damage layer caused by dry etching, and its own optical signal is easy to be fitted and deducted in total thickness measurement, avoiding the introduction of new process deviations due to the over-thickness of the repair layer. As an example, the thickness of the silicon dioxide layer is 15 Å, 20 Å, 30 Å, 40 Å or 45 Å. Further, the thickness of the silicon dioxide layer is 25-35 Å, which can balance the effective repair and the impact on device design within this thickness range.

[0034] S3: After the wafer surface is treated by rapid thermal annealing, a dielectric thin film is deposited on the wafer surface by a plasma enhanced chemical vapor deposition (PECVD) process.

[0035] Specifically, PECVD deposition is performed again on the surface after RTP optimization, so that a denser and more uniform dielectric thin film can be obtained, and the quality of the film / substrate interface is significantly improved. Based on the obtained high-quality interface and thin film, the signal-to-noise ratio of the optical measurement signal is also improved, and the fitting degree, reliability and accuracy of the thickness measurement result are greatly increased.

[0036] S301: First, the thickness of the generated oxide layer on the wafer surface is measured.

[0037] Specifically, this step plays an important role in setting the process parameters of PECVD by first measuring the thickness of the RTP-generated oxide layer as the basis for the subsequent deposition of the dielectric thin film, and then performing PECVD deposition to supplement the remaining thickness. The two together achieve precise control of the final film thickness.

[0038] S302: Subsequently, according to the difference between the measured thickness of the oxide layer and the target thickness, a dielectric thin film of a supplementary thickness is deposited by a PECVD process, so that the total thickness of the oxide layer and the dielectric thin film reaches the target thickness.

[0039] Specifically, the process temperature of PECVD is 380-420℃, and different deposition time is selected according to the target thickness to form a dielectric thin film with a suitable thickness on the surface of the oxide layer. The supplement of PECVD deposition based on the thickness of the oxide layer substantially reduces the difficulty of controlling the accuracy of the total thickness (oxide layer + PECVD layer), and the low-temperature deposition can avoid the re-heating damage to the repaired lattice. In this step, the PECVD process is only responsible for depositing the thickness difference part, and the deposition is performed on the oxide layer with perfect structure and smooth surface, which greatly reduces the error of the final total thickness, thereby improving the accuracy and reliability of the measurement data. Further, the process temperature of PECVD is 400℃, and the deposition rate is 50-200Å / min. The deposition time required is determined according to the thickness difference between the target thickness and the thickness of the oxide layer and the reasonable deposition rate. For example, when the thickness of the layer to be deposited by PECVD is 130Å, in order to achieve optimal film quality and meet the quality requirements of high density and uniformity, a lower deposition rate can be used. The deposition rate of PECVD process is set to 65Å / min, and the deposition process time = target deposition thickness / deposition rate = 130Å / (65Å / min) = 2.0min. Alternatively, a higher deposition rate can be selected according to the process time requirement to improve productivity and reduce process cost under the premise of meeting the film performance. It can be understood that the process time is different at the same deposition rate according to the different target thicknesses required, and the process time does not limit the scope of the technical solutions to be protected by the present application.

[0040] In an optional embodiment, the rapid thermal annealing process and the plasma-enhanced chemical vapor deposition process are continuously performed in situ in the same reaction chamber, which can prevent interface pollution or oxidation caused by device exposure and save wafer transfer time, thereby improving process efficiency.

[0041] In an optional embodiment, the dielectric thin film can be a layer of silicon dioxide (SiO2), silicon nitride (SiN X ) or silicon oxynitride (SiON) and the like. Silicon dioxide, silicon nitride and silicon oxynitride are the most important and common dielectric thin films in semiconductor devices, which are used for device isolation, etching stop layer, sidewall, passivation layer and the like. Further, the dielectric thin film is a layer of silicon dioxide material, which is the same as the oxide layer material formed on the surface of the silicon wafer in the previous step. The same material layer is superimposed, and the optical properties are the same, so there are fewer variables in the thickness monitoring, and the monitoring data is more accurate. This method is especially suitable for semiconductor processes in which a layer of silicon dioxide dielectric is deposited on the surface of a silicon wafer.

[0042] In an optional embodiment, the thickness of the dielectric thin film is less than 200 A. It can be understood that when the thickness of the thin film is less than 200 A, the influence of surface damage, interface roughness and other factors on the performance of the thin film and the accuracy of optical measurement will be sharply enlarged. For a thin film with a thickness of more than 200 A, the structure quality can be improved by other existing technical methods. The technical solution provided in the embodiment is particularly suitable for the silicon dioxide PECVD process when the thickness of the thin film is less than 200 A.

[0043] The following provides a specific example in actual production: Step S1: performing a precursor step such as dry etching on a P-type silicon wafer with a diameter of 8 inches.

[0044] Step S2: rapidly heating the silicon wafer in step S1 to 900°C at a heating rate of 100°C / s under a nitrogen atmosphere. Rapid heating is required in this stage to reduce impurity diffusion. After the temperature is stabilized at 900°C, high-purity oxygen is introduced into the reaction chamber at a flow rate of 1 slm, and the pressure in the reaction cavity is maintained at 200 Torr. A thermal oxidation reaction is performed under this condition for 30 seconds. At this time, the oxygen reacts with the surface of the silicon substrate to generate a dense and uniform silicon dioxide oxide layer. After the oxidation is completed, the oxygen is stopped, and the wafer is rapidly cooled to below 400°C under a nitrogen atmosphere. It is measured that the thickness of the oxide layer generated in this step is about 25 A, which is sufficient to repair the damage to the underlying silicon lattice and form a flat passivation surface.

[0045] Step S3: measuring the thickness of the oxide layer generated in the previous step using an online spectral ellipsometer to confirm that the thickness is 25 A. It is confirmed that a total thickness of 150 A of the silicon dioxide thin film is deposited, and then the temperature of the wafer is adjusted and stabilized at 350°C. Silane (SiH4) and laughing gas (N2O) are introduced into the PECVD reaction cavity as reaction gases, and the plasma is started under the conditions of a radio frequency power of 50 W and a pressure of 300 mTorr. According to the difference between the target total thickness of 150 A and the thickness of the oxide layer of 25 A, that is, the supplementary thickness value of 125 A, a supplementary thickness of silicon dioxide thin film is accurately deposited by controlling the deposition time to be 80 seconds.

[0046] After the deposition is completed, a silicon dioxide thin film stack with a total thickness (oxide layer + PECVD layer) of 150 A is obtained. The above process combines the sequence of RTP repair and PECVD deposition, and can obtain a thin film with stable properties and higher density and uniformity, thereby achieving a synergistic improvement in the performance of the thin film and the accuracy of the measurement.

[0047] In summary, the wafer surface thin film deposition method provided by the present application controls the temperature rising rate by RTP, and raises the wafer to the temperature required by the oxidation process. The high temperature in the heating stage makes the semiconductor crystal structure rearrange to eliminate the lattice defects and improve the order of the crystal, thereby improving the electronic conduction performance of the semiconductor material. After the temperature is stabilized, oxygen is introduced into the reaction chamber and the reaction time is controlled, so that the oxygen and silicon react to generate silicon dioxide on the surface of the silicon wafer. This growth process helps to repair the surface damage to the wafer surface caused by dry etching. High-temperature RTP rapid annealing can also promote the diffusion of impurities from the semiconductor crystal, reducing the concentration of impurities, which is conducive to improving the quality of the device. Therefore, the wafer surface thin film deposition method provided by the present application effectively overcomes the various shortcomings in the prior art, and thus has a high industrial utilization value.

[0048] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of thin film deposition on a wafer surface, characterized by, At least comprising the following steps: S1: providing a wafer processed by dry etching; S2: performing rapid thermal annealing on the wafer to repair surface damage caused by the dry etching; S3: depositing a dielectric film on the wafer surface processed by the rapid thermal annealing through a plasma enhanced chemical vapor deposition process.

2. The thin film deposition method of a wafer surface according to claim 1, wherein Step S2 comprises: S201: controlling the heating rate to heat the wafer to an oxidation temperature; S202: introducing oxygen into the reaction chamber at the oxidation temperature to cause the surface of the wafer to undergo an oxidation reaction to form an oxide layer.

3. The thin film deposition method of a wafer surface according to claim 2, wherein The rapid thermal annealing process has a heating rate of 50-150℃ / s, an oxidation temperature of 800-1000℃, and an oxidation reaction time of 10-60s.

4. The thin film deposition method of a wafer surface according to claim 2, wherein The material of the oxide layer is silicon dioxide.

5. The thin film deposition method of a wafer surface according to claim 2, wherein The thickness of the oxide layer is 10-50Å.

6. The thin film deposition method of a wafer surface according to claim 2, wherein Step S3 comprises: S301: measuring the thickness of the oxide layer formed on the wafer surface; S302: depositing a dielectric film with a complementary thickness through the plasma enhanced chemical vapor deposition process according to the difference between the measured thickness of the oxide layer and a target thickness, so that the total thickness of the oxide layer and the dielectric film reaches the target thickness.

7. The thin film deposition method of a wafer surface according to claim 6, wherein The process temperature of the plasma enhanced chemical vapor deposition process is 380-420℃.

8. The thin film deposition method of a wafer surface according to claim 6, wherein The material of the dielectric film is silicon dioxide, silicon nitride, or silicon oxynitride.

9. The thin film deposition method of a wafer surface according to Claim 1, wherein The thickness of the dielectric film is less than 200Å.

10. The thin film deposition method of a wafer surface according to Claim 1, wherein The rapid thermal annealing process and the plasma enhanced chemical vapor deposition process are continuously performed in situ in the same reaction chamber.

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