Electronic device and manufacturing method thereof

Abstract

An electronic device (10) comprises: a functional unit (102); a substrate (130) that supports the functional unit (102); a first metal film (110) that is formed on the substrate (130) side of the functional unit (102) and functions as an electrode; and a second metal film (140) formed on the substrate (130) and bonded to the first metal film (110). The functional unit (102) has: a first surface (102a) facing the substrate (130), the first metal film (110) being interposed between the first surface (102a) and the substrate (130); and a second surface (102b) extending from the first surface (102a) in a direction different from an extending direction of the first surface (102a). The first metal film (110) is formed from the first surface (102a) of the functional unit (102) to a portion of the second surface (102b).

Description

Technical Field

[0001] This disclosure relates to an electronic device and a method for manufacturing the same. Background Technology

[0002] A technique is known of growing functional parts (functional layers) such as piezoelectric element layers and semiconductor layers on a growth substrate, peeling the functional parts off the growth substrate, and bonding the functional parts to different substrates (for example, see Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-152676 (see abstract) Summary of the Invention

[0006] Technical problem solved by the present invention

[0007] In the aforementioned conventional techniques, when the functional part warps, it may not be able to bond the functional part well to the substrate.

[0008] The purpose of this disclosure is to ensure that the functional parts are well bonded to the substrate even when the functional parts warp.

[0009] Means for solving technical problems

[0010] The electronic device of this disclosure includes a functional part, a substrate supporting the functional part, a first metal film deposited as an electrode on the substrate-facing side of the functional part, and a second metal film formed on the substrate and bonded to the first metal film. The functional part includes a first surface facing the substrate via the first metal film and a second surface extending from the first surface in a direction different from the extending direction of the first surface. The first metal film is deposited from the first surface of the functional part onto a portion of the second surface.

[0011] The method of manufacturing an electronic device disclosed herein includes: depositing a first metal film from a first surface of a functional portion onto a portion of a second surface, the functional portion having the first surface and the second surface extending from the first surface in a direction different from the extending direction of the first surface; and bonding the first metal film deposited on the functional portion to a second metal film formed on a substrate. Another method of manufacturing an electronic device includes: separating a first substrate and a functional portion formed on the first substrate from each other; depositing a first metal film on a first surface of the functional portion, the first surface being a surface separated from the first substrate; and bonding the first metal film deposited on the first substrate to a second metal film formed on a second substrate different from the first substrate.

[0012] Invention Effects

[0013] According to this disclosure, even when the functional part warps, the functional part can be well bonded to the substrate by bonding the first metal film deposited on the functional part with the second metal film formed on the substrate. Attached Figure Description

[0014] Figure 1 (A) is a cross-sectional view showing the growth substrate used in the manufacturing method of the electronic device in the first embodiment. Figure 1 (B) is a cross-sectional view showing the process of forming a functional layer on a growth substrate. Figure 1 (C) is a cross-sectional view showing the process of patterning the growth substrate and functional layer.

[0015] Figure 2 Figure (A) and Figure 2 (B) are cross-sectional views illustrating the etching process of the growth substrate in the manufacturing method of the electronic device in the first embodiment. Figure 2 (C) is a cross-sectional view showing another example of the etching process in the manufacturing method of the electronic device in the first embodiment.

[0016] Figure 3 (A) is a cross-sectional view showing the process of separating the functional layer from the growth substrate in the manufacturing method of the electronic device in the first embodiment. Figure 3 (B) is a cross-sectional view showing the process of forming a first metal film in the manufacturing method of the electronic device in the first embodiment.

[0017] Figure 4 (A) is an enlarged cross-sectional view showing the functional layer and the first metal film in the manufacturing method of the electronic device in the first embodiment. Figure 4 (B) is a schematic diagram showing the angle between the first surface and the second surface of the functional layer in the manufacturing method of the electronic device in the first embodiment.

[0018] Figure 5 (A) is a cross-sectional view showing the process of transferring a functional layer to a device substrate in the manufacturing method of the electronic device according to the first embodiment. Figure 5 (B) is an enlarged cross-sectional view of the second metal film on the device substrate in the manufacturing method of the electronic device in the first embodiment.

[0019] Figure 6 (A) is a cross-sectional view showing the process of bonding the metal film of the functional layer and the metal film of the device substrate together in the manufacturing method of the electronic device in the first embodiment. Figure 6 (B) is a cross-sectional view showing the process of forming an electrode layer on a functional layer in the manufacturing method of the electronic device in the first embodiment.

[0020] Figure 7 Figure (A) and Figure 7 (B) are schematic diagrams illustrating the state in which the functional layer is stripped in the comparative example. Figure 7 (C) and Figure 7 (D) is a schematic diagram illustrating the effect of suppressing functional layer stripping in the first embodiment.

[0021] Figure 8 (A) is a cross-sectional view showing the growth substrate used in the manufacturing method of the electronic device in the second embodiment. Figure 8 (B) is a cross-sectional view showing the process of forming a buffer layer and functional parts on a growth substrate in the manufacturing method of the electronic device according to the second embodiment. Figure 8 (C) is a cross-sectional view showing the process of patterning the growth substrate, buffer layer and functional parts in the manufacturing method of the electronic device in the second embodiment.

[0022] Figure 9 (A) is a cross-sectional view showing the process of forming a Schottky electrode and photoresist on a functional part in the manufacturing method of the electronic device in the second embodiment. Figure 9 (B) is a cross-sectional view showing the process of patterning a Schottky electrode in the manufacturing method of the electronic device in the second embodiment.

[0023] Figure 10 (A) is a cross-sectional view showing the etching process of the growth substrate in the manufacturing method of the electronic device in the second embodiment. Figure 10 (B) is a cross-sectional view showing the process of separating the functional part from the growth substrate in the manufacturing method of the electronic device in the second embodiment.

[0024] Figure 11 (A) is a cross-sectional view showing the process of removing the buffer layer in the manufacturing method of the electronic device in the second embodiment. Figure 11 (B) is a cross-sectional view showing the process of depositing a first metal film on the n+GaN layer of the functional part in the manufacturing method of the electronic device in the second embodiment.

[0025] Figure 12 (A) to Figure 12 (E) is a cross-sectional view showing the process of depositing a first metal film in the manufacturing method of the electronic device in the second embodiment.

[0026] Figure 13 (A) is a cross-sectional view showing the process of transferring functional parts onto a device substrate in the manufacturing method of the electronic device according to the second embodiment. Figure 13(B) is an enlarged cross-sectional view of the second metal film on the device substrate in the manufacturing method of the electronic device in the second embodiment.

[0027] Figure 14 (A) is a cross-sectional view showing the process of bonding the metal film of the functional part and the metal film of the device substrate together in the manufacturing method of the electronic device in the second embodiment. Figure 14 (B) is a cross-sectional view showing the process of forming an insulating layer and a wiring layer on a functional part in the manufacturing method of the electronic device in the second embodiment.

[0028] Figure 15 (A) is a cross-sectional view showing the process of forming a buffer layer and functional parts on a growth substrate in the manufacturing method of the electronic device in the third embodiment. Figure 15 (B) is a cross-sectional view showing the process of patterning the growth substrate, buffer layer and functional parts in the manufacturing method of the electronic device in the third embodiment.

[0029] Figure 16 (A) is a cross-sectional view showing the process of etching the growth substrate in the manufacturing method of the electronic device in the third embodiment. Figure 16 (B) is a cross-sectional view showing the process of separating the functional part from the growth substrate in the manufacturing method of the electronic device in the third embodiment.

[0030] Figure 17 (A) is a cross-sectional view showing the process of removing the buffer layer in the manufacturing method of the electronic device in the third embodiment. Figure 17 (B) is a cross-sectional view showing the process of depositing a first metal film on a functional part in the manufacturing method of the electronic device in the third embodiment. Figure 17 (C) is an enlarged cross-sectional view showing the first metal film in the manufacturing method of the electronic device in the third embodiment.

[0031] Figure 18 (A) is a cross-sectional view showing the process of transferring functional parts onto a device substrate in the manufacturing method of the electronic device according to the third embodiment. Figure 18 (B) is an enlarged cross-sectional view showing the second metal film on the device substrate in the manufacturing method of the electronic device in the third embodiment.

[0032] Figure 19 (A) is a cross-sectional view showing the process of bonding the metal film of the functional part and the metal film of the device substrate together in the manufacturing method of the electronic device in the third embodiment. Figure 19 (B) is a cross-sectional view showing the process of forming P and N electrodes in the manufacturing method of the electronic device in the third embodiment.

[0033] Figure 20 (A) is a cross-sectional view showing the process of forming a buffer layer and functional parts on a growth substrate in the manufacturing method of the electronic device according to the fourth embodiment. Figure 20 (B) is a cross-sectional view showing the process of patterning the growth substrate, buffer layer and functional parts in the manufacturing method of the electronic device in the fourth embodiment.

[0034] Figure 21 (A) is a cross-sectional view showing the process of etching the growth substrate in the manufacturing method of the electronic device in the fourth embodiment. Figure 21 (B) is a cross-sectional view showing the process of separating the functional part from the growth substrate in the manufacturing method of the electronic device in the fourth embodiment.

[0035] Figure 22 (A) is a cross-sectional view showing the process of removing the buffer layer in the manufacturing method of the electronic device in the fourth embodiment. Figure 22 (B) is a cross-sectional view showing the process of depositing a first metal film on a functional part in the manufacturing method of the electronic device in the fourth embodiment. Figure 22 (C) is an enlarged cross-sectional view showing the first metal film in the manufacturing method of the electronic device in the fourth embodiment.

[0036] Figure 23 (A) to Figure 23 (H) is a cross-sectional view showing another example of the process of depositing a first metal film in the manufacturing method of the electronic device in the fourth embodiment.

[0037] Figure 24 (A) is a cross-sectional view showing the process of transferring functional parts onto a device substrate in the manufacturing method of the electronic device according to the fourth embodiment. Figure 24 (B) is an enlarged cross-sectional view showing the second metal film on the device substrate in the manufacturing method of the electronic device in the fourth embodiment.

[0038] Figure 25 (A) is a cross-sectional view showing the process of bonding the metal film of the functional part and the metal film of the device substrate together in the manufacturing method of the electronic device in the fourth embodiment. Figure 25 (B) is a cross-sectional view showing the process of forming an oxide film on a functional part in the manufacturing method of the electronic device in the fourth embodiment.

[0039] Figure 26 (A) is a cross-sectional view showing the process of forming an opening in the oxide film in the manufacturing method of the electronic device according to the fourth embodiment. Figure 26(B) is a cross-sectional view showing the process of forming a trench in a functional part in the manufacturing method of an electronic device in the fourth embodiment.

[0040] Figure 27 (A) is a cross-sectional view showing the process of forming an oxide film and photoresist in a trench in the manufacturing method of the electronic device according to the fourth embodiment. Figure 27 (B) is a cross-sectional view showing the process of forming an opening in the photoresist in the manufacturing method of the electronic device in the fourth embodiment.

[0041] Figure 28 (A) is a cross-sectional view showing the process of exposing the pGaN layer of functional parts in the manufacturing method of the electronic device in the fourth embodiment. Figure 28 (B) is a cross-sectional view showing the process of forming an opening in the photoresist in the manufacturing method of the electronic device in the fourth embodiment.

[0042] Figure 29 (A) is a cross-sectional view showing the process of forming the source electrode and the gate electrode in the manufacturing method of the electronic device in the fourth embodiment. Figure 29 (B) is a cross-sectional view showing the process of removing photoresist in the manufacturing method of the electronic device in the fourth embodiment.

[0043] Figure 30 (A) is a cross-sectional view showing the process of forming a buffer layer and functional parts on a growth substrate in the manufacturing method of the electronic device in the fifth embodiment. Figure 30 (B) is a cross-sectional view showing the process of patterning the growth substrate, buffer layer and functional parts in the manufacturing method of the electronic device in the fifth embodiment.

[0044] Figure 31 (A) is a cross-sectional view showing the process of forming photoresist on a functional part in the manufacturing method of the electronic device in the fifth embodiment. Figure 31 (B) is a cross-sectional view showing the process of forming a trench in a functional part in the manufacturing method of an electronic device in the fifth embodiment.

[0045] Figure 32 (A) is a cross-sectional view showing the process of forming an oxide film and photoresist in a trench in the manufacturing method of the electronic device according to the fifth embodiment. Figure 32 (B) is a cross-sectional view showing the process of etching the growth substrate in the manufacturing method of the electronic device in the fifth embodiment.

[0046] Figure 33 (A) is a cross-sectional view showing the process of separating the functional part from the growth substrate in the manufacturing method of the electronic device in the fifth embodiment. Figure 33(B) is a cross-sectional view showing the process of removing the buffer layer in the manufacturing method of the electronic device in the fifth embodiment.

[0047] Figure 34 (A) is a cross-sectional view showing the process of depositing a first metal film on a functional part in the manufacturing method of the electronic device in the fifth embodiment. Figure 34 (B) is a cross-sectional view showing the process of transferring functional parts onto a device substrate in the manufacturing method of the electronic device in the fifth embodiment.

[0048] Figure 35 (A) is a cross-sectional view showing the process of forming a buffer layer and functional parts on a growth substrate in the manufacturing method of the electronic device according to the sixth embodiment. Figure 35 (B) is a cross-sectional view showing the first patterning process of the functional part in the manufacturing method of the electronic device in the sixth embodiment.

[0049] Figure 36 (A) is a cross-sectional view showing the second patterning process of the growth substrate, buffer layer and functional parts in the manufacturing method of the electronic device in the sixth embodiment. Figure 36 (B) is a cross-sectional view showing the process of etching the growth substrate in the manufacturing method of the electronic device in the sixth embodiment.

[0050] Figure 37 (A) is a cross-sectional view showing the process of separating the functional part from the growth substrate in the manufacturing method of the electronic device in the sixth embodiment. Figure 37 (B) is a cross-sectional view showing the process of removing the buffer layer in the manufacturing method of the electronic device in the sixth embodiment.

[0051] Figure 38 (A) is a cross-sectional view showing the process of depositing a first metal film on a functional part in the manufacturing method of the electronic device in the sixth embodiment. Figure 38 (B) is an enlarged cross-sectional view showing the first metal film in the manufacturing method of the electronic device in the sixth embodiment.

[0052] Figure 39 (A) is a cross-sectional view showing the process of transferring functional parts onto a device substrate in the manufacturing method of the electronic device according to the sixth embodiment. Figure 39 (B) is an enlarged cross-sectional view showing the second metal film on the device substrate in the manufacturing method of the electronic device in the sixth embodiment.

[0053] Figure 40 (A) is a cross-sectional view showing the process of bonding the metal film of the functional part and the metal film of the device substrate together in the manufacturing method of the electronic device in the sixth embodiment. Figure 40 (B) is a cross-sectional view showing the process of forming an oxide film on a functional part in the manufacturing method of the electronic device in the sixth embodiment.

[0054] Figure 41 (A) is a cross-sectional view showing the process of forming an opening in the oxide film in the manufacturing method of the electronic device according to the sixth embodiment. Figure 41 (B) is a cross-sectional view showing the process of forming a trench in a functional part in the manufacturing method of an electronic device in the sixth embodiment.

[0055] Figure 42 (A) is a cross-sectional view showing the process of forming an oxide film and photoresist in a trench in the manufacturing method of the electronic device according to the sixth embodiment. Figure 42 (B) is a cross-sectional view showing the process of forming an opening in the photoresist in the manufacturing method of the electronic device in the sixth embodiment.

[0056] Figure 43 (A) is a cross-sectional view showing the process of exposing the pGaN layer of functional parts in the manufacturing method of the electronic device in the sixth embodiment. Figure 43 (B) is a cross-sectional view showing the process of forming an opening in the photoresist in the manufacturing method of the electronic device in the sixth embodiment.

[0057] Figure 44 (A) is a cross-sectional view showing the process of forming the source electrode and the gate electrode in the manufacturing method of the electronic device in the sixth embodiment. Figure 44 (B) is a cross-sectional view showing the process of removing photoresist in the manufacturing method of the electronic device in the sixth embodiment.

[0058] Figure 45 (A) is a cross-sectional view showing the process of forming a buffer layer and functional parts on a growth substrate in the manufacturing method of the electronic device in the seventh embodiment. Figure 45 (B) is a cross-sectional view showing the process of patterning the growth substrate, buffer layer and functional parts in the manufacturing method of the electronic device in the seventh embodiment.

[0059] Figure 46 (A) is a cross-sectional view showing the process of forming an oxide film on a functional part in the manufacturing method of the electronic device in the seventh embodiment. Figure 46 (B) is a cross-sectional view showing the process of forming a groove in a functional part in the manufacturing method of an electronic device in the seventh embodiment.

[0060] Figure 47(A) is a cross-sectional view showing the process of growing an n-GaN layer in a groove of a functional part in the manufacturing method of the electronic device according to the seventh embodiment. Figure 47 (B) is a cross-sectional view showing the process of forming an opening in the insulating film in the manufacturing method of the electronic device in the seventh embodiment.

[0061] Figure 48 (A) is a cross-sectional view showing the process of implanting ions into the n-GaN layer of the functional part in the manufacturing method of the electronic device in the seventh embodiment. Figure 48 (B) is a cross-sectional view showing the process of forming an oxide film on a functional part in the manufacturing method of the electronic device in the seventh embodiment.

[0062] Figure 49 (A) is a cross-sectional view showing the process of etching the growth substrate in the manufacturing method of the electronic device in the seventh embodiment. Figure 49 (B) is a cross-sectional view showing the process of separating the functional part from the growth substrate in the manufacturing method of the electronic device in the seventh embodiment.

[0063] Figure 50 (A) is a cross-sectional view showing the process of removing the buffer layer in the manufacturing method of the electronic device in the seventh embodiment. Figure 50 (B) is a cross-sectional view showing the process of forming a first metal film on a functional part in the manufacturing method of the electronic device in the seventh embodiment. Figure 50 (C) is an enlarged cross-sectional view showing the first metal film in the manufacturing method of the electronic device in the seventh embodiment.

[0064] Figure 51 (A) is a cross-sectional view showing the process of transferring functional parts onto a device substrate in the manufacturing method of the electronic device according to the seventh embodiment. Figure 51 (B) is an enlarged cross-sectional view showing the second metal film on the device substrate in the manufacturing method of the electronic device in the seventh embodiment.

[0065] Figure 52 (A) is a cross-sectional view showing the process of forming an insulating film on a functional part in the manufacturing method of the electronic device in the seventh embodiment. Figure 52 (B) is a cross-sectional view showing the process of patterning the insulating film in the manufacturing method of the electronic device in the seventh embodiment.

[0066] Figure 53 This is a cross-sectional view showing the process of forming the source electrode and the gate electrode in the manufacturing method of the electronic device in the seventh embodiment. Detailed Implementation

[0067] The electronic devices and their manufacturing methods in various embodiments will now be described with reference to the accompanying drawings. Examples of electronic devices include piezoelectric devices, photoelectric conversion devices, and semiconductor devices. Examples of photoelectric conversion devices include LED (light-emitting diode) devices. Examples of semiconductor devices include Schottky barrier diodes and field-effect transistors.

[0068] (First Implementation)

[0069] The first embodiment relates to an electronic device 10 as an AlN piezoelectric device and a method for manufacturing the same.

[0070] Figure 1 (A) is a cross-sectional view showing the growth substrate 101 used as the first substrate in the manufacturing method of the electronic device in the first embodiment. Figure 1 The growth substrate 101 shown in (A) is, for example, a Si (111) substrate. Incidentally, the growth substrate 101 is not limited to Si (111), and the growth substrate 101 only needs to be a substrate on which the functional layer 102 described below can be grown.

[0071] The following description will focus on the main surface of the growth substrate 101 ( Figure 1 The upper surface of (A) is used as a reference, and the stacking direction of multiple layers stacked on the main surface is defined as the upward direction.

[0072] Figure 1 (B) is a cross-sectional view showing the process of forming functional layer 102. (See diagram below.) Figure 1 As shown in (B), a functional layer 102, serving as an AlN (aluminum nitride) layer, is epitaxially grown on the main surface of the growth substrate 101. The thickness of the functional layer 102 is from 2 μm to 50 μm.

[0073] Figure 1 (C) is a cross-sectional view showing the process of patterning the growth substrate 101 and the functional layer 102. Figure 1 As shown in (C), the growth substrate 101 and the functional layer 102 are patterned into a device shape. The patterning is performed by forming a photoresist (mask) (not shown) on the functional layer 102 and then performing dry etching.

[0074] Dry etching is performed until the depth t of the growth substrate 101 from its main surface reaches 50 nm to 10000 nm. This depth t is also referred to as the over-etching amount. Through this process, a sacrificial layer 101a with an area approximately the same as the lower surface of the functional layer 102 is formed on the main surface of the growth substrate 101. The dry etching conditions are set such that the side surfaces of the functional layer 102 are formed as inclined surfaces.

[0075] Figure 2 (A) and Figure 2(B) is a cross-sectional view showing the process of etching the growth substrate 101. Figure 2 As shown in (A), the growth substrate 101 is etched in the surface direction (i.e. (100) direction) of the growth substrate 101 by means of wet etching using KOH (potassium hydroxide).

[0076] As etching proceeds, the area of ​​the sacrificial layer 101a on the growth substrate 101 decreases. For example... Figure 2 As shown in (B), etching ends with the sacrificial layer 101a of the growth substrate 101 remaining only at the center of the lower surface of the functional layer 102. Therefore, the functional layer 102 is supported in its central portion by a portion of the sacrificial layer 101a of the growth substrate 101 (referred to as the connecting member 101b).

[0077] Since the connecting component 101b is in the separation process described later ( Figure 3 The part to be broken in (A) is such that the area W1 of the connecting part 101b is expected to be less than or equal to 10% of the area of ​​the lower surface of the functional layer 102.

[0078] Incidentally, although in Figure 2 In (B), a portion of the sacrificial layer 101a of the growth substrate 101 is retained as a connecting member 101b, but it can also be as follows: Figure 2 As shown in (C), the sacrificial layer 101a is completely removed. In this case, by removing the sacrificial layer 101a, the functional layer 102 falls onto the main surface of the growth substrate 101 and is supported in the state where the functional layer 102 is placed on the main surface of the growth substrate 101.

[0079] Figure 3 (A) is a cross-sectional view illustrating the process of separating the functional layer 102 from the growth substrate 101. Figure 3 As shown in (A), a mold 120, serving as a retaining member, is attached to the upper surface of the functional layer 102 (the surface opposite to the growth substrate 101). The mold 120 is formed, for example, from an organic material such as an organic resist. It is desirable that the mold 120 is a member with adhesiveness or tackiness on its surface.

[0080] By moving the mold 120 in a direction away from the growth substrate 101, the connecting component 101b ( Figure 2 (B) breaks, and the lower surface 102a of the functional layer 102 separates from the main surface of the growth substrate 101. That is, the functional layer 102 separates from the growth substrate 101.

[0081] Here, the a-axis lattice constant L of the Si(111) substrate forming the growth substrate 101 is... 101 The a-axis lattice constant L of AlN forming functional layer 102 is 3.89 Å.102 It is 3.11 Å. The relationship between these lattice constants is L 101 >L 102 .

[0082] Furthermore, the coefficient of thermal expansion T of the Si(111) substrate forming the growth substrate 101 at room temperature is... 101 2.4 × 10 -6 / K to 4.4×10 -6 / K. The coefficient of thermal expansion T of AlN forming functional layer 102 at room temperature. 102 4.3×10 -6 / K to 4.8×10 -6 / K. The relationship between these coefficients of thermal expansion is T. 102 >T 101 .

[0083] In the epitaxial growth process described above ( Figure 1 In (B), the functional layer 102 is epitaxially grown under tensile stress to make its lattice constant match that of the growth substrate 101. Subsequently, when the functional layer 102 cools to room temperature, due to the difference in thermal expansion, the functional layer 102 shrinks more than the growth substrate 101, resulting in warping of the functional layer 102. Figure 3 As shown in (A), the warping of the functional layer 102 becomes obvious when the functional layer 102 has been separated from the growth substrate 101.

[0084] Figure 3 (B) is a cross-sectional view showing the process of forming the first metal film 110. Figure 3 As shown in (B), a first metal film 110 is deposited on the lower surface 102a of the functional layer 102 (i.e. the surface separated from the growth substrate 101).

[0085] The first metal film 110 is an electrode of the functional layer 102, such as a monolayer of Mo (molybdenum), and is deposited by sputtering or vapor deposition. For example, in... Figure 3 With the functional layer 102 shown in (A) separated from the growth substrate 101, metal atoms for forming the first metal film 110 are continuously applied to the lower surface 102a, thereby forming the first metal film 110 from the lower surface 102a of the functional layer 102 to the side surface 102b of the functional layer 102. Therefore, the first metal film 110 can be deposited without heating the functional layer 102 to a high temperature, and the stress acting on the functional layer 102 can be reduced.

[0086] Incidentally, the first metal film 110 is not limited to a single layer of Mo, but can also be formed by two layers of Mo and Ti (titanium) or two layers of Ti and Au (gold). The thickness of the first metal film 110 is, for example, 100 nm to 10 μm.

[0087] Figure 4 (A) is shown in Figure 3 (B) is an enlarged view of the portion enclosed by the circle indicated by reference numeral A. The lower surface 102a of the functional layer 102 is a surface separated from the growth substrate 101. Each side surface 102b of the functional layer 102 extends from the lower surface 102a in a direction different from the extending direction of the lower surface 102a. In this example, each side surface 102b of the functional layer is an inclined surface inclined relative to the lower surface 102a.

[0088] The tilt direction of functional layer 102 is as follows: as the distance from the lower surface 102a increases (i.e., at... Figure 4 (A) and Figure 4 (B) decreases in the upward direction), the direction in which the size of the functional layer 102 decreases in the plane parallel to the lower surface 102a.

[0089] A first metal film 110 is deposited on the lower surface 102a and extends to the side surface 102b of the functional layer 102. The first metal film 110 serves to hold the lower surface 102a and the side surface 102b of the functional layer 102. Therefore, the integration of the first metal film 110 with the functional layer 102 is improved, and peeling of the functional layer 102 is prevented (see below). Figure 7 (A) to Figure 7 (D)).

[0090] Although the first metal film 110 covers the entire lower surface 102a, it is sufficient for the first metal film 110 to cover at least a portion of each side 102b that is closer to the lower surface 102a.

[0091] Figure 4 (B) is a schematic diagram showing the angle formed by the lower surface 102a and the side surface 102b of the functional layer 102. It is desired that the angle R formed by the lower surface 102a and the side surface 102b of the functional layer 102 is in the range of 45 degrees to 90 degrees, and particularly desired to be greater than or equal to 60 degrees and less than 90 degrees.

[0092] When the angle R is greater than 90 degrees, it is unlikely to achieve the effect of the first metal film 110 clamping the lower surface 102a and the side surface 102b of the functional layer 102. When the angle R is less than 45 degrees, the area of ​​the upper surface of the functional layer 102 becomes smaller relative to the lower surface 102a, thereby reducing the device area. Therefore, as described above, an angle R of 45 to 90 degrees is desirable.

[0093] Incidentally, this angle R can be obtained by... Figure 1The dry etching conditions are set during the patterning process of (C) to adjust the process. Dry etching conditions include, for example, the type and flow rate of the etching gas, plasma density, bias voltage, mask material and thickness, etc.

[0094] Figure 5 (A) is a cross-sectional view illustrating the process of transferring the functional layer 102 to the device substrate 130. Figure 5 As shown in (A), the functional layer 102 held by the mold 120 is transferred onto the device substrate 130, which serves as a second substrate. The device substrate 130 is a substrate different from the growth substrate 101, and is, for example, a Si substrate. However, the device substrate 130 is not limited to Si, and may also be made of, for example, SiC (silicon carbide), glass, etc.

[0095] A second metal film 140 is formed on the main surface of the device substrate 130. The second metal film 140 is a multilayer film comprising multiple metal layers. Figure 5 (B) is an enlarged cross-sectional view showing the second metal film 140. (See diagram below.) Figure 5 As shown in (B), the second metal film 140 includes a first layer 141 made of Ti, a second layer 142 made of Pt (platinum) and a third layer 143 made of Au, which are stacked sequentially from the device substrate 130 side (bottom side).

[0096] The third layer 143 (Au) is a layer with excellent adhesion to the first metal film 110. The first layer 141 (Ti) is a layer with excellent adhesion to the device substrate 130. Furthermore, a second layer 142 (Pt) is disposed between the third layer 143 and the first layer 141 to prevent the Au in the third layer 143 from reacting with the Ti in the first layer.

[0097] The thickness of the first layer 141 and the second layer 142 is, for example, 100 nm. The thickness of the third layer 143 is, for example, 100 nm to 10 μm. The first layer 141, the second layer 142, and the third layer 143 are formed by sputtering or vapor deposition. These layers are almost warp-free because they are not formed at high temperatures as in epitaxial growth. The second metal film 140 is not limited to a combination of Ti, Pt, and Au layers, but can also use other different combinations.

[0098] When the functional layer 102 is transferred onto the device substrate 130, the first metal film 110 and the second metal film 140 are bonded together by applying a specified pressure. Afterward, the mold 120 is peeled off and removed from the upper surface of the functional layer 102.

[0099] Figure 6 (A) is a cross-sectional view showing the process of bonding the metal film 110 of the functional layer 102 and the metal film 140 of the device substrate 130 together. Figure 6 As shown in (A), with the first metal film 110 and the second metal film 140 bonded together, an annealing process is performed at 500°C to 800°C.

[0100] This process bonds the first metal film 110 and the second metal film 140 together. Through the pressing during bonding and the subsequent annealing process, even if the functional layer 102 is warped, the first metal film 110 and the second metal film 140 can be bonded together well without gaps.

[0101] Figure 6 (B) is a cross-sectional view showing the process of forming an electrode layer 151 on the functional layer 102. The electrode layer 151 is made of Pt, for example, and is formed by sputtering or vapor deposition. The electronic device 10, which is a piezoelectric device (more specifically, a vertical AlN piezoelectric device), is completed by connecting wiring to the electrode layer 151 and the second metal film 140 (third layer 143), and connecting the wiring to the drive circuit, etc.

[0102] <Function>

[0103] The function of the first embodiment will now be described. Typically, when the functional layer 102 is peeled (separated) from the growth substrate 101 and transferred to the device substrate 130, warping of the functional layer 102 may occur during peeling. This warping occurs not only when the functional layer 102 is AlN, but also when the functional layer 102 is PZT (lead zirconate titanate), LN (lithium niobate), or LT (lithium tantalate). For electronic devices other than piezoelectric elements, this warping may also occur when the functional layer 102 is a GaN (gallium nitride)-based or GaAs (gallium arsenide)-based semiconductor layer.

[0104] If the warped functional layer 102 is bonded to the device substrate 130, a gap will be generated between the functional layer 102 and the device substrate 130, and a good bonding state cannot be obtained. This will lead to deterioration of electrical performance.

[0105] In contrast, in the first embodiment, such as Figure 6 As shown in (A), the first metal film 110 deposited on the functional layer 102 is bonded to the second metal film 140 formed on the device substrate 130 through a pressurization and annealing process. Therefore, even if the functional layer 102 has warpage, the first metal film 110 and the second metal film 140 can be well bonded.

[0106] Furthermore, in the first embodiment, a first metal film 110 is deposited on the lower surface 102a, thereby extending to the side surface 102b of the functional layer 102. Referring below... Figure 7 (A) to Figure 7(D) describes the effect obtained through this deposition method.

[0107] Figure 7 (A) and Figure 7 (B) is a schematic diagram showing the device substrate 130, the first metal film 110, and the functional layer 102 in a comparative example. In this comparative example, the first metal film 110 only covers the lower surface 102a of the functional layer 102. Residual stress generated during epitaxial growth remains in the functional layer 102 and acts in the direction that causes the functional layer 102 to warp. In this comparative example, warping of the functional layer 102 cannot be suppressed, and the functional layer 102 may... Figure 7 As shown by reference numeral E in (B), it is peeled off from the first metal film 110.

[0108] Figure 7 (C) and Figure 7 (D) is a schematic diagram showing the device substrate 130, the first metal film 110, and the functional layer 102 in the first embodiment. In the first embodiment, the first metal film 110 is deposited on the lower surface 102a, thereby extending to the side surface 102b of the functional layer 102, and serves to hold the lower surface 102a and the side surface 102b. Therefore, warping of the functional layer 102 caused by residual stress can be suppressed, and peeling of the functional layer 102 can be prevented.

[0109] Furthermore, since the first metal film 110 (Mo) is located between the third layer 143 (Au) of the second metal film 140 and the functional layer 102 (AlN), Au can be prevented from diffusing into AlN, and a functional layer 102 with stable performance can be obtained.

[0110] In particular, since the first metal film 110 extends to the side 102b of the functional layer 102, even if the second metal film 140 deforms during the annealing process, it can prevent the third layer 143 (Au) from contacting the functional layer 102 (AlN) and more reliably prevent Au from diffusing into AlN.

[0111] <Effects of the First Implementation>

[0112] As described above, the electronic device 10 in the first embodiment includes a functional layer 102 (functional portion), a device substrate 130 serving as a substrate supporting the functional layer 102, a first metal film 110 deposited as an electrode on the side of the functional layer 102 facing the device substrate 130, and a second metal film 140 formed on the device substrate 130 and bonded to the first metal film 110. The first metal film 110 is deposited from the lower surface (first surface) 102a of the functional layer 102 onto a portion of the side surface (second surface) 102b.

[0113] Because the first metal film 110 deposited on the functional layer 102 is bonded together with the second metal film 140 formed on the device substrate 130 as described above, the functional layer 102 can be well bonded to the device substrate 130 even when the functional layer 102 warps. In particular, since the first metal film 110 is deposited from the lower surface 102a of the functional layer 102 to a portion of the side surface 102b, the integration of the first metal film 110 with the functional layer 102 can be improved, and peeling of the functional layer 102 can be prevented.

[0114] Furthermore, since the side surface 102b of the functional layer 102 has such an inclination that the size of the functional layer 102 in the plane parallel to the lower surface 102a decreases in the upward direction (i.e., as the distance from the lower surface 102a increases), the first metal film 110 can perform the function of clamping the lower surface 102a and the side surface 102b of the functional layer 102, thereby enhancing the effect of preventing the functional layer 102 from peeling off.

[0115] Furthermore, since the functional layer 102 is a piezoelectric element layer including AlN, the electronic device 10 can be formed as a piezoelectric device. Moreover, since the first metal film 110 is deposited on the functional layer 102 (piezoelectric element layer), the functional layer 102 and the second metal film 140 on the device substrate 130 can be electrically connected together via the first metal film 110.

[0116] Furthermore, in the manufacturing method of the electronic device 10 according to the first embodiment, a first metal film 110 is deposited from the lower surface (first surface) 102a of the functional layer (functional portion) 102, which is separated from the growth substrate 101, which is the first substrate, to a portion of the side surface (second surface) 102b. The first metal film 110 deposited on the functional layer 102 is then bonded to a second metal film 140 formed on a device substrate 130, which is a second substrate different from the growth substrate 101. Therefore, even if the functional layer 102 warps, an electronic device 10 with good bonding between the functional layer 102 and the device substrate 130 can be manufactured.

[0117] (Second Implementation)

[0118] The second embodiment relates to an electronic device 20, which is a vertical GaN semiconductor (more specifically, a Schottky barrier diode), and a method for manufacturing the same.

[0119] Figure 8 (A) is a cross-sectional view showing the growth substrate 201 used in the manufacturing method of the electronic device 20 in the second embodiment. Figure 8The growth substrate 201 shown as the first substrate in (A) is, for example, a Si (111) substrate. Incidentally, the growth substrate 201 is not limited to Si (111), and the growth substrate 201 only needs to be a substrate on which the functional part 200 described below can be grown.

[0120] Figure 8 (B) is a cross-sectional view showing the process of forming the buffer layer 202 and the functional part 200. Figure 8 As shown in (B), a buffer layer 202, serving as an AlN layer, is epitaxially grown on the main surface of the growth substrate 201. In this example, the buffer layer 202 is a monolayer AlN, but the buffer layer 202 is not limited to this example. For example, the buffer layer 202 could also be a stack of AlN and AlGaN layers. The thickness of the buffer layer 202 is, for example, from 200 nm to 1 μm.

[0121] An n+GaN layer 203, serving as a contact layer, is epitaxially grown on the buffer layer 202. The thickness of the n+GaN layer 203 is, for example, 500 nm to 3 μm.

[0122] Furthermore, an n-GaN layer 204, serving as a drift layer, is epitaxially grown on the n+GaN layer 203. The thickness of the n-GaN layer 204 is, for example, 500 nm to 20 μm.

[0123] The n+GaN layer 203 and the n-GaN layer 204 constitute the functional part (semiconductor thin film) 200.

[0124] Figure 8 (C) is a cross-sectional view showing the process of patterning the growth substrate 201, buffer layer 202, and functional part 200. Figure 8 As shown in (C), the growth substrate 201, buffer layer 202, and functional part 200 are patterned into a device shape. The patterning is performed by forming a photoresist (not shown) on the n-GaN layer 204 and performing dry etching.

[0125] Dry etching is performed until the depth (over-etching amount) t of the growth substrate 201 from its main surface reaches 50 nm to 10000 nm. Through this process, a sacrificial layer 201a with an area approximately the same as the lower surface of the buffer layer 202 is formed on the main surface of the growth substrate 201.

[0126] As described in the first embodiment, dry etching conditions are set such that the side surface of the functional portion 200 is formed as an inclined surface. Incidentally, the inclined direction of the functional portion 200 is: the dimension of the functional portion 200 in a plane parallel to the lower surface of the functional portion 200 (the lower surface 203a, which will be described later) decreases in the upward direction (i.e., as the distance from the lower surface increases). Although the case where the side surface of the functional portion 200 is an inclined surface is given here, it is sufficient that at least the side surface 203b (described later) of the n+GaN layer 203 (contact layer) is an inclined surface.

[0127] Figure 9 (A) is a cross-sectional view showing the process of forming a Schottky electrode 205 and photoresist 206 on the functional part 200. Figure 9 As shown in (A), a Schottky electrode 205 is formed on the upper surface of the n-GaN layer 204. The Schottky electrode 205 is made of, for example, Ni (nickel), Pd (palladium), Mo, etc., and is formed by sputtering or vapor deposition.

[0128] Furthermore, a photoresist 206 for patterning is formed on the Schottky electrode 205. The photoresist 206 is formed, for example, by spin coating.

[0129] Figure 9 (B) is a cross-sectional view showing the process of patterning the Schottky electrode 205. (See diagram below.) Figure 9 As shown in (B), the Schottky electrode 205 is patterned via photoresist 206 by dry etching or wet etching.

[0130] Figure 10 (A) is a cross-sectional view showing the process of etching the growth substrate 201. Figure 10 As shown in (A), the growth substrate 201 is etched in the surface direction (i.e. (100) direction) of the growth substrate 201 by means of wet etching using KOH.

[0131] The sacrificial layer 201a of the growth substrate 201 can be referred to as in the first embodiment. Figure 2 Partial etching can be performed as described in (B), or as referred to Figure 2 Completely remove as described in (C). Through this process, the functional part 200 becomes easy to separate from the growth substrate 201.

[0132] Figure 10 (B) is a cross-sectional view showing the process of separating the buffer layer 202, the functional part 200, and the Schottky electrode 205 from the growth substrate 201. Figure 10As shown in (B), the mold 220, which serves as a holding member, is attached to the upper surface of the Schottky electrode 205, and then the buffer layer 202, the functional part 200, and the Schottky electrode 205 are separated from the growth substrate 201. The structure of the mold 220 is the same as that of the mold 120 in the first embodiment.

[0133] Here, the a-axis lattice constant L of the Si(111) substrate forming the growth substrate 201 is... 201 The a-axis lattice constant L of AlN forming the buffer layer 202 is 3.89 Å. 202 The a-axis lattice constant L of GaN forming functional units 200 (i.e., n+GaN layer 203 and n-GaN layer 204) is 3.11 Å. 200 It is 3.19 Å. The relationship between these lattice constants is L 201 >L 200 >L 202 .

[0134] Furthermore, the coefficient of thermal expansion T of the Si(111) substrate forming the growth substrate 201 at room temperature is... 201 2.4 × 10 -6 / K to 4.4×10 -6 / K. The coefficient of thermal expansion T of AlN forming the buffer layer 202 at room temperature. 202 4.3×10 -6 / K to 4.8×10 -6 / K. The coefficient of thermal expansion T of GaN forming functional part 200 at room temperature. 200 3.72×10 -6 / K to 5.45×10 -6 / K. The relationship between these coefficients of thermal expansion is T. 200 >T 202 >T 201 .

[0135] During the epitaxial growth process ( Figure 8 In (B), the buffer layer 202 and the functional portion 200 are epitaxially grown under tensile stress, such that their lattice constants are consistent with those of the growth substrate 201. Subsequently, when the buffer layer 202 and the functional portion 200 cool to room temperature, due to differences in thermal expansion, the buffer layer 202 and the functional portion 200 shrink more than the growth substrate 201, and warping occurs in the buffer layer 202 and the functional portion 200. Figure 10 As shown in (B), their warping becomes obvious when the buffer layer 202 and the functional part 200 have been separated from the growth substrate 201.

[0136] Figure 11 (A) is a cross-sectional view showing the process of removing the buffer layer 202. Figure 11As shown in (A), the buffer layer 202 is removed from the functional part 200 by means of etching or polishing such as CMP (chemical mechanical polishing). Through this process, the lower surface 203a of the n+GaN layer 203 of the functional part 200 is exposed. By removing the buffer layer 202, the warpage of the functional part 200 is reduced, but not completely eliminated.

[0137] Figure 11 (B) is a cross-sectional view showing the process of forming the first metal film 210. Figure 11 As shown in (B), a first metal film 210 is formed on the lower surface 203a of the n+GaN layer 203 of the functional part 200. The first metal film 210 is an electrode of the n+GaN layer 203 and is formed of a multilayer film including multiple metal layers.

[0138] A first metal film 210 is deposited on the lower surface 203a to extend to the side surface 203b of the n+GaN layer 203. The angle R (as described in the first embodiment) Figure 4 Similar to (B), the angle formed between the lower surface 203a and the side surface 203b of the n+GaN layer 203 is 45 degrees to 90 degrees, and preferably greater than or equal to 60 degrees and less than 90 degrees.

[0139] Figure 12 (A) to Figure 12 (E) is a cross-sectional view showing step-by-step the method of forming the first metal film 210. As shown... Figure 12 As shown in (A), a first layer 211 made of Ti is deposited on the lower surface 203a of the n+GaN layer 203 by sputtering or vapor deposition. The first layer 211 is deposited on the lower surface 203a to extend to the side surface 203b of the n+GaN layer 203.

[0140] Subsequently, as Figure 12 As shown in (B), a second layer 212 made of Al is deposited on the first layer 211 by sputtering or vapor deposition. The second layer 212 is deposited to completely cover the first layer 211 and reach the side 203b of the n+GaN layer 203.

[0141] Subsequently, as Figure 12 As shown in (C), a third layer 213 made of Ti is deposited on the second layer 212 by sputtering or vapor deposition. The third layer 213 is deposited to completely cover the second layer 212 and reach the side 203b of the n+GaN layer 203.

[0142] Subsequently, as Figure 12As shown in (D), a fourth layer 214 made of Pt is deposited on the third layer 213 by sputtering or vapor deposition. The fourth layer 214 is deposited to completely cover the third layer 213 and extend to the side 203b of the n+GaN layer 203. The fourth layer 214 is also referred to as the barrier metal layer.

[0143] Subsequently, as Figure 12 As shown in (E), a fifth layer 215 made of Au is deposited on the fourth layer 214 by sputtering or vapor deposition. The fifth layer 215 is deposited to completely cover the fourth layer 214 and reach the side 203b of the n+GaN layer 203.

[0144] As described above, the first layer 211 to the fifth layer 215 of the first metal film 210 are deposited such that each layer completely covers the layer below it and reaches the side 203b of the n+GaN layer 203.

[0145] Incidentally, if the third layer 243 (Au) of the second metal film 240 on the device substrate 230, which will be described later, is thicker, the fifth layer 215 (Au) of the first metal film 210 may not be included, and the first metal film 210 may be formed as a four-layer structure including the first layer 211 (Ti) to the fourth layer 214 (Pt).

[0146] The first metal film 210 is deposited by sputtering, vapor deposition, or other methods. For example, in... Figure 11 With the functional part 200 shown in (A) separated from the growth substrate 201, metal atoms for forming the first metal film 210 are applied to the lower surface 203a, thereby forming the first metal film 210 from the lower surface 203a to the side surface 203b.

[0147] In this configuration, since the side surface 203b of the n+GaN layer 203 is an inclined surface at an angle of 45 to 90 degrees (preferably greater than or equal to 60 degrees and less than 90 degrees) relative to the lower surface 203a, the first metal film 210 can be deposited such that it does not contact the side surface of the n-GaN layer 204. By preventing the first metal film 210 from contacting the n-GaN layer 204, the voltage withstand performance of the n-GaN layer 204 (drift layer) can be prevented from deteriorating.

[0148] In addition, such as Figure 12 (D) and Figure 12 As shown in (E), since the fourth layer 214 (Pt) is formed between the second layer 212 (Al) and the fifth layer 215 (Au) of the first metal film 210, and thus extends to the side 203b of the n+GaN layer, the increase in resistance caused by the formation of a eutectic between Al and Au during the annealing process described later can be prevented.

[0149] Mo can also be used instead of Pt as the fourth layer 214, which serves as a barrier metal layer. In this case, the third layer 213 (Ti) can be omitted.

[0150] Figure 13 (A) is a cross-sectional view showing the process of transferring the functional part 200 onto the device substrate 230. Figure 13 As shown in (A), the functional portion 200 held by the mold 220 is transferred onto the device substrate 230, which serves as a second substrate. The device substrate 230 is a substrate different from the growth substrate 201, and is, for example, a SiC substrate. However, the device substrate 230 is not limited to SiC, and may also be made of, for example, Si, glass, etc.

[0151] A second metal film 240 is formed on the main surface of the device substrate 230. Figure 13 (B) is an enlarged cross-sectional view showing the second metal film 240 on the main surface of the device substrate 230. Figure 13 As shown in (B), the second metal film 240 includes a first layer 241 made of Ti, a second layer 242 made of Pt, and a third layer 243 made of Au, which are stacked sequentially from the device substrate 230 side (bottom side).

[0152] The thickness of each of the first layer 241 and the second layer 242 is, for example, 100 nm. The thickness of the third layer 243 is, for example, 100 nm to 10 μm. The first layer 241, the second layer 242, and the third layer 243 are formed by sputtering or vapor deposition, thus causing almost no warping. Incidentally, the second metal film 240 is not limited to three layers of Ti, Pt, and Au, but can also be a combination of different layers.

[0153] When the functional part 200 is transferred onto the device substrate 230, the first metal film 210 and the second metal film 240 are bonded together by applying a predetermined pressure to them. Afterwards, the molding die 220 is peeled off and removed from the upper surface of the Schottky electrode 205.

[0154] Figure 14 (A) is a cross-sectional view showing the process of bonding the metal film 210 of the functional part 200 and the metal film 240 of the device substrate 230 together. Figure 14 As shown in (A), the annealing process is performed at a temperature of 500°C to 800°C with the first metal film 210 and the second metal film 240 bonded together.

[0155] Through this process, the first metal film 210 and the second metal film 240 are bonded together. Through the pressure applied during bonding and the subsequent annealing process, even if the functional part 200 is warped, the first metal film 210 and the second metal film 240 can be bonded together well without gaps.

[0156] Furthermore, through the annealing process, ohmic contact is achieved between the n+GaN layer 203 of the functional part 200 and the first layer 211 (Ti) and the second layer 212 (Al) of the first metal film 210. Moreover, the fifth layer 215 (Au), which is the outermost layer of the first metal film 210, is integrated with the third layer 243 (Au), which is the uppermost layer of the second metal film 240.

[0157] Figure 14 (B) is a cross-sectional view showing the process of forming an insulating film 207 and a wiring layer 208 on the functional part 200. Figure 14 As shown in (B), the insulating film 207 is formed to cover the portion of the functional portion 200 except for the Schottky electrode 205. The insulating film 207 is, for example, a... Oxide films such as silicon dioxide are formed by sputtering or vapor deposition.

[0158] Subsequently, a wiring layer 208 is formed to cover the upper surface of the Schottky electrode 205. The wiring layer 208 is made of, for example, Au or Al. The wiring layer 208 may also be a stack of Ti and Al layers.

[0159] Wiring (not shown) is connected to a second metal film 240 (third layer 243) on the device substrate 230. Through this process, an electronic device 20 is completed as a vertical GaN semiconductor device (more specifically, a Schottky barrier diode).

[0160] In this example, the Schottky electrode 205 is formed before the functional portion 200 is separated from the growth substrate 201 (see [reference]). Figure 9 (A) and Figure 9 (B)), but the Schottky electrode 205 can also be formed after the functional part 200 is transferred onto the device substrate 230. In this case, the Schottky electrode 205 and the wiring layer 208 can be formed integrally.

[0161] In the example described here, the first metal film 210 deposited on the functional part 200 is formed of a Ti layer, an Al layer, a Ti layer, a Pt layer and an Au layer (first layer 211 to fifth layer 215), and the second metal film 240 formed on the device substrate 230 is formed of an Au layer, a Pt layer and a Ti layer (first layer 241 to third layer 243).

[0162] However, the structures of metal films 210 and 240 are not limited to the examples described above. The structures of the layers of metal films 210 and 240 can, for example, be one of the 26 combinations shown in Table 1 below:

[0163] In Table 1, for each layer of the first metal film 210 on the functional unit 200, it is described that the layer further to the right is closer to the bonding interface of the metal films 210 and 240. For each layer of the second metal film 240 on the device substrate 230, it is described that the layer further to the left is closer to the bonding interface of the metal films 210 and 240. For example, in the first combination shown below, the Au layer in the first metal film 210 is closest to the bonding interface, and the Au layer in the second metal film 240 is also closest to the bonding interface.

[0164] Table 1

[0165] Serial Number First metal film 210 Second metal film 240 1 Ti / Al / Ti / Pt / Au Au / Pt / Ti 2 Ti / Al / Ti / Pt / Au Pt / Ti 3 Ti / Al / Ti / Pt / Au Au / Mo / Ti 4 Ti / Al / Ti / Pt / Au Mo / Ti 5 Ti / Al / Ti / Pt / Au Au / Mo 6 Ti / Al / Ti / Mo / Au Au / Pt / Ti 7 Ti / Al / Ti / Mo / Au Au / Mo / Ti 8 Ti / Al / Ti / Mo / Au Pt / Ti 9 Ti / Al / Ti / Mo / Au Mo / Ti 10 Ti / Al / Mo / Au Au / Mo / Ti 11 Ti / Al / Mo / Au Pt / Ti 12 Ti / Al / Mo / Au Mo / Ti 13 Ti / Al / Mo / Au Au / Pt / Ti 14 Ti / Al / Mo / Au Au / Mo 15 Ti / Al / Mo / Au Pt / Ti 16 Ti / Al / Mo / Au Mo 17 Ti / Al / Mo / Au Au / Mo 18 Ti / Al / Ti / Pt Au / Pt / Ti 19 Ti / Al / Ti / Pt Au / Mo / Ti 20 Ti / Al / Ti / Pt Au / Mo 21 Ti / Al / Ti / Mo Au / Pt / Ti 22 Ti / Al / Ti / Mo Au / Mo / Ti 23 Ti / Al / Pt / Au Mo 24 Ti / Al / Mo Au / Pt / Ti 25 Ti / Al / Mo Au / Mo / Ti 26 Ti / Al / Mo Au / Mo

[0166] The combinations shown in Table 1 are applicable not only to the metal films 210 and 240 in the second embodiment, but also to the first and second metal films in the third to seventh embodiments, which will be described later.

[0167] As described above, the electronic device 20 in the second embodiment includes a functional portion 200, a device substrate 230 serving as a substrate supporting the functional portion 200, a first metal film 210 deposited as an electrode on the side of the functional portion 200 facing the device substrate 230, and a second metal film 240 formed on the device substrate 230 and bonded to the first metal film 210. The first metal film 210 is deposited from the lower surface (first surface) 202a of the functional portion 200 onto a portion of the side surface (second surface) 203b. Therefore, similar to the first embodiment, even when the functional portion 200 warps, the functional portion 200 can be well bonded to the device substrate 230, and peeling of the functional portion 200 can be prevented.

[0168] Furthermore, the functional unit 200 includes an n+GaN layer 203 as a contact layer and an n-GaN layer 204 as a drift layer, and a first metal film 210 is formed on the n+GaN layer 203. Therefore, the functional unit 200 and the second metal film 240 on the device substrate 230 can be electrically connected together via the first metal film 210.

[0169] Furthermore, the fourth layer 214 (Pt), which serves as a barrier metal layer, is located between the second layer 212 (Al) and the fifth layer 215 (Au) of the first metal film 210, and also between the second layer 212 (Al) of the first metal film 210 and the third layer 243 (Au) of the second metal film 240. Therefore, a eutectic reaction between Al and Au can be prevented, and poor bonding can be prevented.

[0170] (Third Implementation)

[0171] The third embodiment relates to an electronic device 30 as a vertical GaN light-emitting diode (LED) and a method for manufacturing the same.

[0172] Figure 15 (A) is a cross-sectional view showing the process of forming a buffer layer 302 and a functional part 300 on a growth substrate 301 in the manufacturing method of the electronic device 30 in the third embodiment. Figure 15 The growth substrate 301 shown as the first substrate in (A) is, for example, a Si (111) substrate. Incidentally, the growth substrate 301 is not limited to Si (111), and the growth substrate 301 only needs to be a substrate on which the functional part 300 described below can be grown.

[0173] A buffer layer 302, serving as an AlN layer, is epitaxially grown on the main surface of the growth substrate 301. In this example, the buffer layer 302 is a monolayer AlN, but the buffer layer 302 is not limited to this example; for example, it could also be a stack of AlN and AlGaN layers. The thickness of the buffer layer 302 is, for example, from 200 nm to 1 μm.

[0174] An nGaN layer 303, serving as a contact layer, is epitaxially grown on the buffer layer 302. The thickness of the nGaN layer 303 is, for example, 2 μm.

[0175] Subsequently, an nAlGaN layer 304 as a cladding layer is epitaxially grown on the nGaN layer 303. The thickness of the nAlGaN layer 304 is, for example, 100 nm to 300 nm.

[0176] Furthermore, an InGaN layer 305, serving as an active or emitting layer, is epitaxially grown on the nAlGaN layer 304. The InGaN layer 305 is an MQW (multiple quantum well) layer. The thickness of the InGaN layer 305 is, for example, 100 nm.

[0177] Subsequently, a pAlGaN layer 306 as a cladding layer is epitaxially grown on the InGaN layer 305. The thickness of the pAlGaN layer 306 is, for example, 50 nm.

[0178] Furthermore, a pGaN layer 307, serving as a contact layer, is epitaxially grown on the pAlGaN layer 306. The thickness of the pGaN layer 307 is, for example, 50 nm.

[0179] The nGaN layer 303, nAlGaN layer 304, InGaN layer 305, pAlGaN layer 306, and pGaN layer 307 constitute the functional part (semiconductor thin film) 300.

[0180] Figure 15 (B) is a cross-sectional view showing the process of patterning the growth substrate 301, the buffer layer 302, and the functional part 300. Figure 15As shown in (B), the growth substrate 301, buffer layer 302, and functional part 300 are patterned into a device shape. The patterning is performed by forming a photoresist (not shown) on the pGaN layer 307 and performing dry etching.

[0181] Dry etching is performed until the depth (over-etching amount) t of the growth substrate 301 from its main surface reaches 50 nm to 10000 nm. Through this process, a sacrificial layer 301a with an area approximately the same as the lower surface of the buffer layer 302 is formed on the main surface of the growth substrate 301.

[0182] As described in the first embodiment, dry etching conditions are set such that the side surface of the functional portion 300 is formed as an inclined surface. Incidentally, the inclined direction of the functional portion 300 is: the dimension of the functional portion 300 in a plane parallel to the lower surface of the functional portion 300 (the lower surface 303a, which will be described later) decreases in the upward direction (i.e., as the distance from the lower surface increases). Although the case where the side surface of the functional portion 300 is an inclined surface is given here, it is acceptable as long as at least the side surface 303b (described later) of the nGaN layer 303 (contact layer) is an inclined surface.

[0183] Figure 16 (A) is a cross-sectional view showing the process of etching the growth substrate 301. Figure 16 As shown in (A), the growth substrate 301 is etched in the surface direction (i.e. (100) direction) of the growth substrate 301 by means of wet etching using KOH.

[0184] The sacrificial layer 301a of the growth substrate 301 can be referred to as in the first embodiment. Figure 2 Partial etching can be performed as described in (B), or as referred to Figure 2 Completely remove as described in (C). Through this process, the functional part 300 becomes easy to separate from the growth substrate 301.

[0185] Figure 16 (B) is a cross-sectional view showing the process of separating the buffer layer 302 and the functional part 300 from the growth substrate 301. Figure 16 As shown in (B), the mold 320, which serves as a holding member, is attached to the upper surface of the functional part 300 (the surface opposite to the growth substrate 301), and then the buffer layer 302 and the functional part 300 are separated from the growth substrate 301. The structure of the mold 320 is the same as that of the mold 120 in the first embodiment.

[0186] Here, the a-axis lattice constant L of the Si(111) substrate forming the growth substrate 301 is... 301 The a-axis lattice constant L of AlN forming the buffer layer 302 is 3.89 Å.302 The a-axis lattice constant L is 3.11 Å. This is the value of GaN with multiple layers forming the functional part 300. 300 It is 3.19 Å. The relationship between these lattice constants is L 301 >L 300 >L 302 .

[0187] Furthermore, the coefficient of thermal expansion T of the Si(111) substrate forming the growth substrate 301 at room temperature is... 301 2.4 × 10 -6 / K to 4.4×10 -6 / K. The coefficient of thermal expansion T of AlN forming the buffer layer 302 at room temperature. 302 4.3×10 -6 / K to 4.8×10 -6 / K. The coefficient of thermal expansion T of GaN forming multiple layers of functional part 300 at room temperature. 300 3.72×10 -6 / K to 5.45×10 -6 / K. The relationship between these coefficients of thermal expansion is T. 300 >T 302 >T 301 .

[0188] During the epitaxial growth process ( Figure 15 In (A), the buffer layer 302 and the functional portion 300 are epitaxially grown under tensile stress, such that their lattice constants are consistent with those of the growth substrate 301. Subsequently, when the buffer layer 302 and the functional portion 300 cool to room temperature, due to differences in thermal expansion, the buffer layer 302 and the functional portion 300 shrink more than the growth substrate 301, and warping occurs in the buffer layer 302 and the functional portion 300. Figure 16 As shown in (B), their warping becomes obvious when the buffer layer 302 and the functional part 300 have been separated from the growth substrate 301.

[0189] Figure 17 (A) is a cross-sectional view showing the process of removing the buffer layer 302. Figure 17 As shown in (A), the buffer layer 302 is removed from the functional portion 300 by means of etching or polishing (such as CMP). Through this process, the lower surface 303a of the nGaN layer 303 of the functional portion 300 is exposed. By removing the buffer layer 302, the warpage of the functional portion 300 is reduced, but not completely eliminated.

[0190] Figure 17 (B) is a cross-sectional view showing the process of forming the first metal film 310. Figure 17As shown in (B), a first metal film 310 is deposited on the lower surface 303a of the nGaN layer 303 of the functional part 300. The first metal film 310 is an electrode of the nGaN layer 303 and is formed by multiple layers.

[0191] A first metal film 310 is deposited on the lower surface 303a to extend to the side surface 303b of the nGaN layer 303. The angle R (as described in the first embodiment) Figure 4 Similar to (B), the angle formed between the lower surface 303a and the side surface 303b of the nGaN layer 303 is 45 degrees to 90 degrees, preferably greater than or equal to 60 degrees and less than 90 degrees.

[0192] Figure 17 (C) is shown Figure 17 An enlarged view of the portion enclosed by the circle indicated by reference numeral A in (B). The first metal film 310 includes a first layer 311 made of Ti, a second layer 312 made of Al, a third layer 313 made of Ti, a fourth layer 314 made of Pt, and a fifth layer 315 made of Au, stacked sequentially from the nGaN layer 303 side. The fourth layer 314 is also referred to as the barrier metal layer. The deposition method of these layers is as described in the second embodiment. Figure 12 (A) to Figure 12 As explained in (E).

[0193] As described in the second embodiment, the first metal film 310 is deposited by sputtering, vapor deposition, or other methods. For example, in... Figure 17 With the functional part 300 shown in (A) separated from the growth substrate 301, metal atoms for forming the first metal film 310 are continuously applied to the lower surface 303a, thereby forming the first metal film 310 from the lower surface 303a to the side surface 303b.

[0194] In this case, since the side surface 303b of the nGaN layer 303 is an inclined surface with an angle of 45 to 90 degrees (preferably greater than or equal to 60 degrees and less than 90 degrees) relative to the lower surface 303a, the first metal film 310 can be deposited so as not to extend to the nAlGaN layer 304 and not to contact the side surface of the InGaN layer 305.

[0195] Therefore, leakage current flowing into the InGaN layer 305 due to contact between the first metal film 310 and the side surface of the InGaN layer 305 can be prevented, and thus the luminous efficiency degradation of the InGaN layer 305 (MQW layer) can be prevented. Incidentally, although the first metal film 310 covers a portion of the side surface 303b of the nGaN layer 303 in this example, the first metal film 310 may also further cover a portion of the side surface of the nAlGaN layer 304.

[0196] In addition, such as Figure 17 As shown in (C), since the fourth layer 314 (Pt) is formed between the second layer 312 (Al) and the fifth layer 315 (Au) of the first metal film 310 and extends to the side 303b of the nGaN layer 303, the increase in resistance caused by the formation of a eutectic between Al and Au during the annealing process described later can be prevented.

[0197] Figure 18 (A) is a cross-sectional view showing the process of transferring the functional unit 300 onto the device substrate 330. Figure 18 As shown in (A), the functional portion 300 held by the mold 320 is transferred onto the device substrate 330, which serves as a second substrate. The device substrate 330 is a substrate different from the growth substrate 301, and is, for example, a SiC substrate. However, the device substrate 330 is not limited to SiC, and may also be made of, for example, Si, glass, etc.

[0198] A second metal film 340 is formed on the main surface of the device substrate 330. Figure 18 (B) is an enlarged cross-sectional view showing the second metal film 340 on the main surface of the device substrate 330. Figure 18 As shown in (B), the second metal film 340 includes a first layer 341, a second layer 342 and a third layer 343 stacked sequentially from the device substrate 330 side (bottom side).

[0199] The first layer 341 to the third layer 343 of the second metal film 340 are respectively connected to the first layer 241 to the third layer 243 of the second metal film 240 in the second embodiment. Figure 13 It is formed in the same way as (B).

[0200] When the functional part 300 is transferred onto the device substrate 330, the first metal film 310 and the second metal film 340 are bonded together by applying a predetermined pressure. Afterward, the mold 320 is peeled off and removed from the upper surface of the functional part 300.

[0201] Figure 19 (A) is a cross-sectional view showing the process of bonding the metal film 310 of the functional part 300 and the metal film 340 of the device substrate 330 together. Figure 19 As shown in (A), the annealing process is performed at a temperature of 500°C to 800°C with the first metal film 310 and the second metal film 340 bonded together.

[0202] This process bonds the first metal film 310 and the second metal film 340 together. Through the pressure applied during bonding and the subsequent annealing process, even if the functional part 300 is warped, the first metal film 310 and the second metal film 340 can be bonded together without gaps.

[0203] Furthermore, through the annealing process, an ohmic contact is obtained between the nGaN layer 303 of the functional part 300 and the first layer 311, the third layer 313 (Ti), and the second layer 312 (Al) of the first metal film 310. Figure 17 (C) Furthermore, the fifth layer 315 (Au), which is the outermost layer of the first metal film 310 deposited on the functional part 300, is integrated with the third layer 343 (Au), which is the uppermost layer of the second metal film 340 on the device substrate 330.

[0204] Figure 19 (B) is a cross-sectional view showing the process of forming the P electrode 351 and the N electrode 352 on the functional part 300. Figure 19 As shown in (B), a P electrode 351 is formed on the pGaN layer 307 of the functional part 300. The P electrode 351 is made of, for example, ITO (indium tin oxide) or Ni / Au.

[0205] Furthermore, an N-electrode 352 is formed on the second metal film 340 (third layer 343) of the device substrate 330. The N-electrode 352 is made of Ti or a laminate of Ti, Pt, and Au. Incidentally, the second metal film 340 of the device substrate 330 can also be used as an electrode, without forming the N-electrode 352. Through the above process, an electronic device 30 as a vertical GaN light-emitting diode is completed.

[0206] As described above, the electronic device 30 in the third embodiment includes a functional portion 300, a device substrate 330 serving as a substrate supporting the functional portion 300, a first metal film 310 deposited as an electrode on the side of the functional portion 300 facing the device substrate 330, and a second metal film 340 formed on the device substrate 330 and bonded to the first metal film 310. The first metal film 310 is deposited from the lower surface (first surface) 303a of the functional portion 300 onto a portion of the side surface (second surface) 303b. Therefore, similar to the first embodiment, even when the functional portion 300 warps, the functional portion 300 can be well bonded to the device substrate 330, and peeling of the functional portion 300 can be prevented.

[0207] Furthermore, the functional unit 300 includes an nGaN layer 303 as a contact layer and semiconductor layers (nAlGaN layers 304 to pGaN layers 307) on the nGaN layer 303, and a first metal film 310 is formed on the nGaN layer 303. Therefore, the functional unit 300 and the second metal film 340 on the device substrate 330 can be electrically connected together via the first metal film 310.

[0208] (Fourth Implementation)

[0209] The fourth embodiment relates to an electronic device 40 as a vertical GaN field-effect transistor (FET) device having a trench structure and a method for manufacturing the same.

[0210] Figure 20 (A) is a cross-sectional view showing the process of forming a buffer layer 402 and a functional part 400 on a growth substrate 401 in the manufacturing method of the electronic device 40 in the fourth embodiment. Figure 20 The growth substrate 401 shown as the first substrate in (A) is, for example, a Si (111) substrate. Incidentally, the growth substrate 401 is not limited to Si (111), and the growth substrate 401 only needs to be a substrate on which the functional part 400 described below can be grown.

[0211] A buffer layer 402, serving as an AlN layer, is epitaxially grown on the main surface of the growth substrate 401. Although the buffer layer 402 is a monolayer AlN in this example, it is not limited to this example and could also be a stack of AlN and AlGaN layers. The thickness of the buffer layer 402 is, for example, from 200 nm to 1 μm.

[0212] An n+GaN layer 403, serving as a contact layer, is epitaxially grown on the buffer layer 402. The thickness of the n+GaN layer 403 is, for example, less than or equal to 5 μm. Incidentally, when the n+GaN layer 403 is grown on a GaN substrate, its thickness is greater than or equal to 100 μm, but by growing the n+GaN layer 403 on the growth substrate 401 (Si) via the buffer layer 402, this thickness can be made less than or equal to 5 μm.

[0213] Subsequently, an n-GaN layer 404, serving as a drift layer, is epitaxially grown on the n+GaN layer 403. The thickness of the n-GaN layer 404 is, for example, 2 μm to 50 μm.

[0214] Furthermore, a pGaN layer 405, serving as a contact layer, is epitaxially grown on the n-GaN layer 404. The thickness of the pGaN layer 405 is, for example, less than or equal to 10 μm.

[0215] Subsequently, an n+GaN layer 406 is epitaxially grown on the pGaN layer 405. The thickness of the n+GaN layer 406 is, for example, less than or equal to 1 μm.

[0216] The n+GaN layer 403, n-GaN layer 404, pGaN layer 405 and n+GaN layer 406 constitute the functional part (semiconductor thin film) 400.

[0217] Figure 20 (B) is a cross-sectional view showing the process of patterning the growth substrate 401, buffer layer 402, and functional part 400. Figure 20 As shown in (B), the growth substrate 401, buffer layer 402, and functional portion 400 are patterned into a device shape. The patterning is performed by forming a photoresist (not shown) on the functional portion 400 and performing dry etching.

[0218] Dry etching is performed until the depth (over-etching amount) t of the growth substrate 401 from its main surface reaches 50 nm to 10000 nm. Through this process, a sacrificial layer 401a with an area approximately the same as the lower surface of the buffer layer 402 is formed on the main surface of the growth substrate 401.

[0219] As described in the first embodiment, dry etching conditions are set such that the side surface of the functional portion 400 is formed as an inclined surface. Incidentally, the inclined direction of the functional portion 400 is: the dimension of the functional portion 400 in a plane parallel to the lower surface of the functional portion 400 (the lower surface 403a, which will be described later) decreases in the upward direction (i.e., as the distance from the lower surface increases). Although the description given here is for the side surface of the functional portion 400 to be an inclined surface, it is permissible as long as at least the side surface 403b (described later) of the n+GaN layer 403 (contact layer) is an inclined surface.

[0220] Figure 21 (A) is a cross-sectional view showing the process of etching the growth substrate 401. Figure 21 As shown in (A), the growth substrate 401 is etched in the surface direction (i.e. (100) direction) by means of wet etching using KOH.

[0221] The sacrificial layer 401a of the growth substrate 401 can be referred to as in the first embodiment. Figure 2 Partial etching can be performed as described in (B), or as referred to Figure 2 Completely remove as described in (C). Through this process, the functional part 400 becomes easy to separate from the growth substrate 401.

[0222] Figure 21 (B) is a cross-sectional view showing the process of separating the buffer layer 402 and the functional part 400 from the growth substrate 401. Figure 21As shown in (B), the mold 420, which serves as a holding member, is attached to the upper surface of the functional part 400 (the surface opposite to the growth substrate 401), and the buffer layer 402 and the functional part 400 are separated from the growth substrate 401. The structure of the mold 420 is the same as that of the mold 120 in the first embodiment.

[0223] Here, the a-axis lattice constant L of the Si(111) substrate forming the growth substrate 401 is... 401 The a-axis lattice constant L of AlN forming the buffer layer 402 is 3.89 Å. 402 The a-axis lattice constant L is 3.11 Å. This is the value of GaN with multiple layers forming the functional part 400. 400 It is 3.19 Å. The relationship between these lattice constants is L 401 >L 400 >L 402 .

[0224] Furthermore, the coefficient of thermal expansion T of the Si(111) substrate forming the growth substrate 401 at room temperature is... 401 for The coefficient of thermal expansion T of AlN forming the buffer layer 402 at room temperature is... 402 for The coefficient of thermal expansion T of GaN forming multiple layers of functional part 400 at room temperature is... 400 for The relationship between these coefficients of thermal expansion is T. 400 >T 402 >T 401 .

[0225] During the epitaxial growth process ( Figure 20 In (A), the buffer layer 402 and the functional portion 400 are epitaxially grown under tensile stress, such that their lattice constants are consistent with those of the growth substrate 401. Subsequently, when the buffer layer 402 and the functional portion 400 cool to room temperature, due to differences in thermal expansion, the buffer layer 402 and the functional portion 400 shrink more than the growth substrate 401, resulting in warping of the buffer layer 402 and the functional portion 400. Figure 21 As shown in (B), with the buffer layer 402 and the functional part 400 separated from the growth substrate 401, their warping becomes obvious.

[0226] Figure 22 (A) is a cross-sectional view showing the process of removing buffer layer 402. Figure 22As shown in (A), the buffer layer 402 is removed from the functional portion 400 by etching or polishing (such as CMP). This process exposes the lower surface 403a of the n+GaN layer 403 of the functional portion 400. By removing the buffer layer 402, the warpage of the functional portion 400 is reduced, but not completely eliminated.

[0227] Figure 22 (B) is a cross-sectional view showing the process of depositing a first metal film 410 on the functional section 400. Figure 22 As shown in (B), a first metal film 410 is deposited on the lower surface 403a of the n+GaN layer 403 of the functional part 400. The first metal film 410 is an electrode of the n+GaN layer 403 and is formed of a multilayer film.

[0228] A first metal film 410 is deposited on the lower surface 403a to extend to the side surface 403b of the n+GaN layer 403. The angle R (as described in the first embodiment) Figure 4 Similar to (B), the angle formed between the lower surface 403a and the side surface 403b of the n+GaN layer 403 is 45 degrees to 90 degrees, and preferably greater than or equal to 60 degrees and less than 90 degrees.

[0229] Figure 22 (C) is shown Figure 22 An enlarged view of the portion enclosed by the circle indicated by reference numeral A in (B). The first metal film 410 includes a first layer 411 made of Ti, a second layer 412 made of Al, a third layer 413 made of Ti, a fourth layer 414 made of Pt, and a fifth layer 415 made of Au, stacked sequentially from the n+GaN layer 403 side. The deposition method of these layers is as described in the second embodiment. Figure 12 (A) to Figure 12 As explained in (E).

[0230] As described in the second embodiment, the first metal film 410 is deposited by sputtering, vapor deposition, or other methods. For example, in... Figure 22 With the functional part 400 shown in (A) separated from the growth substrate 401, metal atoms for forming the first metal film 410 are continuously applied to the lower surface 403a, thereby forming the first metal film 410 from the lower surface 403a to the side surface 403b.

[0231] In this configuration, since the side surface 403b of the n+GaN layer 403 is an inclined surface at an angle of 45 to 90 degrees (preferably greater than or equal to 60 degrees and less than 90 degrees) relative to the lower surface 403a, the first metal film 410 can be deposited such that it does not contact the side surface of the n-GaN layer 404. By preventing the first metal film 410 from contacting the n-GaN layer 404, the voltage withstand performance of the n-GaN layer 404 (drift layer) can be prevented from deteriorating.

[0232] In addition, such as Figure 22 As shown in (C), since the fourth layer 414 (Pt) is formed between the second layer 412 (Al) and the fifth layer 415 (Au) of the first metal film 410 to extend to the side 403b of the n+GaN layer 403, the increase in resistance caused by the formation of a eutectic between Al and Au during the annealing process described later can be prevented.

[0233] Figure 23 (A) to Figure 23 (H) is a cross-sectional view showing another example of the deposition method of the first metal film 410. (See diagram below.) Figure 23 As shown in (A), a first layer 411 made of Ti is deposited on the lower surface 403a of the n+GaN layer 403 by sputtering or vapor deposition.

[0234] After that, as Figure 23 As shown in (B), the end of the first layer 411 (more specifically, the end near the side 403b of the n+GaN layer 403) E1 is removed by etching.

[0235] Subsequently, as Figure 23 As shown in (C), a second layer 412 made of Al is deposited by sputtering or vapor deposition to cover the first layer 411. Although the second layer 412 is deposited to cover the first layer 411 and the lower surface 403a exposed due to the removal of the end E1, the second layer 412 is not extended to the side 403b.

[0236] After that, as Figure 23 As shown in (D), the end E2 of the second layer 412 is removed by etching.

[0237] Subsequently, as Figure 23 As shown in (E), a third layer 413 made of Ti is deposited by sputtering or vapor deposition to cover the second layer 412. Although the third layer 413 is deposited to cover the second layer 412 and the lower surface 403a exposed due to the removal of the end E2, the third layer 413 is not allowed to extend to the side 403b.

[0238] After that, as Figure 23 As shown in (F), the end E3 of the third layer 413 is removed by etching.

[0239] Subsequently, as Figure 23 As shown in (G), a fourth layer 414 made of Pt is deposited by sputtering or vapor deposition to cover the third layer 413. Although the fourth layer 414 is deposited to cover the third layer 413 and the lower surface 403a exposed due to the removal of the end E3, the fourth layer 414 is not extended to the side 403b.

[0240] Subsequently, as Figure 23 As shown in (H), a fifth layer 415 made of Au is deposited by sputtering or vapor deposition to cover the fourth layer 414. The fifth layer 415 is deposited to cover the fourth layer 414 and extends to the side 403b.

[0241] As described above, the first layer 411 to the fifth layer 415 of the first metal film 410 are deposited such that each layer completely covers the layer below it. Among the first layer 411 to the fifth layer 415 of the first metal film 410, only the fifth layer 415 extends to the side 403b of the n+GaN layer 403.

[0242] In addition, in the Figure 23 (A) to Figure 23 When the first metal film 410 is deposited using the method shown in (H), the angle formed between the lower surface 403a and the side surface 403b of the n+GaN layer 403 remains between 45 and 90 degrees. This prevents the first metal film 410 from contacting the side surface of the n-GaN layer 404 and also prevents the degradation of the voltage withstand capability of the n-GaN layer 404. Furthermore, since the first metal film 410 serves to hold the lower surface 102a and the side surface 403b of the n+GaN layer 403, it prevents the functional portion 400 from peeling off.

[0243] Furthermore, since the fourth layer 414 (Pt) is located between the second layer 412 (Al) and the fifth layer 415 (Au) of the first metal film 410, the resistance increase caused by the formation of a eutectic between Al and Au during the annealing process can be prevented.

[0244] Although Figure 23 (A) to Figure 23 In the example shown in (H), only the fifth layer 415 of the first metal film 410 extends to the side 403b of the n+GaN layer 403. However, the construction of the first metal film 410 is not limited to this example, and two or more layers, including the fifth layer 415, may extend to the side 403b.

[0245] Figure 24 (A) is a cross-sectional view showing the process of transferring the functional unit 400 onto the device substrate 430. Figure 24As shown in (A), the functional portion 400 held by the mold 420 is transferred onto the device substrate 430, which serves as a second substrate. The device substrate 430 is a substrate different from the growth substrate 401, and is, for example, a SiC substrate. However, the device substrate 430 is not limited to SiC, and may also be made of, for example, Si, glass, etc.

[0246] A second metal film 440 is formed on the main surface of the device substrate 430. Figure 24 (B) is an enlarged cross-sectional view showing the second metal film 440 on the main surface of the device substrate 430. Figure 24 As shown in (B), the second metal film 440 includes a first layer 441, a second layer 442 and a third layer 443 stacked sequentially from the device substrate 430 side (bottom side).

[0247] The first layer 441 to the third layer 443 of the second metal film 440 are respectively connected to the first layer 241 to the third layer 243 of the second metal film 240 in the second embodiment. Figure 13 It is formed in the same way as (B).

[0248] When the functional part 400 is transferred onto the device substrate 430, the first metal film 410 and the second metal film 440 are bonded together by applying a predetermined pressure. Afterward, the mold 420 is peeled off and removed from the upper surface of the functional part 400.

[0249] Figure 25 (A) is a cross-sectional view showing the process of bonding the metal film 410 of the functional part 400 and the metal film 440 of the device substrate 430 together. Figure 25 As shown in (A), an annealing process is performed at a temperature of 500°C to 800°C while the first metal film 410 deposited on the functional part 400 and the second metal film 440 formed on the device substrate 430 are bonded together.

[0250] Through this process, the first metal film 410 and the second metal film 440 are bonded together. Through the pressure applied during bonding and the subsequent annealing process, even if the functional part 400 is warped, the first metal film 410 and the second metal film 440 can be bonded together without gaps.

[0251] Furthermore, through the annealing process, an ohmic contact is obtained between the n+GaN layer 403 of the functional part 400 and the first layer 411 (Ti) and the second layer 412 (Al) of the first metal film 410. Figure 22 (C) Furthermore, the fifth layer 415 (Au), which is the outermost layer of the first metal film 410 deposited on the functional part 400, is integrated with the third layer 443 (Au), which is the uppermost layer of the second metal film 440 on the device substrate 430.

[0252] Figure 25 (B) is a cross-sectional view showing the process of forming an insulating film 451 on the functional part 400. Figure 25 As shown in (B), the insulating film 451 is formed to cover the device substrate 430 and the functional portion 400. The insulating film 451 is, for example, a... The oxide film has a thickness of approximately 10 nm to 1 μm and is formed by sputtering or CVD (chemical vapor deposition).

[0253] Figure 26 (A) is a cross-sectional view showing the process of forming photoresist 452 on insulating film 451 and performing patterning. Figure 26 As shown in (A), photoresist 452 is formed on the insulating film 451 covering the functional portion 400 by, for example, spin coating. Furthermore, the photoresist 452 is patterned, and openings 453 are formed at the trench formation locations, which will be described later.

[0254] Figure 26 (B) is a cross-sectional view showing the process of forming the groove 407 in the functional section 400. (See diagram below.) Figure 26 As shown in (B), dry etching is performed via photoresist 452, thereby forming a trench 407 in the functional section 400 that reaches the n-GaN layer 404 (drift layer).

[0255] Figure 27 (A) is a cross-sectional view showing the process of forming an insulating film 451 and photoresist 452 in trench 407. Figure 27 As shown in (A), an insulating film 451 is formed to cover the inner surface of the trench 407 by, for example, CVD or ALD (atomic layer deposition). Furthermore, a photoresist 452 is formed to cover the insulating film 451 in the trench 407 by, for example, spin coating.

[0256] Figure 27 (B) is a cross-sectional view showing the process of forming an opening 454 in photoresist 452. Figure 27 As shown in (B), the photoresist 452 is exposed and developed, thereby forming an opening 454 at the location where the source electrode 461 will be described later.

[0257] Figure 28 (A) is a cross-sectional view showing the process of forming the groove 455 in the functional section 400. (See diagram for reference.) Figure 28 As shown in (A), dry etching is performed via photoresist 452, thereby forming a trench 455 in the functional portion 400 for forming the source electrode 461. The trench 455 is formed on both sides of the trench 407 to reach the pGaN layer 405.

[0258] Figure 28 (B) is a cross-sectional view showing the process of forming an opening 456 in photoresist 452. Figure 28 As shown in (B), the photoresist 452 is exposed and developed so that an opening 456 slightly larger than the groove 455 is formed at the position where it overlaps with the groove 455.

[0259] Figure 29 (A) is a cross-sectional view showing the process of forming the source electrode 461 and the gate electrode 462. The source electrode 461 is formed as a groove 455 filling the functional portion 400 and an opening 456 in the photoresist 452. The source electrode 461 is made of, for example, Ti or Al, and is formed by sputtering or vapor deposition.

[0260] Furthermore, a gate electrode 462 is formed in a trench 407 of the functional portion 400. The gate electrode 462 is made of, for example, Pd or Mo, and is formed by sputtering or vapor deposition.

[0261] Figure 29 (B) is a cross-sectional view showing the process of removing photoresist 452. (See diagram below.) Figure 29 As shown in (B), the photoresist 452 covering the functional part 400 is removed by peeling off the photoresist 452 or by dissolving the photoresist 452 in an organic solvent.

[0262] As described above, a source electrode 461 and a gate electrode 462 are formed on the functional section 400. Furthermore, the third layer 443 (Au) of the second metal film 440 on the device substrate 430 becomes the drain electrode. Through the above process, an electronic device 40, which is a vertical GaN field-effect transistor with a trench structure, is completed.

[0263] Since the functional part 400 (GaN) is grown on the growth substrate 401 made of Si or the like via the buffer layer 402 (AlN), there is no need to use an expensive GaN substrate as the growth substrate 401, and manufacturing costs can be reduced.

[0264] Furthermore, by removing the buffer layer 402, the first metal film 410, which serves as the drain electrode, can be directly formed on the n+GaN layer 403 and bonded to the second metal film 440 on the device substrate 430, thus enabling a low-resistance vertical structure GaN field-effect transistor (GaN FET).

[0265] Furthermore, since the thickness of the n+GaN layer 403, which serves as the contact layer, can be much smaller than the thickness of the n-GaN layer 404, which serves as the drift layer, an ohmic contact can be obtained between the n+GaN layer 403 and the first metal film 410, which serves as the drain electrode. This can reduce the on-resistance between the source electrode 461 and the drain electrode, and improve the operating efficiency of the electronic device 40.

[0266] In addition, since the SiC substrate can be used as the device substrate 430, the thermal radiation performance of the electronic device 40 can be improved compared with the case of using the GaN substrate.

[0267] As described above, the electronic device 40 in the fourth embodiment includes a functional portion 400, a device substrate 430 serving as a substrate supporting the functional portion 400, a first metal film 410 deposited as an electrode on the side of the functional portion 400 facing the device substrate 430, and a second metal film 440 formed on the device substrate 430 and bonded to the first metal film 410. The first metal film 410 is deposited from the lower surface (first surface) 403a of the functional portion 400 onto a portion of the side surface (second surface) 403b. Therefore, similar to the first embodiment, even when the functional portion 400 warps, the functional portion 400 can be well bonded to the device substrate 430, and peeling of the functional portion 400 can be prevented.

[0268] Furthermore, the functional unit 400 includes an n+GaN layer 403 as a contact layer and semiconductor layers (n-GaN layer 404, pGaN layer 405, and n+GaN layer 406) on the n+GaN layer 403, and a first metal film 410 is formed on the n+GaN layer 403. Therefore, these semiconductor layers and the second metal film 440 on the device substrate 430 can be electrically connected together via the first metal film 410.

[0269] (Fifth implementation method)

[0270] The structure of the electronic device in the fifth embodiment is the same as that of the electronic device 40 in the fourth embodiment. The difference between the manufacturing method of the electronic device in the fifth embodiment and the manufacturing method of the electronic device 40 in the fourth embodiment is that the trench 507 is formed before the functional part 500 is transferred onto the device substrate 530.

[0271] Figure 30 (A) is a cross-sectional view showing the process of forming a buffer layer 502 and a functional part 500 on a growth substrate 501, which serves as a first substrate, in the manufacturing method of an electronic device according to the fifth embodiment.

[0272] Figure 30 The growth substrate 501, buffer layer 502, n+GaN layer 503, n-GaN layer 504, pGaN layer 505 and n+GaN layer 506 shown in (A) are formed in the same manner as the growth substrate 401, buffer layer 402, n+GaN layer 403, n-GaN layer 404, pGaN layer 405 and n+GaN layer 406 described in the fourth embodiment.

[0273] The n+GaN layer 503, n-GaN layer 504, pGaN layer 505, and n+GaN layer 506 constitute the functional unit 500.

[0274] Figure 30 (B) is a cross-sectional view showing the process of patterning the growth substrate 501, buffer layer 502, and functional part 500. Figure 30 As shown in (B), the growth substrate 501, buffer layer 502, and functional part 500 are patterned into element shapes. The patterning method is as previously described in the fourth embodiment. Figure 20 As explained in (B).

[0275] Figure 31 (A) is a cross-sectional view showing the process of forming an insulating film 551 and a photoresist 552 on the functional part 500. Figure 31 As shown in (A), the insulating film 551 is formed to cover the functional portion 500. The insulating film 551 is, for example, a... The oxide film has a thickness of approximately 10 nm to 1 μm and is formed by sputtering or vapor deposition.

[0276] Furthermore, photoresist 552 is formed on the insulating film 551 covering the functional portion 500 by means of, for example, spin coating. The photoresist 552 is then patterned, and openings 553 are formed at the locations where trenches will be formed, as will be described later.

[0277] Figure 31 (B) is a cross-sectional view showing the process of forming the groove 507 in the functional section 500. (See diagram below.) Figure 31 As shown in (B), dry etching is performed via photoresist 552, thereby forming a trench 507 in the functional part 500 that reaches the n-GaN layer 504 (drift layer).

[0278] Figure 32 (A) is a cross-sectional view showing the process of forming an insulating film 551 and photoresist 552 in trench 507. Figure 32 As shown in (A), an insulating film 551 is formed to cover the inner surface of the trench 507 by means of, for example, CVD or ALD. In addition, a photoresist 552 is formed to cover the insulating film 551 in the trench 507 by means of, for example, spin coating.

[0279] Figure 32 (B) is a cross-sectional view showing the process of etching the growth substrate 501. Figure 32 As shown in (B), the growth substrate 501 is etched in the surface direction (i.e. (100) direction) of the growth substrate 501 by means of wet etching using KOH.

[0280] The sacrificial layer 501a of the growth substrate 501 can be referred to as in the first embodiment. Figure 2 Partial etching can be performed as described in (B), or as referred to Figure 2 Completely remove as described in (C). Through this process, the functional part 500 becomes easy to separate from the growth substrate 501.

[0281] Figure 33 (A) is a cross-sectional view showing the process of separating the buffer layer 502 and the functional part 500 from the growth substrate 501. Figure 33 As shown in (A), the mold 520, which serves as a holding member, is attached to the upper surface of the functional part 500, and the buffer layer 502 and the functional part 500 are separated from the growth substrate 501. The structure of the mold 520 is the same as that of the mold 120 in the first embodiment.

[0282] As described in the fourth embodiment, when the buffer layer 502 and the functional part 500 have been separated from the growth substrate 501, their warping becomes obvious.

[0283] Figure 33 (B) is a cross-sectional view showing the process of removing buffer layer 502. Figure 33 As shown in (B), the buffer layer 502 is removed by etching or polishing (such as CMP). This process exposes the lower surface 503a of the n+GaN layer 503 of the functional part 500. By removing the buffer layer 502, the warpage of the functional part 500 is reduced, but not completely eliminated.

[0284] Figure 34 (A) is a cross-sectional view showing the process of depositing the first metal film 510. Figure 34 As shown in (A), a first metal film 510 is deposited on the lower surface 503a of the n+GaN layer 503 of the functional part 500. The first metal film 510 is an electrode of the n+GaN layer 503. The structure of the first metal film 510 is the same as that of the first metal film 410 in the fourth embodiment. Figure 22 The structure of (C) is the same.

[0285] Figure 34 (B) is a cross-sectional view showing the process of transferring the functional unit 500 onto the device substrate 530. Figure 34 As shown in (B), the functional part 500 held by the mold 520 is transferred onto the device substrate 530, which serves as the second substrate. A second metal film 540 is formed on the main surface of the device substrate 530.

[0286] Device substrate 530 and second metal film 540 are the same as device substrate 430 and second metal film 440 in the fourth embodiment. Figure 24(B) is the same. In addition, the layers of metal films 510 and 540 in the fifth embodiment can also use the combination shown in Table 1 of the second embodiment.

[0287] The process of attaching the functional unit 500 to the device substrate 530 is the same as in the fourth embodiment. Figure 25 (A) to Figure 29 The process described in (B) is the same. Through this process, an electronic device is completed as a vertical GaN field-effect transistor with a trench structure.

[0288] As described above, in the method for manufacturing an electronic device according to the fifth embodiment, the trench 507 is formed before the functional portion 500 is separated from the growth substrate 501, thus reducing the number of process steps performed after the functional portion 500 is transferred onto the device substrate 530. Therefore, stress and the like acting on the metal films 510 and 540 can be reduced, and poor bonding can be prevented.

[0289] (Sixth Implementation Method)

[0290] Similar to the fourth and fifth embodiments, the sixth embodiment relates to an electronic device 60 used as a vertical GaN field-effect transistor (FET) device with a trench structure and a method for manufacturing the same.

[0291] Figure 35 (A) is a cross-sectional view showing the process of forming a buffer layer 602 and a functional part 600 on a growth substrate 601, which serves as a first substrate, in the manufacturing method of the electronic device 60 in the sixth embodiment. Figure 35 The growth substrate 601, buffer layer 602, n+GaN layer 603, n-GaN layer 604, pGaN layer 605, and n+GaN layer 606 shown in (A) are respectively aligned with the growth substrate 401, buffer layer 402, n+GaN layer 403, n-GaN layer 404, pGaN layer 405, and n+GaN layer 406 described in the fourth embodiment. Figure 20 It is formed in the same way as (A).

[0292] The n+GaN layer 603, n-GaN layer 604, pGaN layer 605 and n+GaN layer 606 constitute the functional part (semiconductor thin film) 600.

[0293] Figure 35 (B) is a cross-sectional view showing the first patterning process of the functional unit 600. (See diagram below.) Figure 35 As shown in (B), the n-GaN layer 604, pGaN layer 605, and n+GaN layer 606 of the functional unit 600 are patterned into a first element shape. The first patterning process is performed by forming a photoresist (mask) (not shown) on the functional unit 600 and performing dry etching.

[0294] The dry etching conditions for the first patterning process are set to form the sides of the n-GaN layer 604, pGaN layer 605 and n+GaN layer 606 of the functional part 600 as vertical surfaces (i.e. surfaces orthogonal to the main surface of the growth substrate 601).

[0295] Figure 36 (A) is a cross-sectional view showing the second patterning process of the growth substrate 601, buffer layer 602, and functional part 600. Figure 36 As shown in (A), the growth substrate 601, buffer layer 602, and n+GaN layer 603 are patterned into a second element shape. The second patterning process is performed by forming a photoresist (mask) (not shown) on the functional part 600 and performing dry etching.

[0296] During the second patterning process, dry etching is performed until the depth (over-etching amount) t of the growth substrate 601 from its main surface reaches 50 nm to 10000 nm. Through this process, a sacrificial layer 601a with an area approximately the same as the lower surface of the buffer layer 602 is formed on the main surface of the growth substrate 601.

[0297] The dry etching conditions for the second patterning process are set to form inclined surfaces on the sides of the buffer layer 602 and the n+GaN layer 603. It is desired that these dry etching conditions be set to form a step S between the n+GaN layer 603 and the n-GaN layer 604.

[0298] Through these two patterning processes, the functional unit 600 includes a first portion (n+GaN layer 603) with inclined surfaces on its sides and a second portion (n-GaN layer 604, pGaN layer 605, and n+GaN layer 606) with vertical surfaces on its sides. Incidentally, the sides of the second portion are not limited to vertical surfaces, but can also be inclined surfaces with a different inclination angle than the sides of the first portion.

[0299] Figure 36 (B) is a cross-sectional view showing the process of etching the growth substrate 601. Figure 36 As shown in (B), the growth substrate 601 is etched in the surface direction (i.e. (100) direction) of the growth substrate 601 by means of wet etching using KOH.

[0300] The sacrificial layer 601a of the growth substrate 601 can be referred to as in the first embodiment. Figure 2 Partial etching can be performed as described in (B), or as referred to Figure 2 Completely remove it as described in (C). Through this process, the functional part 600 becomes easy to separate from the growth substrate 601.

[0301] Figure 37 (A) is a cross-sectional view showing the process of separating the buffer layer 602 and the functional part 600 from the growth substrate 601. Figure 37 As shown in (A), the mold 620, which serves as a holding member, is attached to the upper surface of the functional part 600 (the surface opposite to the growth substrate 601), and the buffer layer 602 and the functional part 600 are separated from the growth substrate 601. The structure of the mold 620 is the same as that of the mold 120 in the first embodiment.

[0302] As described in the fourth embodiment, when the buffer layer 602 and the functional part 600 have been separated from the growth substrate 601, their warping becomes obvious.

[0303] Figure 37 (B) is a cross-sectional view showing the process of removing buffer layer 602. Figure 37 As shown in (B), the buffer layer 602 is removed by etching or polishing (such as CMP). This process exposes the lower surface 603a of the n+GaN layer 603 of the functional part 600. By removing the buffer layer 602, the warpage of the functional part 600 is reduced, but not completely eliminated.

[0304] Figure 38 (A) is a cross-sectional view showing the process of forming the first metal film 610. Figure 38 As shown in (A), a first metal film 610 is formed on the lower surface 603a of the n+GaN layer 603 of the functional part 600. The first metal film 610 is an electrode of the n+GaN layer 603 and is formed of multiple films.

[0305] A first metal film 610 is deposited on the lower surface 603a to extend to the side surface 603b of the n+GaN layer 603. The angle formed by the lower surface 603a and the side surface 603b of the n+GaN layer 603 is greater than the angle R described in the first embodiment. Figure 4 (B)), and for example, 80 to 90 degrees.

[0306] Figure 38 (B) is shown Figure 38 An enlarged view of the portion enclosed by the circle indicated by reference numeral A in (A). The first metal film 610 includes a first layer 611 made of Ti, a second layer 612 made of Al, a third layer 613 made of Ti, a fourth layer 614 made of Pt, and a fifth layer 615 made of Au, stacked sequentially from the n+GaN layer 603 side. The deposition method of these layers is as described in the previous second embodiment. Figure 12 (A) to Figure 12 As explained in (E).

[0307] As described in the second embodiment, the first metal film 610 is deposited by sputtering, vapor deposition, or other methods. For example, in... Figure 37 With the functional part 600 shown in (B) separated from the growth substrate 601, metal atoms for forming the first metal film 610 are continuously applied to the lower surface 603a, thereby forming the first metal film 610 from the lower surface 603a to the side surface 603b.

[0308] In this configuration, since the side surface 603b of the n+GaN layer 603 is an inclined surface at an angle of 80 to 90 degrees relative to the lower surface 603a, the first metal film 610 can be deposited such that it does not contact the side surface of the n-GaN layer 604. By preventing the first metal film 610 from contacting the n-GaN layer 604, the voltage withstand performance of the n-GaN layer 604 (active layer) can be prevented from deteriorating.

[0309] Furthermore, since a two-step etching process was performed in the sixth embodiment ( Figure 35 (B) Figure 36 Therefore, a step portion S can be formed between the n+GaN layer 603 and the n-GaN layer 604. Consequently, the side surface of the n-GaN layer 604 can be recessed towards the interior of the functional portion 600 relative to the side surface 603b of the n+GaN layer 603. Therefore, the first metal film 610 becomes less likely to contact the n-GaN layer 604, and the effect of preventing degradation of the voltage withstand performance of the n-GaN layer 604 can be enhanced.

[0310] In addition, such as Figure 38 As shown in (B), since the fourth layer 614 (Pt) is formed between the second layer 612 (Al) and the fifth layer 615 (Au) of the first metal film 610 to extend to the side 603b of the n+GaN layer 603, the increase in resistance caused by the formation of a eutectic between Al and Au during the annealing process described later can be prevented.

[0311] Figure 39 (A) is a cross-sectional view showing the process of transferring the functional unit 600 onto the device substrate 630. Figure 39 As shown in (A), the functional part 600 held by the mold 620 is transferred to the device substrate 630, which serves as the second substrate. The device substrate 630 is the same as the device substrate 430 described in the fourth embodiment.

[0312] A second metal film 640 is formed on the main surface of the device substrate 630. Figure 39 (B) is an enlarged cross-sectional view showing the second metal film 640 on the main surface of the device substrate 630. Figure 39As shown in (B), the second metal film 640 includes a first layer 641, a second layer 642 and a third layer 643 stacked sequentially from the device substrate 630 side (bottom side).

[0313] The first layer 641 to the third layer 643 of the second metal film 640 are formed in the same manner as the first layer 441 to the third layer 443 of the second metal film 440 described in the fourth embodiment. Furthermore, the layers of the metal films 610 and 640 may also use the combinations shown in Table 1 of the second embodiment.

[0314] When the functional part 600 is transferred onto the device substrate 630, the first metal film 610 and the second metal film 640 are bonded together by applying a predetermined pressure. Afterward, the mold 620 is peeled off and removed from the upper surface of the functional part 600.

[0315] Figure 40 (A) is a cross-sectional view showing the process of bonding the metal film 610 of the functional part 600 and the metal film 640 of the device substrate 630 together. Figure 40 As shown in (A), the annealing process is performed at a temperature of 500°C to 800°C with the first metal film 610 and the second metal film 640 bonded together.

[0316] This process bonds the first metal film 610 and the second metal film 640 together. Through the pressure applied during bonding and the subsequent annealing process, even if the functional part 600 is warped, the first metal film 610 and the second metal film 640 can be bonded together without gaps.

[0317] Furthermore, through the annealing process, an ohmic contact is obtained between the n+GaN layer 603 of the functional part 600 and the first layer 611 (Ti) and the second layer 612 (Al) of the first metal film 610. Moreover, the fifth layer 615 (Au), which is the outermost layer of the first metal film 610 deposited on the functional part 600, is integrated with the third layer 643 (Au), which is the uppermost layer of the second metal film 640 on the device substrate 630.

[0318] Figure 40 (B) is a cross-sectional view showing the process of forming an insulating film 651 on the functional part 600. Figure 40 As shown in (B), the insulating film 651 is formed to cover the device substrate 630 and the functional portion 600. The insulating film 651 is, for example, a... The oxide film has a thickness of approximately 10 nm to 1 μm and is formed by sputtering or vapor deposition.

[0319] Figure 41(A) is a cross-sectional view showing the process of forming and patterning photoresist 652 on insulating film 651. Figure 41 As shown in (A), photoresist 652 is formed on the insulating film 651 covering the functional portion 600 by, for example, spin coating. Furthermore, the photoresist 652 is patterned, and openings 653 are formed at the trench formation locations, which will be described later.

[0320] Figure 41 (B) is a cross-sectional view showing the process of forming the groove 607 in the functional section 600. (See diagram below.) Figure 41 As shown in (B), dry etching is performed via photoresist 652, thereby forming a trench 607 in the functional part 600 that reaches the n-GaN layer 604 (drift layer).

[0321] Figure 42 (A) is a cross-sectional view showing the process of forming an insulating film 651 and photoresist 652 in trench 607. Figure 42 As shown in (A), an insulating film 651 is formed to cover the inner surface of the trench 607 by means of, for example, CVD or ALD. In addition, a photoresist 652 is formed to cover the insulating film 651 in the trench 607 by means of, for example, spin coating.

[0322] Figure 42 (B) is a cross-sectional view showing the process of forming an opening 654 in photoresist 652. Figure 42 As shown in (B), the photoresist 652 is exposed and developed, thereby forming an opening 654 at the location where the source electrode 661 will be described later.

[0323] Figure 43 (A) is a cross-sectional view showing the process of forming the groove 655 in the functional section 600. Figure 43 As shown in (A), dry etching is performed via photoresist 652, thereby forming a trench 655 in the functional portion 600 for forming the source electrode 661. The trench 655 is formed to reach the pGaN layer 605.

[0324] Figure 43 In (B), by exposing and developing the photoresist 652, an opening 656 slightly larger than the groove 655 is formed at the position where it overlaps with the groove 655. Furthermore, the photoresist 652 is removed from the trench 607.

[0325] Figure 44 (A) is a cross-sectional view showing the process of forming the source electrode 661 and the gate electrode 662. The source electrode 661 is formed as a groove 655 filling the functional portion 600 and an opening 656 for the photoresist 652. The source electrode 661 is made of, for example, Ti or Al, and is formed by sputtering or vapor deposition.

[0326] Furthermore, a gate electrode 662 is formed in a trench 607 of the functional portion 600. The gate electrode 662 is made of, for example, Pd or Mo, and is formed by sputtering or vapor deposition.

[0327] Figure 44 (B) is a cross-sectional view showing the process of removing photoresist 652. Figure 44 As shown in (B), the photoresist 652 covering the functional part 600 is removed by peeling off the photoresist 652 or by dissolving the photoresist 652 in an organic solvent.

[0328] As described above, a source electrode 661 and a gate electrode 662 are formed on the functional section 600, and the third layer 643 (Au) of the second metal film 640 on the device substrate 630 becomes the drain electrode. Through the above process, an electronic device 60 is completed as a vertical GaN field-effect transistor with a trench structure.

[0329] As described above, the electronic device 60 in the sixth embodiment includes a functional portion 600, a device substrate 630 serving as a substrate supporting the functional portion 600, a first metal film 610 deposited as an electrode on the side of the functional portion 600 facing the device substrate 630, and a second metal film 640 formed on the device substrate 630 and bonded to the first metal film 610. The first metal film 610 is deposited from the lower surface (first surface) 603a of the functional portion 600 onto a portion of the side surface (second surface) 603b. Therefore, similar to the first embodiment, even when the functional portion 600 warps, the functional portion 600 can be well bonded to the device substrate 630, and peeling of the functional portion 600 can be prevented.

[0330] Furthermore, the first portion (n+GaN layer 603) of functional unit 600 has a tilt angle on its sides, while the second portion (i.e., n-GaN layer 604, pGaN layer 605, and n+GaN layer 606) of functional unit 600 does not have a tilt angle on its sides. Therefore, functional unit 600 can be formed to a larger size compared to functional unit 400 in the fourth embodiment and functional unit 500 in the fifth embodiment.

[0331] Furthermore, since the n-GaN layer 604 of the functional part 600 can be formed at a position that is recessed relative to the n+GaN layer 603 in a direction parallel to the main surface of the device substrate 630, it can prevent the first metal film 610 or the second metal film 640 from contacting the n-GaN layer 604, and can prevent the voltage withstand performance of the n-GaN layer 604 from deteriorating.

[0332] (Seventh Implementation)

[0333] The seventh embodiment relates to an electronic device 70 as a vertical GaN field-effect transistor (FET) device having a planar structure and a method for manufacturing the same.

[0334] Figure 45 (A) is a cross-sectional view showing the process of forming a buffer layer 702 and a functional part 700 on a growth substrate 701, which serves as a first substrate, in the manufacturing method of the electronic device 70 in the seventh embodiment. Figure 45 The growth substrate 701 shown in (A) is, for example, a Si (111) substrate. Incidentally, the growth substrate 701 is not limited to Si (111), and the growth substrate 701 only needs to be a substrate on which the functional part 700 described below can be grown.

[0335] A buffer layer 702, serving as an AlN layer, is epitaxially grown on the main surface of the growth substrate 701. Although the buffer layer 702 is a monolayer AlN in this example, it is not limited to this example and could also be a stack of AlN and AlGaN layers. The thickness of the buffer layer 702 is, for example, from 200 nm to 1 μm.

[0336] An n+GaN layer 703, serving as a contact layer, is epitaxially grown on the buffer layer 702. The thickness of the n+GaN layer 703 is, for example, less than or equal to 5 μm.

[0337] Subsequently, an n-GaN layer 704, serving as a drift layer, is epitaxially grown on the n+GaN layer 703. The thickness of the n-GaN layer 704 is, for example, 2 μm to 50 μm.

[0338] Furthermore, a pGaN layer 705 is epitaxially grown on the n-GaN layer 704. The thickness of the pGaN layer 705 is, for example, less than or equal to 10 μm.

[0339] The n+GaN layer 703, the n-GaN layer 704, and the pGaN layer 705 constitute the functional unit 700.

[0340] Figure 45 (B) is a cross-sectional view showing the process of patterning the growth substrate 701, the buffer layer 702, and the functional part 700. Figure 45 As shown in (B), the growth substrate 701, buffer layer 702, and functional part 700 are patterned into a device shape. The patterning is performed by forming a photoresist (mask) (not shown) on the functional part 700 and performing dry etching.

[0341] Dry etching is performed until the depth (over-etching amount) t of the growth substrate 701 from its main surface reaches 50 nm to 10000 nm. Through this process, a sacrificial layer 701a with an area approximately the same as the lower surface of the buffer layer 702 is formed on the main surface of the growth substrate 701.

[0342] As described in the first embodiment, dry etching conditions are set such that the side surface of the functional portion 700 is formed as an inclined surface. Incidentally, the inclined direction of the functional portion 700 is: the dimension of the functional portion 700 in a plane parallel to the lower surface of the functional portion 700 (the lower surface 703a, which will be described later) decreases in the upward direction (i.e., as the distance from the lower surface increases). Although the description given here is for the side surface of the functional portion 700 to be an inclined surface, it is permissible as long as at least the side surface 703b of the n+GaN layer 703 (contact layer), which will be described later, is an inclined surface.

[0343] Figure 46 (A) is a cross-sectional view showing the process of forming an insulating film 751 on the functional part 700. Figure 46 As shown in (A), the insulating film 751 is formed to cover the functional portion 700. The insulating film 751 is, for example, a... The oxide film has a thickness of approximately 10 nm to 1 μm and is formed by sputtering or vapor deposition.

[0344] Furthermore, the insulating film 751 is patterned using photoresist (not shown), and the groove 753 will be described later. Figure 46 An opening 752 is formed above the formation position of (B).

[0345] Figure 46 (B) is a cross-sectional view showing the process of forming the groove 753 in the functional section 700. (See diagram below.) Figure 46 As shown in (B), a trench 753 reaching the n-GaN layer 704 (drift layer) is formed in the functional part 700 by dry etching.

[0346] Figure 47 (A) is a cross-sectional view showing the process of epitaxially growing an n-GaN layer 704 in the trench 753. Figure 47 As shown in (A), an n-GaN layer 704 is epitaxially grown to fill the groove 753 of the functional part 700.

[0347] Figure 47 (B) is a cross-sectional view showing the process of forming an opening 754 in the insulating film 751. Figure 47 As shown in (B), the insulating film 751 is patterned using a photoresist (not shown) to remove the portion above the pGaN layer 705, thereby forming an opening 754. The opening 754 is formed in the groove 753 (…). Figure 46 The two sides of the n-GaN layer 704 in (B)).

[0348] Figure 48(A) is a cross-sectional view showing the process of forming n+GaN layers 755 and 756 by implanting ions into pGaN layer 705. Figure 48 As shown in (A), n+GaN layers 755 and 756 are formed by implanting Si ions into pGaN layer 705 through opening 754 of insulating film 751.

[0349] Figure 48 (B) is a cross-sectional view showing the process of reforming the insulating film 751. Figure 48 As shown in (B), the insulating film 751 is formed to cover the n-GaN layer 704 and the n+GaN layers 755 and 756 in the trench 753.

[0350] Figure 49 (A) is a cross-sectional view showing the process of etching the growth substrate 701. Figure 49 As shown in (A), the growth substrate 701 is etched in the surface direction (i.e. (100) direction) of the growth substrate 701 by means of wet etching using KOH.

[0351] The sacrificial layer 701a of the growth substrate 701 can be referred to as in the first embodiment. Figure 2 Partial etching can be performed as described in (B), or as referred to Figure 2 Completely remove it as described in (C). Through this process, the functional part 700 becomes easy to separate from the growth substrate 701.

[0352] Figure 49 (B) is a cross-sectional view showing the process of separating the buffer layer 702 and the functional part 700 from the growth substrate 701. Figure 49 As shown in (B), the mold 720, which serves as a holding member, is attached to the upper surface of the functional part 700 (the surface opposite to the growth substrate 701), and then the buffer layer 702 and the functional part 700 are separated from the growth substrate 701. The structure of the mold 720 is the same as that of the mold 120 in the first embodiment.

[0353] As described in the fourth embodiment, when the buffer layer 702 and the functional part 700 have been separated from the growth substrate 701, their warping becomes obvious.

[0354] Figure 50 (A) is a cross-sectional view showing the process of removing the buffer layer 702 from the functional unit 700. Figure 50 As shown in (A), the buffer layer 702 is removed by etching or polishing (such as CMP). This process exposes the lower surface 703a of the n+GaN layer 703 of the functional part 700. By removing the buffer layer 702, the warpage of the functional part 700 is reduced, but not completely eliminated.

[0355] Figure 50 (B) is a cross-sectional view showing the process of forming the first metal film 710. Figure 50 As shown in (B), a first metal film 710 is formed on the lower surface 703a of the n+GaN layer 703 of the functional part 700. The first metal film 710 is an electrode of the n+GaN layer 703 and is formed of multiple films.

[0356] A first metal film 710 is deposited on the lower surface 703a to extend to the side surface 703b of the n+GaN layer 703. The angle R (as described in the first embodiment) Figure 4 Similar to (B), the angle formed between the lower surface 703a and the side surface 703b of the n+GaN layer 703 is 45 degrees to 90 degrees, and preferably greater than or equal to 60 degrees and less than 90 degrees.

[0357] As described in the second embodiment, the first metal film 710 is deposited by sputtering, vapor deposition, or other methods. For example, in... Figure 50 With the functional part 700 shown in (A) separated from the growth substrate 701, metal atoms for forming the first metal film 710 are continuously applied to the lower surface 703a, thereby forming the first metal film 710 from the lower surface 703a to the side surface 703b.

[0358] In this configuration, since the side surface 703b of the n+GaN layer 703 is an inclined surface at an angle of 45 to 90 degrees (preferably greater than or equal to 60 degrees and less than 90 degrees) relative to the lower surface 703a, the first metal film 710 can be deposited such that it does not contact the side surface of the n-GaN layer 704. By preventing the first metal film 710 from contacting the n-GaN layer 704, the voltage withstand performance of the n-GaN layer 704 (drift layer) can be prevented from deteriorating.

[0359] In addition, such as Figure 50 As shown in (C), since the fourth layer 714 (Pt) is formed between the second layer 712 (Al) and the fifth layer 715 (Au) of the first metal film 710 to extend to the side 703b of the n+GaN layer 703, the increase in resistance caused by the formation of a eutectic between Al and Au during the annealing process described later can be prevented.

[0360] Figure 50 (C) is shown Figure 50 An enlarged view of the portion enclosed by the circle indicated by reference numeral A in (B). The first metal film 710 includes a first layer 711 made of Ti, a second layer 712 made of Al, a third layer 713 made of Ti, a fourth layer 714 made of Pt, and a fifth layer 715 made of Au. The deposition method of these layers is as described in the previous second embodiment. Figure 12(A) to Figure 12 As explained in (E).

[0361] Figure 51 (A) is a cross-sectional view showing the process of transferring the functional unit 700 onto the device substrate 730. Figure 51 As shown in (A), the functional portion 700 held by the mold 720 is transferred onto the device substrate 730, which serves as the second substrate. The device substrate 730 is the same as the device substrate 430 described in the fourth embodiment.

[0362] A second metal film 740 is formed on the main surface of the device substrate 730. Figure 51 (B) is an enlarged cross-sectional view showing the second metal film 740 on the main surface of the device substrate 730. Figure 51 As shown in (B), the second metal film 740 includes a first layer 741 made of Ti, a second layer 742 made of Pt, and a third layer 743 made of Au, which are stacked sequentially from the device substrate 730 side.

[0363] The first layer 741 to the third layer 743 are formed in the same manner as the first layer 441 to the third layer 443 of the second metal film 440 described in the fourth embodiment. Furthermore, the layer structures of the metal films 710 and 740 in the seventh embodiment can also adopt the combinations shown in Table 1 of the second embodiment.

[0364] When the functional part 700 is transferred onto the device substrate 730, the first metal film 710 and the second metal film 740 are bonded together by applying a predetermined pressure to them. Afterward, the mold 720 is peeled off and removed from the upper surface of the functional part 700.

[0365] Figure 52 (A) is a cross-sectional view showing the process of bonding the metal film 710 of the functional part 700 and the metal film 740 of the device substrate 730 together. Figure 52 As shown in (A), the annealing process is performed at a temperature of 500°C to 800°C with the first metal film 710 and the second metal film 740 bonded together.

[0366] Through this process, the first metal film 710 and the second metal film 740 are bonded together. Through the pressure applied during bonding and the subsequent annealing process, even if the functional part 700 is warped, the first metal film 710 and the second metal film 740 can be bonded together without gaps.

[0367] Furthermore, through the annealing process, an ohmic contact is obtained between the n+GaN layer 703 of the functional part 700 and the first layer 711 (Ti) and the second layer 712 (Al) of the first metal film 710. Moreover, the fifth layer 715 (Au), which is the outermost layer of the first metal film 710 deposited on the functional part 700, is integrated with the third layer 743 (Au), which is the uppermost layer of the second metal film 740 on the device substrate 730.

[0368] Figure 52 (B) is a cross-sectional view showing the process of patterning the insulating film 751. Figure 52 As shown in (B), the insulating film 751 on the functional part 700 is patterned, and the insulating film 751 used to form the gate electrode 763, which will be described later, is removed. Figure 53 The area outside of the part of ).

[0369] Figure 53 This is a cross-sectional view showing the process of forming source electrodes 761, 762 and gate electrode 763. (See diagram below.) Figure 53 As shown, source electrode 761 is formed bridging the n+GaN layer 755 and pGaN layer 705 on one side, and source electrode 762 is formed bridging the n+GaN layer 756 and pGaN layer 705 on the other side. Source electrodes 761 and 762 are made of, for example, Ti or Al, and are formed by sputtering or vapor deposition.

[0370] Furthermore, the gate electrode 763 is formed on an insulating film 751 bridging the two n+ GaN layers 755 and 756. The gate electrode 763 is made of, for example, Pd or Mo, and is formed by sputtering or vapor deposition.

[0371] As described above, source electrodes 761, 762 and gate electrode 763 are formed on the functional part 700, and the third layer 743 (Au) of the second metal film 740 on the device substrate 730 becomes the drain electrode. Through the above process, an electronic device 70 as a planar vertical GaN field-effect transistor is completed.

[0372] As described above, the electronic device 70 in the seventh embodiment includes a functional portion 700, a device substrate 730 serving as a substrate supporting the functional portion 700, a first metal film 710 deposited as an electrode on the side of the functional portion 700 facing the device substrate 730, and a second metal film 740 formed on the device substrate 730 and bonded to the first metal film 710. The first metal film 710 is deposited from the lower surface (first surface) 703a of the functional portion 700 onto a portion of the side surface (second surface) 703b. Therefore, similar to the first embodiment, even when the functional portion 700 warps, the functional portion 700 can be well bonded to the device substrate 730, and peeling of the functional portion 700 can be prevented.

[0373] The first to seventh embodiments described above can be appropriately combined.

[0374] In the first embodiment, the functional layer 102 (functional part) is formed of AlN, and in the second to seventh embodiments, the functional parts 200, 300, 400, 500, 600, and 700 are formed of GaN. However, the functional parts in this disclosure are not limited to AlN and GaN; any nitride-containing epitaxial layer is acceptable. Furthermore, in addition to nitride-containing epitaxial layers, the functional parts may also be GaAs-based semiconductor layers, InP-based semiconductor layers, or piezoelectric element layers made of PZT, LN, LT, etc. The layers of functional parts 200, 300, 400, 500, 600, and 700 are not limited to the layers described in the above embodiments, and the functional part may be a functional layer comprising multiple layers. The functional part may have a multilayer structure, which includes semiconductor layers such as nitride-containing semiconductor layers, GaAs-based semiconductor layers, or InP-based semiconductor layers stacked individually or in any combination. The functional unit may also have a multilayer piezoelectric element, which includes piezoelectric layers such as PZT, LN, or LT, either individually or in any combination. Furthermore, the functional unit is not limited to the configuration described in the above embodiments, but may also be configured as an element (e.g., a device) including the configuration described in any of the above embodiments. For example, depending on the device, each of functional layer 102 and functional units 200, 300, 400, 500, 600, and 700 may be configured as an element including electrodes (Schottky electrodes, source electrodes, gate electrodes, or drain electrodes) and an insulating film.

[0375] In the first to seventh embodiments, although the functional layers (AlN layers, GaN layers) formed on the growth substrate are patterned into individual elements (electronic devices) and then transferred to the device substrate, the embodiments are not limited to this example. For example, a functional layer (AlN layer, GaN layer) including multiple elements may be formed on the growth substrate, the functional layer may be transferred to the device substrate, and then the functional layer may be patterned into individual elements.

[0376] Furthermore, in the first to seventh embodiments, although functional units are formed on the growth substrate as electronic devices and then transferred to the device substrate, N (e.g., 4) functional units can also be formed on the growth substrate in a matrix (e.g., 2 rows and 2 columns). In this case, a first metal film can be formed on each of the N functional units, a second metal film that can be bonded to these N functional units can be formed on the device substrate, and the N functional units can be transferred to the second metal film. Additionally, depending on the device, a functional layer 102 and any one of functional units 200, 300, 400, 500, 600, and 700, which are elements of a device structure including electrodes (Schottky electrodes, source electrodes, gate electrodes, or drain electrodes) and insulating films, can be formed on the growth substrate, and then the functional unit can be transferred to the device substrate.

[0377] In the manufacturing method of the electronic device in each of the first to seventh embodiments, a first substrate (e.g., a growth substrate) and a functional portion formed on the first substrate are separated from each other, and a first metal film is deposited on a first surface of the functional portion (i.e., the surface separated from the growth substrate). Then, the first metal film deposited on the first substrate is bonded to a second metal film formed on a second substrate (e.g., a device substrate) different from the first substrate. Therefore, the functional portion can be well bonded from the first substrate, which is different from the second substrate, to the second substrate. Furthermore, in this manufacturing method, it is not necessary to use an expensive GaN substrate as the first substrate (growth substrate), and thus manufacturing costs can be reduced.

[0378] In the above-described method for manufacturing electronic devices, a functional portion and a buffer layer epitaxially grown on a first substrate (e.g., a growth substrate) are separated from the first substrate. The buffer layer is removed from the functional portion, and then a first metal film is deposited on the first surface on which the buffer layer has been removed. Since the buffer layer is removed as described above, the first metal film, serving as an electrode, can be directly formed on the functional portion (e.g., an n+GaN layer), and this first metal film is bonded to a second metal film on a second substrate (e.g., a device substrate). Therefore, a vertically structured GaN device with low resistance, for example, can be realized.

[0379] The preferred embodiments have been described in detail above, but this disclosure is not limited to the above embodiments and various improvements or modifications can be made.

[0380] This disclosure applies to electronic devices such as piezoelectric devices, photoelectric conversion devices (e.g., LED devices), and semiconductor devices (e.g., Schottky barrier diodes, field-effect transistors) and methods of manufacturing thereof.

[0381] Explanation of reference numerals in the attached figures

[0382] 10, 20, 30, 40, 60, 70: Electronic devices; 101, 201, 301, 401, 501, 601, 701: Growth substrate (first substrate); 101a, 201a, 301a, 401a, 501a, 601a, 701a: Sacrificial layers; 102: Functional layer (functional part); 102a, 203a, 303a, 403a, 503a, 603a, 703a: Lower surface (first surface); 10 2b, 203b, 303b, 403b, 503b, 603b, 703b: Side surface (second surface); 110, 210, 310, 410, 510, 610, 710: First metal film; 120, 220, 320, 420, 520, 620, 720: Molding (holding member); 130, 230, 330, 430, 530, 630, 730: Device substrate (second substrate, substrate); 140, 24 0, 340, 440, 540, 640, 740: Second metal film; 200, 300, 400, 500, 600, 700: Functional part; 202, 302, 402, 502, 602, 702: Buffer layer; 203: n+GaN layer (contact layer); 204: n-GaN layer (drift layer); 230: Device substrate; 303: nGaN layer (contact layer); 304: nAlGaN layer (cladding layer); 305: InGaN layer (active layer); 306: pAlGaN layer (cladding layer); 307: pGaN layer (contact layer); 403, 503, 603, 703: n+GaN layer (contact layer); 404, 504, 604, 704: n-GaN layer (drift layer); 405, 505, 605, 705: pGaN layer (contact layer); 406, 506, 606: n+GaN layer; 407, 507, 607: trench.

Claims

1. An electronic device, the electronic device comprising: Functional departments; A substrate that supports the functional unit; A first metal film is deposited as an electrode on the side of the functional part facing the substrate; as well as A second metal film is formed on the substrate and bonded to the first metal film. The functional unit includes: A first surface, the first surface facing the substrate via the first metal film; and A second surface extends from the first surface in a direction different from the extending direction of the first surface. The first metal film is deposited from the first surface of the functional part onto a portion of the second surface.

2. The electronic device according to claim 1, wherein, The functional part has an inclined surface, which is inclined such that the size of the functional part in a plane parallel to the first surface decreases with increasing distance from the first surface. The second surface is the inclined surface.

3. The electronic device according to claim 1 or 2, wherein, The functional unit includes: A contact layer having a first surface and a second surface; and At least one semiconductor layer is formed on the contact layer.

4. The electronic device according to any one of claims 1 to 3, wherein, The first metal film comprises multiple metal layers, and Each of the plurality of metal layers is deposited as a layer covering the side of each layer closer to the functional part.

5. The electronic device according to any one of claims 1 to 4, wherein, The functional part includes a first part and a second part arranged from one side close to the substrate, and The tilt angle of the side of the first part is different from that of the side of the second part.

6. The electronic device according to any one of claims 1 to 5, wherein, The first metal film comprises an Al layer and an Au layer, and A metal barrier layer comprising at least one of Ti, Pt, and Mo is formed between the Al layer and the Au layer.

7. The electronic device according to any one of claims 1 to 6, wherein, The second metal film comprises multiple metal layers.

8. The electronic device according to any one of claims 1 to 7, wherein, The functional part is an epitaxial layer containing nitride.

9. A method for manufacturing an electronic device, the method comprising: A first metal film is deposited from a first surface of a functional portion onto a portion of a second surface, the functional portion having the first surface and a second surface extending from the first surface in a direction different from the extension direction of the first surface; as well as The first metal film deposited on the functional part is bonded together with the second metal film formed on the substrate.

10. The method for manufacturing an electronic device according to claim 9, wherein, The functional part is a functional part separated from the first substrate, which is different from the second substrate that serves as the substrate. The first surface is the surface of the functional part that is separated from the first substrate.

11. The method for manufacturing an electronic device according to claim 10, wherein, Before depositing the first metal film, the functional portion and the buffer layer, which are epitaxially grown on the first substrate via the buffer layer, are separated from the first substrate. Specifically, the buffer layer is removed from the functional unit, and The first metal film is formed on the first surface of the functional part where the buffer layer has been removed.

12. A method for manufacturing an electronic device, the method comprising: Separate the first substrate from the functional parts formed on the first substrate; A first metal film is deposited on a first surface of the functional part, the first surface being a surface separated from the first substrate; as well as The first metal film deposited on the first substrate is bonded to a second metal film formed on a second substrate different from the first substrate.

13. The method for manufacturing an electronic device according to claim 12, wherein, The functional portion epitaxially grown on the first substrate via the buffer layer and the buffer layer are separated from the first substrate, and The buffer layer is removed from the functional part, and then the first metal film is deposited on the first surface where the buffer layer has been removed.

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