Backside molding compound flash suppression trench for exposing die package
By forming molding compound flash suppression trenches on the back side of the semiconductor die, the problem of molding compound encroaching on the non-molding compound area is solved, enabling reliable attachment of components such as heat sinks and improving the heat dissipation performance of the package.
Patent Information
- Application Number
- CN202380100044.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-31
- Filing Date
- 2023-12-29
- Publication Date
- 2026-02-03
AI Technical Summary
In the prior art, semiconductor die packages with exposed back sides are prone to encroaching on the unmolded compound area during the molding compound formation process, making it impossible to directly attach components such as heat sinks.
Trenches are formed on the back side of the semiconductor die to act as reservoirs to prevent molding compounds from encroaching on areas without molding compounds. Molding compound flash is formed by ablation on the back side of the wafer to suppress trenches, ensuring the cleanliness of areas without molding compounds.
It effectively prevents molding compound from entering the non-molding compound area, provides a clean surface for direct attachment of components such as heat sinks, and improves the heat dissipation performance and reliability of the package.
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Figure CN121464754A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the field of semiconductor packaging. More specifically, but not exclusively, the present disclosure relates to packages with backside exposed semiconductor dies. BACKGROUND
[0002] Packages with backside exposed semiconductor dies have become a popular choice for compact high performance integrated circuit packages. Backside exposed packages provide a convenient method of attaching a heat sink to the packaged semiconductor die. Package solutions such as quad flat no-lead (QFN) packages have become a popular choice for compact high performance integrated circuit packages and can be manufactured with backside exposed semiconductor dies. Other package solutions that allow for backside exposed semiconductor dies are also within the scope of the present disclosure. SUMMARY
[0003] A backside exposed semiconductor die package has a plurality of leads surrounding a perimeter of the semiconductor die package, a semiconductor die electrically coupled to the plurality of leads, and a backside of the semiconductor die that is exposed with a mold compound free zone to allow a heat sink or other component to be directly attached to the semiconductor die. An electrically insulative mold compound contacts the plurality of leads and the semiconductor die. A trench on the backside of the semiconductor die prevents the mold compound from encroaching on the mold compound free zone on the backside of the semiconductor die.
[0004] When the semiconductor die is in wafer form, the trench on the backside of the semiconductor die can be formed by ablation on the backside of the wafer. After singulation of the wafer and attachment of the semiconductor die to a leadframe, a backside exposed microelectronic package can be formed using a mold compound that electrically contacts the plurality of leads and all faces of the semiconductor die except for the mold compound free zone on the backside of the semiconductor die. The trench on the backside of the semiconductor die acts as a reservoir to prevent the mold compound from encroaching on the mold compound free zone. After the semiconductor die package is formed on the leadframe, the individual semiconductor dies are singulated and a component such as a heat sink can be subsequently attached to the mold compound free zone of the semiconductor die. BRIEF DESCRIPTION OF DRAWINGS
[0005] Figures 1A-1O are top, cross-sectional, and perspective views of a semiconductor die package with a backside mold compound flash inhibiting trench and a backside mold compound free zone depicted in successive stages of an example formation method. DETAILED DESCRIPTION
[0006] The disclosure is described with reference to the accompanying drawings. The drawings are not drawn to scale and are provided merely to illustrate the disclosure. Several aspects of the disclosure are described below with reference made to examples applications. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the disclosure. The disclosure is not limited to the acts or blocks shown and described, as some acts or blocks can occur in different orders and / or concurrently with other acts or blocks. Furthermore, not all illustrated acts or blocks are required to implement the methods in accordance with the disclosure.
[0007] A semiconductor die package has leads surrounding a perimeter of the semiconductor die package. The leads are attached to a leadframe. A semiconductor die containing a plurality of backside molding compound inhibiting trenches (referred to herein as trenches) is electrically coupled to a plurality of the leads. An electrically insulating molding compound forms the semiconductor die package contacting the plurality of leads and the semiconductor die. The trenches on the backside of the semiconductor die act as reservoirs to prevent the molding compound from encroaching on the molding compound free regions.
[0008] After the semiconductor die package is formed on the leadframe, the individual semiconductor die packages are singulated by sawing through the leads. Singulation by sawing enables the formation of multiple semiconductor die packages simultaneously using the leadframe because the molding compound can be formed on all of the semiconductor die packages in one operation. After singulation, components such as heat spreaders can be subsequently attached to the molding compound free regions of the semiconductor die.
[0009] Note that terms such as top, bottom, above, below, and beneath can be used in this disclosure. These terms are not to be construed as limiting the position or orientation of structures or elements, but should be used to provide a spatial relationship between structures or elements.
[0010] Figures 1A-1L are top, cross-sectional, and perspective views of a semiconductor die package with backside molding compound flash inhibiting trenches depicted in successive stages of an example formation method.
[0011] Reference Figure 1A , a top view of a section of a semiconductor wafer containing a semiconductor die 104 and an adjacent semiconductor die 104a is shown. A dicing lane 106 exists between the semiconductor die 104 and the adjacent semiconductor die 104a. A sawing region 108 in the dicing lane 106 indicates the approximate region between the semiconductor die 104 and the adjacent semiconductor die 104a for sawing. The dicing lane 106 provides space for a saw to saw between the semiconductor die 104 and the adjacent semiconductor die 104a for packaging the semiconductor die 104 and the adjacent semiconductor die 104a. The dicing lane 106 can also contain features such as lithography alignment marks and parametric test structures (not specifically shown) and other features needed for semiconductor wafer fabrication. InFigure 1A A semiconductor die 104 is shown with the backside of the semiconductor wafer facing the viewer. The backside of the semiconductor wafer includes a mold compound free zone 110. The mold compound free zone 110 is an area on the backside 114 of the semiconductor die 104 (see Figure 1C ) that must remain free of mold compound 150 throughout the packaging process to provide a mold compound free zone 110 for certain types of semiconductor packages, i.e., the backside area of the semiconductor package that must be free of mold compound when a heat sink or other component can be subsequently bonded to the backside of the semiconductor die 104 after packaging. The mold compound free zone 110 can be greater than fifty percent of the area of the backside 114 of the semiconductor die 104.
[0012] Referring to Figure 1B , a close-up view of Figure 1A is shown focusing on the semiconductor die 104. An adjacent semiconductor die 104a is also shown. Between the semiconductor die 104 and the adjacent semiconductor die 104a is a scribe lane 106. In the center of the scribe lane 106 is a sawing area 108. As shown in Figure 1A , the backside of the semiconductor wafer faces forward. The semiconductor die 104 has a mold compound free zone 110 that remains free of mold compound during the packaging process. Figure 1C A cross-section of the semiconductor die 104 is shown in
[0013] Referring to Figure 1C , a cross-section of the semiconductor die 104 of Figure 1B is shown while the semiconductor die 104 is still in wafer form. A scribe lane 106 is located between the semiconductor die 104 and an adjacent semiconductor die 104a. In the center of the scribe lane 106 is a sawing area 108. The semiconductor die 104 has a backside 114 and a device side 136. On the backside 114 is a mold compound free zone 110. The mold compound free zone 110 can be greater than fifty percent of the area of the backside 114 of the semiconductor die 104 to allow for components such as heat sinks to be directly bonded to the backside 114 of the semiconductor die 104. A sawing tape 116 is attached to the device side 136 of the semiconductor die 104.
[0014] Referring to Figure 1D , a top view of a semiconductor wafer containing semiconductor dies 104 and adjacent semiconductor dies 104a facing forward is shown. In Figure 1D , the backside of the semiconductor die 104 faces the viewer. Figure 1D The top view of the semiconductor wafer shown in Figure 1HThis is shown at a point previously. After the back-side grinding operation, a plurality of molding compound flash suppression trenches 120 are formed in the back side 114 of the semiconductor die 104 between the scribe line 106 and the unmolded compound region 110. The plurality of molding compound flash suppression trenches 120 are also formed in adjacent semiconductor dies 104a. The molding compound flash suppression trenches 120 are formed by ablation of the material from the back side of the semiconductor die 104 using a laser or similar technique, or by using a partial sawing method. The molding compound flash suppression trenches 120 have a trench depth 126 and a trench width 124 (see [link to documentation]). Figure 1F ). Figure 1D The example illustrates a series of molded compound flash suppression trenches 120 perpendicular to each other, wherein one or more of the plurality of molded compound flash suppression trenches 120 on the back side 114 of the semiconductor die 104 intersect and form a continuous trench region surrounding the unmolded compound region 110. Molded compound flash suppression trenches 120 at angles other than perpendicular, and molded compound flash suppression trenches 120 having a geometry that causes one or more of the plurality of molded compound flash suppression trenches 120 to be discontinuous and non-intersecting around the unmolded compound region 110 (e.g., Figure 1E (As shown) is also within the scope of this disclosure.
[0015] Figure 1F Is it through Figure 1D The cross-section of semiconductor die 104. Figure 1F The cross-section shown is after the back-side grinding operation (not specifically shown) during the packaging process, after the formation of the molding compound flash suppression trench 120, and during the wafer sawing operation (see [link]). Figure 1H (As shown at a previous point.) The device side 136 of the semiconductor die 104 is attached to the saw blade 116. The dicing track 106 is located between the semiconductor die 104 and the adjacent semiconductor die 104a. The sawing area 108 is located near the center of the dicing track 106. Figure 1E The cross-sectional view also shows the unmolded compound region 110. The unmolded compound region 110 is located on the back side 114 of the semiconductor die 104. The unmolded compound region 110 is larger than 50% or more of the area of the back side 114 of the semiconductor die 104. An unmolded compound region 110 larger than 50% of the area of the back side 114 of the semiconductor die 104 is advantageous because it provides for the absence of subsequently formed molding compound 150 (see reference). Figure 1K Sufficient area to provide a clean surface for subsequent bonding of components such as heat sink 168 (refer to Figure N and Figure 1O ).
[0016] Molded compound flash suppression trenches 120 are formed on the back side 114 of semiconductor die 104 between the scribe line 106 and the outer periphery of the unmolded compound region 110. The molded compound flash suppression trenches 120 have a trench width 124 and a trench depth 126. The trench width 124 is 0.1 micrometers or greater. The trench depth 126 is greater than 0.1 micrometers. The molded compound suppression trenches can be formed using a laser ablation process 122. The trench width 124 and trench depth 126 can be changed by adjusting the laser energy or laser dwell time of the laser ablation process 122. Multiple passes of the laser ablation process 122 may be required to achieve the desired trench width 124 and trench depth 126. The molded compound flash suppression trenches 120 can also be formed by a partial sawing process (not specifically shown). The trench depth 126 is less than the thickness of the bulk material of the wafer and does not reach a depth that would allow it to intersect with the active semiconductor die 104.
[0017] Figure 1G This is a cross-sectional view of a serrated molding compound flash suppression groove 120, a vertical-walled molding compound flash suppression groove 120a, and a U-shaped molding compound flash suppression groove 120b. Other cross-sectional geometries of the molding compound flash suppression grooves are also within the scope of this disclosure. The serrated molding compound flash suppression groove 120 has a groove width of 124 and a groove depth of 126. The serrated molding compound flash suppression groove 120 profile can be formed by using an ablation process in multiple passes. The vertical-walled molding compound flash suppression groove 120a has vertical sidewalls and a flat bottom, as well as a groove width of 124 and a groove depth of 126. The vertical-walled molding compound flash suppression groove 120a profile can be formed when a sawing process is used to form the vertical-walled molding compound flash suppression groove 120a. The U-shaped molding compound flash suppression groove 120b has a U-shaped profile. If a single-pass ablation method is used to form the U-shaped molding compound flash suppression groove 120b, the contour of the U-shaped molding compound flash suppression groove 120b can be formed.
[0018] Figure 1H This is a top view of semiconductor die 104 and adjacent semiconductor die 104a after wafer dicing. Figure 1I After cutting the order Figure 1H Cross-sections of semiconductor die 104 and adjacent semiconductor die 104a. (Reference) Figure 1H and Figure 1Isemiconductor die 104 and adjacent semiconductor die 104a are removed from saw tape 116 and bonded to leadframe 144 as discussed in Figure 1J and Figure 1K Although the examples in Figure 1H and Figure 1I are directed to singulation by sawing, other singulation methods are within the scope of the present disclosure.
[0019] Figure 1J is a top view of semiconductor package 100, and Figure 1K is a cross-section of semiconductor package 100 after semiconductor die 104 is sawn from a semiconductor wafer and mounted on leadframe 144 Figure 1J Leadframe 144 can contain adjacent semiconductor packages (not specifically shown). Semiconductor package 100 includes a plurality of leads 146 as part of leadframe 144.
[0020] As shown in Figure 1K device side 136 of semiconductor die 104 is attached to the plurality of leads 146 of leadframe 144 via conductive die-to-leadframe bonding material 148. Mold compound 150 is formed on leadframe 144, including contacting the plurality of leads 146, portions of semiconductor die 104, and on conductive die-to-leadframe bonding material 148. In this example, mold compound 150 is formed between bottom mold plate 154 and top mold plate 152. In this example, a top compressible release film 156 is located between top mold plate 152 and a bottom surface of semiconductor die 104. A bottom compressible release film 158 is located between bottom mold plate 154 and a bottom surface of the plurality of leads 146. Mold compound 150 is electrically insulating. Top compressible release film 156 between backside 114 of semiconductor die 104 and top mold plate 152 does not provide a seal sufficient to prevent mold compound 150 from leaking onto backside 114 of semiconductor die 104. It is advantageous to add mold compound flash containment trench 120 to backside 114 of semiconductor die 104 to prevent mold compound 150 from impinging on mold compound free zone 110. As shown in Figure 1JThe molding compound flash inhibiting trenches 120 on the backside 114 of the semiconductor die 104 shown form a continuous trench between the outer periphery of the semiconductor die 104 and the molding compound free region 110. Molding compound flash inhibiting trenches 120 that do not intersect each other, as shown in Figure 1E are also within the scope of the present disclosure. As shown in Figure 1K After the molding compound has been formed between the top mold plate 152 and the bottom mold plate 154, the molding compound flash inhibiting trenches 120 advantageously provide a reservoir for any molding compound 150 that can extend beyond the outer periphery of the semiconductor die 104 toward the molding compound free region 110 between the top compressible release film 156 and the backside 114 of the semiconductor die 104. While the molding compound flash inhibiting trenches 120 can be filled with molding compound 150 in some areas and residual molding compound 160 can extend beyond the molding compound flash inhibiting trenches 120 in some areas, the void volume of the molding compound flash inhibiting trenches 120 prevents the residual molding compound 160 from impinging into the molding compound free region 110. After the semiconductor package 100 is formed, the semiconductor package 100 is singulated (not specifically shown) from adjacent semiconductor packages 100.
[0021] Figure 1L is a perspective view of the semiconductor package 100 containing the molding compound flash inhibiting trenches 120 after singulation. Figure 1L The semiconductor package 100 shown in Figure 1M is a quad flat no-lead (QFN) package in which the backside 114 of the semiconductor die 104 is exposed. Figure 1L is a cross-sectional view of the semiconductor package 100 shown in Figure 1L and Figure 1M The molding compound free region 110 on the backside 114 of the semiconductor die 104 is free of molding compound 150. While the molding compound free region 110 is free of molding compound 150, in some areas the molding compound flash inhibiting trenches 120 can be filled with molding compound 150 and residual molding compound 160 can be present on the backside 114 of the semiconductor die 104 between the molding compound free region 110 and the molding compound flash inhibiting trenches 120. The molding compound flash inhibiting trenches 120 keep the molding compound free region 110 completely free of molding compound 150, allowing for subsequent direct bonding of a heat sink or other element to the backside 114 of the semiconductor die 104. Other areas of the molding compound flash inhibiting trenches 120 are not completely filled with molding compound 150. The leadframe 144 is connected to the device side 136 of the semiconductor die 104 via the die-to-leadframe bonding material 148.
[0022] Reference is made to Figure 1N andFigure 1O , Figure 1N A perspective view of the semiconductor package 100 shown in Figure 1L and Figure 1M is shown after the heat spreader 168 has been attached to the semiconductor package 100. Figure 1N A perspective view of the semiconductor package 100 shown in Figure 1N is shown after the heat spreader 168 has been attached to the semiconductor package 100. Figure 1O is Figure 1N is shown after the heat spreader 168 has been attached to the semiconductor package 100. Figure 1O Referring to
[0023] While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present disclosure should not be limited by any of the above described embodiments, but should be defined in accordance with the following claims and their equivalents.
Claims
1. A semiconductor package comprising: Multiple leads surround the perimeter of the semiconductor package; A semiconductor die electrically coupled to the plurality of leads, the semiconductor die comprising a device side and a back side; Multiple trenches on the back side of the semiconductor die; A molding compound, the portion of which contacts the plurality of leads and the semiconductor die, and A moldless compound region, located on the back side of the semiconductor die between the plurality of trenches, wherein the moldless compound region is free of the molding compound.
2. The semiconductor package of claim 1, wherein one or more of the plurality of trenches on the back side of the semiconductor die intersect with another of the plurality of trenches.
3. The semiconductor package of claim 1, wherein one or more of the plurality of trenches on the back side of the semiconductor die do not intersect with another of the plurality of trenches.
4. The semiconductor package of claim 1, wherein the unmolded compound region on the back side of the semiconductor die is greater than 50 percent of the area of the back side of the semiconductor die.
5. The semiconductor package of claim 1, wherein the depth of the plurality of trenches on the back side of the semiconductor die is greater than 0.1 micrometers.
6. The semiconductor package of claim 1, wherein the width of the plurality of trenches on the back side of the semiconductor die is greater than 0.1 micrometers.
7. The semiconductor package of claim 1, wherein one or more of the plurality of trenches on the back side of the semiconductor die are perpendicular to adjacent trenches.
8. The semiconductor package of claim 1, wherein the molding compound extends across one or more of the plurality of trenches on the back side of the semiconductor die, but does not extend into the unmolded compound region.
9. The semiconductor package of claim 1, wherein the plurality of trenches are located between the outer periphery of the semiconductor die and the outer periphery of the unmolded compound region.
10. The semiconductor package of claim 1, further comprising a heat sink, the heat sink being attached to the back side of the semiconductor die in the unmolded compound region using a heat sink attachment material.
11. A method for forming a semiconductor package, comprising: Multiple trenches are formed on the back side of the semiconductor wafer; The semiconductor wafer is diced into multiple semiconductor dies, each semiconductor die containing one or more of the multiple trenches; Electrically couple the semiconductor die to a plurality of leads that extend to the perimeter of the semiconductor package; as well as A molding compound is formed on the plurality of leads and the semiconductor die, wherein the molding compound does not extend into the unmolded compound region between the plurality of trenches on the back side of the semiconductor die, and the molding compound is electrically insulating.
12. The method of claim 11, wherein one or more of the plurality of trenches are formed by an ablation process.
13. The method of claim 11, wherein one or more of the plurality of grooves are formed using a sawing process.
14. The method of claim 11, wherein the depth of the plurality of trenches is greater than 0.1 micrometers.
15. The method of claim 11, wherein the width of the plurality of trenches is greater than 0.1 micrometers.
16. The semiconductor package of claim 11, wherein the plurality of trenches intersect with adjacent trenches and form a continuous trench around the unmolded compound region.
17. The method of claim 11, wherein one or more of the plurality of trenches do not intersect with another of the plurality of trenches.
18. The method of claim 11, wherein one or more of the plurality of trenches are formed perpendicular to adjacent trenches.
19. The method of claim 11, wherein the molding compound extends across one or more of the plurality of trenches, but does not extend into the region without molding compound.
20. The semiconductor package of claim 11, wherein the plurality of trenches are formed between the outer periphery of the semiconductor die and the outer periphery of the unmolded compound region.