An organic semiconductor vertical heterojunction single crystal array and a preparation method thereof

Abstract

The application provides an organic semiconductor longitudinal heterojunction monocrystal array and a preparation method thereof, and the preparation method comprises the following steps: providing a first silicon column template, a second silicon column template and a substrate; the first silicon column template and the second silicon column template are respectively provided with a first silicon column array and a second silicon column array, and the first silicon column template, the second silicon column template and the substrate are respectively provided with a first alignment mark, a second alignment mark and a third alignment mark; based on the melting point difference of different organic semiconductor systems, a longitudinal heterojunction monocrystal array with a determined crystal orientation and a controllable structure size is prepared through step-by-step melting, directional crystallization and alignment control. Compared with the traditional longitudinal heterojunction which is usually prepared layer by layer by using a solution method, the solvent is easy to damage the first layer of crystals when the second layer of crystals is formed, the step-by-step crystallization is realized by using the melting point difference in the application, the influence of the solvent on the first layer of crystals is avoided, and the application has the advantages of high controllability, good stability and strong applicability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to an organic semiconductor vertical heterojunction single crystal array and its preparation method. Background Technology

[0002] A heterojunction is an interface structure formed by the contact of two different semiconductor materials. Its core characteristics are band alignment and built-in potential at the interface, which can effectively control the injection, separation, and transport behavior of charge carriers. As one of the most crucial structural units in optoelectronic devices, heterojunctions achieve efficient energy and charge management through this interface barrier. In the field of inorganic semiconductors, heterojunction technology has been widely used in devices such as transistors, solar cells, light-emitting diodes, and photodetectors, significantly improving the response efficiency and stability of these devices. In contrast, organic semiconductor materials, due to their advantages such as designable molecular structures, flexibility, and low-cost processing, show unique potential in realizing lightweight, wearable, and large-area optoelectronic devices. In particular, organic semiconductor single crystals, with their highly ordered molecular packing and extremely low defect density, outperform polycrystalline or thin-film structures in terms of carrier mobility, optical response, and interface quality, making them ideal materials for constructing high-performance organic heterojunction devices.

[0003] The fabrication of existing organic semiconductor single-crystal heterojunctions typically relies on molecular structure design or specific interfacial interactions. By controlling molecular coplanarity, terminal substituents, or energy level matching, epitaxial growth or self-assembly can be achieved to form heterojunctions. However, such methods are often only applicable to specific molecular systems, have strict requirements on lattice matching, interfacial energy levels, and solvent conditions, and have poor material universality. At the same time, multi-step epitaxial or transfer processes are prone to interfacial contamination, inconsistent crystal orientation, or structural damage, making it difficult to achieve high-precision array integration. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide an organic semiconductor vertical heterojunction single crystal array and its preparation method. By utilizing the melting point differences of different organic materials, a high-quality heterojunction is constructed through stepwise melting and directional crystallization.

[0005] To achieve this objective, the present invention adopts the following technical solution:

[0006] In a first aspect, the present invention provides a method for fabricating a vertical heterojunction single-crystal array of an organic semiconductor. The method includes: providing a first silicon pillar template, a second silicon pillar template, and a substrate; the first silicon pillar template includes a first template body, on which at least one first silicon pillar array is disposed, the first silicon pillar array comprising a plurality of first silicon pillars arranged in an array; the second silicon pillar template includes a second template body, on which at least one second silicon pillar array is disposed, the second silicon pillar array comprising a plurality of second silicon pillars arranged in an array; the first silicon pillar array and the second silicon pillar array are spatially symmetrically arranged; a plurality of injection vias are formed on the substrate, the plurality of injection vias being sequentially arranged at the same end of the substrate; a first alignment mark, a second alignment mark, and a third alignment mark are respectively disposed on the first template body, the second template body, and the substrate; the substrate is placed over the first silicon pillar template, the third alignment mark is aligned with the first alignment mark, and the substrate is then aligned with the first alignment mark. The substrate is pressurized to bring it close to the first silicon pillar template, with at least a portion of the filling vias corresponding one-to-one with one end of the first silicon pillar. A first organic powder is added into the filling vias, and a first melting process is performed to form a first single-crystal micron-line array between several of the first silicon pillars and the substrate. The first silicon pillar template is then removed. The substrate with the first single-crystal micron-line array is placed over the second silicon pillar template, bringing the first single-crystal micron-line array close to the second silicon pillar template. The third alignment mark is aligned with the second alignment mark. The substrate is pressurized to bring it close to the second silicon pillar template, with at least a portion of the filling vias corresponding one-to-one with one end of the second silicon pillar. A second organic powder is added into the filling vias, and a second melting process is performed to form a second single-crystal micron-line array between several of the second silicon pillars and the first single-crystal micron-line array. The second silicon pillar template is then removed to obtain a vertical heterojunction single-crystal array. The glass transition temperature of the first organic powder is greater than the glass transition temperature of the second organic powder.

[0007] This invention employs a melting method and utilizes silicon pillar templates with special morphology and periodic structure to control the directional transport of the melt. Through a two-stage alignment process, it achieves precise control over the position and size of the two vertical crystal layers, breaking the dependence on molecular structure and lattice matching. Based on the melting point differences between different materials, it forms a low-defect, highly oriented single-crystal interface through stepwise melting and directional crystallization, thereby realizing the fabrication of a high-density, highly crystallizable organic semiconductor single-crystal vertical heterojunction patterned array.

[0008] As a preferred embodiment of the present invention, a first alignment mark located on the first template body and a second alignment mark located on the second template body are respectively provided, and the first alignment mark and the second alignment mark have the same shape and size.

[0009] In one embodiment of the present invention, in a first direction, the linear length of the first silicon pillar is greater than or equal to the linear length of the second silicon pillar; the first direction is the arrangement direction of the first silicon pillar or the second silicon pillar.

[0010] As one embodiment of the present invention, the linear lengths of the first silicon pillar and the second silicon pillar in the first direction are independently 1 to 10000 μm, for example, they can be 1 μm, 5 μm, 10 μm, 100 μm, 500 μm, 1000 μm, 2000 μm, 3000 μm, 5000 μm or 10000 μm, but are not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0011] As one embodiment of the present invention, the spacing between two adjacent first silicon pillars is 1 to 100 μm, for example, it can be 1 μm, 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm or 100 μm, but is not limited to the listed values, other unlisted values ​​within this range are also applicable.

[0012] As one embodiment of the present invention, the spacing between two adjacent second silicon pillars is 1 to 100 μm, for example, it can be 1 μm, 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm or 100 μm, but is not limited to the listed values, other unlisted values ​​within this range are also applicable.

[0013] As a preferred technical solution of the present invention, the first silicon pillar template and the second silicon pillar template are respectively subjected to asymmetric wetting modification, so that the top surface of the first silicon pillar and the second silicon pillar away from the first mold body and the second mold body is hydrophilic, while the side wall surface is hydrophobic.

[0014] The wettability treatment of the present invention is an asymmetric wettability treatment process based on different regions of the first silicon pillar or the second silicon pillar, which realizes the control of the width of the formed melt to obtain a single crystal array structure with controllable size and precise position.

[0015] As a preferred embodiment of the present invention, the first alignment mark, the second alignment mark, and the third alignment mark are all identical in shape and size.

[0016] As one embodiment of the present invention, the substrate material includes at least one of glass, quartz, silicon, or silicon with a silicon oxide layer deposited on it.

[0017] As one embodiment of the present invention, the plurality of injection vias include at least two first injection vias and at least two second injection vias. The first injection vias and the second injection vias are alternately and sequentially disposed at the same end of the substrate. The first injection vias correspond one-to-one with the first silicon pillars, and the second injection vias correspond one-to-one with the second silicon pillars.

[0018] In one embodiment of the present invention, the first filling through hole and the second filling through hole are arranged side by side, or the orthographic projection of the first filling through hole on the vertical plane does not coincide with the orthographic projection of the second filling through hole on the vertical plane, or at least part of the orthographic projection of the first filling through hole on the vertical plane coincides with the orthographic projection of the second filling through hole on the vertical plane.

[0019] In one embodiment of the present invention, the diameter of the first filling via is smaller than the first length, where the first length is the sum of the linear length of the first silicon pillar in the first direction and the distance between two adjacent first silicon pillars. The diameter of the second filling via is smaller than the second length, where the second length is the sum of the linear length of the second silicon pillar in the first direction and the distance between two adjacent second silicon pillars.

[0020] As a preferred embodiment of the present invention, the glass transition temperature of the first organic powder is lower than its own decomposition temperature, and the glass transition temperature of the second organic powder is lower than its own decomposition temperature.

[0021] The glass transition temperatures of both the first organic powder and the second organic powder are lower than the melting point of the substrate, and the glass transition temperatures of both the first organic powder and the second organic powder are lower than the melting points of the first silicon pillar template and the second silicon pillar template.

[0022] As a preferred embodiment of the present invention, the first melting process includes: adding the first organic powder to the filling through hole and then performing a heating treatment, and continuously applying pressure to melt the first organic powder and spread it along the surface of the first silicon pillar, and then performing a cooling treatment to form the first single crystal micron array between the plurality of first silicon pillars and the substrate.

[0023] The secondary melting process includes: adding the second organic powder to the filling through hole and then performing a secondary heating process, while continuously applying pressure to melt the second organic powder and spread it along the surface of the second silicon pillar, followed by a secondary cooling process to form the second single-crystal micron array between several second silicon pillars and the first single-crystal micron array.

[0024] As one embodiment of the present invention, the applied pressure is adjusted to achieve thickness adjustment of the first single-crystal micron-line array and the second single-crystal micron-line array.

[0025] As one embodiment of the present invention, after the pressure application is terminated, the distance between the first silicon pillar or the second silicon pillar and the substrate is less than or equal to 1000 nm.

[0026] As a preferred embodiment of the present invention, the first heating process includes: first heating to a first temperature to melt the first organic powder, then holding the temperature and applying pressure to make the melted first organic powder form a melt that covers the surface of the first silicon pillar near the substrate.

[0027] The secondary heating process includes: first heating to a second temperature to melt the second organic powder, then holding the temperature for a second time and continuously applying pressure, so that the melted second organic powder forms a melt that covers the surface of the second silicon pillar near the first single-crystal micron array.

[0028] In one embodiment of the present invention, both the primary cooling and the secondary cooling include sequentially performing a first-stage cooling and a second-stage cooling, and the cooling rate of the first-stage cooling is less than the cooling rate of the second-stage cooling.

[0029] As a preferred embodiment of the present invention, the heating rates of the first heating and the second heating are independently 1~20℃ / min, for example, they can be 1℃ / min, 2℃ / min, 3℃ / min, 5℃ / min, 8℃ / min, 10℃ / min, 12℃ / min, 15℃ / min, 16℃ / min, 18℃ / min or 20℃ / min, but are not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0030] In one embodiment of the present invention, the first temperature is greater than the glass transition temperature of the first organic powder and less than the thermal decomposition temperature of the first organic powder. The second temperature is greater than the glass transition temperature of the second organic powder and less than the thermal decomposition temperature of the second organic powder, and simultaneously less than the glass transition temperature of the first organic powder.

[0031] As one embodiment of the present invention, the time for the first heat preservation and the second heat preservation are each independently 5 to 60 minutes, for example, 5 minutes, 10 minutes, 15 minutes, 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes or 60 minutes, but are not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0032] As one embodiment of the present invention, the cooling rate of the cooling segment is 0.1~1.0℃ / min, for example, it can be 0.1℃ / min, 0.2℃ / min, 0.3℃ / min, 0.4℃ / min, 0.5℃ / min, 0.6℃ / min, 0.7℃ / min, 0.8℃ / min, 0.9℃ / min or 1.0℃ / min, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0033] The cooling rate of the two-stage cooling is 1~10℃ / min, for example, it can be 1℃ / min, 2℃ / min, 3℃ / min, 4℃ / min, 5℃ / min, 6℃ / min, 7℃ / min, 8℃ / min, 9℃ / min or 10℃ / min, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0034] This invention regulates the crystallization process of the melt by precisely controlling the heating and cooling rates, ensuring that the melt spreads evenly and directionally on the silicon pillar surface, reducing crystal defects and increasing single crystal density.

[0035] In a second aspect, the present invention provides an organic semiconductor vertical heterojunction single crystal array, wherein the organic semiconductor vertical heterojunction single crystal array is fabricated using the method for fabricating an organic semiconductor vertical heterojunction single crystal array described in the first aspect. The organic semiconductor vertical heterojunction single crystal array includes a substrate, on which a plurality of first single crystal micrometer lines are arranged in an array. A second single crystal micrometer line is disposed on the side of the first single crystal micrometer line away from the substrate. The first single crystal micrometer line and the second single crystal micrometer line are coaxially arranged, and the glass transition temperature of the first single crystal micrometer line is higher than that of the second single crystal micrometer line.

[0036] As a preferred embodiment of the present invention, the height ratio of the first single-crystal micron wire to the second single-crystal micron wire is 1:(0.01~100), for example, it can be 1:0.01, 1:0.05, 1:0.1, 1:0.5, 1:1, 1:10, 1:20, 1:30, 1:40, 1:50, 1:60, 1:70, 1:80, 1:90 or 1:100, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0037] In one embodiment of the present invention, the width of the first single-crystal micrometer wire is greater than the width of the second single-crystal micrometer wire.

[0038] As one embodiment of the present invention, the ratio of the width of the first single-crystal micron wire to the width of the second single-crystal micron wire is 1:(1~100), for example, it can be 1:1, 2:1, 5:1, 10:1, 20:1, 30:1, 40:1, 50:1, 60:1, 70:1, 80:1, 90:1 or 100:1, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0039] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0040] (1) Based on the difference in melting point of different semiconductor systems, this invention realizes the preparation of high-quality single-crystal heterojunction patterned arrays through step-by-step melting and directional crystallization. It has the advantages of strong universality, simple process, high interface quality of heterojunction array obtained, and good array controllability. It provides a universal and scalable new way to construct high-quality heterojunctions between different organic semiconductor materials, and lays the foundation for the integrated manufacturing of high-performance organic optoelectronic devices.

[0041] (2) The present invention designs a silicon pillar template with a special structure, induces the directional spreading of organic semiconductor melt through capillary liquid bridge, and uses a two-step alignment melting method to obtain a patterned array of organic semiconductor single crystal heterojunction with high density, uniform size and high crystallinity.

[0042] (3) In the melting process, the molecules are fully rearranged in the liquid state, avoiding the influence of solvent molecules, thus ensuring the quality of the crystal and forming a single crystal interface with low defects and high orientation. At the same time, the auxiliary template guides and precise temperature control regulates the position, size and orientation of the crystal, preventing damage caused by solvent action and artificial transfer, and also avoiding the damage caused by organic solvents to the human body and the environment. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of the substrate covering the first silicon pillar template in Embodiment 1 of the present invention.

[0044] Figure 2 This is a schematic diagram of the structure of a substrate with a first single-crystal micron-line array covering a second silicon pillar template in Embodiment 1 of the present invention.

[0045] Figure 3 An optical microscope image of an organic semiconductor longitudinal heterojunction single crystal array provided in Embodiment 1 of the present invention.

[0046] Figure 4 This is a schematic diagram of the structure of an organic phototransistor device provided as an application example of the present invention.

[0047] Figure 5 The transfer curves of the organic phototransistor device provided as an application example of the present invention under darkness and different lighting conditions.

[0048] Figure 6 An optical microscope image of an organic semiconductor longitudinal heterojunction single crystal array provided in Embodiment 2 of the present invention.

[0049] Figure 7 An optical microscope image of an organic semiconductor longitudinal heterojunction single crystal array provided in Embodiment 3 of the present invention.

[0050] Figure 8 An atomic force microscope image of an organic semiconductor longitudinal heterojunction single crystal array provided in Embodiment 4 of the present invention.

[0051] Wherein, 1-first silicon pillar template; 11-first template body; 12-first alignment mark; 13-first silicon pillar array; 131-first silicon pillar; 2-second silicon pillar template; 21-second template body; 22-second alignment mark; 23-second silicon pillar array; 231-second silicon pillar; 3-substrate; 31-substrate body; 32-third alignment mark; 33-filling via. Detailed Implementation

[0052] It should be understood that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0053] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0054] In one specific embodiment, the present invention provides a method for fabricating an organic semiconductor vertical heterojunction single-crystal array, the method comprising:

[0055] S1: Provides a first silicon pillar template, a second silicon pillar template, and a substrate.

[0056] The first silicon pillar template includes a first template body, on which at least one first silicon pillar array is disposed, the first silicon pillar array including a plurality of first silicon pillars arranged in an array; the second silicon pillar template includes a second template body, on which at least one second silicon pillar array is disposed, the second silicon pillar array including a plurality of second silicon pillars arranged in an array; the first silicon pillar array and the second silicon pillar array are spatially symmetrical.

[0057] The substrate has a plurality of injection through holes, which are arranged sequentially at the same end of the substrate. The plurality of injection through holes may be identical or partially identical.

[0058] The first template, the second template, and the substrate are respectively provided with a first alignment mark, a second alignment mark, and a third alignment mark.

[0059] It should be noted that the spatial symmetry setting described in this invention means that after the first silicon pillar template and the second silicon pillar template are stacked, the first silicon pillar and the second silicon pillar have the same distribution, the same number, and corresponding positions, and their center lines are vertically aligned, that is, the first silicon pillar and the second silicon pillar are coaxial.

[0060] Specifically, the first and second mold modules are identical in shape and size. Both the first and second mold modules can be cuboid structures. A plurality of the first silicon pillars can be arranged along the length of the first mold module and extend along its width, or vice versa. Similarly, a plurality of the second silicon pillars can be arranged along the length of the second mold module and extend along its width, or vice versa. The first and second silicon pillars have the same distribution pattern and orientation, and their positions on the respective mold modules correspond one-to-one. The spacing between two adjacent first silicon pillars and two adjacent second silicon pillars is the same, specifically 1~100μm.

[0061] The arrangement direction of the first silicon pillar or the second silicon pillar is denoted as the first direction, and the linear length of the first silicon pillar is greater than or equal to the linear length of the second silicon pillar. Specifically, the linear lengths of the first silicon pillar and the second silicon pillar in the first direction are independently 1~10000μm.

[0062] In this invention, the first silicon pillar template and the second silicon pillar template are prepared by photolithography and plasma etching methods. The preparation steps include sequential spin coating of photoresist, pre-baking, exposure, development, rinsing, post-baking, plasma etching, and photoresist removal. This invention does not specifically limit the operation steps and process parameters of the above processes.

[0063] A first alignment mark on the first template body and a second alignment mark on the second template body are correspondingly arranged, and the first alignment mark and the second alignment mark have the same shape and size. In this invention, the first alignment mark is usually set in the blank area on the first template body other than the first silicon pillar array, and similarly, the second alignment mark is usually set in the blank area on the second template body other than the second silicon pillar array. This invention does not specifically limit the shape and size of the first alignment mark and the second alignment mark, and those skilled in the art can adjust them according to the actual situation.

[0064] It should be noted that the first alignment mark and the second alignment mark are set to correspond to each other, meaning that after the first silicon pillar template and the second silicon pillar template are stacked, the first alignment mark and the second alignment mark are aligned vertically, and their orthographic projections on the horizontal plane coincide. Furthermore, the dimensions mentioned in this invention include geometric dimensions such as length, width, thickness, and area.

[0065] In some embodiments, the preparation method of the present invention further includes: performing asymmetric wetting treatment on the provided first silicon pillar template and second silicon pillar template respectively, such that the top surface of the first silicon pillar away from the first template body is hydrophilic, while the sidewall surface is hydrophobic, and the top surface of the second silicon pillar away from the second template body is hydrophilic, while the sidewall surface is hydrophobic. In the present invention, the hydrophilicity of the top surfaces of the first and second silicon pillars away from the template body facilitates the directional flow of the melt along the silicon pillars until it covers their entire surface. The hydrophobicity of the sidewall surfaces of the first and second silicon pillars prevents lateral diffusion of the melt, which could lead to uncontrollable changes in the size and morphology of the melt, and also reduces cross-contamination. It should be noted that the sidewall surface mentioned in the present invention refers to the surface other than the surface of the first or second silicon pillar near the substrate and the surface near the first or second template body, specifically including the wall surfaces of two adjacent first silicon pillars on opposite sides or two adjacent second silicon pillars on opposite sides.

[0066] The substrate described in this invention includes a substrate body, and the material includes at least one of glass, quartz, silicon, or silicon with a silicon oxide layer deposited on it.

[0067] In some embodiments, for different silicon pillar arrays, a plurality of injection vias are provided, including at least two first injection vias and at least two second injection vias. The first injection vias and the second injection vias are alternately and spaced at the same end of the substrate. The first injection vias correspond one-to-one with the first silicon pillars and are the same in number. The second injection vias correspond one-to-one with the second silicon pillars and are the same in number.

[0068] Specifically, the first filling through hole and the second filling through hole are arranged side by side, or the orthographic projection of the first filling through hole on the vertical plane does not coincide with the orthographic projection of the second filling through hole on the vertical plane, or at least part of the orthographic projection of the first filling through hole on the vertical plane coincides with the orthographic projection of the second filling through hole on the vertical plane.

[0069] When the orthographic projection of the first filling through hole on the vertical plane does not coincide with the orthographic projection of the second filling through hole on the vertical plane, the first filling through hole can be set closer to the edge of the substrate, that is, the second filling through hole is set further forward than the first filling through hole.

[0070] The diameter of the first filling via is smaller than the first length, which is the sum of the linear length of the first silicon pillar in the first direction and the distance between two adjacent first silicon pillars. The diameter of the second filling via is smaller than the second length, which is the sum of the linear length of the second silicon pillar in the first direction and the distance between two adjacent second silicon pillars.

[0071] When this invention is used in thin-film transistors, at least one coating layer can be formed on the surface of the substrate near the silicon pillar template. Specifically, the material of the coating layer includes, but is not limited to, silicon oxide, aluminum oxide, hafnium oxide, etc.

[0072] In this invention, the first alignment mark, the second alignment mark, and the third alignment mark are all the same in shape and size, so as to ensure that the third alignment mark is aligned point-to-point with the first alignment mark and the second alignment mark respectively in the subsequent preparation process, so that the injection via corresponds to the end of the top surface of the first silicon pillar or the second silicon pillar respectively.

[0073] S2: Cover the substrate over the first silicon pillar template, align the third alignment mark with the first alignment mark point-to-point, apply pressure to the substrate to bring it close to the first silicon pillar template, at least some of the injection vias correspond one-to-one with one end of the first silicon pillar, add the first organic powder into the injection vias, and perform a melting process to form a first single-crystal micron-line array in the gaps between several first silicon pillars and the substrate, and then remove the first silicon pillar template.

[0074] Specifically, the first melting process includes: adding the first organic powder to the filling through hole and then heating it once, while continuously applying pressure to melt the first organic powder and spread it along the surface of the first silicon pillar, followed by cooling to form the first single-crystal micron-line array in the gap between several first silicon pillars and the substrate.

[0075] In this invention, the first organic powder includes, but is not limited to, at least one of C8-BTBT, C10-BTBT, DPA, C6-DPA, DNTT, C10-DNTT, C8-NTDA, PDI8-CN2, and DFHCO-4T. The glass transition temperature of the first organic powder is lower than its own decomposition temperature and lower than the melting point of the substrate, and also lower than the melting points of the first silicon ingot template and the second silicon ingot template.

[0076] In some embodiments, the first heating process includes: first heating to a first temperature to melt the first organic powder, then holding the temperature and applying pressure again, so that the melted first organic powder forms a melt that covers the surface of the first silicon pillar near the surface of the substrate to form a first single-crystal microwire.

[0077] Specifically, the heating rate for the first heating step is 1~20℃ / min, and the first temperature is greater than the glass transition temperature of the first organic powder and less than the thermal decomposition temperature of the first organic powder. The holding time for the first heating step is 5~60min. During the first heating step, the melt formed by the melting of the first organic powder spreads along the first silicon pillars until it covers all the first silicon pillars, and the multiple melt pillars formed constitute the first single-crystal micron-line array.

[0078] In some embodiments, the primary cooling includes sequentially performing a first-stage cooling and a second-stage cooling, wherein the cooling rate of the first-stage cooling is less than the cooling rate of the second-stage cooling.

[0079] Specifically, the cooling rate of the first stage of cooling is 0.1~1℃ / min, and the cooling rate of the second stage of cooling is 1~10℃ / min.

[0080] In some embodiments, the present invention adjusts the applied pressure to regulate the height of the molten bridge formed on the surface of the first silicon pillar, thereby adjusting the thickness of the first single-crystal micron-line array. After the pressure is applied, the distance between the first silicon pillar and the substrate is less than or equal to 1000 nm. Since the first single-crystal micron-line array is formed between the top surface of the first silicon pillar and the substrate, the distance between the top surface of the first silicon pillar and the substrate can be controlled by adjusting the applied pressure, thereby obtaining a product with the desired thickness.

[0081] The present invention performs the substrate covering process under a microscope, and the microscope is equipped with a three-dimensional moving platform to ensure that the third alignment mark and the first alignment mark can be aligned point-to-point.

[0082] S3: Cover the substrate with the first single-crystal micron line array on top of the second silicon pillar template, so that the first single-crystal micron line array is close to the second silicon pillar template. Align the third alignment mark with the second alignment mark point-to-point, apply pressure to the substrate to make it close to the second silicon pillar template, at least some of the filling through holes correspond one-to-one with one end of the second silicon pillar, add the second organic powder into the filling through holes, and perform a secondary melting process to form a second single-crystal micron line array between several second silicon pillars and the first single-crystal micron line array. Remove the second silicon pillar template to obtain a vertical heterojunction single-crystal array.

[0083] Specifically, the secondary melting process includes: adding the second organic powder to the filling through hole and then performing a secondary heating process, and continuously applying pressure to melt the second organic powder and spread it along the surface of the second silicon pillar, and then performing a secondary cooling process to form the second single crystal micron array in the gaps between several second silicon pillars and the base first single crystal micron array.

[0084] In this invention, the second organic powder includes, but is not limited to, at least one of C8-BTBT, C10-BTBT, DPA, C6-DPA, DNTT, C10-DNTT, C8-NTDA, PDI8-CN2, and DFHCO-4T. The glass transition temperature of the first organic powder is lower than its own decomposition temperature and lower than the glass transformation temperature of the first organic powder, and also lower than the melting points of the substrate, the first silicon ingot template, and the second silicon ingot template.

[0085] In some embodiments, the secondary heating process includes: first heating the second temperature to a second temperature to melt the second organic powder, then holding the temperature for a second time and continuously applying pressure, so that the melted second organic powder forms a melt that covers the surface of the second silicon pillar near the first single-crystal micron array, forming the second single-crystal micron array.

[0086] Specifically, the heating rate of the secondary heating is 1~20℃ / min. The second temperature is greater than the glass transition temperature of the second organic powder and less than the thermal decomposition temperature of the second organic powder, and also less than the glass transition temperature of the first organic powder. The secondary holding time is 5~60min. In this invention, the heating rates of the primary and secondary heating can be the same or different. Similarly, the holding times of the primary and secondary heating can be the same or different. During the primary heating process, the melt formed after the second organic powder melts spreads along the second silicon pillars until it covers all the second silicon pillars, and the multiple melts formed constitute the second single-crystal micron-wire array.

[0087] In some embodiments, the secondary cooling includes sequentially performing a first-stage cooling and a second-stage cooling, wherein the cooling rate of the first-stage cooling is less than the cooling rate of the second-stage cooling.

[0088] Specifically, the cooling rate of the first stage of cooling is 0.1~1.0℃ / min, and the cooling rate of the second stage of cooling is 1~10℃ / min. In this invention, the cooling rates of the first and second melting processes can be the same or different, and those skilled in the art can make adaptive adjustments based on the properties of different organic powders.

[0089] In some embodiments, the present invention adjusts the applied pressure to regulate the height of the molten bridge formed on the surface of the second silicon pillar, thereby adjusting the thickness of the second single-crystal micron-line array. After the pressure application ends, the distance between the second silicon pillar and the first single-crystal micron-line is less than or equal to 1000 nm. Since the second single-crystal micron-line array is formed between the top surface of the second silicon pillar and the substrate, the spacing between the top surface of the second silicon pillar and the first single-crystal micron-line can be controlled by adjusting the applied pressure, thereby obtaining a product with the desired thickness.

[0090] The present invention performs the substrate covering process under a microscope, and the microscope is equipped with a three-dimensional moving platform to ensure that the third alignment mark is aligned point-to-point with the first alignment mark.

[0091] This invention achieves the fabrication of patterned arrays of organic semiconductor single-crystal heterojunctions with high density, uniform size, and high crystallinity through stepwise melting and directional crystallization.

[0092] In another specific embodiment, the present invention provides an organic semiconductor vertical heterojunction single-crystal array, which is fabricated using the method described in a specific embodiment. The organic semiconductor vertical heterojunction single-crystal array includes a substrate, on which a plurality of first single-crystal microwires are arranged in an array. Second single-crystal microwires are disposed on the side of the first single-crystal microwires away from the substrate. The first and second single-crystal microwires are coaxially arranged, and the glass transition temperature of the first single-crystal microwires is higher than that of the second single-crystal microwires.

[0093] In this invention, the first single-crystal microwire and the second single-crystal microwire are arranged in a vertical stack, and their center lines coincide on the orthographic projection of the substrate plane. At the same time, the first single-crystal microwire and the second single-crystal microwire have different semiconductor system compositions.

[0094] In some embodiments, the height ratio of the first single-crystal microwire to the second single-crystal microwire is 1:(0.01~100). The present invention achieves thickness control of the first single-crystal microwire and the second single-crystal microwire by adjusting the pressure applied in the primary and secondary melting processes during the preparation process.

[0095] In this invention, the width of the first single-crystal microwire is greater than the width of the second single-crystal microwire. The width refers to the linear length of the first single-crystal microwire along its arrangement direction.

[0096] Specifically, the width ratio of the first single-crystal micrometer line to the width of the second single-crystal micrometer line is (1~100):1. This invention, by adjusting the widths of the first and second silicon pillars used in the fabrication process, controls the width ratio of the first and second single-crystal micrometer lines, which is beneficial for meeting the requirements of different devices regarding the position and size of the overlapping region of the heterojunction array.

[0097] Example 1

[0098] This embodiment provides an organic semiconductor vertical heterojunction single-crystal array and its fabrication method, specifically including the following steps:

[0099] (1) Provide a first silicon pillar template 1, a second silicon pillar template 2 and a substrate 3.

[0100] like Figure 1 As shown, the first silicon pillar template 1 includes a first template body 11, on which a first silicon pillar array 13 is disposed. The first silicon pillar array 13 includes a plurality of first silicon pillars 131 arranged in an array. The first template body 11 is also provided with a first alignment mark 12. Figure 2As shown, the second silicon pillar template 2 includes a second template body 21, on which a second silicon pillar array 23 is disposed. The second silicon pillar array 23 includes a plurality of second silicon pillars 231 arranged in an array. A second alignment mark 22 is also disposed on the second template body 21. The first template body 11 and the second template body 21 have a cuboid structure and are identical in shape and size. The first silicon pillar array 13 and the second silicon pillar array 23 are spatially symmetrically arranged. The number of first silicon pillars 131 and second silicon pillars 231 is the same. Both the first silicon pillars 131 and the second silicon pillars 231 are arranged along the length direction of the first template body 11 and the second template body 21, and extend along their width direction. The width of the first silicon pillar 131 is 6 μm, and the width of the second silicon pillar 231 is 2 μm. The spacing between two adjacent first silicon pillars 131 in the first silicon pillar array 13 is 8 μm, and the spacing between two adjacent second silicon pillars 231 in the second silicon pillar array 23 is 12 μm. The first alignment mark 12 and the second alignment mark 22 have the same shape and size, and are positioned correspondingly. The width refers to the linear length of the first silicon pillar 131 and the second silicon pillar 231 in the length direction of the first mold body 11 and the second mold body 21.

[0101] The substrate 3 includes a substrate body 31, which is made of quartz sheet. The substrate body 31 has multiple injection vias 33, each consisting of multiple first injection vias and multiple second injection vias. The first and second injection vias are alternately spaced at the same end of the substrate 3. The number of first injection vias is the same as the number of first silicon pillars 131, and the number of second injection vias is the same as the number of second silicon pillars 231. The substrate body 31 also has a third alignment mark 32, which has the same shape and size as the first alignment mark 12 and the second alignment mark 22.

[0102] (2) The first silicon pillar template 1 and the second silicon pillar template 2 are subjected to asymmetric wetting treatment, so that the top surface of the first silicon pillar 131 away from the first template body 11 is hydrophilic while the side wall surface is hydrophobic, and the top surface of the second silicon pillar 231 away from the second silicon pillar template 2 is hydrophilic while the side wall surface is hydrophobic.

[0103] (3) Under a microscope equipped with a three-dimensional moving platform, the substrate 3 is placed over the first silicon pillar template 1, as shown. Figure 1 As shown, the third alignment mark 32 is aligned point-to-point with the first alignment mark 12, and then pressure is applied to the substrate 3 to bring it close to the first silicon pillar template 1, ensuring that the distance between the two is less than or equal to 100nm, and that the first injection via corresponds one-to-one with one end of the first silicon pillar 131 and is located directly above the first silicon pillar 131.

[0104] (4) Add the first organic powder PDI8-CN2 into the first filling hole. Its molecular structure is as follows: The temperature is then increased to 285°C at a rate of 20°C / min, and held for 20 minutes. Pressure is continuously applied to melt the first organic powder and spread it along the top surface of the first silicon pillar 131. The temperature is then slowly reduced at a rate of 1°C / min until the glass transition temperature of the first organic powder is reached. The temperature is then rapidly reduced at a rate of 10°C / min until room temperature is reached. A first single-crystal micron-line pillar is formed in the gap between the first silicon pillar 131 and the substrate 3, constituting a first single-crystal micron-line array. The thickness of the first single-crystal micron-line array is adjusted by adjusting the pressure. The first silicon pillar template 1 is then removed.

[0105] (5) Under a microscope equipped with a three-dimensional moving platform, the substrate 3 with the first single-crystal micron-line array is placed over the second silicon pillar template 2, as shown. Figure 2 As shown, the third alignment mark 32 is aligned point-to-point with the second alignment mark 22, and then pressure is applied to the substrate 3 to bring it close to the second silicon pillar template 2, ensuring that the distance between them is less than or equal to 100nm, and that the second injection via corresponds one-to-one with one end of the second silicon pillar 231 and is located directly above the second silicon pillar 231.

[0106] (6) Add the second organic powder C8-BTBT into the second filling hole. Its molecular structure is as follows: The temperature is then increased to 110°C at a rate of 20°C / min, and held for 20 minutes. Continuous pressure is applied to melt the second organic powder and spread it along the top surface of the second silicon pillar 231. Then, the temperature is slowly reduced at a rate of 1°C / min until the glass transition temperature of the second organic powder is reached. Then, the temperature is rapidly reduced at a rate of 10°C / min until room temperature is reached. A second single-crystal micro-pillar is formed in the gap between the second silicon pillar 231 and the first single-crystal micro-pillar, forming a second single-crystal micro-array. During this process, the pressure is adjusted to adjust the thickness of the second single-crystal micro-array. Then, the second silicon pillar template 2 is removed to obtain a vertical heterojunction single-crystal array.

[0107] The organic semiconductor vertical heterojunction single-crystal array fabricated in this embodiment includes a substrate 3. Multiple first single-crystal microwires are arranged in an array on the substrate 3. Second single-crystal microwires are disposed on the side of the first single-crystal microwires away from the substrate 3, such as... Figure 3 As shown, the first single-crystal micrometer line and the second single-crystal micrometer line are coaxially arranged. The height ratio of the first single-crystal micrometer line to the second single-crystal micrometer line is 1:1. The width of the first single-crystal micrometer line is 6μm, the spacing between two adjacent first single-crystal micrometer lines is 8μm, and the width of the second single-crystal micrometer line is 2μm.

[0108] Application examples

[0109] In this application example, a 5nm Cr coating and a 30nm Au coating were deposited on the surface of the vertical heterojunction single crystal array of Example 1 using a metal perforated mask, and then integrated onto a substrate such as... Figure 4 On the organic phototransistor device shown, and the following was detected: Figure 5 The transfer curves of the phototransistor shown are in darkness and under different lighting conditions (the horizontal axis represents the gate voltage, and the vertical axis represents the source and drain current). The organic phototransistor device includes a stacked gate and a dielectric layer. Several sets of drains and sources are disposed on the dielectric layer. A vertical heterojunction single crystal array is formed between the drains and sources. The gate is P++Si (heavily doped polycrystalline silicon), and the dielectric layer is SiO2.

[0110] Example 2

[0111] This embodiment provides an organic semiconductor vertical heterojunction single-crystal array and its fabrication method, specifically including the following steps:

[0112] (1) Provide a first silicon pillar template 1, a second silicon pillar template 2 and a substrate 3.

[0113] The first silicon pillar template 1 includes a first template body 11, on which a first silicon pillar array 13 is disposed. The first silicon pillar array 13 includes a plurality of first silicon pillars 131 arranged in an array. The first template body 11 also has a first alignment mark 12 disposed on it. The second silicon pillar template 2 includes a second template body 21, on which a second silicon pillar array 23 is disposed. The second silicon pillar array 23 includes a plurality of second silicon pillars 231 arranged in an array. The second template body 21 also has a second alignment mark 22 disposed on it. The first template body 11 and the second template body 21 have a cuboid structure and are identical in shape and size. The first silicon pillar array 13 and the second silicon pillar array 23 are spatially symmetrically arranged. The number of first silicon pillars 131 and second silicon pillars 231 is the same. The first silicon pillars 131 and the second silicon pillars 231 are arranged along the length direction of the first template body 11 and the second template body 21, and extend along their width direction. The width of the first silicon pillar 131 is 5 μm, and the width of the second silicon pillar 231 is 2.5 μm. The spacing between two adjacent first silicon pillars 131 in the first silicon pillar array 13 is 10 μm, and the spacing between two adjacent second silicon pillars 231 in the second silicon pillar array 23 is 11 μm. The first alignment mark 12 and the second alignment mark 22 have the same shape and size, and are positioned correspondingly.

[0114] The substrate 3 includes a substrate body 31, which is made of quartz sheet. The substrate body 31 has multiple injection vias 33, each consisting of multiple first injection vias and multiple second injection vias. The first and second injection vias are alternately spaced at the same end of the substrate 3. The number of first injection vias is the same as the number of first silicon pillars 131, and the number of second injection vias is the same as the number of second silicon pillars 231. The substrate body 31 also has a third alignment mark 32, which has the same shape and size as the first alignment mark 12 and the second alignment mark 22.

[0115] (2) The first silicon pillar template 1 and the second silicon pillar template 2 are subjected to asymmetric wetting treatment, so that the top surface of the first silicon pillar 131 away from the first template body 11 is hydrophilic, while the side wall surface is hydrophobic, and the top surface of the second silicon pillar 231 away from the second silicon pillar template 2 is hydrophilic, while the side wall surface is hydrophobic.

[0116] (3) Under a microscope equipped with a three-dimensional moving platform, the substrate 3 is placed over the first silicon pillar template 1, the third alignment mark 32 is aligned with the first alignment mark 12, and then pressure is applied to the substrate 3 to bring it close to the first silicon pillar template 1, ensuring that the distance between the two is less than or equal to 100nm, and that the first injection through hole corresponds one-to-one with one end of the first silicon pillar 131 and is located directly above the first silicon pillar 131.

[0117] (4) Add the first organic powder C10-DNTT into the first filling hole. Its molecular structure is as follows: The temperature is then increased to 290°C at a rate of 20°C / min, and held for 20 minutes. Pressure is continuously applied to melt the first organic powder and spread it along the top surface of the first silicon pillar 131. The temperature is then slowly reduced at a rate of 1°C / min until the glass transition temperature of the first organic powder is reached. The temperature is then rapidly reduced at a rate of 10°C / min until room temperature is reached. A first single-crystal micron-shaped wire pillar is formed in the gap between the first silicon pillar 131 and the substrate 3, forming a first single-crystal micron-shaped wire array. During this process, the pressure is adjusted to adjust the thickness of the first single-crystal micron-shaped wire array. The first silicon pillar template 1 is then removed.

[0118] (5) Under a microscope equipped with a three-dimensional moving platform, the substrate 3 with the first single-crystal micron line array is placed on top of the second silicon pillar template 2. The third alignment mark 32 is aligned with the second alignment mark 22. Then, pressure is applied to the substrate 3 to bring it close to the second silicon pillar template 2, ensuring that the distance between the two is less than or equal to 100 nm, and that the second injection via corresponds one-to-one with one end of the second silicon pillar 231 and is located directly above the second silicon pillar 231.

[0119] (6) Add the second organic powder C8-BTBT into the second filling hole. Its molecular structure is as follows: The temperature is then increased to 110°C at a rate of 20°C / min, and held for 20 minutes. Continuous pressure is applied to melt the second organic powder and spread it along the top surface of the second silicon pillar 231. Then, the temperature is slowly reduced at a rate of 1°C / min until the glass transition temperature of the second organic powder is reached. Then, the temperature is rapidly reduced at a rate of 10°C / min until room temperature is reached. A second single-crystal micro-pillar is formed in the gap between the second silicon pillar 231 and the first single-crystal micro-pillar, forming a second single-crystal micro-array. During this process, the pressure is adjusted to adjust the thickness of the second single-crystal micro-array. Then, the second silicon pillar template 2 is removed to obtain a vertical heterojunction single-crystal array.

[0120] The organic semiconductor vertical heterojunction single-crystal array fabricated in this embodiment includes a substrate 3. Multiple first single-crystal microwires are arranged in an array on the substrate 3. Second single-crystal microwires are disposed on the side of the first single-crystal microwires away from the substrate 3, such as... Figure 6 As shown, the first single-crystal micrometer line and the second single-crystal micrometer line are coaxially arranged. The height ratio of the first single-crystal micrometer line to the second single-crystal micrometer line is 1:2. The width of the first single-crystal micrometer line is 5.8 μm, the spacing between two adjacent first single-crystal micrometer lines is 8.4 μm, and the width of the second single-crystal micrometer line is 2.3 μm.

[0121] Example 3

[0122] This embodiment provides an organic semiconductor vertical heterojunction single-crystal array and its fabrication method, specifically including the following steps:

[0123] (1) Provide a first silicon pillar template 1, a second silicon pillar template 2 and a substrate 3.

[0124] The first silicon pillar template 1 includes a first template body 11, on which a first silicon pillar array 13 is disposed. The first silicon pillar array 13 includes a plurality of first silicon pillars 131 arranged in an array. The first template body 11 also has a first alignment mark 12 disposed on it. The second silicon pillar template 2 includes a second template body 21, on which a second silicon pillar array 23 is disposed. The second silicon pillar array 23 includes a plurality of second silicon pillars 231 arranged in an array. The second template body 21 also has a second alignment mark 22 disposed on it. The first template body 11 and the second template body 21 have a cuboid structure and are identical in shape and size. The first silicon pillar array 13 and the second silicon pillar array 23 are spatially symmetrically arranged. The number of first silicon pillars 131 and second silicon pillars 231 is the same. The first silicon pillars 131 and the second silicon pillars 231 are arranged along the length direction of the first template body 11 and the second template body 21, and extend along their width direction. The width of the first silicon pillar 131 is 6 μm, and the width of the second silicon pillar 231 is 2 μm. The spacing between two adjacent first silicon pillars 131 in the first silicon pillar array 13 is 8 μm, and the spacing between two adjacent second silicon pillars 231 in the second silicon pillar array 23 is 12 μm. The first alignment mark 12 and the second alignment mark 22 have the same shape and size, and are positioned correspondingly.

[0125] The substrate 3 includes a substrate body 31, which is made of quartz sheet. The substrate body 31 has multiple injection vias 33, each consisting of multiple first injection vias and multiple second injection vias. The first and second injection vias are alternately spaced at the same end of the substrate 3. The number of first injection vias is the same as the number of first silicon pillars 131, and the number of second injection vias is the same as the number of second silicon pillars 231. The substrate body 31 also has a third alignment mark 32, which has the same shape and size as the first alignment mark 12 and the second alignment mark 22.

[0126] (2) The first silicon pillar template 1 and the second silicon pillar template 2 are subjected to asymmetric wetting treatment, so that the top surface of the first silicon pillar 131 away from the first template body 11 is hydrophilic while the side wall surface is hydrophobic, and the surface of the second silicon pillar 231 away from the second silicon pillar template 2 is hydrophilic while the side wall surface is hydrophobic.

[0127] (3) Under a microscope equipped with a three-dimensional moving platform, the substrate 3 is placed over the first silicon pillar template 1, the third alignment mark 32 is aligned with the first alignment mark 12, and then pressure is applied to the substrate 3 to bring it close to the first silicon pillar template 1, ensuring that the distance between the two is less than or equal to 100nm, and that the first injection through hole corresponds one-to-one with one end of the first silicon pillar 131 and is located directly above the first silicon pillar 131.

[0128] (4) Add the first organic powder DPA into the first filling hole. Its molecular structure is as follows: The temperature is then increased to 320°C at a heating rate of 20°C / min, and held for 30 minutes. Pressure is continuously applied to melt the first organic powder and spread it along the top surface of the first silicon pillar 131. The temperature is then slowly reduced at a cooling rate of 1°C / min until the glass transition temperature of the first organic powder is reached. The temperature is then rapidly reduced at a cooling rate of 10°C / min until room temperature is reached. A first single-crystal micron-line pillar is formed in the gap between the first silicon pillar 131 and the substrate 3, constituting a first single-crystal micron-line array. The thickness of the first single-crystal micron-line array is adjusted by adjusting the pressure applied. The first silicon pillar template 1 is then removed.

[0129] (5) Under a microscope equipped with a three-dimensional moving platform, the substrate 3 with the first single-crystal micron line array is placed on top of the second silicon pillar template 2. The third alignment mark 32 is aligned with the second alignment mark 22. Then, pressure is applied to the substrate 3 to bring it close to the second silicon pillar template 2, ensuring that the distance between the two is less than or equal to 100 nm, and that the second injection via corresponds one-to-one with one end of the second silicon pillar 231 and is located directly above the second silicon pillar 231.

[0130] (6) Add the second organic powder PDI8-CN2 into the second filling hole. Its molecular structure is as follows:

[0131] The temperature is then increased to 285°C at a rate of 20°C / min, and held for 20 minutes. Continuous pressure is applied to melt the second organic powder and spread it along the top surface of the second silicon pillar 231. Then, the temperature is slowly reduced at a rate of 1°C / min until the glass transition temperature of the second organic powder is reached. Then, the temperature is rapidly reduced at a rate of 10°C / min until room temperature is reached. A second single-crystal micro-pillar is formed in the gap between the second silicon pillar 231 and the first single-crystal micro-pillar, forming a second single-crystal micro-array. During this process, the pressure is adjusted to adjust the thickness of the second single-crystal micro-array. Then, the second silicon pillar template 2 is removed to obtain a vertical heterojunction single-crystal array.

[0132] The organic semiconductor vertical heterojunction single-crystal array fabricated in this embodiment includes a substrate 3. Multiple first single-crystal microwires are arranged in an array on the substrate 3. Second single-crystal microwires are disposed on the side of the first single-crystal microwires away from the substrate 3, such as... Figure 7 As shown, the first single-crystal micrometer line and the second single-crystal micrometer line are coaxially arranged. The height ratio of the first single-crystal micrometer line to the second single-crystal micrometer line is 2:1. The width of the first single-crystal micrometer line is 6μm, the spacing between two adjacent first single-crystal micrometer lines is 8μm, and the width of the second single-crystal micrometer line is 2μm.

[0133] Example 4

[0134] This embodiment provides an organic semiconductor vertical heterojunction single-crystal array and its fabrication method, specifically including the following steps:

[0135] (1) Provide a first silicon pillar template 1, a second silicon pillar template 2 and a substrate 3.

[0136] The first silicon pillar template 1 includes a first template body 11, on which a first silicon pillar array 13 is disposed. The first silicon pillar array 13 includes a plurality of first silicon pillars 131 arranged in an array. The first template body 11 also has a first alignment mark 12 disposed on it. The second silicon pillar template 2 includes a second template body 21, on which a second silicon pillar array 23 is disposed. The second silicon pillar array 23 includes a plurality of second silicon pillars 231 arranged in an array. The second template body 21 also has a second alignment mark 22 disposed on it. The first template body 11 and the second template body 21 have a cuboid structure and are identical in shape and size. The first silicon pillar array 13 and the second silicon pillar array 23 are spatially symmetrically arranged. The number of first silicon pillars 131 and second silicon pillars 231 is the same. The first silicon pillars 131 and the second silicon pillars 231 are arranged along the length direction of the first template body 11 and the second template body 21, and extend along their width direction. The width of the first silicon pillar 131 is 6 μm, and the width of the second silicon pillar 231 is 2 μm. The spacing between two adjacent first silicon pillars 131 in the first silicon pillar array 13 is 8 μm, and the spacing between two adjacent second silicon pillars 231 in the second silicon pillar array 23 is 12 μm. The first alignment mark 12 and the second alignment mark 22 have the same shape and size, and are positioned correspondingly.

[0137] The substrate 3 includes a substrate body 31, which is made of quartz sheet. The substrate body 31 has multiple injection vias 33, each consisting of multiple first injection vias and multiple second injection vias. The first and second injection vias are alternately spaced at the same end of the substrate 3. The number of first injection vias is the same as the number of first silicon pillars 131, and the number of second injection vias is the same as the number of second silicon pillars 231. The substrate body 31 also has a third alignment mark 32, which has the same shape and size as the first alignment mark 12 and the second alignment mark 22.

[0138] (2) The first silicon pillar template 1 and the second silicon pillar template 2 are respectively subjected to wettability treatment, so that the top surface of the first silicon pillar 131 away from the first template body 11 is hydrophilic while the side wall surface is hydrophobic, and the top surface of the second silicon pillar 231 away from the second silicon pillar template 2 is hydrophilic while the side wall surface is hydrophobic.

[0139] (3) Under a microscope equipped with a three-dimensional moving platform, the substrate 3 is placed over the first silicon pillar template 1, the third alignment mark 32 is aligned with the first alignment mark 12, and then pressure is applied to the substrate 3 to bring it close to the first silicon pillar template 1, ensuring that the distance between the two is less than or equal to 100nm, and that the first injection through hole corresponds one-to-one with one end of the first silicon pillar 131 and is located directly above the first silicon pillar 131.

[0140] (4) Add the first organic powder DPA into the first filling hole. Its molecular structure is as follows: The temperature is then increased to 320°C at a heating rate of 20°C / min, and held for 30 minutes. Pressure is continuously applied to melt the first organic powder and spread it along the top surface of the first silicon pillar 131. The temperature is then slowly reduced at a cooling rate of 1°C / min until the glass transition temperature of the first organic powder is reached. The temperature is then rapidly reduced at a cooling rate of 10°C / min until room temperature is reached. A first single-crystal micron-line pillar is formed in the gap between the first silicon pillar 131 and the substrate 3, constituting a first single-crystal micron-line array. The thickness of the first single-crystal micron-line array is adjusted by adjusting the pressure applied. The first silicon pillar template 1 is then removed.

[0141] (5) Under a microscope equipped with a three-dimensional moving platform, the substrate 3 with the first single-crystal micron line array is placed on top of the second silicon pillar template 2. The third alignment mark 32 is aligned with the second alignment mark 22. Then, pressure is applied to the substrate 3 to bring it close to the second silicon pillar template 2, ensuring that the distance between the two is less than or equal to 100 nm, and that the second injection via corresponds one-to-one with one end of the second silicon pillar 231 and is located directly above the second silicon pillar 231.

[0142] (6) Add the second organic powder C8-BTBT into the second filling hole. Its molecular structure is as follows: The temperature is then increased to 110°C at a rate of 20°C / min, and held for 20 minutes. Continuous pressure is applied to melt the second organic powder and spread it along the top surface of the second silicon pillar 231. Then, the temperature is slowly reduced at a rate of 1°C / min until the glass transition temperature of the second organic powder is reached. Then, the temperature is rapidly reduced at a rate of 10°C / min until room temperature is reached. A second single-crystal micro-pillar is formed in the gap between the second silicon pillar 231 and the first single-crystal micro-pillar, forming a second single-crystal micro-array. During this process, the pressure is adjusted to adjust the thickness of the second single-crystal micro-array. Then, the second silicon pillar template 2 is removed to obtain a vertical heterojunction single-crystal array.

[0143] The organic semiconductor vertical heterojunction single-crystal array fabricated in this embodiment includes a substrate 3. Multiple first single-crystal microwires are arranged in an array on the substrate 3. Second single-crystal microwires are disposed on the side of the first single-crystal microwires away from the substrate 3, such as... Figure 8As shown, the first single-crystal micrometer line and the second single-crystal micrometer line are coaxially arranged. The height ratio of the first single-crystal micrometer line to the second single-crystal micrometer line is 2:3. The width of the first single-crystal micrometer line is 6μm, the spacing between two adjacent first single-crystal micrometer lines is 8μm, and the width of the second single-crystal micrometer line is 2μm.

[0144] Example 5

[0145] This embodiment provides an organic semiconductor vertical heterojunction single crystal array and its preparation method. The difference from Embodiment 1 is that the substrate body 31 is made of a silicon wafer coated with a silicon oxide layer, while the other preparation steps, process parameters and structures are the same as in Embodiment 1.

[0146] This invention breaks away from the dependence on molecular structure and lattice matching, utilizing only the melting point differences between different materials to achieve the construction of high-quality heterojunctions through stepwise melting and directional crystallization. During the melting process, the invention allows molecules to fully rearrange in the liquid state, forming a low-defect, highly oriented single-crystal interface. Furthermore, through template guidance and precise temperature control, the position, size, and orientation of the crystals are controllable, avoiding the damage caused by solvent action and artificial transfer. This provides a universal and scalable new approach for constructing high-quality heterojunctions between different organic semiconductor materials, laying the foundation for the integrated manufacturing of high-performance organic optoelectronic devices.

[0147] The applicant declares that the above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.

Claims

1. A method for fabricating a vertical heterojunction single-crystal array of organic semiconductors, characterized in that, The preparation method includes: Provides a first silicon pillar template, a second silicon pillar template, and a substrate; The first silicon pillar template includes a first template body, on which at least one first silicon pillar array is disposed, the first silicon pillar array comprising a plurality of first silicon pillars arranged in an array; the second silicon pillar template includes a second template body, on which at least one second silicon pillar array is disposed, the second silicon pillar array comprising a plurality of second silicon pillars arranged in an array; the first silicon pillar array and the second silicon pillar array are spatially symmetrically arranged; a plurality of injection vias are formed on the substrate, the plurality of injection vias being sequentially arranged at the same end of the substrate; a first alignment mark, a second alignment mark, and a third alignment mark are respectively disposed on the first template body, the second template body, and the substrate; The substrate is placed over the first silicon pillar template, the third alignment mark is aligned with the first alignment mark, pressure is applied to the substrate to bring it close to the first silicon pillar template, at least some of the injection vias correspond one-to-one with one end of the first silicon pillar, the first organic powder is added into the injection vias, and a melting process is performed to form a first single-crystal micron-line array in the gap between several first silicon pillars and the substrate, and the first silicon pillar template is removed. A substrate with a first single-crystal micron-line array is placed over the second silicon pillar template, so that the first single-crystal micron-line array is close to the second silicon pillar template. The third alignment mark is aligned with the second alignment mark, and pressure is applied to the substrate to bring it close to the second silicon pillar template. At least a portion of the injection vias correspond one-to-one with one end of the second silicon pillar. A second organic powder is added into the injection vias and a secondary melting process is performed to form a second single-crystal micron-line array between several second silicon pillars and the first single-crystal micron-line array. The second silicon pillar template is then removed to obtain a vertical heterojunction single-crystal array. The glass transition temperature of the first organic powder is greater than that of the second organic powder.

2. The method for fabricating an organic semiconductor vertical heterojunction single-crystal array according to claim 1, characterized in that, The first alignment mark on the first template body and the second alignment mark on the second template body are respectively set to correspond to each other, and the first alignment mark and the second alignment mark have the same shape and size; And / or, in the first direction, the linear length of the first silicon pillar is greater than or equal to the linear length of the second silicon pillar; The first direction is the arrangement direction of the first silicon pillar or the second silicon pillar; And / or, the linear lengths of the first silicon pillar and the second silicon pillar in the first direction are independently 1~10000μm; And / or, the spacing between two adjacent first silicon pillars is 1~100μm; And / or, the spacing between two adjacent second silicon pillars is 1~100μm.

3. The method for fabricating an organic semiconductor vertical heterojunction single-crystal array according to claim 1, characterized in that, The first silicon pillar template and the second silicon pillar template are respectively subjected to asymmetric wettability modification, so that the top surface of the first silicon pillar and the second silicon pillar away from the first mold body and the second mold body is hydrophilic, while the side wall surface is hydrophobic.

4. The method for fabricating an organic semiconductor vertical heterojunction single-crystal array according to claim 1, characterized in that, The first alignment mark, the second alignment mark, and the third alignment mark are all the same in shape and size; And / or, the material of the substrate includes at least one of glass, quartz, silicon, or silicon with a deposited silicon oxide layer; And / or, the plurality of filling vias include at least two first filling vias and at least two second filling vias, the first filling vias and the second filling vias being alternately and alternately disposed at the same end of the substrate, the first filling vias corresponding one-to-one with the first silicon pillars, and the second filling vias corresponding one-to-one with the second silicon pillars; And / or, the first filling through hole and the second filling through hole are arranged side by side, or the orthographic projection of the first filling through hole on the vertical plane does not coincide with the orthographic projection of the second filling through hole on the vertical plane, or at least part of the orthographic projection of the first filling through hole on the vertical plane coincides with the orthographic projection of the second filling through hole on the vertical plane; And / or, the diameter of the first filling via is less than the first length, the first length being the sum of the linear length of the first silicon pillar in the first direction and the distance between two adjacent first silicon pillars; The diameter of the second injection via is smaller than the second length, which is the sum of the linear length of the second silicon pillar in the first direction and the distance between two adjacent second silicon pillars.

5. The method for fabricating an organic semiconductor vertical heterojunction single-crystal array according to claim 1, characterized in that, The glass transition temperature of the first organic powder is lower than its own decomposition temperature, and the glass transition temperature of the second organic powder is lower than its own decomposition temperature. The glass transition temperatures of both the first organic powder and the second organic powder are lower than the melting point of the substrate, and the glass transition temperatures of both the first organic powder and the second organic powder are lower than the melting points of the first silicon pillar template and the second silicon pillar template.

6. The method for fabricating an organic semiconductor vertical heterojunction single-crystal array according to any one of claims 1-5, characterized in that, The first melting process includes: adding the first organic powder to the filling through hole and then heating it once, and continuously applying pressure to make the first organic powder melt and spread along the surface of the first silicon pillar, and then cooling it once to form the first single crystal micron line array between several first silicon pillars and the substrate. The secondary melting process includes: adding the second organic powder to the filling through hole and then performing a secondary heating process, and continuously applying pressure to make the second organic powder melt and spread along the surface of the second silicon pillar, and then performing a secondary cooling process to form the second single crystal micron array between several second silicon pillars and the first single crystal micron array; And / or, adjust the applied pressure respectively to achieve thickness adjustment of the first single-crystal micron-line array and the second single-crystal micron-line array; And / or, after the pressure application ends, the distance between the first silicon pillar or the second silicon pillar and the substrate is less than or equal to 1000 nm.

7. The method for fabricating an organic semiconductor vertical heterojunction single-crystal array according to claim 6, characterized in that, The first heating process includes: first heating to a first temperature to melt the first organic powder, then holding the temperature and applying pressure to make the melted first organic powder form a melt that covers the surface of the first silicon pillar near the substrate. The secondary heating process includes: first heating to a second temperature to melt the second organic powder, then holding the temperature for a second time and continuously applying pressure, so that the melted second organic powder forms a melt that covers the surface of the second silicon pillar near the first single crystal micron array; And / or, both the primary cooling and the secondary cooling include sequentially performing a first-stage cooling and a second-stage cooling, and the cooling rate of the first-stage cooling is less than the cooling rate of the second-stage cooling.

8. The method for fabricating an organic semiconductor vertical heterojunction single-crystal array according to claim 7, characterized in that, The heating rates for the first heating and the second heating are independent, each ranging from 1 to 20 °C / min. And / or, the first temperature is greater than the glass transition temperature of the first organic powder and less than the thermal decomposition temperature of the first organic powder; The second temperature is greater than the glass transition temperature of the second organic powder and less than the thermal decomposition temperature of the second organic powder, and is also less than the glass transition temperature of the first organic powder. And / or, the duration of the first heat preservation and the duration of the second heat preservation are each 5~60 min independently; And / or, the cooling rate of the first stage of cooling is 0.1~1.0℃ / min, and the cooling rate of the second stage of cooling is 1~10℃ / min.

9. An organic semiconductor vertical heterojunction single-crystal array, characterized in that, The organic semiconductor vertical heterojunction single crystal array is prepared by the method of any one of claims 1-8. The organic semiconductor vertical heterojunction single crystal array includes a substrate, on which a plurality of first single crystal micrometer lines are arranged in an array. A second single crystal micrometer line is arranged on the side of the first single crystal micrometer line away from the substrate. The first single crystal micrometer line and the second single crystal micrometer line are coaxially arranged, and the glass transition temperature of the first single crystal micrometer line is higher than that of the second single crystal micrometer line.

10. The organic semiconductor vertical heterojunction single-crystal array according to claim 9, characterized in that, The height ratio of the first single-crystal micron wire to the second single-crystal micron wire is 1:(0.01~100); And / or, the width of the first single-crystal micrometer wire is greater than the width of the second single-crystal micrometer wire; And / or, the ratio of the width of the first single-crystal micrometer wire to the width of the second single-crystal micrometer wire is (1~100):1.

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