Linear voltage regulator
By introducing a zero-point compensation unit into the linear regulator and adjusting the zero point using a current mirror and an RC adjustment module, the stability problem of the linear regulator under load changes is solved, achieving stable output in the no-load and light-load ranges and reducing costs.
Patent Information
- Application Number
- CN202511812093.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-03
- Publication Date
- 2026-02-06
AI Technical Summary
When the output load changes from no load to a lighter load, the loop of a linear regulator cannot guarantee stable operation, especially since the output pole position cannot be fixed as the load current and load capacitance change.
An error amplifier, buffer unit, power transistor, feedback unit, and zero-point compensation unit are used. Through the first and second sampling units, current generation unit, and zero-point generation unit, the zero-point position is adaptively followed to follow load changes. The zero point is adjusted by a current mirror and RC adjustment module to ensure stability.
Under different load conditions, the zero point position accurately follows the load change, ensuring that the zero point still follows the load change in the light load range, which improves the output stability and uses fewer components, thus reducing costs.
Smart Images
Figure CN121478066A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a linear voltage regulator. Background Technology
[0002] Linear regulators are typically two-pole systems and need to support a wide range of load currents and capacitances. Because their output poles change with load current and capacitance, their position cannot be fixed under different load conditions. For two-pole systems, single-zero compensation is commonly used, requiring a zero-point compensation loop that follows load changes. This leads to adaptive compensation methods, where the compensation zero-point changes with the load, while a fixed bias current ensures stability and robustness under very light loads. However, when the output load is between no-load and light-load conditions, the compensation zero-point is primarily determined by the fixed bias current and does not change with the output, thus failing to guarantee stable loop operation under all loads within this range.
[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to provide a linear voltage regulator that can ensure stable operation of the loop when the output load is between no load and light load.
[0005] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution: A linear regulator, comprising: an error amplifier, a buffer unit, a power transistor, a feedback unit, and a zero-point compensation unit. The first input terminal of the error amplifier is connected to a reference voltage, and the output terminal of the error amplifier is connected to the control terminal of the power transistor through the buffer unit. The first terminal of the power transistor is connected to the input voltage, and the second terminal of the power transistor is connected to the feedback unit to form the output terminal of the linear regulator. The feedback unit generates a feedback voltage based on the output voltage of the linear regulator, and the second input terminal of the error amplifier is used to receive the feedback voltage.
[0006] The zero-point compensation unit includes:
[0007] The first sampling unit is connected to the control terminal of the power transistor to sample the current on the power transistor to obtain the first sampling current;
[0008] The first current generating unit is used to generate a first current.
[0009] The arithmetic unit is connected to the first sampling unit and the first current generation unit to obtain the first arithmetic current based on the first sampling current and the first current.
[0010] The second sampling unit is connected to the control terminal of the power transistor to sample the current on the power transistor to obtain the second sampling current;
[0011] A second current generating unit is used to generate a second current; and
[0012] A zero-point generation unit is connected to the arithmetic unit, the second sampling unit, and the second current generation unit to generate a zero point that varies with the current based on the first arithmetic current, the second current, and the second sampling current. The zero-point generation unit is connected to the output terminal of the error amplifier to perform zero-point adjustment on the output terminal of the error amplifier.
[0013] In one or more embodiments of the present invention, the first sampling unit includes a first sampling tube and a first current mirror. The control terminal of the first sampling tube is connected to the control terminal of the power tube. The first terminal of the first sampling tube is connected to the input voltage. The first current mirror is connected to the second terminal of the first sampling tube, a first current generation unit, and a computing unit. The first current mirror is used to mirror the current on the first sampling tube to generate a first sampling current.
[0014] In one or more embodiments of the present invention, the computing unit includes a second current mirror, which is connected to a first current generation unit and a first sampling unit. The second current mirror is used to obtain the difference current between a first sampling current and a first current, and to generate a first computing current by mirroring the difference current.
[0015] In one or more embodiments of the present invention, the second sampling unit includes a second sampling tube, the first end of the second sampling tube is connected to the input voltage, the control end of the second sampling tube is connected to the control end of the power tube, and the second end of the second sampling tube is connected to a second current generating unit, an arithmetic unit, and a zero-point generating unit.
[0016] In one or more embodiments of the present invention, the zero-point generation unit includes a voltage generation module and an RC adjustment module. The voltage generation module is used to generate a second operational current based on a first operational current, a second current, and a second sampling current, and to generate a control voltage that varies with the second operational current based on the second operational current. The RC adjustment module is connected to the voltage generation module and the output terminal of the error amplifier to adjust its own capacitance and / or resistance value based on the control voltage to generate a corresponding zero point.
[0017] In one or more embodiments of the present invention, the voltage generation module includes a control transistor, the second terminal of which is connected to the control terminal of the control transistor, an arithmetic unit, a second sampling unit, and a second current generation unit, and the control terminal of the control transistor is connected to an RC adjustment module.
[0018] In one or more embodiments of the present invention, the RC adjustment module includes an adjustment tube and a capacitor. The control terminal of the adjustment tube is connected to the voltage generation module, the second terminal of the adjustment tube is connected to the first terminal of the capacitor, the first terminal of the adjustment tube is connected to the reference voltage, and the second terminal of the capacitor is connected to the output terminal of the error amplifier.
[0019] In one or more embodiments of the present invention, the RC adjustment module further includes a resistor connected in series with a capacitor and connected to the second terminal of the adjustment tube and the output terminal of the error amplifier.
[0020] In one or more embodiments of the present invention, the first current mirror includes a first transistor and a second transistor. The second terminal of the first transistor is connected to the control terminal of the first transistor, the second terminal of the first sampling transistor, and the control terminal of the second transistor. The second terminal of the second transistor is connected to the first current generating unit and the arithmetic unit. The first terminal of the first transistor and the first terminal of the second transistor are connected to a reference voltage.
[0021] In one or more embodiments of the present invention, the second current mirror includes a third transistor and a fourth transistor. The second terminal of the third transistor is connected to the control terminal of the third transistor, the first current generating unit and the first sampling unit. The second terminal of the fourth transistor is connected to the second current generating unit, the second sampling unit and the zero-point generating unit. The first terminals of the third transistor and the fourth transistor are connected to a reference voltage.
[0022] Compared with the prior art, the linear regulator of the present invention enables the zero point position to follow the load change precisely under different load conditions. It can still follow the load change in the light load range, thus better ensuring output stability. Moreover, it uses fewer components, which can effectively reduce costs. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a circuit diagram of a linear regulator according to an embodiment of the present invention.
[0025] Figure 2 This is a circuit diagram of a zero-point compensation unit in one embodiment of the present invention. Detailed Implementation
[0026] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.
[0027] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.
[0028] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.
[0029] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.
[0030] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0031] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.
[0032] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.
[0033] like Figure 1 As shown, a linear regulator in one embodiment of the present invention includes: an error amplifier EA, a buffer unit BUFFER, a power transistor MP0, a feedback unit, and a zero-point compensation unit 10.
[0034] The first input terminal of the error amplifier EA is connected to the reference voltage VREF. The output terminal VEA of the error amplifier EA is connected to the control terminal VG of the power transistor MP0 through the buffer unit BUFFER. The first terminal of the power transistor MP0 is connected to the input voltage VIN, and the second terminal of the power transistor MP0 is connected to the feedback unit to form the output terminal VOUT of the linear regulator. The feedback unit generates a feedback voltage VFB based on the output voltage of the linear regulator, and the second input terminal of the error amplifier EA is used to receive the feedback voltage VFB. The zero-point compensation unit 10 is connected to the control terminal VG of the power transistor MP0 and the output terminal VEA of the error amplifier EA to perform zero-point compensation on the output terminal VEA of the error amplifier EA based on the voltage of the control terminal VG of the power transistor MP0. The first input terminal of the error amplifier EA is a positive input terminal, and the second input terminal of the error amplifier EA is a negative input terminal. In other embodiments, the first input terminal of the error amplifier EA is a negative input terminal, and the second input terminal of the error amplifier EA is a positive input terminal.
[0035] In one embodiment, the feedback unit includes a first voltage divider resistor RFB1 and a second voltage divider resistor RFB2. The first end of the first voltage divider resistor RFB1 is connected to the second end of the power transistor MP0 to form the output terminal VOUT of the linear regulator. The first end of the second voltage divider resistor RFB2 is connected to the second end of the first voltage divider resistor RFB1 to generate a feedback voltage VFB. The second end of the second voltage divider resistor RFB2 is connected to a reference voltage, which is ground voltage.
[0036] The linear regulator also includes a resistor esr and a capacitor Cout, which are connected in series and to the output terminal VOUT of the linear regulator. The output terminal VOUT of the linear regulator is also used to connect the load resistor RLOAD.
[0037] like Figure 2 As shown, the zero-point compensation unit 10 includes: a first sampling unit 11, a first current generation unit 12, an arithmetic unit 13, a second sampling unit 14, a second current generation unit 15, and a zero-point generation unit 16.
[0038] The first sampling unit 11 is connected to the control terminal VG of the power transistor MP0 to sample the current on the power transistor MP0 to obtain a first sampling current I1; the first current generating unit 12 is used to generate a first current IB1; the arithmetic unit 13 is connected to the first sampling unit 11 and the first current generating unit 12 to obtain a first operational current I3 based on the first sampling current I1 and the first current IB1. In one embodiment, the first operational current I3 is the difference current between the first current IB1 and the first sampling current I1.
[0039] The second sampling unit 14 is connected to the control terminal VG of the power transistor MP0 to sample the current on the power transistor MP0 to obtain the second sampling current IS2; the second current generation unit 15 is used to generate the second current IB2; the zero-point generation unit 16 is connected to the operation unit 13, the second sampling unit 14, and the second current generation unit 15 to generate a zero point that varies with the current based on the first operational current I3, the second current IB2, and the second sampling current IS2. The zero-point generation unit 16 is connected to the output terminal VEA of the error amplifier EA to perform zero-point adjustment on the output terminal VEA of the error amplifier EA. In one embodiment, the zero-point generation unit 16 generates a corresponding control voltage based on the second current IB2, the second sampling current IS2, and the first operational current I3, and generates a corresponding resistor based on the control voltage to obtain the corresponding zero point. The control voltage changes with the second sampling current IS2 and the first operational current I3. Specifically, the total current of the sum of the second current IB2 and the second sampling current IS2 is first obtained, then the difference current between the total current and the first operational current I3 is obtained, and the corresponding control voltage is obtained based on the difference current.
[0040] In one embodiment, the first sampling unit 11 includes a first sampling transistor MP1 and a first current mirror. The control terminal of the first sampling transistor MP1 is connected to the control terminal VG of the power transistor MP0, and the first terminal of the first sampling transistor MP1 is connected to the input voltage VIN. The first sampling transistor MP1 is used to proportionally sample the current ILOAD on the power transistor MP0 to obtain the corresponding current IS1. The first current mirror is connected to the second terminal of the first sampling transistor MP1, the first current generation unit 12, and the arithmetic unit 13. The first current mirror is used to mirror the current IS1 on the first sampling transistor MP1 to generate a first sampling current I1.
[0041] like Figure 2As shown, the first current mirror includes a first transistor MN0 and a second transistor MN1. The second terminal of the first transistor MN0 is connected to the control terminal of the first transistor MN0, the second terminal of the first sampling transistor MP1, and the control terminal of the second transistor MN1. The second terminal of the second transistor MN1 is connected to the first current generation unit 12 and the arithmetic unit 13. The first terminals of the first transistor MN0 and the first terminals of the second transistor MN1 are connected to a reference voltage. The second transistor MN1 mirrors the current on the first transistor MN0 to generate a first sampling current I1.
[0042] In one embodiment, the arithmetic unit 13 includes a second current mirror, which is connected to the first current generation unit 12 and the first sampling unit 11. The second current mirror is used to obtain the difference current between the first sampling current I1 and the first current IB1, and to generate the first operational current I3 by mirroring the difference current.
[0043] like Figure 2 As shown, the second current mirror includes a third transistor MN2 and a fourth transistor MN3. The second terminal of the third transistor MN2 is connected to the control terminal of the third transistor MN2, the second terminal of the second transistor MN1 of the first current generation unit 12 and the first sampling unit 11. The second terminal of the fourth transistor MN3 is connected to the second current generation unit 15, the second sampling unit 14 and the zero-point generation unit 16. The first terminals of the third transistor MN2 and the fourth transistor MN3 are connected to the reference voltage. The difference current between the first sampling current I1 and the first current IB1 is obtained through the third transistor MN2, and the first operational current I3 is generated by mirroring this difference current through the fourth transistor MN3.
[0044] like Figure 2 As shown, the first current generating unit 12 includes a first current source A1. The first terminal of the first current source A1 is connected to the second terminal of the second transistor MN1 and the second terminal of the third transistor MN2. The second terminal of the first current source A1 is connected to the input voltage VIN. The first current source A1 is used to generate a first current IB1.
[0045] like Figure 2 As shown, the second sampling unit 14 includes a second sampling transistor MP2. The first terminal of the second sampling transistor MP2 is connected to the input voltage VIN, and the control terminal of the second sampling transistor MP2 is connected to the control terminal VG of the power transistor MP0. The second terminal of the second sampling transistor MP2 is connected to the second terminal of the fourth transistor MN3 of the second current generation unit 15, the arithmetic unit 13, and the zero-point generation unit 16. The second sampling transistor MP2 is used to perform proportional sampling of the current ILOAD on the power transistor MP0 to obtain the corresponding current IS2.
[0046] In one embodiment, the zero-point generation unit 16 includes a voltage generation module and an RC adjustment module. The voltage generation module is used to generate a second operational current I4 based on a first operational current I3, a second current IB2, and a second sampling current IS2, and to generate a control voltage that varies with the second operational current I4. The RC adjustment module is connected to the voltage generation module and the output terminal VEA of the error amplifier EA to adjust its own capacitance and / or resistance value based on the control voltage to generate a corresponding zero point.
[0047] like Figure 2 As shown, the voltage generation module includes a control transistor MN4. The second terminal of the control transistor MN4 is connected to the control terminal of the control transistor MN4, the second terminal of the fourth transistor MN3 of the arithmetic unit 13, the second terminal of the second sampling transistor MP2 of the second sampling unit 14, and the second current generation unit 15. The control terminal of the control transistor MN4 is connected to the RC adjustment module. The control terminal of the control transistor MN4 generates a corresponding control voltage based on the second operational current I4 obtained by adding the second current IB2 and the second sampling current IS2 and subtracting it from the first operational current I3.
[0048] The RC adjustment module includes an adjusting transistor MN5, a resistor R1, and a capacitor C1. The control terminal of the adjusting transistor MN5 is connected to the control terminal of the control transistor MN4 of the voltage generation module. In one embodiment, the adjusting transistor MN5 and the control transistor MN4 also form a current mirror, allowing the adjusting transistor MN5 to proportionally mirror the current on the control transistor MN4. The second terminal of the adjusting transistor MN5 is connected to the first terminal of the resistor R1, the first terminal of the resistor R1 is connected to the first terminal of the capacitor C1, the first terminal of the adjusting transistor MN5 is connected to the reference voltage, and the second terminal of the capacitor C1 is connected to the output terminal VEA of the error amplifier EA. Under the control of the control voltage, the on-resistance of the adjusting transistor MN5 changes with the change of the control voltage, and a variable zero point is obtained by combining the resistor R1 and the capacitor C1. In other embodiments, the order of the resistor R1 and the capacitor C1 can be interchanged, and the resistor R1 can be omitted.
[0049] The second current generating unit 15 includes a second current source A2. The first terminal of the second current source A2 is connected to the second terminal of the fourth transistor MN3, the second terminal of the control transistor MN4, and the second terminal of the second sampling transistor MP2. The second terminal of the second current source A2 is connected to the input voltage VIN. The second current source A2 is used to generate a second current IB2.
[0050] The power transistor MP0, the first sampling transistor MP1, and the second sampling transistor MP2 are P-channel insulated gate field effect transistors, and the first transistor MN0, the second transistor MN1, the third transistor MN2, the fourth transistor MN3, the control transistor MN4, and the regulating transistor MN5 are N-channel insulated gate field effect transistors. In other embodiments, the power transistor MP0, the first sampling transistor MP1, and the second sampling transistor MP2 are N-channel insulated gate field effect transistors, and the first transistor MN0, the second transistor MN1, the third transistor MN2, the fourth transistor MN3, the control transistor MN4, and the regulating transistor MN5 are P-channel insulated gate field effect transistors.
[0051] The first ends of the power transistor MP0, the first sampling transistor MP1, the first transistor MN0, the second transistor MN1, the third transistor MN2, the fourth transistor MN3, the second sampling transistor MP2, the control transistor MN4, and the regulating transistor MN5 are source electrodes; the second ends of the power transistor MP0, the first sampling transistor MP1, the first transistor MN0, the second transistor MN1, the third transistor MN2, the fourth transistor MN3, the second sampling transistor MP2, the control transistor MN4, and the regulating transistor MN5 are drain electrodes; the control ends of the power transistor MP0, the first sampling transistor MP1, the first transistor MN0, the second transistor MN1, the third transistor MN2, the fourth transistor MN3, the second sampling transistor MP2, the control transistor MN4, and the regulating transistor MN5 are gate electrodes.
[0052] In one embodiment, the aspect ratio of the first sampling transistor MP1 to the power transistor MP0 is 1:K1; the aspect ratio of the second sampling transistor MP2 to the power transistor MP0 is 1:K2. Therefore, the current IS1 on the first sampling transistor MP1 = ILOAD / K1, the current IS2 on the second sampling transistor MP2 = ILOAD / K2, and ILOAD is the current on the power transistor MP0.
[0053] And when ILOAD < K1×IB1, there is a first sampling current I1 = IS1, the current I2 on the third transistor MN2 = IB1 - I1 = IB1 - IS1, and the first operational current I3 = I2.
[0054] Therefore, the current on the control transistor MN4 .
[0055] According to the saturation region current formula of the MOS transistor, the drain-source voltage of the control transistor MN4 can be calculated as
[0056]
[0057] Thus, the equivalent impedance of the regulating transistor MN5 is calculated as:
[0058]
[0059]
[0060] where K is the ratio of the width-to-length ratio of the regulating transistor MN5 to that of the control transistor MN4, is the electron mobility, is the capacitance per unit area of the gate oxide layer, and W / L is the width-to-length ratio of the control transistor MN4.
[0061] Therefore, when ILOAD = 0,
[0062]
[0063] the compensation zero point is
[0064]
[0065] where, under light load conditions, R1 ≪ R5 and IB2 > IB1; therefore, under no-load conditions, the zero point is mainly determined by the first current IB1, the second current IB2, and the capacitor C1.
[0066] When ILOAD ≥ K1×IB1, IS1 ≥ IB1, then I1 = IB1 and I2 = 0, and thus:
[0067]
[0068] the compensated zero point is:
[0069]
[0070] The compensated zero point is independent of the first current IB1 and is mainly determined by ILOAD and the capacitor C1;
[0071] When 0 < ILOAD < K1×IB1,
[0072]
[0073] the compensated zero point is:
[0074]
[0075] The compensated zero point is related to ILOAD. The larger ILOAD is, the smaller R5 is, and the more backward the zero point is.
[0076] The zero point compensation unit 10 enables the position of the zero point generated under different load conditions to accurately follow the load change. It can ensure that the compensated zero point in the light load range can still follow the load change, thus better guaranteeing the output stability.
[0077] By adjusting the ratio of the first current IB1 and the second current IB2 according to the required output load range, stability compensation can be precisely achieved within a small range such as 1mA-10mA, while ensuring stable output voltage of the output capacitor within a wide range of 0.47uF to 220uF.
[0078] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0079] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A linear voltage regulator, characterized in that, include: The system includes an error amplifier, a buffer unit, a power transistor, a feedback unit, and a zero-point compensation unit. The first input terminal of the error amplifier is connected to a reference voltage. The output terminal of the error amplifier is connected to the control terminal of the power transistor through the buffer unit. The first terminal of the power transistor is connected to the input voltage. The second terminal of the power transistor is connected to the feedback unit to form the output terminal of a linear regulator. The feedback unit generates a feedback voltage based on the output voltage of the linear regulator. The second input terminal of the error amplifier is used to receive the feedback voltage. The zero-point compensation unit includes: The first sampling unit is connected to the control terminal of the power transistor to sample the current on the power transistor to obtain the first sampling current; The first current generating unit is used to generate a first current. The arithmetic unit is connected to the first sampling unit and the first current generation unit to obtain the first arithmetic current based on the first sampling current and the first current. The second sampling unit is connected to the control terminal of the power transistor to sample the current on the power transistor to obtain the second sampling current; A second current generating unit is used to generate a second current; and A zero-point generation unit is connected to the arithmetic unit, the second sampling unit, and the second current generation unit to generate a zero point that varies with the current based on the first arithmetic current, the second current, and the second sampling current. The zero-point generation unit is connected to the output terminal of the error amplifier to perform zero-point adjustment on the output terminal of the error amplifier.
2. The linear voltage regulator according to claim 1, characterized in that, The first sampling unit includes a first sampling tube and a first current mirror. The control terminal of the first sampling tube is connected to the control terminal of the power tube. The first terminal of the first sampling tube is connected to the input voltage. The first current mirror is connected to the second terminal of the first sampling tube, the first current generation unit, and the arithmetic unit. The first current mirror is used to mirror the current on the first sampling tube to generate a first sampling current.
3. The linear voltage regulator according to claim 1, characterized in that, The computing unit includes a second current mirror, which is connected to the first current generation unit and the first sampling unit. The second current mirror is used to obtain the difference current between the first sampling current and the first current, and to generate the first computing current through the mirror difference current.
4. The linear voltage regulator according to claim 1, characterized in that, The second sampling unit includes a second sampling tube, the first end of which is connected to the input voltage, the control end of which is connected to the control end of the power tube, and the second end of which is connected to the second current generation unit, the arithmetic unit, and the zero-point generation unit.
5. The linear voltage regulator according to claim 1, characterized in that, The zero-point generation unit includes a voltage generation module and an RC adjustment module. The voltage generation module is used to generate a second operational current based on a first operational current, a second current, and a second sampling current, and to generate a control voltage that varies with the second operational current based on the second operational current. The RC adjustment module is connected to the voltage generation module and the output terminal of the error amplifier to adjust its own capacitance and / or resistance value based on the control voltage to generate a corresponding zero point.
6. The linear voltage regulator according to claim 5, characterized in that, The voltage generation module includes a control transistor. The second terminal of the control transistor is connected to the control terminal of the control transistor, the arithmetic unit, the second sampling unit, and the second current generation unit. The control terminal of the control transistor is connected to the RC adjustment module.
7. The linear voltage regulator according to claim 5, characterized in that, The RC adjustment module includes an adjustment tube and a capacitor. The control terminal of the adjustment tube is connected to the voltage generation module, the second terminal of the adjustment tube is connected to the first terminal of the capacitor, the first terminal of the adjustment tube is connected to the reference voltage, and the second terminal of the capacitor is connected to the output terminal of the error amplifier.
8. The linear regulator according to claim 7, characterized in that, The RC adjustment module also includes a resistor, which is connected in series with a capacitor and connected to the second terminal of the adjustment tube and the output terminal of the error amplifier.
9. The linear voltage regulator according to claim 2, characterized in that, The first current mirror includes a first transistor and a second transistor. The second terminal of the first transistor is connected to the control terminal of the first transistor, the second terminal of the first sampling transistor, and the control terminal of the second transistor. The second terminal of the second transistor is connected to the first current generating unit and the arithmetic unit. The first terminal of the first transistor and the first terminal of the second transistor are connected to the reference voltage.
10. The linear regulator according to claim 3, characterized in that, The second current mirror includes a third transistor and a fourth transistor. The second terminal of the third transistor is connected to the control terminal of the third transistor, the first current generating unit, and the first sampling unit. The second terminal of the fourth transistor is connected to the second current generating unit, the second sampling unit, and the zero-point generating unit. The first terminals of the third transistor and the fourth transistor are connected to a reference voltage.