High-order temperature compensation band-gap reference circuit with high power supply rejection ratio based on CMOS (complementary metal oxide semiconductor) process

Abstract

The invention discloses a CMOS (Complementary Metal Oxide Semiconductor) process-based high-order temperature compensation band-gap reference circuit with a high power supply rejection ratio, which comprises a starting and biasing circuit, an operational amplifier circuit and a band-gap reference main body circuit which are connected in sequence, the circuit can simultaneously realize low temperature coefficient, low offset voltage and high power supply rejection ratio in a wide temperature range, the bit number requirement of the trimming circuit is reduced by reducing the offset voltage, the chip area is effectively controlled, and the increasingly improved performance and cost requirements of a modern integrated circuit on a reference voltage source are met.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits and relates to a high-order temperature-compensated bandgap reference circuit with high power supply rejection ratio based on CMOS technology. Background Technology

[0002] The bandgap reference voltage source is a core module in analog and mixed-signal integrated circuits. Its function is to generate a stable reference voltage that is independent of power supply voltage, process technology, and temperature variations. The accuracy and stability of this voltage directly determine the performance of the entire system. For example, the performance of high-precision analog-to-digital converters, power management chips, and radio frequency chips all depend on a high-quality reference voltage.

[0003] Traditional first-order temperature-compensated bandgap reference circuits theoretically achieve zero temperature coefficient at a specific temperature point by adding two voltages with opposite temperature coefficients (the base-emitter voltage VBE of the transistor and the thermal voltage VT) with appropriate weights. However, VBE itself has a high-order nonlinear temperature term, which causes the reference output voltage to exhibit significant curvature changes over a wide temperature range, limiting further optimization of the temperature coefficient. Furthermore, as modern CMOS processes move towards lower supply voltages, the output voltage swing and accuracy design of traditional structures face severe challenges. Additionally, the input offset voltage of operational amplifiers introduces reference errors, typically requiring complex trimming circuits for compensation, which not only increases chip area but also raises testing costs. Simultaneously, fluctuations in the supply voltage can couple to the reference output through paths such as current mirrors and device channel modulation effects, leading to a decrease in its power supply rejection ratio (PSRR) performance, making it difficult to meet the requirements of high-precision applications.

[0004] Therefore, there is an urgent need for a new bandgap reference circuit structure based on standard CMOS technology that can simultaneously achieve low temperature coefficient, low offset voltage, and high power supply rejection ratio over a wide temperature range. By reducing the offset voltage, the bit requirement of the trimming circuit can be reduced, thereby effectively controlling the chip area and meeting the increasingly demanding performance and cost requirements of modern integrated circuits for reference voltage sources. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-order temperature-compensated bandgap reference circuit with high power supply rejection ratio based on CMOS technology. This circuit can simultaneously achieve low temperature coefficient, low offset voltage and high power supply rejection ratio over a wide temperature range. By reducing the offset voltage, the bit requirement of the trimming circuit is reduced, effectively controlling the chip area and meeting the increasingly higher performance and cost requirements of modern integrated circuits for reference voltage sources.

[0006] To achieve the above objectives, this invention discloses a high-order temperature-compensated bandgap reference circuit with high power supply rejection ratio based on CMOS technology, comprising a startup and bias circuit, an operational amplifier circuit, and a bandgap reference main circuit, wherein the startup and bias circuit, the operational amplifier circuit, and the bandgap reference main circuit are connected in sequence.

[0007] Furthermore, the startup and bias circuit includes MOSFETs PM1, PM2, PM3, NM1, NM2, NM3, and NM4; wherein, the gate of MOSFET PM1 is connected to ground (GND), the source of MOSFET PM1 is connected to the power supply (VCC), and the drain of MOSFET PM1 is connected to the gate of MOSFET NM2 and the drain of MOSFET NM1; the gate of MOSFET PM2 is connected to the output terminal VP of the startup and bias circuit, the source of MOSFET PM2 is connected to the power supply (VCC), and the drain of MOSFET PM2 is connected to the output terminal VN of the startup and bias circuit; the gate of MOSFET PM3 is connected to the output terminal VP of the startup and bias circuit, the source of MOSFET PM3 is connected to the power supply (VCC), and the drain of MOSFET PM3 is connected to the output terminal VP of the startup and bias circuit; MOSFET PM4... The gate of NM1 is connected to the output terminal VN of the startup and bias circuit. The source of MOSFET NM1 is connected to ground GND. The drain of MOSFET NM1 is connected to the drain of MOSFET PM1 and the gate of MOSFET NM2. The gate of MOSFET NM2 is connected to the drain of MOSFET PM1 and the drain of MOSFET NM1. The source of MOSFET NM2 is connected to ground GND. The drain of MOSFET NM2 is connected to the output terminal VP of the startup and bias circuit. The gate of MOSFET NM3 is connected to the output VN of the startup and bias circuit. The source of MOSFET NM3 is connected to ground GND. The drain of MOSFET NM3 is connected to the output terminal VN of the startup and bias circuit. The gate of MOSFET NM4 is connected to the output terminal VN of the startup and bias circuit. The source of MOSFET NM4 is connected to ground GND. The drain of MOSFET NM4 is connected to the output terminal VP of the startup and bias circuit.

[0008] Furthermore, the operational amplifier circuit includes internal operational amplifier A1, internal operational amplifier A2, MOSFET PM4, MOSFET PM5, MOSFET PM6, MOSFET PM7, MOSFET PM8, MOSFET PM9, MOSFET PM10, MOSFET NM5, MOSFET NM6, MOSFET NM7, MOSFET NM8, MOSFET NM9 and MOSFET NM10; In this configuration, the gate of MOSFET PM4 is connected to the gate of MOSFET PM7, the drain of MOSFET PM5, and the drain of MOSFET NM5, respectively. The source of MOSFET PM4 is connected to the power supply VCC, and the drain of MOSFET PM4 is connected to the inverting input of internal operational amplifier A2 and the source of MOSFET PM5, respectively. The gate of MOSFET PM5 is connected to the non-inverting output of internal operational amplifier A2, and the source of MOSFET PM5 is connected to the inverting input of internal operational amplifier A2 and the drain of MOSFET PM4, respectively. The drain of MOSFET PM5 is connected to the gate of MOSFET PM4, the gate of MOSFET PM7, and the drain of MOSFET NM5, respectively. MOSFET PM6... The gate of MOSFET PM6 is connected to the output terminal VP of the startup and bias circuit. The source of MOSFET PM6 is connected to the power supply VCC. The drain of MOSFET PM6 is connected to the sources of MOSFET PM9 and MOSFET PM10, respectively. The gate of MOSFET PM7 is connected to the gate of MOSFET PM4, the drain of MOSFET PM5, and the drain of MOSFET NM5, respectively. The source of MOSFET PM7 is connected to the power supply VCC. The drain of MOSFET PM7 is connected to the non-inverting input terminal of internal operational amplifier A2 and the source terminal of MOSFET PM8, respectively. The gate of MOSFET PM8 is connected to the inverting output terminal of internal operational amplifier A2. The source of MOSFET PM8 is connected to the non-inverting output terminal of internal operational amplifier A2, respectively. The input terminal of MOSFET PM8 is connected to the drain of MOSFET PM7, and the drain of MOSFET PM8 is connected to the output terminal VZ of the operational amplifier circuit. The gate of MOSFET PM9 is connected to the input terminal VX of the operational amplifier circuit. The source of MOSFET PM9 is connected to the drain of MOSFET PM6 and the source of MOSFET PM10, respectively. The drain of MOSFET PM9 is connected to the gate of MOSFET NM7, the drain of MOSFET NM7, and the gate of MOSFET NM6, respectively. The gate of MOSFET PM10 is connected to the output terminal VY of the operational amplifier circuit, and the drain of MOSFET PM10 is connected to the gate of MOSFET NM8, the drain of MOSFET NM8, and the gate of MOSFET NM10, respectively. The gate of M5 is connected to the inverting output of the internal operational amplifier A1. The source of MOSFET NM5 is connected to the non-inverting input of the internal operational amplifier A1 and the drain of MOSFET NM6. The drain of MOSFET NM5 is connected to the drain of MOSFET PM5, the gate of MOSFET PM4, and the gate of MOSFET PM7. The source of MOSFET NM6 is connected to ground (GND). The drain of MOSFET NM6 is connected to the non-inverting input of the internal operational amplifier A1 and the source of MOSFET NM5. The gate of MOSFET NM7 is connected to the drain of MOSFET NM7, the drain of MOSFET PM9, and the gate of MOSFET NM6. The source of MOSFET NM7 is connected to ground (GND).The gate of MOSFET NM8 is connected to the drain of MOSFET NM8, the drain of MOSFET PM10, and the gate of MOSFET NM10. The source of MOSFET NM8 is connected to ground (GND). The drain of MOSFET NM8 is connected to the gate of MOSFET NM8, the drain of MOSFET PM10, and the gate of MOSFET NM10. The gate of MOSFET NM9 is connected to the non-inverting output of internal operational amplifier A1. The source of MOSFET NM9 is connected to the drain of NM10 and the inverting input of internal operational amplifier A1. The drain of NM9 is connected to the output VZ of the operational amplifier. The gate of MOSFET NM10 is connected to the gate of MOSFET NM8, the drain of MOSFET NM8, and the drain of MOSFET PM10. The source of MOSFET NM10 is connected to ground (GND). The drain of MOSFET NM10 is connected to the source of MOSFET NM9 and the inverting input of internal operational amplifier A1.

[0009] Furthermore, the bandgap reference main circuit includes MOSFETs PM11, PM12, PM13, PM14, PM15, PM16, PM17, and PM18; resistors R1, R2, R3, R4, R5, and R6; and transistors Q1, Q2, and Q3. The gate of MOSFET PM11 is connected to the output terminal VZ of the operational amplifier, the source of MOSFET PM11 is connected to the power supply VCC, and the drain of MOSFET PM11 is connected to the source of MOSFET PM12. The gate of MOSFET PM12 is connected to the input terminal VX of the operational amplifier. The source of MOSFET PM2 is connected to the drain of MOSFET PM11; the drain of MOSFET PM12 is connected to the input terminal VX of the operational amplifier; the gate of MOSFET PM13 is connected to the output terminal VZ of the operational amplifier; the source of MOSFET PM13 is connected to the power supply VCC; the drain of MOSFET PM13 is connected to the source of MOSFET PM14; the gate of MOSFET PM14 is connected to the input terminal VX of the operational amplifier; the source of MOSFET PM14 is connected to the drain of MOSFET PM13; the drain of MOSFET PM14 is connected to the input terminal VY of the operational amplifier; the gate of MOSFET PM15 is connected to the output terminal VZ of the operational amplifier circuit; the source of MOSFET PM15 is connected to the power supply VCC. The drain of transistor PM15 is connected to the source of MOSFET PM16; the gate of PM16 is connected to the input VX of the operational amplifier, and the source of PM16 is connected to the drain of PM15; the gate of MOSFET PM17 is connected to the output VZ of the operational amplifier, the source of MOSFET PM17 is connected to the power supply VCC, and the drain of MOSFET PM17 is connected to the source of MOSFET PM18; the gate of MOSFET PM18 is connected to the input VX of the operational amplifier, the source of MOSFET PM18 is connected to the drain of MOSFET PM17, and the drain of MOSFET PM18 is connected to the output VOUT; one end of resistor R1 is connected to the input VX of the operational amplifier, and the other end of resistor R1 is connected to ground GND; One end of resistor R2 is connected to the input terminal VY of the operational amplifier, and the other end of resistor R2 is connected to the emitter of transistor Q2; one end of resistor R3 is connected to the input terminal VY of the operational amplifier, and the other end of resistor R3 is connected to ground GND; one end of resistor R4 is connected to the input terminal VX of the operational amplifier, and the other end of resistor R4 is connected to the other end of resistor R5, the drain of MOSFET PM16, and the emitter of transistor Q3; one end of resistor R5 is connected to the input terminal VX of the operational amplifier, and the other end of resistor R5 is connected to the other end of resistor R4, the drain of MOSFET PM16, and the emitter of transistor Q3; one end of resistor R6 is connected to the output VOUT, and the other end of resistor R6 is connected to ground GND.The base of transistor Q1 is connected to ground GND, the collector of transistor Q1 is connected to ground GND, and the emitter of transistor Q1 is connected to the input terminal VX of the operational amplifier; the base of transistor Q2 is connected to ground GND, and the collector of transistor Q2 is connected to ground GND; the base of transistor Q3 is connected to ground GND, the collector of transistor Q3 is connected to ground GND, and the emitter of transistor Q3 is connected to the other end of resistor R4, the other end of resistor R5, and the drain of MOSFET PM16. Furthermore, the internal operational amplifier circuit includes MOSFETs NM11, NM12, NM13, NM14, NM15, PM19, PM20, PM21, PM22, and PM23, as well as resistors R7, R8, R9, and R10; wherein VIP+, VIP-, VOP+, and VOP- are the non-inverting input, inverting input, non-inverting output, and inverting output terminals of operational amplifier A1, respectively; and VIN+, VIN-, VON+, and VON- are the non-inverting input, inverting input, non-inverting output, and inverting output terminals of operational amplifier A2, respectively. The gate of MOSFET NM11 is connected to the gate of MOSFET NM12, one end of resistor R7, and one end of resistor R8, respectively. The source of MOSFET NM11 is connected to ground (GND), and the drain of MOSFET NM11 is connected to the non-inverting output terminal VOP+ of operational amplifier A1. The source of MOSFET NM12 is connected to ground (GND), and the drain of MOSFET NM12 is connected to the inverting output terminal VOP- of operational amplifier A1. The gate of MOSFET NM13 is connected to the non-inverting input terminal VIN+ of operational amplifier A2. The source of MOSFET NM13 is connected to the source of MOSFET NM14 and the drain of MOSFET NM15, respectively. The drain of MOSFET NM13 is connected to the inverting output terminal VIN+ of operational amplifier A2. ON- is connected; the gate of MOSFET NM14 is connected to the inverting input terminal VIN- of operational amplifier A2, the source of MOSFET NM14 is connected to the source of MOSFET NM13 and the drain of MOSFET NM15, and the drain of MOSFET NM14 is connected to the non-inverting output terminal VON+ of operational amplifier A2; the gate of MOSFET NM15 is connected to the output terminal VN of the startup and bias circuit, and the source of MOSFET NM15 is connected to ground GND; the gate of MOSFET PM19 is connected to the output terminal VP of the startup and bias circuit, the source of MOSFET PM19 is connected to the power supply VCC, and the drain of MOSFET PM19 is connected to the source of MOSFET PM20 and the source of MOSFET PM21. The gate of MOSFET PM20 is connected to the inverting input terminal VIP- of operational amplifier A1. The source of MOSFET PM20 is connected to the drain of MOSFET PM19 and the source of MOSFET PM21. The drain of MOSFET PM20 is connected to the non-inverting output terminal VOP+ of operational amplifier A1. The gate of MOSFET PM21 is connected to the non-inverting input terminal VIP+ of operational amplifier A1. The source of MOSFET PM21 is connected to the drain of MOSFET PM19 and the source of MOSFET PM20. The drain of MOSFET PM21 is connected to the inverting output terminal VOP- of operational amplifier A1. The gate of MOSFET PM22 is connected to the gate of MOSFET PM23, one end of resistor R9, and resistor R12. One end of R10 is connected to the source of MOSFET PM22, which is connected to the power supply VCC. The drain of MOSFET PM22 is connected to the inverting output terminal VON- of operational amplifier A2. The gate of MOSFET PM23 is connected to the gate of MOSFET PM22, one end of resistor R9, and one end of resistor R10. The source of MOSFET PM23 is connected to the power supply VCC. The drain of MOSFET PM23 is connected to the non-inverting output terminal VON+ of operational amplifier A2. The other end of resistor R7 is connected to the non-inverting output terminal VOP+ of operational amplifier A1. The other end of resistor R8 is connected to the inverting output terminal VOP- of operational amplifier A1. The other end of resistor R9 is connected to the inverting output terminal VON- of operational amplifier A2.The other end of resistor R10 is connected to the non-inverting output terminal VON+ of operational amplifier A2.

[0010] Furthermore, resistors R1, R3, R4, and R5 are adjustable resistors.

[0011] Furthermore, the resistance value of resistor R1 is equal to the resistance value of resistor R3.

[0012] Furthermore, the resistance value of resistor R4 is equal to the resistance value of resistor R5.

[0013] Furthermore, the current flowing through resistors R4 and R5 is:

[0014] in, For 300K, V represents temperature. T Thermoelectric voltage, This is the resistance value of resistor R4.

[0015] Furthermore, the expression for the output voltage is:

[0016] Among them, resistors R1 and R3 have the same resistance value, and resistors R4 and R5 have the same resistance value. V T is the thermal voltage, and n is the ratio of the junction area of ​​transistor Q2 to that of transistor Q1.

[0017] The present invention has the following beneficial effects: The high-power supply rejection ratio (PSRR) high-order temperature-compensated bandgap reference circuit based on CMOS technology described in this invention significantly enhances loop gain and output impedance through the coordinated operation of a gain-boosting operational amplifier and a cascode current mirror, thereby achieving an extremely high PSRR over a wide bandwidth. Furthermore, this invention introduces a high-order temperature compensation network to precisely cancel the nonlinear temperature term of the transistor's VBE voltage, ensuring ultra-low temperature drift of the output voltage over a wide temperature range. Simultaneously, the use of a high-gain operational amplifier structure with common-mode feedback effectively reduces system offset, minimizing the area of ​​the adjustment section while comprehensively improving the accuracy and stability of the reference voltage, thus comprehensively solving the technical challenges of high PSRR and low temperature coefficient. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1a This is a circuit diagram of the present invention; Figure 1b This is a circuit diagram of the internal operational amplifier A1 and internal operational amplifier A2 in this invention; Figure 2 The output voltage power supply rejection ratio waveform is shown in the simulation experiment. Figure 3 This is a simulation diagram of the output voltage temperature coefficient in a simulation experiment. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] In the description of this invention, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0022] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0023] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this invention generally indicates that the preceding and following objects have an "or" relationship.

[0024] It should be understood that although terms such as first, second, third, etc., may be used in the embodiments of the present invention to describe the preset range, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0025] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0027] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0028] refer to Figure 1a The high-order temperature-compensated bandgap reference circuit based on CMOS technology with high power supply rejection ratio described in this invention includes a startup and bias circuit, an operational amplifier circuit, and a bandgap reference main circuit, wherein the startup and bias circuit, the operational amplifier circuit, and the bandgap reference main circuit are connected in sequence.

[0029] The startup and bias circuit includes MOSFETs PM1, PM2, PM3, NM1, NM2, NM3, and NM4. The gate of MOSFET PM1 is connected to ground (GND), the source of MOSFET PM1 is connected to the power supply (VCC), and the drain of MOSFET PM1 is connected to both the gate of MOSFET NM2 and the drain of MOSFET NM1. The gate of MOSFET PM2 is connected to the output terminal VP of the startup and bias circuit, the source of MOSFET PM2 is connected to the power supply (VCC), and the drain of MOSFET PM2 is connected to the output terminal VN of the startup and bias circuit. The gate of MOSFET PM3 is connected to the output terminal VP of the startup and bias circuit, the source of MOSFET PM3 is connected to the power supply (VCC), and the drain of MOSFET PM3 is connected to the output terminal VP of the startup and bias circuit. The gate of transistor NM1 is connected to the output terminal VN of the startup and bias circuit. The source of transistor NM1 is connected to ground GND. The drain of transistor NM1 is connected to the drain of transistor PM1 and the gate of transistor NM2. The gate of transistor NM2 is connected to the drain of transistor PM1 and the drain of transistor NM1. The source of transistor NM2 is connected to ground GND. The drain of transistor NM2 is connected to the output terminal VP of the startup and bias circuit. The gate of transistor NM3 is connected to the output VN of the startup and bias circuit. The source of transistor NM3 is connected to ground GND. The drain of transistor NM3 is connected to the output terminal VN of the startup and bias circuit. The gate of transistor NM4 is connected to the output terminal VN of the startup and bias circuit. The source of transistor NM4 is connected to ground GND. The drain of transistor NM4 is connected to the output terminal VP of the startup and bias circuit. The operational amplifier circuit includes internal operational amplifier A1, internal operational amplifier A2, MOSFET PM4, MOSFET PM5, MOSFET PM6, MOSFET PM7, MOSFET PM8, MOSFET PM9, MOSFET PM10, MOSFET NM5, MOSFET NM6, MOSFET NM7, MOSFET NM8, MOSFET NM9 and MOSFET NM10; In this configuration, the gate of MOSFET PM4 is connected to the gate of MOSFET PM7, the drain of MOSFET PM5, and the drain of MOSFET NM5, respectively. The source of MOSFET PM4 is connected to the power supply VCC, and the drain of MOSFET PM4 is connected to the inverting input of internal operational amplifier A2 and the source of MOSFET PM5, respectively. The gate of MOSFET PM5 is connected to the non-inverting output of internal operational amplifier A2, and the source of MOSFET PM5 is connected to the inverting input of internal operational amplifier A2 and the drain of MOSFET PM4, respectively. The drain of MOSFET PM5 is connected to the gate of MOSFET PM4, the gate of MOSFET PM7, and the drain of MOSFET NM5, respectively. MOSFET PM6... The gate of MOSFET PM6 is connected to the output terminal VP of the startup and bias circuit. The source of MOSFET PM6 is connected to the power supply VCC. The drain of MOSFET PM6 is connected to the sources of MOSFET PM9 and MOSFET PM10, respectively. The gate of MOSFET PM7 is connected to the gate of MOSFET PM4, the drain of MOSFET PM5, and the drain of MOSFET NM5, respectively. The source of MOSFET PM7 is connected to the power supply VCC. The drain of MOSFET PM7 is connected to the non-inverting input terminal of internal operational amplifier A2 and the source terminal of MOSFET PM8, respectively. The gate of MOSFET PM8 is connected to the inverting output terminal of internal operational amplifier A2. The source of MOSFET PM8 is connected to the non-inverting output terminal of internal operational amplifier A2, respectively. The input terminal of MOSFET PM8 is connected to the drain of MOSFET PM7, and the drain of MOSFET PM8 is connected to the output terminal VZ of the operational amplifier circuit. The gate of MOSFET PM9 is connected to the input terminal VX of the operational amplifier circuit. The source of MOSFET PM9 is connected to the drain of MOSFET PM6 and the source of MOSFET PM10, respectively. The drain of MOSFET PM9 is connected to the gate of MOSFET NM7, the drain of MOSFET NM7, and the gate of MOSFET NM6, respectively. The gate of MOSFET PM10 is connected to the output terminal VY of the operational amplifier circuit, and the drain of MOSFET PM10 is connected to the gate of MOSFET NM8, the drain of MOSFET NM8, and the gate of MOSFET NM10, respectively. The gate of M5 is connected to the inverting output of the internal operational amplifier A1. The source of MOSFET NM5 is connected to the non-inverting input of the internal operational amplifier A1 and the drain of MOSFET NM6. The drain of MOSFET NM5 is connected to the drain of MOSFET PM5, the gate of MOSFET PM4, and the gate of MOSFET PM7. The source of MOSFET NM6 is connected to ground (GND). The drain of MOSFET NM6 is connected to the non-inverting input of the internal operational amplifier A1 and the source of MOSFET NM5. The gate of MOSFET NM7 is connected to the drain of MOSFET NM7, the drain of MOSFET PM9, and the gate of MOSFET NM6. The source of MOSFET NM7 is connected to ground (GND).The gate of MOSFET NM8 is connected to the drain of MOSFET NM8, the drain of MOSFET PM10, and the gate of MOSFET NM10. The source of MOSFET NM8 is connected to ground (GND). The drain of MOSFET NM8 is connected to the gate of MOSFET NM8, the drain of MOSFET PM10, and the gate of MOSFET NM10. The gate of MOSFET NM9 is connected to the non-inverting output of internal operational amplifier A1. The source of MOSFET NM9 is connected to the drain of NM10 and the inverting input of internal operational amplifier A1. The drain of NM9 is connected to the output VZ of the operational amplifier. The gate of MOSFET NM10 is connected to the gate of MOSFET NM8, the drain of MOSFET NM8, and the drain of MOSFET PM10. The source of MOSFET NM10 is connected to ground (GND). The drain of MOSFET NM10 is connected to the source of MOSFET NM9 and the inverting input of internal operational amplifier A1.

[0030] The bandgap reference circuit includes MOSFETs PM11, PM12, PM13, PM14, PM15, PM16, PM17, and PM18; resistors R1, R2, R3, R4, R5, and R6; and transistors Q1, Q2, and Q3. The gate of MOSFET PM11 is connected to the output terminal VZ of the operational amplifier, the source of MOSFET PM11 is connected to the power supply VCC, and the drain of MOSFET PM11 is connected to the source of MOSFET PM12. The gate of MOSFET PM12 is connected to the input terminal VX of the operational amplifier, and the source of MOSFET PM12... The gate of MOSFET PM13 is connected to the drain of MOSFET PM11, and the drain of MOSFET PM12 is connected to the input terminal VX of the operational amplifier. The gate of MOSFET PM13 is connected to the output terminal VZ of the operational amplifier, the source of MOSFET PM13 is connected to the power supply VCC, and the drain of MOSFET PM13 is connected to the source of MOSFET PM14. The gate of MOSFET PM14 is connected to the input terminal VX of the operational amplifier, the source of MOSFET PM14 is connected to the drain of MOSFET PM13, and the drain of MOSFET PM14 is connected to the input terminal VY of the operational amplifier. The gate of MOSFET PM15 is connected to the output terminal VZ of the operational amplifier circuit, and the source of MOSFET PM15 is connected to the power supply VCC. The drain of M15 is connected to the source of MOSFET PM16; the gate of PM16 is connected to the input VX of the operational amplifier, and the source of PM16 is connected to the drain of PM15; the gate of MOSFET PM17 is connected to the output VZ of the operational amplifier, the source of MOSFET PM17 is connected to the power supply VCC, and the drain of MOSFET PM17 is connected to the source of MOSFET PM18; the gate of MOSFET PM18 is connected to the input VX of the operational amplifier, the source of MOSFET PM18 is connected to the drain of MOSFET PM17, and the drain of MOSFET PM18 is connected to the output VOUT; one end of resistor R1 is connected to the input VX of the operational amplifier, and the other end of resistor R1 is connected to ground GND; resistor One end of resistor R2 is connected to the input terminal VY of the operational amplifier, and the other end of resistor R2 is connected to the emitter of transistor Q2; one end of resistor R3 is connected to the input terminal VY of the operational amplifier, and the other end of resistor R3 is connected to ground GND; one end of resistor R4 is connected to the input terminal VX of the operational amplifier, and the other end of resistor R4 is connected to the other end of resistor R5, the drain of MOSFET PM16, and the emitter of transistor Q3; one end of resistor R5 is connected to the input terminal VX of the operational amplifier, and the other end of resistor R5 is connected to the other end of resistor R4, the drain of MOSFET PM16, and the emitter of transistor Q3; one end of resistor R6 is connected to the output VOUT, and the other end of resistor R6 is connected to ground GND.The base of transistor Q1 is connected to ground GND, the collector of transistor Q1 is connected to ground GND, and the emitter of transistor Q1 is connected to the input terminal VX of the operational amplifier; the base of transistor Q2 is connected to ground GND, and the collector of transistor Q2 is connected to ground GND; the base of transistor Q3 is connected to ground GND, the collector of transistor Q3 is connected to ground GND, and the emitter of transistor Q3 is connected to the other end of resistor R4, the other end of resistor R5, and the drain of MOSFET PM16. The internal operational amplifier circuit includes MOSFETs NM11, NM12, NM13, NM14, NM15, PM19, PM20, PM21, PM22, and PM23, as well as resistors R7, R8, R9, and R10. VIP+, VIP-, VOP+, and VOP- are the non-inverting input, inverting input, non-inverting output, and inverting output terminals of operational amplifier A1, respectively; VIN+, VIN-, VON+, and VON- are the non-inverting input, inverting input, non-inverting output, and inverting output terminals of operational amplifier A2, respectively. The gate of MOSFET NM11 is connected to the gate of MOSFET NM12, one end of resistor R7, and one end of resistor R8, respectively. The source of MOSFET NM11 is connected to ground (GND), and the drain of MOSFET NM11 is connected to the non-inverting output terminal VOP+ of operational amplifier A1. The source of MOSFET NM12 is connected to ground (GND), and the drain of MOSFET NM12 is connected to the inverting output terminal VOP- of operational amplifier A1. The gate of MOSFET NM13 is connected to the non-inverting input terminal VIN+ of operational amplifier A2. The source of MOSFET NM13 is connected to the source of MOSFET NM14 and the drain of MOSFET NM15, respectively. The drain of MOSFET NM13 is connected to the inverting output terminal VIN+ of operational amplifier A2. ON- is connected; the gate of MOSFET NM14 is connected to the inverting input terminal VIN- of operational amplifier A2, the source of MOSFET NM14 is connected to the source of MOSFET NM13 and the drain of MOSFET NM15, and the drain of MOSFET NM14 is connected to the non-inverting output terminal VON+ of operational amplifier A2; the gate of MOSFET NM15 is connected to the output terminal VN of the startup and bias circuit, and the source of MOSFET NM15 is connected to ground GND; the gate of MOSFET PM19 is connected to the output terminal VP of the startup and bias circuit, the source of MOSFET PM19 is connected to the power supply VCC, and the drain of MOSFET PM19 is connected to the source of MOSFET PM20 and the source of MOSFET PM21. The gate of MOSFET PM20 is connected to the inverting input terminal VIP- of operational amplifier A1. The source of MOSFET PM20 is connected to the drain of MOSFET PM19 and the source of MOSFET PM21. The drain of MOSFET PM20 is connected to the non-inverting output terminal VOP+ of operational amplifier A1. The gate of MOSFET PM21 is connected to the non-inverting input terminal VIP+ of operational amplifier A1. The source of MOSFET PM21 is connected to the drain of MOSFET PM19 and the source of MOSFET PM20. The drain of MOSFET PM21 is connected to the inverting output terminal VOP- of operational amplifier A1. The gate of MOSFET PM22 is connected to the gate of MOSFET PM23, one end of resistor R9, and resistor R12. One end of R10 is connected to the source of MOSFET PM22, which is connected to the power supply VCC. The drain of MOSFET PM22 is connected to the inverting output terminal VON- of operational amplifier A2. The gate of MOSFET PM23 is connected to the gate of MOSFET PM22, one end of resistor R9, and one end of resistor R10. The source of MOSFET PM23 is connected to the power supply VCC. The drain of MOSFET PM23 is connected to the non-inverting output terminal VON+ of operational amplifier A2. The other end of resistor R7 is connected to the non-inverting output terminal VOP+ of operational amplifier A1. The other end of resistor R8 is connected to the inverting output terminal VOP- of operational amplifier A1. The other end of resistor R9 is connected to the inverting output terminal VON- of operational amplifier A2.The other end of resistor R10 is connected to the non-inverting output terminal VON+ of operational amplifier A2.

[0031] The resistors R1, R3, R4 and R5 are adjustable resistors, and R1=R3 and R4=R5.

[0032] The working principle of this invention is as follows: The startup and bias circuit provides bias voltage to the current mirror tube in the operational amplifier circuit, and at the same time provides current after the circuit is powered on, so that the main circuit of the bandgap reference can get rid of the degeneracy point and enter the normal working state. The bandgap reference circuit utilizes the clamping function of the operational amplifier circuit to keep the potentials at points VX and VY equal, and utilizes the BE junction voltage of the transistor. Negative temperature characteristics and transistor BE junction voltage difference The positive temperature coefficient characteristic allows for the acquisition of a voltage with a near-zero temperature coefficient. The high gain of the operational amplifier circuit can effectively reduce the offset of the operational amplifier input voltage and improve the power supply rejection ratio. Therefore, gain enhancement technology is used. The gain of the operational amplifier circuit is:

[0033] Where K is the width-to-length ratio of MOSFET NM10 to MOSFET NM8; g m r is the transconductance of the MOSFET. o A1 represents the AC impedance of the MOSFET, and A2 represents the gains of internal operational amplifiers A1 and A2, respectively.

[0034] For a transistor with a standard junction area, the BE junction voltage Based on the temperature characteristics of the flowing current, we can approximate the following:

[0035] in, The bandgap voltage at 300K. The BE junction voltage at 300K. For 300K, It refers to temperature, and its unit is Kelvin. V is a constant. T Thermoelectric voltage; Therefore, the current flowing through resistors R4 and R5 is a higher-order term of the transistor's BE junction voltage, i.e.:

[0036] The expression for the final output voltage is:

[0037] Among them, resistors R1 and R3 have the same resistance value, and resistors R4 and R5 have the same resistance value. V T Where is the thermal voltage, and n is the ratio of the junction area of ​​transistor Q2 to that of transistor Q1. Ultimately, by adjusting the resistance ratio appropriately, the bandgap reference voltage with low temperature drift can be obtained.

[0038] Simulation Experiment Simulation experimental conditions: The simulation experimental components of this invention are manufactured using TSMC 0.18µm technology, and the simulation circuit of this invention is built on the Cadence IC617 simulation experimental platform.

[0039] The circuit of this invention was simulated using the Spectre simulation tool, and the operating temperature was 27℃.

[0040] Simulation content: Simulation 1: This is a simulation of the power supply rejection ratio (PSRR). The results are as follows: Figure 2 As shown, the power supply rejection ratio (PSRR) is -84dB at low frequencies, and in the worst case, the PSRR is less than -10dB.

[0041] Simulation 2: Simulations were performed on the output voltage at different temperatures, and the results are as follows. Figure 3 As shown, the temperature drift coefficient is 2.82 ppm / ℃.

[0042] The theoretical analysis and simulation results above show that the high-order temperature-compensated bandgap reference circuit based on CMOS technology with high power supply rejection ratio proposed in this invention can meet the application requirements of high power supply rejection ratio and low temperature drift, and can meet the requirements of various integrated circuit applications with stringent requirements for reference voltage accuracy and stability.

[0043] This invention has the following characteristics: This invention combines an operational amplifier with gain-boosting technology with a cascode current mirror structure. This synergistic effect significantly improves the loop gain of the negative feedback loop, enhancing the system's ability to suppress power supply noise. Furthermore, the high output impedance of the cascode structure effectively blocks power supply fluctuations from coupling to the output via the current mirror. These dual measures together ensure an extremely high power supply rejection ratio across a wide frequency range, from DC to higher frequencies.

[0044] This invention introduces a high-order temperature compensation network based on traditional first-order temperature compensation. This network generates a compensation amount that cancels out the high-order nonlinear temperature term of the bipolar transistor's base-emitter voltage (VBE) through precise resistance ratios and current relationships, effectively "flattening" the curve of the reference output voltage versus temperature. Simultaneously, resistor adjustments ensure that the circuit maintains extremely low temperature drift over a wide temperature range at different process angles, significantly improving the accuracy and stability of the reference voltage.

[0045] The operational amplifier in this invention employs gain enhancement technology and a five-transistor OTA structure with common-mode feedback. These combined effects significantly improve the open-loop gain and common-mode rejection ratio of the operational amplifier, and effectively reduce the system offset voltage. This results in a reduction in the number of resistor trimming bits and the trimming circuit area, while the core node voltage of the bandgap reference can be maintained more accurately, directly improving the initial accuracy and consistency of the reference output voltage.

[0046] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and disclosure of the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0047] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

[0048] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the present invention. Any simple modifications, alterations, or equivalent structural changes made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A high-order temperature-compensated bandgap reference circuit with high power supply rejection ratio based on CMOS technology, characterized in that, It includes a startup and bias circuit, an operational amplifier circuit, and a bandgap reference main circuit, wherein the startup and bias circuit, the operational amplifier circuit, and the bandgap reference main circuit are connected in sequence.

2. The high-order temperature-compensated bandgap reference circuit based on CMOS technology with high power supply rejection ratio according to claim 1, characterized in that, The startup and bias circuit includes MOSFETs PM1, PM2, PM3, NM1, NM2, NM3, and NM4. The gate of MOSFET PM1 is connected to ground (GND), the source of MOSFET PM1 is connected to the power supply (VCC), and the drain of MOSFET PM1 is connected to both the gate of MOSFET NM2 and the drain of MOSFET NM1. The gate of MOSFET PM2 is connected to the output terminal VP of the startup and bias circuit, the source of MOSFET PM2 is connected to the power supply (VCC), and the drain of MOSFET PM2 is connected to the output terminal VN of the startup and bias circuit. The gate of MOSFET PM3 is connected to the output terminal VP of the startup and bias circuit, the source of MOSFET PM3 is connected to the power supply (VCC), and the drain of MOSFET PM3 is connected to the output terminal VP of the startup and bias circuit. The gate of transistor NM1 is connected to the output terminal VN of the startup and bias circuit. The source of transistor NM1 is connected to ground GND. The drain of transistor NM1 is connected to the drain of transistor PM1 and the gate of transistor NM2. The gate of transistor NM2 is connected to the drain of transistor PM1 and the drain of transistor NM1. The source of transistor NM2 is connected to ground GND. The drain of transistor NM2 is connected to the output terminal VP of the startup and bias circuit. The gate of transistor NM3 is connected to the output VN of the startup and bias circuit. The source of transistor NM3 is connected to ground GND. The drain of transistor NM3 is connected to the output terminal VN of the startup and bias circuit. The gate of transistor NM4 is connected to the output terminal VN of the startup and bias circuit. The source of transistor NM4 is connected to ground GND. The drain of transistor NM4 is connected to the output terminal VP of the startup and bias circuit.

3. The high-order temperature-compensated bandgap reference circuit based on CMOS technology with high power supply rejection ratio according to claim 2, characterized in that, The operational amplifier circuit includes internal operational amplifier A1, internal operational amplifier A2, MOSFET PM4, MOSFET PM5, MOSFET PM6, MOSFET PM7, MOSFET PM8, MOSFET PM9, MOSFET PM10, MOSFET NM5, MOSFET NM6, MOSFET NM7, MOSFET NM8, MOSFET NM9 and MOSFET NM10; In this configuration, the gate of MOSFET PM4 is connected to the gate of MOSFET PM7, the drain of MOSFET PM5, and the drain of MOSFET NM5, respectively. The source of MOSFET PM4 is connected to the power supply VCC, and the drain of MOSFET PM4 is connected to the inverting input of internal operational amplifier A2 and the source of MOSFET PM5, respectively. The gate of MOSFET PM5 is connected to the non-inverting output of internal operational amplifier A2, and the source of MOSFET PM5 is connected to the inverting input of internal operational amplifier A2 and the drain of MOSFET PM4, respectively. The drain of MOSFET PM5 is connected to the gate of MOSFET PM4, the gate of MOSFET PM7, and the drain of MOSFET NM5, respectively. MOSFET PM6... The gate of MOSFET PM6 is connected to the output terminal VP of the startup and bias circuit. The source of MOSFET PM6 is connected to the power supply VCC. The drain of MOSFET PM6 is connected to the sources of MOSFET PM9 and MOSFET PM10, respectively. The gate of MOSFET PM7 is connected to the gate of MOSFET PM4, the drain of MOSFET PM5, and the drain of MOSFET NM5, respectively. The source of MOSFET PM7 is connected to the power supply VCC. The drain of MOSFET PM7 is connected to the non-inverting input terminal of internal operational amplifier A2 and the source terminal of MOSFET PM8, respectively. The gate of MOSFET PM8 is connected to the inverting output terminal of internal operational amplifier A2. The source of MOSFET PM8 is connected to the non-inverting output terminal of internal operational amplifier A2, respectively. The input terminal of MOSFET PM8 is connected to the drain of MOSFET PM7, and the drain of MOSFET PM8 is connected to the output terminal VZ of the operational amplifier circuit. The gate of MOSFET PM9 is connected to the input terminal VX of the operational amplifier circuit. The source of MOSFET PM9 is connected to the drain of MOSFET PM6 and the source of MOSFET PM10, respectively. The drain of MOSFET PM9 is connected to the gate of MOSFET NM7, the drain of MOSFET NM7, and the gate of MOSFET NM6, respectively. The gate of MOSFET PM10 is connected to the output terminal VY of the operational amplifier circuit, and the drain of MOSFET PM10 is connected to the gate of MOSFET NM8, the drain of MOSFET NM8, and the gate of MOSFET NM10, respectively. The gate of M5 is connected to the inverting output of the internal operational amplifier A1. The source of MOSFET NM5 is connected to the non-inverting input of the internal operational amplifier A1 and the drain of MOSFET NM6. The drain of MOSFET NM5 is connected to the drain of MOSFET PM5, the gate of MOSFET PM4, and the gate of MOSFET PM7. The source of MOSFET NM6 is connected to ground (GND). The drain of MOSFET NM6 is connected to the non-inverting input of the internal operational amplifier A1 and the source of MOSFET NM5. The gate of MOSFET NM7 is connected to the drain of MOSFET NM7, the drain of MOSFET PM9, and the gate of MOSFET NM6. The source of MOSFET NM7 is connected to ground (GND).The gate of MOSFET NM8 is connected to the drain of MOSFET NM8, the drain of MOSFET PM10, and the gate of MOSFET NM10. The source of MOSFET NM8 is connected to ground (GND). The drain of MOSFET NM8 is connected to the gate of MOSFET NM8, the drain of MOSFET PM10, and the gate of MOSFET NM10. The gate of MOSFET NM9 is connected to the non-inverting output of internal operational amplifier A1. The source of MOSFET NM9 is connected to the drain of NM10 and the inverting input of internal operational amplifier A1. The drain of NM9 is connected to the output VZ of the operational amplifier. The gate of MOSFET NM10 is connected to the gate of MOSFET NM8, the drain of MOSFET NM8, and the drain of MOSFET PM10. The source of MOSFET NM10 is connected to ground (GND). The drain of MOSFET NM10 is connected to the source of MOSFET NM9 and the inverting input of internal operational amplifier A1.

4. The high-order temperature-compensated bandgap reference circuit based on CMOS technology with high power supply rejection ratio according to claim 3, characterized in that, The bandgap reference circuit includes MOSFETs PM11, PM12, PM13, PM14, PM15, PM16, PM17, and PM18; resistors R1, R2, R3, R4, R5, and R6; and transistors Q1, Q2, and Q3. The gate of MOSFET PM11 is connected to the output terminal VZ of the operational amplifier, the source of MOSFET PM11 is connected to the power supply VCC, and the drain of MOSFET PM11 is connected to the source of MOSFET PM12. The gate of MOSFET PM12 is connected to the input terminal VX of the operational amplifier, and the source of MOSFET PM12... The gate of MOSFET PM13 is connected to the drain of MOSFET PM11, and the drain of MOSFET PM12 is connected to the input terminal VX of the operational amplifier. The gate of MOSFET PM13 is connected to the output terminal VZ of the operational amplifier, the source of MOSFET PM13 is connected to the power supply VCC, and the drain of MOSFET PM13 is connected to the source of MOSFET PM14. The gate of MOSFET PM14 is connected to the input terminal VX of the operational amplifier, the source of MOSFET PM14 is connected to the drain of MOSFET PM13, and the drain of MOSFET PM14 is connected to the input terminal VY of the operational amplifier. The gate of MOSFET PM15 is connected to the output terminal VZ of the operational amplifier circuit, and the source of MOSFET PM15 is connected to the power supply VCC. The drain of M15 is connected to the source of MOSFET PM16; the gate of PM16 is connected to the input VX of the operational amplifier, and the source of PM16 is connected to the drain of PM15; the gate of MOSFET PM17 is connected to the output VZ of the operational amplifier, the source of MOSFET PM17 is connected to the power supply VCC, and the drain of MOSFET PM17 is connected to the source of MOSFET PM18; the gate of MOSFET PM18 is connected to the input VX of the operational amplifier, the source of MOSFET PM18 is connected to the drain of MOSFET PM17, and the drain of MOSFET PM18 is connected to the output VOUT; one end of resistor R1 is connected to the input VX of the operational amplifier, and the other end of resistor R1 is connected to ground GND; resistor One end of resistor R2 is connected to the input terminal VY of the operational amplifier, and the other end of resistor R2 is connected to the emitter of transistor Q2; one end of resistor R3 is connected to the input terminal VY of the operational amplifier, and the other end of resistor R3 is connected to ground GND; one end of resistor R4 is connected to the input terminal VX of the operational amplifier, and the other end of resistor R4 is connected to the other end of resistor R5, the drain of MOSFET PM16, and the emitter of transistor Q3; one end of resistor R5 is connected to the input terminal VX of the operational amplifier, and the other end of resistor R5 is connected to the other end of resistor R4, the drain of MOSFET PM16, and the emitter of transistor Q3; one end of resistor R6 is connected to the output VOUT, and the other end of resistor R6 is connected to ground GND.The base and collector of transistor Q1 are connected to ground (GND), and the emitter of transistor Q1 is connected to the input terminal VX of the operational amplifier. The base and collector of transistor Q2 are also connected to ground (GND). The base and collector of transistor Q3 are both connected to ground (GND), and the emitter of transistor Q3 is connected to the other ends of resistors R4 and R5, as well as the drain of MOSFET PM16.

5. The high-order temperature-compensated bandgap reference circuit based on CMOS technology with high power supply rejection ratio according to claim 4, characterized in that, The internal operational amplifier circuit includes MOSFETs NM11, NM12, NM13, NM14, NM15, PM19, PM20, PM21, PM22, and PM23, as well as resistors R7, R8, R9, and R10. VIP+, VIP-, VOP+, and VOP- are the non-inverting input, inverting input, non-inverting output, and inverting output terminals of operational amplifier A1, respectively; VIN+, VIN-, VON+, and VON- are the non-inverting input, inverting input, non-inverting output, and inverting output terminals of operational amplifier A2, respectively. The gate of MOSFET NM11 is connected to the gate of MOSFET NM12, one end of resistor R7, and one end of resistor R8, respectively. The source of MOSFET NM11 is connected to ground (GND), and the drain of MOSFET NM11 is connected to the non-inverting output terminal VOP+ of operational amplifier A1. The source of MOSFET NM12 is connected to ground (GND), and the drain of MOSFET NM12 is connected to the inverting output terminal VOP- of operational amplifier A1. The gate of MOSFET NM13 is connected to the non-inverting input terminal VIN+ of operational amplifier A2. The source of MOSFET NM13 is connected to the source of MOSFET NM14 and the drain of MOSFET NM15, respectively. The drain of MOSFET NM13 is connected to the inverting output terminal VIN+ of operational amplifier A2. ON- is connected; the gate of MOSFET NM14 is connected to the inverting input terminal VIN- of operational amplifier A2, the source of MOSFET NM14 is connected to the source of MOSFET NM13 and the drain of MOSFET NM15, and the drain of MOSFET NM14 is connected to the non-inverting output terminal VON+ of operational amplifier A2; the gate of MOSFET NM15 is connected to the output terminal VN of the startup and bias circuit, and the source of MOSFET NM15 is connected to ground GND; the gate of MOSFET PM19 is connected to the output terminal VP of the startup and bias circuit, the source of MOSFET PM19 is connected to the power supply VCC, and the drain of MOSFET PM19 is connected to the source of MOSFET PM20 and the source of MOSFET PM21. The gate of MOSFET PM20 is connected to the inverting input terminal VIP- of operational amplifier A1. The source of MOSFET PM20 is connected to the drain of MOSFET PM19 and the source of MOSFET PM21. The drain of MOSFET PM20 is connected to the non-inverting output terminal VOP+ of operational amplifier A1. The gate of MOSFET PM21 is connected to the non-inverting input terminal VIP+ of operational amplifier A1. The source of MOSFET PM21 is connected to the drain of MOSFET PM19 and the source of MOSFET PM20. The drain of MOSFET PM21 is connected to the inverting output terminal VOP- of operational amplifier A1. The gate of MOSFET PM22 is connected to the gate of MOSFET PM23, one end of resistor R9, and resistor R12. One end of R10 is connected to the source of MOSFET PM22, which is connected to the power supply VCC. The drain of MOSFET PM22 is connected to the inverting output terminal VON- of operational amplifier A2. The gate of MOSFET PM23 is connected to the gate of MOSFET PM22, one end of resistor R9, and one end of resistor R10. The source of MOSFET PM23 is connected to the power supply VCC. The drain of MOSFET PM23 is connected to the non-inverting output terminal VON+ of operational amplifier A2. The other end of resistor R7 is connected to the non-inverting output terminal VOP+ of operational amplifier A1. The other end of resistor R8 is connected to the inverting output terminal VOP- of operational amplifier A1. The other end of resistor R9 is connected to the inverting output terminal VON- of operational amplifier A2.The other end of resistor R10 is connected to the non-inverting output terminal VON+ of operational amplifier A2.

6. The high-order temperature-compensated bandgap reference circuit based on CMOS technology with high power supply rejection ratio according to claim 5, characterized in that, The resistors R1, R3, R4 and R5 are adjustable resistors.

7. The high-order temperature-compensated bandgap reference circuit based on CMOS technology with high power supply rejection ratio according to claim 5, characterized in that, The resistance value of resistor R1 is equal to the resistance value of resistor R3.

8. The high-order temperature-compensated bandgap reference circuit based on CMOS technology with high power supply rejection ratio according to claim 5, characterized in that, The resistance value of resistor R4 is equal to the resistance value of resistor R5.

9. The high-order temperature-compensated bandgap reference circuit based on CMOS technology with high power supply rejection ratio according to claim 5, characterized in that, The current flowing through resistors R4 and R5 is: in, For 300K, V represents temperature. T Thermoelectric voltage, This is the resistance value of resistor R4.

10. The high-order temperature-compensated bandgap reference circuit based on CMOS technology with high power supply rejection ratio according to claim 5, characterized in that, The expression for the output voltage is: Among them, resistors R1 and R3 have the same resistance value, and resistors R4 and R5 have the same resistance value. V T is the thermal voltage, and n is the ratio of the junction area of ​​transistor Q2 to that of transistor Q1.

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