Slave device clock control method and microprocessor system using same

Abstract

The better embodiment of the invention relates to a slave device clock control method and a microprocessor system using the same, and the slave device clock control method comprises the following steps: connecting a microprocessor and a plurality of slave devices on a flat cable; in the plurality of slave devices, a plurality of corresponding clock gate circuits are used for controlling whether clock signals are conducted or not; decoding an instruction output by the microprocessor to the flat cable in advance to obtain an address of the instruction; finding out a specific slave device corresponding to the address from the plurality of slave devices; and when a clock gate circuit corresponding to the specific slave device is not conducted, controlling the clock gate circuit to enable the specific slave device to operate normally so as to receive the instruction.

Description

Technical Field

[0001] This application relates to a technology for a microprocessor system, and more particularly to a slave device clock control method and a microprocessor system using the same. Background Technology

[0002] Clock management is a critical issue in embedded system design. Most modern microcontrollers (MCUs) contain multiple subsystems, each typically with its own dedicated clock source. To conserve power, these clock sources are turned off when not in use. However, improper management of these clock switches can lead to troublesome system problems.

[0003] This situation is common in some microcontroller units. Such units typically contain a main central processing unit (CPU) core and one or more dedicated digital signal processing (DSP) subsystems. Each DSP subsystem has its own instruction memory (RAM) and data memory, directly accessible from the main CPU. However, to access these memories, the clock of the corresponding DSP subsystem must first be enabled. If the DSP subsystem's clock has not been stably started before accessing the instruction / data memory, the main CPU may enter a hang state, ultimately leading to a hardware fault and a crash. Summary of the Invention

[0004] Embodiments of this application provide a slave device clock control method and a microprocessor system using the same, to avoid hardware faults causing crashes in the microprocessor system.

[0005] Embodiments of this application provide a microprocessor system including a ribbon cable, a microprocessor, a plurality of clock gates, and a clock gate control circuit. The microprocessor and each of the plurality of slave devices are electrically connected to the ribbon cable. Each of the plurality of clock gates is coupled to a corresponding slave device to determine whether each slave device receives a corresponding clock signal. The clock gate control circuit is coupled to the microprocessor and the plurality of clock gates to pre-decode an instruction output by the microprocessor to the ribbon cable, obtain an address of the instruction, and identify the slave device corresponding to the address from among the plurality of slave devices. When a corresponding clock gate is not turned on among the plurality of clock gates, the clock gate control circuit forces the corresponding clock gate to turn on.

[0006] Another embodiment of this application provides a slave device clock control method, which includes: connecting a microprocessor and a plurality of slave devices on a ribbon cable; controlling whether a clock signal is turned on through a plurality of corresponding clock gate circuits in the plurality of slave devices; pre-decoding an instruction output by the microprocessor to the ribbon cable to obtain an address of the instruction; finding a specific slave device corresponding to the address from the plurality of slave devices; and controlling the clock gate circuit to make the specific slave device operate normally to receive instructions when a clock gate circuit corresponding to the specific slave device is not turned on.

[0007] In summary, embodiments of this application provide a microprocessor system and a slave device clock control method. By using clock control circuits and clock gate circuits, the system can selectively enable specific slave devices to receive clock signals based on the instructions and addresses output by the microprocessor, thereby enabling normal operation and instruction execution. This design can effectively save energy because unnecessary slave devices will not receive clock signals when not selected, thus reducing unnecessary power consumption. Simultaneously, it simplifies the system control flow; the microprocessor only needs to output instructions and addresses, without requiring additional control signals to control the startup of slave devices, improving system flexibility and scalability. Therefore, embodiments of this application are beneficial for improving the energy efficiency and control simplicity of microprocessor systems.

[0008] To further understand the techniques, methods, and effects of this application, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of this application. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the invention. Attached Figure Description

[0009] The accompanying drawings are provided to enable those skilled in the art to further understand this application and are incorporated in and constitute a part of the specification of this application. The drawings illustrate exemplary embodiments of this application and are used, together with the specification of this application, to explain the principles of this application.

[0010] Figure 1 The diagram illustrates a circuit block diagram of a microprocessor system according to a preferred embodiment of this application.

[0011] Figure 2 The diagram illustrates a circuit block diagram of a microprocessor system according to a preferred embodiment of this application.

[0012] Figure 3 The flowchart illustrates a preferred embodiment of the slave device clock control method of this application.

[0013] Symbol explanation:

[0014] 101 ribbon cable;

[0015] 102 clock gate control circuit;

[0016] MCU (Microprocessor)

[0017] SLV from the device;

[0018] IGC clock gate circuit;

[0019] S301-S308 are the flow steps of a preferred embodiment of the slave device clock control method of the present invention. Detailed Implementation

[0020] Reference will now be made in detail to exemplary embodiments of this application, which are illustrated in the accompanying drawings. Where possible, the same component symbols are used in the drawings and description to refer to the same or similar parts. Furthermore, the practices of these exemplary embodiments are merely one way of implementing the design concept of this application, and the following examples are not intended to limit this application.

[0021] Figure 1 The diagram illustrates a circuit block diagram of a microprocessor system according to a preferred embodiment of this application. Please refer to... Figure 1 This microprocessor system includes a microprocessor (MCU), a ribbon cable 101, a plurality of slave devices (SLVs), a plurality of clock gates (IGCs), and a clock gate control circuit (gating circuit) 102. The MCU and each slave device (SLV) are electrically connected to the ribbon cable 101. In a microprocessor system, there are typically many peripheral IP (Intellectual Property) modules, which are the aforementioned slave devices (SLVs). These IP modules have different operating clock frequency requirements. Therefore, the clock signals connected to the clock gates (IGCs) corresponding to the slave devices (SLVs) will also vary depending on the properties of the SLV.

[0022] In this embodiment, the microprocessor system employs clock gating technology, only activating the corresponding clock supply when the slave device (SLV) actually needs to operate. This allows for the setting of the most suitable clock frequency and clock activation time for each SLV module, avoiding excessive overclocking and resource waste. In this embodiment, the clock gate control circuit 102 plays the role of turning the aforementioned clock gate circuit IGC on or off at appropriate times.

[0023] For example, the clock gate control circuit 102 can execute an artificial intelligence model to dynamically output the corresponding weights of the aforementioned slave device SLVs based on user operations. In one embodiment, the clock gate control circuit 102 can also adjust the operating speed of each slave device SLV. For instance, each slave device SLV uses a clock with a corresponding clock divider. By controlling the clock divider, the frequency of the clock used by each slave device SLV can be adjusted, thereby speeding up or slowing down the operating speed of each slave device SLV. This controls the on and off times of the corresponding clock gate circuits of the aforementioned slave device SLVs. Therefore, when training this artificial intelligence model, user scenarios are also used to adjust the parameters of the artificial intelligence model, thereby dynamically adjusting the corresponding weights of the slave device SLVs to control the corresponding clock gate circuits separately. Depending on the product attributes, user scenarios may include, for example, standby mode, power saving mode, memory mode, maximum performance mode, slave device temperature, slave device usage rate, etc. At least one of the above operating modes, temperatures, usage rates, etc., is selected to adjust (train) the parameters of the artificial intelligence model. Furthermore, generally speaking, the adjustment targets for the parameters of the aforementioned artificial intelligence model can be, for example, maximizing the response time and minimizing the system power consumption. In one embodiment, each usage scenario corresponds to the current usage time / standby time of the MCU in that usage scenario. This time can be provided to the user as a basis for adjustment. In one embodiment, the aforementioned usage time / standby time can be adjusted by adjusting the switching and frequency of the slave device SLV through the clock gate control circuit 102.

[0024] However, even using an artificial intelligence model, the clock gate control circuit 102 may still experience unexpected clock shutdowns. That is, when the microprocessor (MCU) needs to access a slave device (SLV), if the corresponding clock gate (IGC) for that SLV is closed, the clock signal will not be supplied to the SLV. This situation can cause the entire system to crash.

[0025] In this embodiment, the clock gate control circuit 102 also includes the function of decoding microprocessor (MCU) instructions. When the MCU sends an instruction to the ribbon cable 101, the clock gate control circuit 102 simultaneously receives the instruction from the MCU and pre-decodes the instruction output by the MCU to the ribbon cable to obtain the corresponding address of the instruction. At this time, the clock gate control circuit 102 can immediately know which slave device (SLV) clock signal needs to be enabled. If the slave device SLV clock signal is already enabled, the clock gate control circuit 102 does not operate. If the slave device SLV clock signal is not enabled, the clock gate control circuit 102 immediately forces the IGC clock gate circuit corresponding to this slave device SLV to be enabled, avoiding unexpected system crashes.

[0026] Figure 2The diagram illustrates a circuit block diagram of a microprocessor system according to a preferred embodiment of the present invention. Please refer to... Figure 1 as well as Figure 2 , Figure 2 The circuitry of the microprocessor system and Figure 1 The difference in the circuits is that, Figure 2 The coupling between the microprocessor (MCU) and the clock gate control circuit 102 differs in this embodiment. In this embodiment, the MCU needs to send instructions to the clock gate control circuit 102 first, and then the clock gate control circuit 102 sends them to the ribbon cable 101. Both embodiments are possible, and this invention is not limited to the coupling relationship between the clock gate control circuit 102 and the microprocessor (MCU).

[0027] The above embodiments can be summarized into a method for controlling the clock of a device. Figure 3 The flowchart illustrates a preferred embodiment of the slave device clock control method of the present invention. Please refer to... Figure 3 This slave device clock control method includes the following steps:

[0028] Step S301: Begin.

[0029] Step S302: Connect a microprocessor and a plurality of slave devices on a row of wires.

[0030] Step S303: In the plurality of slave devices, the clock signal is controlled to be turned on or off through the corresponding plurality of clock gate circuits. As in the above embodiment, each slave device SLV has a corresponding clock gate circuit IGC.

[0031] Step S304: Pre-decode an instruction output by the microprocessor to the ribbon cable to obtain an address of the instruction. In the above embodiment, the clock gate control circuit 102 pre-decodes the instruction output by the microprocessor (MCU) to the ribbon cable to obtain the address of the slave device (SLV) corresponding to the instruction.

[0032] Step S305: From the majority of slave devices, find the specific slave device corresponding to the address.

[0033] Step S306: Determine whether the clock gate circuit of the specific slave device is turned on. If the determination is no, proceed to step S307. If the determination is yes, proceed to step S308.

[0034] Step S307: Control the corresponding clock gate circuit to enable the specific slave device to operate normally in order to receive instructions.

[0035] Step S308: No action taken.

[0036] In summary, embodiments of the present invention provide a microprocessor system and a slave device clock control method. By using clock control circuits and clock gate circuits, the system can selectively enable specific slave devices to receive clock signals based on the instructions and addresses output by the microprocessor, thereby enabling them to operate normally and execute instructions. This design can effectively save energy because unnecessary slave devices will not receive clock signals when not selected, thus reducing unnecessary power consumption. Simultaneously, it simplifies the system control flow; the microprocessor only needs to output instructions and addresses, without requiring additional control signals to control the startup of slave devices, improving system flexibility and scalability. Therefore, embodiments of the present invention are beneficial for improving the energy efficiency and control simplicity of microprocessor systems.

[0037] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes thereto will be suggested to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims.

Claims

1. A microprocessor system, characterized by Comprising: a bus line; a microprocessor electrically connected to the bus line; a plurality of slave devices, wherein each of the plurality of slave devices is electrically connected to the bus line; a plurality of clock gate circuits, wherein each of the plurality of clock gate circuits is coupled to a corresponding one of the plurality of slave devices to determine whether the corresponding one of the plurality of slave devices receives a corresponding clock signal; and a clock gate control circuit coupled to the microprocessor and the plurality of clock gate circuits to pre-decode an instruction output by the microprocessor to the bus line, obtain an address of the instruction, and find a first slave device corresponding to the address from the plurality of slave devices, wherein, before the microprocessor executes the instruction, when a clock gate circuit corresponding to the first slave device from the plurality of clock gate circuits is not turned on, the clock gate control circuit forces the clock gate circuit corresponding to the first slave device to be turned on.

2. The microprocessor system of claim 1, wherein: the clock gate control circuit executes an artificial intelligence model to dynamically output corresponding weights of the plurality of slave devices to control the plurality of clock gate circuits, respectively, according to a user context of the microprocessor system.

3. The microprocessor system of claim 2, wherein: the user context is selected from at least one of a standby mode, a power saving mode, a memory mode, a maximum performance mode, a temperature of each of the plurality of slave devices, and a usage rate of the plurality of slave devices.

4. The microprocessor system of claim 2, wherein, adjustment targets of the adjustment parameters of the artificial intelligence model include: a maximum reaction time; and a minimum power consumption of the system.

5. A method of clocking a device from a clock, characterized by, Comprising: connecting a microprocessor and a plurality of slave devices on a bus line; controlling, in the plurality of slave devices, whether a clock signal is turned on by a corresponding plurality of clock gate circuits; pre-decoding an instruction output by the microprocessor to the bus line to obtain an address of the instruction; finding a specific slave device corresponding to the address from the plurality of slave devices; and when a clock gate circuit corresponding to the specific slave device is not turned on, controlling the clock gate circuit to enable the specific slave device to normally operate to receive the instruction. Further comprising:

6. The slave device clock control method of claim 5, wherein, executing an artificial intelligence model to dynamically output corresponding weights of the plurality of slave devices to control the plurality of clock gate circuits, respectively, according to a user context.

7. The slave device clock control method of claim 6, wherein: the user context is selected from at least one of a standby mode, a power saving mode, a memory mode, a maximum performance mode, a temperature of each of the plurality of slave devices, and a usage rate of the plurality of slave devices. adjustment targets of the adjustment parameters of the artificial intelligence model include:

8. The slave device clock control method of claim 6, wherein, a maximum reaction time; and a minimum power consumption of the system. ​

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