Method and system for block random access memory data initialization within an FPGA

Abstract

The present disclosure provides a method and system for initializing block random access memory data in FPGA. The method comprises: connecting an upper computer to an initialization controller of a block random access memory in FPGA through an enable signal line and a data signal line; pulling the enable signal line high at the falling edge of a clock to indicate the start of initialization; starting to serially transmit the address and data of the target block random access memory on the data signal line at the next clock cycle after the enable signal is valid; the initialization controller parses the address and data and writes them into the storage unit of the corresponding block random access memory; and pulling the enable signal line low after the initialization is completed. Some embodiments of the present disclosure aim to solve the problems of bulky protocol, excessive use of data lines and inability to dynamically initialize in the prior art.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, specifically to a method and system for initializing block random access memory data in an FPGA. Background Technology

[0002] Block Random Access Memory (BRAM) is a high-performance hard-core SRAM storage unit pre-placed inside an FPGA. Each block typically ranges from a few kilobytes to tens of kilobytes in size and can be configured as a single-port or dual-port RAM / ROM / FIFO, supporting synchronous clock operation and concurrent access. It offers advantages such as low latency, high bandwidth, reduced logic resources, and predictable timing, and is widely used in image / video caching, digital filter lookup tables, local memory for embedded processors, FIFO queues, state machine control tables, and neural network weight storage. Initializing the data in the BRAM (such as loading lookup data, program code, or static constants) enables "power-on" functionality—the system can start quickly and execute stably without rewriting after configuration, maintaining consistency and facilitating simulation and testing, effectively improving system reliability and efficiency.

[0003] Existing FPGA Block RAM initialization schemes suffer from bottlenecks in hardware interface protocols, data bus usage, and flexibility, including: **Protocol bloat:** Reliance on standard buses (such as AXI4-Lite) or custom parallel interfaces necessitates multi-channel handshaking (separation of address / data / control signals), leading to a surge in state machine complexity (>15 state transitions). **Data bus redundancy:** Typical schemes occupy 20+ physical lines (e.g., 16 data lines + 10 address lines + 4 control lines = 30 lines), unacceptable in small to medium-sized FPGAs with limited I / O resources (such as the Fudan Microelectronics FMQL series). **Poor flexibility:** Data is preloaded into the BRAM during synthesis via initialization files (.COE for Xilinx / .MIF for Intel) and burned into the FPGA along with the bitstream. However, modifying the data requires resynthesis, which is very time-consuming. This can lead to: **routing congestion, resulting in a 15-30% decrease in timing margin and limiting the maximum operating frequency.** **Pin occupancy exceeds 40%, hindering the expansion of peripherals (such as ADCs and Gigabit Ethernet ports). The protocol state machine uses hardware exceeding 60k equivalent logic gates (>60kGE). It is programmed simultaneously with the bits, making dynamic editing impossible.

[0004] Therefore, existing technologies still need to be improved and enhanced.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] To address at least one of the aforementioned problems, as well as one or more other potential problems, this disclosure proposes a block random access memory (BRAM) data initialization method within an FPGA. This method aims to initialize the BRAM with a minimal hardware interface and protocol, using the fewest physical connections (theoretically close to the minimum), while maintaining precise address and data specification capabilities and supporting dynamic data updates after the FPGA bitstream programming is completed. This significantly reduces system complexity, area overhead, and routing pressure, while improving timing performance and resource utilization, all while ensuring functional integrity.

[0007] In a first aspect of this disclosure, a method for initializing block random access memory (BRAM) data within an FPGA is provided. The method includes: a host computer connecting to an initialization controller of the BRAM within the FPGA via an enable signal line and a data signal line; the enable signal line being pulled high on the falling edge of a clock cycle to indicate the start of initialization; the data signal line serially transmitting the address and data of the target BRAM starting in the next clock cycle after the enable signal is active; the initialization controller parsing the address and data and writing them into the corresponding memory cell of the BRAM; and the enable signal line being pulled low after initialization is complete.

[0008] Furthermore, in some embodiments, the data packets transmitted by the data signal line include an address field, a data field, and a check field.

[0009] Furthermore, in some embodiments, the verification field is one of a parity check bit, a cyclic redundancy check code, or a checksum.

[0010] Furthermore, in some embodiments, if a data transmission error occurs, the initialization controller pulls the enable signal line low, triggering the host computer to retransmit the data.

[0011] Furthermore, in some embodiments, if N consecutive transmissions fail, the initialization controller generates an interrupt signal and stops the initialization operation, where N is a user-configurable positive integer.

[0012] A second aspect of this disclosure also provides a hardware system for implementing the method described above, the hardware system comprising: a host computer for generating initialization data and control signals; an initialization controller disposed within an FPGA for receiving and parsing serial data sent by the host computer and controlling the writing of block random access memory; and at least one block random access memory connected to the initialization controller.

[0013] Furthermore, in some embodiments, the initialization controller and the host computer are connected only through an enable signal line and a data signal line.

[0014] Furthermore, in some embodiments, a single initialization controller connects to multiple block random access memories and distinguishes each block random access memory by a chip select signal or address encoding.

[0015] Furthermore, in some embodiments, multiple initialization controllers share the same enable signal line and data signal line, and each initialization controller selectively responds to data writes according to the address number.

[0016] Furthermore, in some embodiments, the state machine complexity of the initialization controller is less than 10 states, and a single initialization controller occupies only about 1.5k equivalent logic gates.

[0017] A third aspect of this disclosure provides an FPGA internal block random access memory data initialization system, the initialization system comprising: an initialization controller configured to be connected to a host computer, the initialization controller and the host computer being connected via a data line and an enable signal line, the data line and the enable signal line being respectively configured as physical channels for transmitting a single binary bit; and a block memory configured to be connected to the initialization controller.

[0018] Furthermore, in some embodiments, each of the plurality of initialization controllers is configured to be connected to a host computer via a data line and a shared enable signal line, wherein the data line of each of the plurality of initialization controllers is respectively connected to the host computer, the shared enable signal line is respectively configured to come from the same enable signal, and the shared enable signal line is configured as a physical channel for transmitting a single binary bit.

[0019] Furthermore, in some embodiments, each of the plurality of initialization controllers is configured to be connected to a host computer via a data line and an enable signal line, wherein the data line and enable signal line of each of the plurality of initialization controllers are respectively connected to the host computer.

[0020] Furthermore, in some embodiments, the initialization controller and the host computer are further configured to include a block memory select line, which is configured as a physical channel for transmitting a single binary bit; multiple block memories are configured to be connected to the initialization controller respectively through internal interfaces.

[0021] Furthermore, in some embodiments, the initialization controller is assigned a fixed number, and multiple initialization controllers with different fixed numbers are configured to be connected to the host computer via a shared data line and a shared enable signal line, respectively. The shared data line and the shared enable signal line are configured as physical channels for transmitting a single binary bit; each of the multiple block memories is configured to be connected to the corresponding fixed-numbered initialization controller via an internal interface.

[0022] A fourth aspect of this disclosure provides a method for initializing data in an FPGA block random access memory, the method comprising: generating an enable signal according to a system clock; after one or more system clock cycles following the enable signal being at a set level, transmitting initialization data from a host computer to an initialization controller via a single binary bit physical channel; and transmitting the initialization data from the initialization controller to the block memory via an internal channel.

[0023] Furthermore, in some embodiments, the initialization data is transmitted from the initialization controller to the block memory via an internal channel, including: first transmitting memory address data to the block memory, and then transmitting initial data to the block memory.

[0024] Furthermore, in some embodiments, after the initial data is transmitted to the block memory, the verification data is then transmitted to the block memory.

[0025] Furthermore, in some embodiments, when the verification data determines that the transmitted initialization data is inconsistent, the enable signal at a set level is changed once, and the initialization data is retransmitted to the block memory.

[0026] Furthermore, in some embodiments, when the verification data determines that the number of times the transmitted initialization data is inconsistent is N, the transmission of initialization data from the host computer to the initialization controller is interrupted, and the enable signal at the set level is changed.

[0027] This disclosure, compared to the prior art, includes at least the following beneficial effects:

[0028] In some embodiments, protocol simplification reduces state machine complexity and decreases control logic resource consumption (a single initialization controller requires only approximately 1.5k equivalent logic gates). Furthermore, in some embodiments, data line requirements are compressed to a theoretical minimum (clock (CLK) + 1 data line + enable), significantly saving I / O resources. Further, in some embodiments, precise addressing and data writing are supported, allowing for flexible configuration of BRAM initialization content. Further, in some embodiments, dynamic initialization is supported, improving system reconfigurability and debugging efficiency. Further, in some embodiments, data verification and retransmission mechanisms are included, enhancing data transmission reliability. Further, in some embodiments, the overall structure is simple, with low area overhead, making it easy to integrate into various FPGA systems. Attached Figure Description

[0029] The above and other features and advantages of the embodiments of this disclosure will become more apparent, taking into account the accompanying drawings and the following detailed description, wherein:

[0030] Figure 1 A schematic diagram of the structure of an initialization controller according to some embodiments of the present disclosure is shown;

[0031] Figure 2 A schematic diagram showing the connection between an initialization controller and a block random access memory according to some embodiments of the present disclosure is shown;

[0032] Figure 3 A schematic diagram of the existing AXI4 bus connection is shown;

[0033] Figure 4 A schematic diagram of the existing Wishbone bus connection is shown;

[0034] Figure 5 A schematic diagram of a data protocol according to some embodiments of the present disclosure is shown;

[0035] Figure 6-1 A timing diagram illustrating the start portion of a transmission according to some embodiments of the present disclosure is shown;

[0036] Figure 6-2 A timing diagram illustrating potential data loss according to some embodiments of the present disclosure is shown;

[0037] Figure 7 A timing diagram of the address switching portion of a transmission according to some embodiments of the present disclosure is shown;

[0038] Figure 8 A timing diagram illustrating the end portion of a transmission according to some embodiments of the present disclosure is shown;

[0039] Figure 9A timing diagram illustrating the addition of even parity after data transmission according to some embodiments of the present disclosure is shown;

[0040] Figure 10 A timing diagram illustrating retransmission after an error is detected, according to some embodiments of the present disclosure, is shown.

[0041] Figure 11 A schematic diagram illustrating a connection of multiple controllers controlling multiple memory groups and sharing a common enable according to some embodiments of the present disclosure is shown.

[0042] Figure 12 A schematic diagram illustrating the connection of multiple controllers controlling multiple memory groups and enabling them independently, according to some embodiments of the present disclosure, is shown.

[0043] Figure 13 A schematic diagram illustrating the connection of a single controller controlling multiple sets of memory according to some embodiments of the present disclosure is shown;

[0044] Figure 14 A schematic diagram illustrating the connection of multiple controllers controlling multiple sets of memory and sharing enable and data according to some embodiments of the present disclosure is shown; and

[0045] In the various figures, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0046] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0047] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0048] Generally, the initialization of BRAM in FPGAs currently employs the following methods: First, initialization based on standard bus protocols: Initial data is written to the BRAM by an external host (such as a processor) or internal controller via standard bus interfaces such as AXI4-Lite and Wishbone. This approach requires the implementation of complete address, data, and control signal channels and their handshake protocols, resulting in a complex control state machine (typically exceeding 15 states) and consuming significant hardware resources (logic scale exceeding 60k equivalent logic gates). Simultaneously, such bus interfaces typically require more than 20 physical connections (e.g., 16 data lines, 10 address lines, and 4 control lines, totaling 30 lines). In low-to-mid-range FPGAs with limited I / O resources (such as the Fudan Microelectronics FMQL series), this can consume an excessively high proportion of pin resources (potentially exceeding 40%), severely impacting the system's ability to expand with other peripherals (such as ADCs and Gigabit Ethernet interfaces). Furthermore, the complex protocols and routing can easily cause routing congestion, leading to a 15% to 30% decrease in timing margin and limiting the system's maximum operating frequency. Secondly, static initialization based on pre-loading initialization files: During the FPGA synthesis phase, data is directly embedded into the FPGA's bitstream using a dedicated initialization file (such as a Xilinx .COE file or an Intel .MIF file). This data is then programmed into the BRAM along with the bitstream during FPGA configuration. The drawback of this method is that any modification to the initialization data requires re-executing the entire synthesis, implementation, and bitstream generation process, which is time-consuming and cannot meet the needs of dynamically updating initialization data (e.g., switching lookup tables based on application scenarios or updating firmware after system operation). In summary, existing technologies suffer from significant problems such as high protocol complexity, high hardware resource (I / O and logic) consumption, impacted timing performance, and a lack of flexibility in dynamic initialization.

[0049] To address at least one of the aforementioned problems, and one or more other potential problems, exemplary embodiments of this disclosure provide a block random access memory data initialization method within an FPGA, as well as a corresponding device or system. The following description, in conjunction with accompanying drawings, provides a detailed explanation.

[0050] Reference Figure 1 and Figure 2 The hardware system for implementing the block random access memory (BRAM) data initialization method within the FPGA includes a host computer (not shown), a memory initialization controller, and a BRAM. The host computer and the controller are connected via an enable signal line (EN) and a data signal line (DATA). The clock signal (CLK) is typically provided internally by the FPGA or synchronously by the host computer.

[0051] In some embodiments, the initialization method 100 includes: step 110, the host computer prepares to initialize the data stream. The data stream format is as follows: Figure 5 As shown: First, there is an N-bit start address, followed by M bits of data. N and M are determined based on the address depth and data width of the BRAM. Step 120: The host computer pulls the enable (EN) signal high on the falling edge of the clock (CLK) to start initialization. Step 130: In the next clock cycle after the enable (EN) is pulled high, the host computer begins serially outputting address bits on the data (DATA) line, from the most significant bit (MSB) to the least significant bit (LSB). The controller samples the data (DATA) line based on the clock (CLK). Step 140: After the address transmission is complete, the data bits are then serially output. After receiving the address, the controller's internal address counter starts working. After each complete data word is received, it is written to the BRAM cell pointed to by the current address, and then the address is automatically incremented, ready to receive the next data word. Step 150: After all data is written, the host computer pulls the enable (EN) signal low, and the initialization ends. It should be understood that the key point in this embodiment is: to ensure reliable reception of the first address bit, this embodiment adopts... Figure 6-1 Timing. The controller internally synchronizes and detects the enable (EN) signal, and only begins sampling address data on the data (DATA) lines in the next clock cycle after the enable (EN) signal is detected as valid and stable. This avoids… Figure 6-2 Data errors may occur due to setup / hold timing violations caused by simultaneous transitions of enable (EN) and data (DATA).

[0052] Based on the above embodiments, data reliability assurance can be further enhanced. This is manifested in some embodiments by implementing an initialization method with checksum and retransmission. This method 200 includes: step 210, whereby the host computer, after sending a complete data word (e.g., 16 bits), additionally sends a checksum bit, such as an even parity bit (e.g., an even parity bit). Figure 9 The parity bit is the XOR inverse of all bits in the data word. Step 220: After receiving a data word and its parity bit, the controller immediately performs a parity calculation. Step 230: If the parity passes, the controller continues with subsequent operations. Step 240: If the parity fails (e.g., ...), ... Figure 10The controller immediately pulls the enable (EN) signal line low (or keeps it low). The host computer continuously monitors the enable signal line. If it finds that the enable (EN) is pulled low by the controller (which is inconsistent with its drive state), it determines that the transmission has failed. In step 244, the host computer pauses data transmission, waits for at least one clock cycle, and then restarts from the erroneous address, pulls the enable (EN) high, and retransmits the data word and check bit corresponding to that address until the transmission is successful or the retry limit is reached. In step 248, if the retry fails N times consecutively (e.g., N=3), the host computer generates an error interrupt and terminates the initialization process of the BRAM. It should be understood that data verification information is handled by both the host and slave. Verification methods include, for example, parity check / CRC / checksum. In some embodiments, parity check is used as an example: Host: After sending a data (assuming it is 8 bits), a check bit follows immediately. At this time, a data packet has 8 data bits + 1 check bit, for a total of 9 bits. This check bit is generated by the slave device based on the corresponding algorithm (in this case, parity check) when sending data. While receiving 8 bits of data, the slave device calculates the check bit. If the check bit calculated by the slave device matches the check bit sent by the master device, the data is considered correct; otherwise, the data is considered incorrect. In the embodiments of this disclosure, the slave device will pull low to enable the check bit, indicating that the received data does not match the expected data.

[0053] Furthermore, in an expansion scheme with multiple controllers, refer to Figure 11 The system has n block memories (block memory 1 to block memory n) and n corresponding controllers (block memory initialization controller 1 to block memory initialization controller n). All controllers share an enable (EN) signal from the host computer. Data signal lines (data line 1 to data line n) can be independent (e.g., ...). Figure 11 (This can also be partially bus-based.) It should be understood that during initialization, the host computer can time-share data lines. For example, first, block memory 1 controlled by block memory initialization controller 1 is initialized via data line 1. After completion, block memory 2 is initialized via data line 2, and so on. (See reference...) Figure 14 In one alternative embodiment, all controllers (block memory initialization controller 1 to block memory initialization controller n) share the same enable signal line and the same data line. Each controller is assigned a unique ID (e.g., a 2-bit code). In the data stream sent by the host computer, the first few bits (e.g., the high 2 bits) of the address field are used to represent the target controller ID. Each controller continuously listens to the data line, but only activates and executes subsequent address and data write operations when the parsed ID matches its own ID; controllers with mismatched IDs ignore the data stream. This approach further reduces the number of connections.

[0054] Furthermore, in an embodiment where a single controller controls multiple block memories, refer to Figure 13 The system uses a single controller to manage multiple block memories simultaneously. A memory select signal line (SEL) is added between the host computer and the controller, or a block memory select code is embedded in the address field of the data stream. For example, when the highest two bits of the address field are "00", it indicates that block memory 1 is selected; when they are "01", block memory 2 is selected, and so on. After the controller parses the select code, it writes subsequent data to the corresponding selected block memory port. This method saves controller resources, but may require more complex data routing logic within the controller.

[0055] It should also be understood that the block memory in the accompanying drawings of this disclosure may be the BRAM described above. In some embodiments, the control system provided in this disclosure, such as Figure 1 As shown, the input terminal is connected to the host computer, and the output terminal is connected to the BRAM (e.g., ...). Figure 2 (The block memory shown). For the host computer, only two data lines are needed to initialize the BRAM. However, in the prior art, AXI4-Lite or Wishbone (such as...) might be used. Figure 3 , 4 Bus protocols (as shown) are used to allow communication between the host computer and the controller. This method uses more than 30 data lines for communication, which can cause signal redundancy and delays due to multiple handshakes. Furthermore, because the protocols are complex, the control logic of the controller and the host computer is also relatively complex, consuming more hardware resources.

[0056] Furthermore, in some embodiments, a custom protocol (such as...) is used. Figure 5 As shown in the figure, the host computer only needs one data line and one enable line, and the controller can configure the specified data at the specified address of the specified block memory, thus realizing the function of configuring the initial data of the BRAM.

[0057] In some embodiments, the transmission section uses two data lines: one is an enable signal that marks the start and stop of memory initialization; the other is a data line that serially transmits the address and data to be written. Its operation can be as follows: at the start of initialization, the enable signal will be pulled high on the falling edge of the clock. After one clock cycle, the data line will serially write the memory address (e.g., the address to be stored) into the memory. Figure 6-1 As shown, using an 8-bit address as an example (the address is adjustable), initial data (the data bit width is also adjustable) is continuously written after the address. This process writes from the first address of the candidate memory to the last address; this is one write operation. After completing the write to one memory location, the address of the next memory location to be written to will be continuously written (e.g., ...). Figure 7As shown in the image), the system continues writing the data required for the next memory address, resulting in multiple consecutive writes of address and data. After writing is complete, the enable signal will be pulled low, indicating the end of initialization, and no more data will be written to the memory afterward (as shown in the image). Figure 8 (As shown).

[0058] It should also be understood that in some embodiments, for actual data transmission, if the data and enable signals are simultaneously pulled high and data transmission begins directly (e.g.) Figure 6-2 As shown), the first data loss problem may occur. To ensure data integrity, certain measures need to be taken. This design uses a method of delaying the data enable by one clock cycle (e.g., Figure 6-1 As shown in the figure, the first data loss problem was solved.

[0059] Meanwhile, in some embodiments, to address the issue that data transmission errors may occur during actual deployment due to environmental factors, compromising data integrity, this disclosure introduces data verification and retransmission functions to handle these potential transmission errors caused by interference. For example, in some embodiments, parity checking is used. During data transmission, after each initial data transmission, an odd / even parity bit (e.g., ...) is added. Figure 9 As shown, this is even parity. When the controller detects a discrepancy between the parity bit and the actual data received, it pulls the enable signal line low. At this point, the host computer detects the enable line being pulled low during transmission and determines that the data write is incorrect. It then resends the initialization data to this memory block. (e.g.) Figure 10 (As shown).

[0060] Furthermore, in some implementations, when multiple consecutive initialization failures occur with the same memory, it indicates that there may be some non-infrequent errors in the connection between the host computer and the memory initialization controller. In this case, the initialization operation needs to be stopped to avoid an infinite loop. Therefore, when the controller detects N consecutive data transmission errors (which can be specified by the user), the host computer will generate an interrupt signal to indicate the error and simultaneously pull down the enable of the block memory initialization controller to prevent invalid writes. This significantly reduces the number of pins used for communication between the host computer and the controller, simplifies the complexity of the control logic, reduces the hardware area occupied by the control logic, and improves the efficiency of data transmission. It can effectively ensure low structural complexity and relatively low area overhead. Furthermore, adjustments can be made according to the data bit width, address number, and number of controlled block memories of the memory to be initialized (which will be mentioned in Section 7), allowing for flexible adjustment according to different needs.

[0061] In some alternative embodiments, with Figure 2The memory initialization scheme shown is an example. There can be one or more memories and controllers to be initialized, and the enable signal can be either shared or a separate signal (e.g., ...). Figure 9 , 10 (As shown).

[0062] In some alternative embodiments, for multiple memories to be initialized, in addition to a one-to-one correspondence between block memories and initialization controllers, a single controller can also be used to control multiple memories simultaneously (e.g., ...). Figure 11 Additionally, a memory select line is added for connection to the host computer. The connection between the controller and the memory can be either independent or partially shared, with some parts independent.

[0063] In some alternative embodiments, for cases with multiple controllers and multiple memories, each controller can be numbered in the initial state, and all controllers share a single enable and data line. A controller will only write to the memory with that number when it detects the memory address corresponding to that number on the data line, ignoring data from other numbers (such as...). Figure 12 (As shown).

[0064] In some alternative embodiments, for cases with only one controller and one memory, the protocol content can be regarded as writing to the address in the memory and the data at the corresponding address; this enables precise setting of the data in the memory.

[0065] In some alternative embodiments, the controller can be fine-tuned to adapt to block memories with different data bit widths and sizes, which is also considered as the same design.

[0066] In some alternative embodiments, different verification methods, such as CRC and checksum, are also considered to be the same design.

[0067] It should also be understood that the purpose of this disclosure is to overcome the aforementioned deficiencies of the prior art and provide a method and hardware system implementation for initializing BRAM data within an FPGA. This method aims to initialize the BRAM with a minimal hardware interface and protocol, using the fewest physical connections (theoretically close to the minimum), while maintaining precise address and data specification capabilities and supporting dynamic data updates after the FPGA bitstream programming is completed. This significantly reduces system complexity, area overhead, and routing pressure while ensuring functional integrity, and improves timing performance and resource utilization.

[0068] In some implementations, an FPGA-internal block random access memory (BRAM) data initialization system is provided, comprising: a host computer for generating initialization data and instructions; at least one BRAM located inside the FPGA, serving as the initialization target; and at least one memory initialization controller located inside the FPGA, serving as the interface between the host computer and the BRAM. The host computer and the memory initialization controller are connected via two signal lines: one is an enable signal line used to indicate the start and end of the initialization process; the other is a data signal line used for serially transmitting a bit stream containing the target BRAM address information and initialization data information. The memory initialization controller, based on the received enable and data signals, parses the target address and corresponding data, and generates write operation signals conforming to the BRAM interface timing, thus completing the initialization of the specified BRAM.

[0069] Furthermore, the bit stream format transmitted on the data signal line is as follows: during the enable signal period, the target address field and the data field are transmitted sequentially and serially. The bit widths of the address field and the data field can be parameterized according to the actual configuration (address depth, data width) of the target BRAM.

[0070] Furthermore, in some implementations, when the system contains multiple BRAMs, the configuration scheme can be expanded as follows: First alternative: Each BRAM corresponds to an independent memory initialization controller. All controllers share the same enable signal line, and the data signal lines are independent or partially shared. The host computer carries the target controller's identification information (such as the BRAM number) in the data stream. Second alternative: Multiple BRAMs share a single memory initialization controller. A memory select signal line is added between the host computer and the controller, or selection information is embedded in the data stream. The controller writes data to the corresponding BRAM based on this information. Third alternative: Each BRAM corresponds to an independent controller. All controllers share the same enable signal line and the same data signal line. Each controller is pre-assigned a unique number and only responds to initialization commands in the data stream whose address field matches its number.

[0071] Furthermore, the memory initialization controller includes a timing alignment module for handling the relative timing of the enable signal and the data signal. Specifically, by delaying the sampling of the data signal by one clock cycle relative to the activation of the enable signal, the problem of losing the first data bit due to data instability near the edge of the enable signal is avoided.

[0072] Furthermore, the system also includes a data verification and retransmission mechanism. After sending a set of initialization data, the host computer adds a verification bit (such as a parity check bit, CRC checksum, etc.). After receiving the data, the memory initialization controller performs verification calculations. If the verification fails, it reports the error to the host computer by pulling the enable signal line low. If the host computer detects that the enable signal has been unexpectedly pulled low, it triggers a retransmission of the current data block.

[0073] Furthermore, to prevent retransmission deadlocks caused by permanent faults, the system sets an error count threshold. When the number of consecutive retransmission failures reaches this threshold (N times, N is configurable), the host computer or controller will generate an interrupt signal to report an error and forcibly terminate the initialization process.

[0074] Furthermore, based on the aforementioned system, a method for initializing FPGA internal block random access memory (BRAM) data is proposed. This initialization method 300 includes the following steps: Step 310: Initialization Startup. The host computer pulls up the enable signal on the falling edge of the clock and, after one clock cycle, begins serially outputting a bit stream on the data signal line. Step 320: Address and Data Transmission. The bit stream contains at least the starting address information of the target BRAM and a continuous data sequence to be written. During the enable signal's validity period, the controller continuously receives and parses the address and data from the data signal line. Step 330: Data Writing. The controller sequentially writes the corresponding data into the corresponding memory cell of the target BRAM according to the parsed address. Step 340: Optional Multi-BRAM Processing. If multiple BRAMs need to be initialized, after completing the data stream of one BRAM, the address information and new data sequence of the next BRAM are directly and continuously sent on the data signal line. Step 350: Initialization End. After all data is written, the host computer pulls down the enable signal. Step 360: Optional Data Verification and Retransmission. In step 320, the host computer adds a check bit to each group of data; the controller performs the check, and if it fails, it reports the error through the enable line, triggering the retransmission in steps 320-330; if it fails N times in a row, it reports an error and terminates.

[0075] It should also be understood that, compared with the prior art, some embodiments of this disclosure have the following significant advantages: 1) Extremely simple protocol and low resource consumption: A custom-designed extremely simple serial protocol is adopted, requiring only two signal lines, an enable line and a data line, to complete communication, reducing I / O pin consumption to the theoretical minimum (CLK + data line + enable line), greatly freeing up FPGA pin resources and facilitating the expansion of other peripherals. 2) Simple control logic and low area overhead: Compared with complex standard bus state machines (typically >15 states, >60kGE), the controller state machine of this invention is extremely simplified, requiring significantly fewer logic resources, reducing the overall system area overhead, reducing wiring congestion, and improving timing margin and the system's maximum operating frequency. 3) Supports dynamic initialization and high flexibility: Initialization data is dynamically input through an external interface, independent of the initialization file embedded in the bitstream. Modifying the initialization data does not require resynthesizing, implementing, and generating the bitstream, realizing the dynamic update capability of "initialization after bitstream programming," improving the system's flexibility and maintainability. 4) Full functionality and high reliability: Even with a minimalist interface, it can accurately specify any address of any BRAM and write data. By introducing timing alignment and data verification / retransmission mechanisms, the integrity and reliability of data transmission are effectively guaranteed. 5) Good scalability: Through different controller-BRAM connection topologies (one-to-one, one-to-many, many-to-many, etc.) and parameterized address / data bit widths, it can flexibly adapt to FPGA application scenarios of different sizes and configurations. It should also be understood that for the number of equivalent logic gates, other protocols may manage multiple BRAMs through a single control module, meaning that managing 10, 5, or even 1 BRAM requires approximately 60k-90k controllers. In this embodiment, each BRAM has a separate controller, meaning managing 10 BRAMs requires 15k equivalent logic gates, and managing 1 BRAM requires 1.5k equivalent logic gates. Therefore, it has a significant advantage on small FPGAs. Furthermore, even in the design of medium-sized FPGAs, such as 40 BRAMs, it is assumed that some embodiments require 60k equivalent logic gates. Even under these circumstances, the design in the embodiments of this disclosure still offers architectural advantages, namely, sparse routing. For example, modules using protocols such as AXI tend to have concentrated routing because all RAM is centrally managed by a single controller, resulting in a large amount of routing resources being used near the controller (e.g., clusters of more than 30 wires). This is detrimental to the FPGA architecture and subsequent planning. However, in the embodiments of this disclosure, only 2 wires are needed for each BRAM module, resulting in a more even distribution of global routing resources and avoiding excessive concentration. This is highly beneficial for global routing of the FPGA.

[0076] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0077] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for initializing block random access memory data within an FPGA, characterized in that, include: The host computer is connected to the initialization controller of the block random access memory in the FPGA through an enable signal line and a data signal line. The enable signal line and the data signal line are both physical channels of a single binary bit. The enable signal in the enable signal line is pulled high on the falling edge of the clock to indicate the start of initialization; The data signal line begins serial transmission of the target block random access memory address and corresponding data in one or more clock cycles after the enable signal is enabled; The initialization controller writes the corresponding data into the storage unit of the target block random access memory according to the parsed address of the target block random access memory; After initialization, the enable signal in the enable signal line is pulled low.

2. The initialization method according to claim 1, characterized in that, The data packets transmitted by the data signal line include an address field, a data field, and a check field.

3. The initialization method according to claim 2, characterized in that, The verification field is one of parity check bit, cyclic redundancy check code, or checksum.

4. The initialization method according to claim 1, characterized in that, If a data transmission error occurs, the initialization controller pulls the enable signal line low, triggering the host computer to retransmit the data.

5. The initialization method according to claim 4, characterized in that, If N consecutive transmissions fail, the initialization controller generates an interrupt signal and stops the initialization operation, where N is a user-configurable positive integer.

6. The initialization method according to claim 1, characterized in that, Also includes: Generate an enable signal based on the system clock; After one or more system clock cycles following the enable signal being at a set level, the initialization data is transmitted from the host computer to the initialization controller via a single binary bit physical channel. The initialization data is transmitted from the initialization controller to the block memory via an internal channel.

7. The initialization method according to claim 6, characterized in that, The initialization data is transmitted from the initialization controller to the block memory via an internal channel, including: First, the memory address data is transmitted to the block memory, and then the initial data is transmitted to the block memory.

8. The initialization method according to claim 7, characterized in that, After the initial data is transmitted to the block memory, the verification data is then transmitted to the block memory.

9. The initialization method according to claim 8, characterized in that, When the verification data determines that the transmitted initialization data is inconsistent, the enable signal at the set level is changed once, and the initialization data is retransmitted to the block memory.

10. The initialization method according to claim 9, characterized in that, When the verification data determines that the number of times the transmitted initialization data is inconsistent is N, the transmission of initialization data from the host computer to the initialization controller is interrupted, and the enable signal at the set level is changed, where N is a positive integer that can be configured by the user.

11. A hardware system for implementing the method of any one of claims 1-10, characterized in that, include: The host computer is used to generate initialization data and control signals; The initialization controller, located inside the FPGA, is used to receive and parse the serial data sent by the host computer and control the writing of the block random access memory. At least one random access memory is connected to the initialization controller.

12. The hardware system according to claim 11, characterized in that, The initialization controller is connected to the host computer only through an enable signal line and a data signal line.

13. The hardware system according to claim 11, characterized in that, A single initialization controller connects to multiple block random access memories and distinguishes each block random access memory by a chip select signal or address encoding.

14. The hardware system according to claim 11, characterized in that, Multiple initialization controllers share the same enable signal line and data signal line, and each initialization controller selectively responds to data writes according to the address number.

15. The hardware system according to claim 11, characterized in that, The state machine complexity of the initialization controller is less than 10 states, and a single initialization controller occupies 1.5k equivalent logic gates.

16. An initialization system for implementing the method of any one of claims 1-10, characterized in that, include: An initialization controller is configured to connect to a host computer. The initialization controller and the host computer are connected via a data line and an enable signal line, which are respectively configured as physical channels for transmitting a single binary bit. A block memory is configured to be connected to the initialization controller.

17. The initialization system according to claim 16, characterized in that, Each of the multiple initialization controllers is configured to be connected to a host computer via a data line and a shared enable signal line. The data line of each initialization controller is connected to the host computer, and the shared enable signal line is configured to originate from the same enable signal. The shared enable signal line is configured as a physical channel for transmitting a single binary bit.

18. The initialization system according to claim 16, characterized in that, Each of the plurality of initialization controllers is configured to be connected to the host computer via a data line and an enable signal line, wherein the data line and enable signal line of each of the plurality of initialization controllers are respectively connected to the host computer.

19. The initialization system according to claim 16, characterized in that, The initialization controller and the host computer are configured to include a block memory select line, which is configured as a physical channel for transmitting a single binary bit. Multiple block memories are configured to connect to the initialization controller via internal interfaces.

20. The initialization system according to claim 16, characterized in that, The initialization controller is assigned a fixed number, and multiple initialization controllers with different fixed numbers are configured to be connected to the host computer via a shared data line and a shared enable signal line, respectively. The shared data line and the shared enable signal line are configured as physical channels for transmitting a single binary bit. Each of the multiple block memories is configured to connect to a corresponding fixed-number initialization controller via an internal interface.

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