A low-power MCU bus expansion circuit for power automation supporting terminals

Abstract

This invention provides a low-power MCU bus expansion circuit for power automation supporting terminals. It includes an MCU establishing a data connection with a memory circuit, a bus driver circuit, and a decoding circuit via a shared FEMC data bus; circuits that select corresponding modules on the shared FEMC data bus based on multiple primary chip select signals; a memory circuit for MCU access to corresponding memories; a bus driver circuit establishing a data connection with multiple control modules in the power automation supporting terminal system via the shared MCU bus for bidirectional data transmission between the MCU and the power automation supporting terminal; and a decoding circuit that expands a primary chip select signal into multiple secondary chip select signals and selects corresponding control modules on the shared MCU bus via these secondary chip select signals. This invention expands an MCU bus through FEMC bus driving and chip select decoding to meet the expansion requirements of FTUs, DTUs, and centralized DTUs, thereby replacing MPUs and meeting the needs of low-power and low-cost power products.

Description

Technical Field

[0001] This invention relates to the field of remote control, remote telemetry, and remote telemetry technology for power automation supporting terminals, specifically to a low-power MCU bus expansion circuit for power automation supporting terminals. Background Technology

[0002] Currently, MPU systems are commonly used in power automation terminals. An MPU (Microprocessor Unit) is a high-performance processor chip with powerful processing capabilities and versatility, primarily used to perform complex computational tasks and run operating systems. MPUs mostly use Arm Cortex-A series cores and have rich peripheral interfaces, making them suitable for more complex DTU (Data Transfer Unit) and centralized DTU equipment systems. In contrast, less complex FTU (Feeder Terminal Unit) systems can use general-purpose embedded processors (MCUs). MCUs (Microcontroller Units) are integrated circuit chips, mostly using Arm Cortex-M series cores. Compared to MPUs, they offer advantages such as lower cost, lower power consumption, faster startup speed, and easier development, thus serving as auxiliary systems to MPU systems to perform some functions of complex systems.

[0003] With the development of technology and applications, as well as the advancement of 3D packaging and chiplet technology, many functions that were previously only available in MPUs have been moved to MCUs. For example, some MCUs come with simple software drivers for more complex peripherals. However, due to limitations in their own bus and chip select signal lines, MCUs still cannot completely replace MPUs to meet the expansion needs of power FTUs, DTUs, and centralized DTUs.

[0004] Therefore, in order to meet the low-power application requirements of power systems, it is necessary to design a low-power MCU bus expansion circuit that can replace the MPU to meet the expansion requirements of FTU, DTU and centralized DTU. Summary of the Invention

[0005] To address the common problems in existing technologies, the present invention aims to provide a low-power MCU bus expansion circuit for power automation terminals. This invention, based on FEMC (Flexible External Memory Controller), expands an MCU bus through bus driving and chip select decoding to meet the expansion needs of FTU, DTU, and centralized DTU, overcoming the shortcomings of MCU bus and chip select signal lines, and achieving the goal of replacing MPU and meeting the requirements of low power consumption and low cost power products.

[0006] The present invention achieves the above objectives through the following technical solutions:

[0007] A low-power MCU bus expansion circuit for power automation supporting terminals includes an MCU, a memory circuit, a bus driver circuit, and a decoding circuit. The MCU has a built-in FEMC controller, which establishes a data connection with the memory circuit via the FEMC data bus through the parallel interface of the FEMC controller, and also establishes a data connection with the bus driver circuit and the decoding circuit through the shared FEMC data bus. The MCU has multiple primary chip select signals, and the FEMC controller selects the corresponding circuits sharing the FEMC data bus based on the multiple primary chip select signals. The memory circuit is used for the MCU to access the corresponding memory. The bus driver circuit establishes a data connection with multiple control modules in the power automation supporting terminal system through the shared MCU bus, for bidirectional data transmission between the MCU and the power automation supporting terminal. The decoding circuit expands one primary chip select signal into multiple secondary chip select signals and outputs them, and selects the corresponding control modules sharing the MCU bus through the secondary chip select signals.

[0008] According to the low-power MCU bus expansion circuit for power automation supporting terminals provided by the present invention, the FEMC controller has two areas in the system memory of the MCU, including the FEMC controller area and the FEMC external storage area. The FEMC controller area corresponds to the register space of the FEMC controller. The MCU sets the corresponding parameters of the bus access parameter data by configuring the FEMC register values. The FEMC external storage area corresponds to the address space of the memory circuit and the decoding circuit.

[0009] According to the low-power MCU bus expansion circuit for power automation supporting terminals provided by the present invention, the multiple primary chip select signals include a first primary chip select signal and a second primary chip select signal, the generation of which includes:

[0010] The FEMC external storage area is divided into two sub-regions, which correspond to the first chip select signal and the second chip select signal, respectively.

[0011] The FEMC controller accesses the corresponding address and its sub-region based on the FEMC register value.

[0012] The first chip select signal is output to the memory circuit, or the second chip select signal is output to the bus driver circuit and the decoding circuit, depending on the sub-region.

[0013] According to the low-power MCU bus expansion circuit for power automation supporting terminals provided by the present invention, the setting of the bus access parameter data includes:

[0014] By configuring the FEMC register value, corresponding timing parameters can be set for different chip select spaces.

[0015] The FEMC controller accesses the corresponding address and its chip select space according to the FEMC register value, and calls the timing parameters corresponding to the chip select space to generate the bus access parameter data.

[0016] The chip select space includes: the memory circuit that has undergone a first chip select, and a plurality of the control modules that have undergone a second chip select.

[0017] According to the low-power MCU bus expansion circuit for power automation supporting terminals provided by the present invention, the MCU adopts a dual-core microcontroller of model HPM6750, which adopts a RISC-V core; the FEMC controller area of ​​the dual-core microcontroller is 0xF3050000~0xF3053FFF, and the FEMC external storage area is 0x40000000~0x4FFFFFFF, wherein the maximum capacity of the FEMC external storage area is 256MB.

[0018] According to the low-power MCU bus expansion circuit for power automation supporting terminals provided by the present invention, the memory circuit adopts SDRAM memory, and the space address of the SDRAM memory is expanded to 32 MB or 64 MB through the 32-bit or 64-bit FEMC data bus.

[0019] The chip select pin of the SDRAM memory is connected to a first chip select signal. When the first chip select signal is low, the SDRAM memory is selected and corresponding access operations are performed on it.

[0020] According to the low-power MCU bus expansion circuit for power automation supporting terminals provided by the present invention, the bus driving circuit adopts a CMOS 16-channel tri-state bus driver, which shares the 16-bit FEMC data bus with the SDRAM memory and forms 16 data channels with high level, low level or high impedance state.

[0021] The chip select pin of the bus driver receives a second primary chip select signal. When the second primary chip select signal is low, the bus driver is selected; otherwise, the 16 data channels are in a high-impedance state.

[0022] According to the low-power MCU bus expansion circuit for power automation supporting terminals provided by the present invention, the decoding circuit adopts a 3-line to 8-line decoder, which shares a 3-bit FEMC data bus with the SDRAM memory, and is used to decode the 3-bit FEMC data bus as an address bus, thereby expanding one primary chip select signal into eight secondary chip select signals and outputting them to multiple control modules respectively.

[0023] Of the eight secondary chip select signals, one is a low-level valid signal and the rest are high-level.

[0024] According to the low-power MCU bus expansion circuit for power automation supporting terminals provided by the present invention, the eight secondary chip select signals are respectively input to eight control modules, wherein the control modules are remote signaling modules, remote control modules, or telemetry modules, and the corresponding three-remote modules are selected according to the low-level validity of the secondary chip select signals.

[0025] Among them, the eight remote control modules have 16×a channels for remote signal input, 16×b channels for remote control output, and 16×c channels for telemetry signal sampling.

[0026] Where a+b+c=8, and a, b, and c are all non-negative integers.

[0027] According to the low-power MCU bus expansion circuit for power automation supporting terminals provided by the present invention, when the chip select space is a remote signaling module or a remote control module, the timing parameters are configured according to the stability of its digital signal input or output.

[0028] When the chip select space is a telemetry module, the timing parameters are configured according to the timing requirements of the ADC sampling chip in the telemetry module.

[0029] Therefore, compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. This invention combines the FEMC data bus with a bus driver circuit and a decoding circuit, using only the limited primary chip select signal of the MCU to expand up to 8 independent secondary chip select signals and a 16-bit data bus driver. It can flexibly meet the expansion needs of power terminals such as FTU, DTU, and centralized DTU for multiple remote signaling, telemetry, and remote control ports, effectively overcoming the limitation of the number of chip select pins of the MCU itself, and realizing the expansion capability that was previously required by MPU.

[0031] 2. The present invention is based on the MCU architecture, which has low operating power consumption. Combined with its fast startup and sleep mechanism, it can replace the MPU for application scenarios with strict power consumption requirements, especially for FTU products that meet the requirements of low power consumption.

[0032] 3. The MCU of this invention has a lower cost than the more complex MPU, and its mature technology facilitates the localization of equipment design. Furthermore, it adopts the open-source and free RISC-V architecture instruction set, which saves on expensive architecture licensing fees and facilitates subsequent system expansion and upgrades compared to the traditional ARM system. Therefore, this invention can significantly reduce R&D and production costs, enhance product competitiveness, and provide a technical path for the localization of power system terminal equipment based on the open RISC-V architecture, thus possessing significant strategic value.

[0033] 4. The MCU bus expansion circuit of this invention is compatible with the same core board size as the MPU, enabling existing FTU / DTU products developed based on the MPU to be replaced with MCU with minimal modifications, greatly saving the cost of redeveloping the hardware; at the same time, the MCU-based development environment supports debugging methods such as online simulation and setting breakpoints, which is more convenient for troubleshooting errors in hardware drivers and applications compared to traditional programming under the Linux system.

[0034] 5. The FEMC controller of this invention allows for independent configuration of access timing for different chip select spaces. For high-speed telemetry ADCs, timing can be flexibly set to ensure data acquisition accuracy; for low-speed telemetry / remote control chips, a more relaxed general timing can be used to enhance stability; flexible setting of timing parameters is beneficial to optimizing the overall system performance.

[0035] 6. This invention, through the high-speed parallel bus of the DMA controller and the FEMC controller, can directly control the high-speed transmission of bus access parameter data between various control modules and memory circuits, meeting the bandwidth requirements of scenarios such as high-speed ADC sampling; at the same time, it reduces the number of CPU interventions and the CPU burden, and the CPU can process other tasks in parallel during data transmission, thus improving the overall system efficiency.

[0036] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0037] Figure 1 This is a circuit diagram of an embodiment of a low-power MCU bus expansion circuit for power automation supporting terminals according to the present invention.

[0038] Figure 2 This is a schematic diagram of the memory circuit in an embodiment of a low-power MCU bus expansion circuit for power automation supporting terminals of the present invention.

[0039] Figure 3 This is a schematic diagram of the bus driver circuit in an embodiment of a low-power MCU bus expansion circuit for power automation supporting terminals of the present invention.

[0040] Figure 4 This is a schematic diagram of a decoding circuit in an embodiment of a low-power MCU bus expansion circuit for power automation supporting terminals of the present invention.

[0041] Figure 5 This is a schematic diagram of an SD card chip circuit in an embodiment of a low-power MCU bus expansion circuit for power automation supporting terminals according to the present invention.

[0042] Figure 6 This is a schematic diagram of a remote signaling extension circuit in an embodiment of a low-power MCU bus extension circuit for power automation supporting terminals according to the present invention.

[0043] Figure 7 This is a schematic diagram of a remote control expansion circuit in an embodiment of a low-power MCU bus expansion circuit for power automation supporting terminals of the present invention.

[0044] Figure 8 This is a schematic diagram of a telemetry extension circuit in an embodiment of a low-power MCU bus extension circuit for power automation supporting terminals according to the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0046] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0047] See Figure 1This invention discloses a low-power MCU bus expansion circuit for power automation supporting terminals, comprising an MCU 10, a memory circuit 20, a bus driver circuit 30, and a decoding circuit 40. The MCU 10 has a built-in FEMC controller, which is used to establish a data connection with the memory circuit 20 via the parallel interface of the FEMC controller through the FEMC data bus, and to establish a data connection with the bus driver circuit 30 and the decoding circuit 40 through the shared FEMC data bus. The MCU 10 has multiple primary chip select signals and bus access parameter data. The FEMC controller is used to select the corresponding circuits sharing the FEMC data bus according to the multiple primary chip select signals. The memory circuit 20 is used for the MCU 10 to access the corresponding memory. The bus driver circuit 30 establishes a data connection with multiple control modules in the power automation supporting terminal system through the shared MCU 10 bus, for bidirectional data transmission between the MCU 10 and the power automation supporting terminal. The decoding circuit 40 is used to expand one primary chip select signal into multiple secondary chip select signals for output, and to select the corresponding control modules sharing the MCU 10 bus through the secondary chip select signals.

[0048] Specifically, the MCU bus expansion circuit in this embodiment is compatible with the same core board size as the TI AM3352 series MPU, enabling existing FTU / DTU products developed based on AM3352 to be smoothly migrated to this solution with minimal modifications, greatly saving hardware redevelopment costs. Meanwhile, the MCU-based development environment supports low-level debugging methods such as online simulation and breakpoint setting, making it easier to troubleshoot errors in hardware drivers and applications compared to programming under a Linux system.

[0049] Specifically, the MCU10 bus expansion circuit in this embodiment also includes a power supply circuit 80, which is used to provide operating power for the various circuits at 5V and 3.3V.

[0050] See Figure 5 Specifically, the MCU10 bus expansion circuit in this embodiment also includes an SD card chip circuit 90. The SD card chip circuit 90 uses an industrial-grade SD card chip with the model number CSNP4GCR01-AMW and a capacity of 512MB. It is used as a large-capacity non-volatile storage medium to make up for the insufficient capacity of the built-in Flash memory of the MCU10.

[0051] Specifically, in this embodiment, the industrial-grade SD card chip is connected to the MCU10 via the SD card bus. It is an SLC chip employing single-layer storage technology, characterized by high durability and data reliability, simple structure, and fast read / write speeds, with a write / erase cycle life of 100,000 times. The MCU10 of this invention uses an HPM6750 system combined with this industrial-grade SD card chip, achieving an interface transfer speed of 25MB / s in high-speed mode.

[0052] Specifically, the industrial-grade SD card chip used in this embodiment is merely an example. Depending on actual needs, an industrial-grade SD card chip of the corresponding capacity can be flexibly replaced without modifying its peripheral hardware circuitry.

[0053] Specifically, in this embodiment, the MCU10 integrates a DMA (Direct Memory Access Controller). After acquiring control of the FEMC data bus, the DMA controller directly controls the bus access parameter data to perform high-speed transmission between various control modules and memory circuits 20 without going through the CPU of the MCU10. This reduces the number of times the CPU intervenes, greatly reducing the CPU burden. During data transmission, the CPU can process other tasks in parallel, improving the overall system efficiency. The DMA controller, in conjunction with the high-speed parallel bus of the FEMC controller, can perform large data volume transmission with extremely high efficiency, meeting the bandwidth requirements of scenarios such as high-speed ADC sampling.

[0054] Specifically, this embodiment uses high-speed telemetry data acquisition as an example to illustrate the data transmission process:

[0055] The currently selected control module is the telemetry module 70. The CPU configures the DMA controller, sets its source address to the mapping address of the ADC sampling chip in the telemetry module 70 in the external storage area of ​​the FEMC, and sets its target address to a buffer in the SDRAM memory of the memory circuit 20.

[0056] The CPU configures the FEMC controller to set precise read timings for the ADC sampling chip.

[0057] After the DMA controller transfer is initiated, the DMA controller directly stores the sampled data into the SDRAM memory through the FEMC data bus each time the ADC sampling chip completes sampling.

[0058] Once a set number of sampled data points are collected, the DMA controller generates an interrupt signal and sends it to the CPU, which then begins to calculate or analyze the sampled data in the SDRAM memory.

[0059] After the DMA controller transmission is initiated, the telemetry module 70 sends a sampling data transmission request to the DMA controller. The DMA controller requests control of the FEMC data bus from the CPU based on the data transmission request. After obtaining control, it takes over the FEMC data bus and performs sampling data transmission.

[0060] Once the sampling data transmission is complete, the DMA controller releases control of the FEMC data bus and generates an interrupt signal to notify the CPU that the transmission is complete.

[0061] In this embodiment, the FEMC controller has two areas in the system memory of the MCU10, including the FEMC controller area and the FEMC external storage area. The FEMC controller area corresponds to the register space of the FEMC controller. The MCU10 sets the corresponding parameters of the bus access parameter data by configuring the FEMC register values. The FEMC external storage area corresponds to the address space of the memory circuit 20 and the decoding circuit 40.

[0062] Specifically, in this embodiment, when the CPU accesses the address of the FEMC external storage area, the FEMC controller automatically drives the relevant pins according to the FEMC register configuration to generate corresponding signals to realize read and write control of the SDRAM memory or control module.

[0063] In this embodiment, the multiple primary chip select signals include a first primary chip select signal DRAM_nCS0 and a second primary chip select signal DRAM_nCS1, the generation of which includes:

[0064] The FEMC external memory area is divided into two sub-regions, which correspond to the first chip select signal DRAM_nCS0 and the second chip select signal DRAM_nCS1, respectively.

[0065] The FEMC controller accesses the corresponding address and its sub-region based on the FEMC register value;

[0066] The first chip select signal DRAM_nCS0 is output to the memory circuit 20, or the second chip select signal DRAM_nCS1 is output to the bus driver circuit 30 and the decoding circuit 40, depending on the sub-region.

[0067] In this embodiment, the setting of the bus access parameter data includes:

[0068] By configuring the FEMC register value, corresponding timing parameters can be set for different chip select spaces.

[0069] The FEMC controller accesses the corresponding address and its chip select space according to the FEMC register value, and calls the timing parameters corresponding to the chip select space to generate the bus access parameter data.

[0070] The chip select space includes: a memory circuit 20 that has undergone one chip select and multiple control modules that have undergone two chip selects.

[0071] In this embodiment, MCU10 uses a dual-core microcontroller of model HPM6750, which adopts a RISC-V core; the FEMC controller area of ​​the dual-core microcontroller is 0xF3050000~0xF3053FFF, and the FEMC external storage area is 0x40000000~0x4FFFFFFF, wherein the maximum capacity of the FEMC external storage area is 256MB.

[0072] See Figure 2 In this embodiment, the memory circuit 20 uses an SDRAM memory, and the space address of the SDRAM memory is expanded to 32MB or 64MB through the 32-bit or 64-bit FEMC data bus.

[0073] The chip select terminal of the SDRAM memory is connected to the first chip select signal DRAM_nCS0. When the first chip select signal DRAM_nCS0 is low, the SDRAM memory is selected and corresponding access operations are performed on it.

[0074] Specifically, the bus address routing in the SDRAM memory peripheral circuit of this embodiment includes: bus address SDRAM_DQ[31:0] and extended address SDRAM_A[12:0]. When using a 32MB address space SDRAM memory, simply solder the chip of the corresponding capacity and leave the high-order SDRAM_A12 pin of the extended address floating; when using a 64MB address space SDRAM memory, simply solder the chip of the corresponding capacity and add the high-order SDRAM_A12 pin of the extended address. No hardware circuit modification is required, which shows that the memory circuit 20 of this invention can be compatible with memory chips of two different capacities.

[0075] See Figure 3 In this embodiment, the bus driving circuit 30 adopts a CMOS 16-channel tri-state bus driver, which shares the 16-bit FEMC data bus with the SDRAM memory and forms 16 data channels with high level, low level or high impedance state.

[0076] Specifically, this embodiment uses a bus driver of model 74LVCH162245, which shares the FEMC data bus of SDRAM_DQ0-SDRAM_DQ15 with the SDRAM memory. The bus driver is composed of a tri-state buffer made of 16 CMOS circuits, which can meet the tri-state control requirements of 16 data channels.

[0077] The chip select terminal of the bus driver receives the second primary chip select signal DRAM_nCS1. When the second primary chip select signal DRAM_nCS1 is low, the bus driver is selected; otherwise, the 16 data channels are in a high-impedance state.

[0078] In this invention, the bus driver is in a high-impedance state when not selected, which can reduce interference to the current selection circuit of the FEMC data bus, especially the 16-way bus shared with the SDRAM memory. This can avoid signal level confusion and power consumption surge caused by shared bus conflicts. Secondly, the bus driver consumes almost no drive current when in the high-impedance state, thereby reducing the static power consumption of the system.

[0079] When the bus driver is activated, the bus driver switches the data transmission direction through the read signal NOE (SDRAM_A12) to achieve bidirectional data transmission.

[0080] When NOE (SDRAM_A12) is low, the data of the control module that is selected by the secondary chip select is read into MCU10.

[0081] When NOE (SDRAM_A12) is high, the bus access parameter data is sent to the control module that is selected by the secondary chip select at this time.

[0082] Specifically, this embodiment also includes a buffer chip. The buffer chip adopts a dual-channel Schmitt trigger buffer to expand the driving capability of read and write signals. Under a 3.3V power supply voltage, it has an output driving capability of ±24mA, which meets the needs of expanding the read and write driving capability of multiple chips.

[0083] See Figure 4 In this embodiment, the decoding circuit 40 adopts a 3-line to 8-line decoder, which shares the 3-bit FEMC data bus with the SDRAM memory. It is used to decode the 3-bit FEMC data bus as an address bus, expand one primary chip select signal into eight secondary chip select signals, and output them to multiple control modules respectively.

[0084] Specifically, in this embodiment, the 3-to-8 line decoder shares the FEMC data bus of SDRAM_DQ24-SDRAM_DQ26 or SDRAM_DQ29-SDRAM_DQ31 with the SDRAM memory. When accessing external data memory, that is, the corresponding address bus A16-A18 or A21-A23, the 3-to-8 line decoder is activated when the second primary chip select signal DRAM_nCS1 received by the 3-to-8 line decoder is low.

[0085] Of the eight secondary chip select signals, one is a low-level valid signal and the rest are high-level.

[0086] Specifically, in this embodiment, the 3-to-8 line decoder used in the decoding circuit 40 is a preferred option in combination with the aforementioned bus driver, but it is not the only option. For example, a 4-to-16 line decoder can be used to expand 16 secondary chip select signals to meet the needs of a centralized DTU with more channels, but more external bus drivers are required to expand the driving capability of the bus driver accordingly.

[0087] In this embodiment, the eight secondary chip select signals are respectively input to eight control modules, which are remote signaling module 50, remote control module 60 or remote measurement module 70. The corresponding three-remote module is selected according to the validity of the low level of the secondary chip select signal.

[0088] Among them, the eight remote control modules have 16×a channels for remote signal input, 16×b channels for remote control output, and 16×c channels for telemetry signal sampling.

[0089] Where a+b+c=8, and a, b, and c are all non-negative integers.

[0090] Specifically, this embodiment flexibly uses eight secondary chip select signals YX_YK_YC_CS0~YX_YK_YC_CS7 according to actual needs to meet the requirements of different products. For example, the telemetry module 70 can occupy four of the secondary chip select signals and connect four external ADC sampling chips to achieve 64 channels of analog data acquisition; the remote signaling module 50 occupies three of the secondary chip select signals to achieve 48 channels of remote signaling input, etc.

[0091] In this embodiment, when the chip select space is the remote signaling module 50 or the remote control module 60, the timing parameters are configured according to the stability of its digital signal input or output.

[0092] When the chip select space is the telemetry module 70, the timing parameters are configured according to the timing requirements of the ADC sampling chip in the telemetry module 70.

[0093] Specifically, this embodiment uses telemetry data acquisition as an example to illustrate its timing parameter settings:

[0094] Select the parallel mode timing of the ADC sampling chip;

[0095] Configure timing parameters according to the timing requirements of the parallel mode, including:

[0096] Falling edge to Falling edge establishment time rising edge to Rising edge hold time High-level pulse width, Low-level pulse width, Data access time after falling edge Rising edge to bus high impedance time arrive Establishment time, High-level pulse width, Low-level pulse width, Keep time, configure data to Establish time, configure data to Duration and configuration Data settling time from rising edge to rising edge of CONVST.

[0097] in, This is a secondary chip select signal pulse; For parallel data reading control input pulses; The parallel data writing control input pulse is used; CONVST is the analog-to-digital conversion start signal.

[0098] Specifically, this embodiment uses the selection of one remote signaling module 50, one remote control module 60, and one telemetry module 70 respectively as an example to illustrate the data transmission process:

[0099] See Figure 6 The remote signaling module 50 includes 16 remote signaling signal inputs from YX1 to YX16. It receives a secondary chip select signal, YX_YK_YC_CS0. When YX_YK_YC_CS0 is low, the remote signaling module 50 is activated and the remote signaling signal is read into the CPU for processing.

[0100] See Figure 7 The remote control module 60 includes 16 remote control signal outputs from DO1 to DO16. It receives a secondary chip select signal, YX_YK_YC_CS1. YX_YK_YC_CS1 is connected to the latch signal terminal of the data latch U299 via an inverter U29A. When YX_YK_YC_CS1 is low, the latch signal is high, which selects the remote control module 60 and sends the remote control signal from the CPU to the corresponding port of the remote control module 60.

[0101] The enable pin of the remote control chip U300 is directly connected to the CPU pin via a pull-up resistor, receiving the KOUTEN_YK10 and KOUTEN_YK11 signals. Upon power-up, the CPU pin is in input mode, and the pull-up resistor ensures the remote control chip U300 is in a high-impedance state, effectively suppressing random signal jumps caused by electromagnetic interference. During system initialization, the CPU pin is initialized as an output pin, and KOUTEN_YK10 and KOUTEN_YK11 are configured to high level. When the application runs and the CPU pin is confirmed to be in output mode, KOUTEN_YK10 and KOUTEN_YK11 are configured to low level again, thereby triggering the remote control chip U300 to execute the remote control task.

[0102] See Figure 8 The telemetry module 70 includes 16 telemetry signal inputs from AIN1+ to AIN16+. It receives a secondary chip select signal YX_YK_YC_CS2. When YX_YK_YC_CS2 is low, the telemetry module 70 is selected. The 16 analog signals are collected by the ADC sampling chip and read into the CPU for processing.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A low-power MCU bus expansion circuit for power automation supporting terminals, characterized in that, include: The system comprises an MCU, a memory circuit, a bus driver circuit, and a decoding circuit. The MCU has a built-in FEMC controller, which establishes a data connection with the memory circuit via the FEMC data bus through the parallel interface of the FEMC controller, and also establishes a data connection with the bus driver circuit and the decoding circuit through the shared FEMC data bus. The MCU has multiple primary chip select signals, and the FEMC controller selects the corresponding circuits sharing the FEMC data bus based on these primary chip select signals. The memory circuit is used for the MCU to access the corresponding memory. The bus driver circuit establishes a data connection with multiple control modules in the power automation terminal system through the shared MCU bus, enabling bidirectional data transmission between the MCU and the power automation terminal. The decoding circuit expands one primary chip select signal into multiple secondary chip select signals, and selects the corresponding control modules sharing the MCU bus through these secondary chip select signals. The FEMC controller has two areas in the system memory of the MCU: the FEMC controller area and the FEMC external storage area. The FEMC controller area corresponds to the register space of the FEMC controller, and the MCU sets the bus access parameter data by configuring the FEMC register values. The FEMC external storage area corresponds to the address space of the memory circuit and the decoding circuit.

2. The low-power MCU bus expansion circuit for power automation supporting terminals according to claim 1, characterized in that: The multiple primary chip select signals include a first primary chip select signal and a second primary chip select signal, the generation of which includes: The FEMC external storage area is divided into two sub-regions, which correspond to the first chip select signal and the second chip select signal, respectively. The FEMC controller accesses the corresponding address and its sub-region based on the FEMC register value; The first chip select signal is output to the memory circuit, or the second chip select signal is output to the bus driver circuit and the decoding circuit, depending on the sub-region.

3. The low-power MCU bus expansion circuit for power automation supporting terminals according to claim 1, characterized in that: The settings for the bus access parameter data include: By configuring the FEMC register value, corresponding timing parameters can be set for different chip select spaces; The FEMC controller accesses the corresponding address and its chip select space according to the FEMC register value, and calls the timing parameters corresponding to the chip select space to generate the bus access parameter data; The chip select space includes: the memory circuit that has undergone a first chip select, and a plurality of the control modules that have undergone a second chip select.

4. The low-power MCU bus expansion circuit for power automation supporting terminals according to any one of claims 1-3, characterized in that: The MCU is a dual-core microcontroller of model HPM6750, which uses a RISC-V core. The FEMC controller area of ​​the dual-core microcontroller is 0xF3050000~0xF3053FFF, and the FEMC external storage area is 0x40000000~0x4FFFFFFF. The maximum capacity of the FEMC external storage area is 256MB.

5. The low-power MCU bus expansion circuit for power automation supporting terminals according to claim 4, characterized in that: The memory circuit uses SDRAM memory, and the address space of the SDRAM memory is expanded to 32 MB or 64 MB through the 32-bit or 64-bit FEMC data bus. The chip select pin of the SDRAM memory is connected to a first chip select signal. When the first chip select signal is low, the SDRAM memory is selected and corresponding access operations are performed on it.

6. The low-power MCU bus expansion circuit for power automation supporting terminals according to claim 5, characterized in that: The bus driving circuit adopts a CMOS 16-channel tri-state bus driver, which shares the 16-bit FEMC data bus with the SDRAM memory and forms 16 data channels with high level, low level or high impedance state. The chip select pin of the bus driver receives a second primary chip select signal. When the second primary chip select signal is low, the bus driver is selected; otherwise, the 16 data channels are in a high-impedance state.

7. The low-power MCU bus expansion circuit for power automation supporting terminals according to claim 6, characterized in that: The decoding circuit uses a 3-to-8 line decoder, which shares a 3-bit FEMC data bus with the SDRAM memory. It is used to decode the 3-bit FEMC data bus as an address bus, thereby expanding one primary chip select signal into eight secondary chip select signals and outputting them to multiple control modules respectively. Of the eight secondary chip select signals, one is a low-level valid signal and the rest are high-level.

8. The low-power MCU bus expansion circuit for power automation supporting terminals according to claim 7, characterized in that: The eight secondary chip select signals are respectively input to eight control modules, which are remote signaling modules, remote control modules, or telemetry modules. The corresponding three-remote module is selected according to the validity of the low level of the secondary chip select signal. Among them, the eight remote control modules have 16×a channels for remote signal input, 16×b channels for remote control output, and 16×c channels for telemetry signal sampling. Where a+b+c=8, and a, b, and c are all non-negative integers.

9. The low-power MCU bus expansion circuit for power automation supporting terminals according to claim 8, characterized in that: When the chip select space is a remote signaling module or a remote control module, the timing parameters are configured according to the stability of its digital signal input or output; When the chip select space is a telemetry module, the timing parameters are configured according to the timing requirements of the ADC sampling chip in the telemetry module.

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