Chip sorting identification circuit

Abstract

The invention provides a chip sorting identification circuit. The first control circuit couples the resistance circuit to a first operating voltage or a first contact according to whether the chip is coupled with a post-stage chip. The second control circuit couples the resistance circuit to a second operating voltage or a third contact according to whether the chip is coupled to the preceding-stage chip. And the identification circuit judges the sequence of the chips according to the reference voltage provided by the resistance circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to a detection circuit, in particular to a chip rank identification circuit. BACKGROUND

[0002] Currently, the area of dynamic random access memory integrated circuit (DRAM IC) is limited, and therefore, through silicon via (TSV) is used to link multiple DRAM ICs in a stack to increase the capacity. However, each stacked IC needs to know its rank position in the stack to correctly access the DRAM rank. SUMMARY

[0003] The present application provides a chip rank identification circuit, which can effectively utilize the TSV area and achieve chip rank identification.

[0004] The chip rank identification circuit of the present application is suitable for detecting the rank of a chip. The chip rank identification circuit includes a detection circuit and an identification circuit. The detection circuit has a first contact and a second contact, and includes a first switch circuit, a resistance circuit, and a first control circuit. The first switch circuit is coupled to the first contact. The resistance circuit is coupled to the first switch circuit. The first control circuit is coupled to the first switch circuit and the second contact, and determines whether the chip is coupled to a next-stage chip according to the voltage on the second contact, and controls the first switch circuit to switch the resistance circuit to be coupled to the first contact or to be coupled to a first operating voltage. The identification circuit is coupled to the resistance circuit, and determines the rank of the chip according to the reference voltage provided by the resistance circuit.

[0005] In an embodiment of the present application, the detection circuit includes a third contact, a fourth contact, a second switch circuit, and a second control circuit. The second control circuit is coupled to the second switch circuit and the fourth contact, and determines whether the chip is coupled to a previous-stage chip according to the voltage on the fourth contact, and controls the second switch circuit to switch the resistance circuit to be coupled to the third contact or to be coupled to a second operating voltage.

[0006] In an embodiment of the present application, the identification circuit includes a voltage dividing circuit, a selection circuit, and a determination circuit. The voltage dividing circuit is coupled to the resistance circuit, and divides the reference voltage to generate a first divided voltage. The selection circuit selects the reference voltage or the first divided voltage as an output signal according to the reference voltage, the first divided voltage, a first threshold voltage, and a second threshold voltage. The determination circuit determines the rank of the chip according to the output signal.

[0007] In an embodiment of the present application, the selection circuit includes a first comparator circuit and a second comparator circuit. The first comparator circuit has its positive input coupled to the first threshold voltage and its negative input coupled to the reference voltage. The second comparator circuit has its positive input coupled to the second threshold voltage and its negative input coupled to the first divided voltage. A multiplexer circuit has its inputs coupled to the outputs of the first and second comparator circuits and has its output coupled to the output signal. The output signal is indicative of the rank of the chip.

[0008] In an embodiment of the present application, the selection circuit includes a first comparator circuit and a second comparator circuit. The first comparator circuit has its positive input coupled to the first threshold voltage and its negative input coupled to the reference voltage. The second comparator circuit has its positive input coupled to the second threshold voltage and its negative input coupled to the first divided voltage. A multiplexer circuit has its inputs coupled to the outputs of the first and second comparator circuits and has its output coupled to the output signal. The output signal is indicative of the rank of the chip.

[0009] In an embodiment of the present application, the selection circuit includes a first comparator circuit and a second comparator circuit. The first comparator circuit has its positive input coupled to the first threshold voltage and its negative input coupled to the reference voltage. The second comparator circuit has its positive input coupled to the second threshold voltage and its negative input coupled to the first divided voltage. A multiplexer circuit has its inputs coupled to the outputs of the first and second comparator circuits and has its output coupled to the output signal. The output signal is indicative of the rank of the chip.

[0010] In an embodiment of the present application, the selection circuit includes a first comparator circuit and a second comparator circuit. The first comparator circuit has its positive input coupled to the first threshold voltage and its negative input coupled to the reference voltage. The second comparator circuit has its positive input coupled to the second threshold voltage and its negative input coupled to the first divided voltage. A multiplexer circuit has its inputs coupled to the outputs of the first and second comparator circuits and has its output coupled to the output signal. The output signal is indicative of the rank of the chip.

[0011] In an embodiment of the present application, the selection circuit includes a first comparator circuit and a second comparator circuit. The first comparator circuit has its positive input coupled to the first threshold voltage and its negative input coupled to the reference voltage. The second comparator circuit has its positive input coupled to the second threshold voltage and its negative input coupled to the first divided voltage. A multiplexer circuit has its inputs coupled to the outputs of the first and second comparator circuits and has its output coupled to the output signal. The output signal is indicative of the rank of the chip.

[0012] In an embodiment of the present application, the selection circuit includes a first comparator circuit and a second comparator circuit. The first comparator circuit has its positive input coupled to the first threshold voltage and its negative input coupled to the reference voltage. The second comparator circuit has its positive input coupled to the second threshold voltage and its negative input coupled to the first divided voltage. A multiplexer circuit has its inputs coupled to the outputs of the first and second comparator circuits and has its output coupled to the output signal. The output signal is indicative of the rank of the chip.

[0013] In an embodiment of the present application, the second control circuit includes a transistor, a first end of the transistor is coupled to the control end of the multiplexer circuit and the fourth junction, a second end of the transistor is coupled to the ground, and a control end of the transistor is controlled by the enable signal to be turned on, the transistor generates the selection control signal according to the voltage on the first end of the transistor to control the multiplexer circuit to couple the resistance circuit to the third junction or the second operating voltage.

[0014] In an embodiment of the present application, the third junction is directly or indirectly connected to a first front-stage connection through silicon via.

[0015] In an embodiment of the present application, the chip is coupled to a front-stage chip through the first front-stage connection through silicon via.

[0016] In an embodiment of the present application, the fourth junction is directly or indirectly connected to a second front-stage connection through silicon via, and the chip is coupled to the front-stage chip through the second front-stage connection through silicon via.

[0017] In an embodiment of the present application, the first junction is directly or indirectly connected to a first back-stage connection through silicon via.

[0018] In an embodiment of the present application, the chip is coupled to a back-stage chip through the first back-stage connection through silicon via.

[0019] In an embodiment of the present application, the second junction is directly or indirectly connected to a second back-stage connection through silicon via, and the chip is coupled to the back-stage chip through the second back-stage connection through silicon via.

[0020] Based on the above, the first control circuit of the embodiment of the present application couples the resistance circuit to the first operating voltage or the first back-stage connection through silicon via according to the coupling situation with the back-stage chip, the second control circuit couples the resistance circuit to the second operating voltage or the first front-stage connection through silicon via according to the coupling situation with the front-stage chip, and the identification circuit can judge the order of the chip according to the reference voltage provided by the resistance circuit. Since the embodiment of the present application only needs to occupy two through silicon vias between two chips, the through silicon via area can be effectively utilized, and the order identification of the chip is realized.

[0021] In order to make the above features and advantages of the present application more obvious and easy to understand, the following specific embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 With Figure 2 is a schematic diagram of a chip order identification circuit according to an embodiment of the present application;

[0023] Figure 3 is a schematic diagram of resistance circuit series connection of a plurality of chips according to an embodiment of the present application;

[0024] Figure 4 is a chip rank-resistor size correspondence diagram according to an embodiment of the present application;

[0025] Figure 5 is a schematic diagram of a recognition circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order that the present application can be more readily understood, the following specific embodiments are given as examples in which the present application can be implemented. In addition, wherever possible, the same reference numerals are used in the drawings and the embodiments to represent the same or similar components.

[0027] Figure 1 is a schematic diagram of a chip rank recognition circuit according to an embodiment of the present application, please refer to Figure 1 . The chip rank recognition circuit 100 can be disposed in each chip in the chip stack, so that each chip can automatically determine its chip rank. The chip rank recognition circuit 100 can include a detection circuit 102 and a recognition circuit 104, wherein the detection circuit 102 has contacts CT1-CT4, and can include a first switching circuit 106, a second switching circuit 108, a first control circuit 110, a second control circuit 112 and a resistor circuit 114. Due to the possible existence of process structures of strengthening functions or reinforcing structures between the contacts and the through silicon vias, the contacts CT1-CT4 are respectively directly or indirectly connected to the first back-end connection through silicon via TSV1, the second back-end connection through silicon via TSV2, the first front-end connection through silicon via TSV3 and the second front-end connection through silicon via TSV4. The resistor circuit 114 is connected in series between the contacts CT1 and CT3 with the first switching circuit 106 and the second switching circuit 108, and the resistor circuit 114 is also coupled to the recognition circuit 104, the control circuit 110 is coupled to the first switching circuit 106 and the contact CT2, and the control circuit 112 is coupled to the second switching circuit 108 and the contact CT4.

[0028] The first control circuit 110 can determine whether the chip is coupled to the subsequent chip (i.e., whether there is a stack of chips above the chip in the application chip sorting and identification circuit 100) based on the voltage on the second subsequent stage connection silicon via TSV2, and control the first switching circuit 106 to switch the resistor circuit 114 to the first subsequent stage connection silicon via TSV1 to couple with the resistor circuit of the subsequent chip, or switch the resistor circuit 114 to the first operating voltage VCCP. For example, when the voltage on the second subsequent stage connection silicon via TSV2 is the first default voltage, the first control circuit 110 can determine that the second subsequent stage connection silicon via TSV2 is coupled to the subsequent chip, and control the first switching circuit 106 to switch the resistor circuit 114 to the first subsequent stage connection silicon via TSV1 to couple with the resistor circuit of the subsequent chip. Conversely, if the voltage on the second downstream connected silicon via TSV2 is not the first default voltage, it can be determined that the chip in the application chip sorting identification circuit 100 is the topmost chip. At this time, the first control circuit 110 controls the first switching circuit 106 to switch the resistor circuit 114 to the first operating voltage VCCP.

[0029] Similarly, the second control circuit 112 can determine whether the chip is coupled to the front-end chip (i.e., whether the chip of the application chip sorting identification circuit 100 is stacked on top of the front-end chip) based on the voltage on the second front-end connection silicon via TSV4, and control the second switching circuit 108 to switch the resistor circuit 114 to the first front-end connection silicon via TSV3 to couple with the resistor circuit of the front-end chip, or switch the resistor circuit 114 to the second operating voltage VSS, where the second operating voltage VSS can be, for example, ground voltage, but is not limited thereto. For example, when the voltage on the second front-end connection silicon via TSV4 is the second default voltage, the second control circuit 112 can determine that the second front-end connection silicon via TSV4 is coupled to the front-end chip, and control the second switching circuit 108 to switch the resistor circuit 114 to the first front-end connection silicon via TSV3 to couple with the resistor circuit of the front-end chip. Conversely, if the voltage on the second front-end connected silicon via TSV4 is not the second default voltage, it can be determined that the chip in the application chip sorting identification circuit 100 is the bottom chip. At this time, the second control circuit 112 controls the second switching circuit 108 to switch the resistor circuit 114 to the second operating voltage VSS.

[0030] The resistor circuit 114 can generate a reference voltage Vref1 for the identification circuit 104 in the case of the application chip sorting and identification circuit 100 stacking chips with other chips. The identification circuit 104 can determine the sorting of the chips in the application chip sorting and identification circuit 100 based on the reference voltage Vref1.

[0031] In detail, the implementation of the chip sorting and recognition circuit 100 can be as follows: Figure 2The first switching circuit 106 and the second switching circuit 108 can be implemented by multiplexer circuits MUX1 and MUX2, respectively, and the first control circuit 110 and the second control circuit 112 can be implemented by transistors M1 and M2, respectively. The resistance circuit 114 can include resistors RD1 and RD2, for example, which can have the same resistance value, but are not limited thereto.

[0032] The input of the multiplexer circuit MUX1 is coupled to the first back-side TSV 1 and one end of the transistor M1 is coupled to the second back-side TSV 2 and the control terminal of the multiplexer circuit MUX1. The other end of the transistor M1 is coupled to ground, and the control terminal of the transistor M1 is controlled by the enable signal VEN1 to be turned on. The transistor M1 can generate a selection control signal at one end coupled to the second back-side TSV 2 to control the multiplexer circuit MUX1, so as to control the multiplexer circuit MUX1 to couple the resistance circuit 114 to the first back-side TSV 1 or the first operating voltage VCCP. The resistors RD1 and RD2 are connected in series between the output of the multiplexer circuit MUX1 and the output of the multiplexer circuit MUX2, and the common connection point of the resistors RD1 and RD2 is coupled to the identification circuit 104. The input of the multiplexer circuit MUX2 is coupled to the second operating voltage VSS and the first front-side TSV 3, and one end of the transistor M2 is coupled to the second front-side TSV 4 and the control terminal of the multiplexer circuit MUX2. The other end of the transistor M1 is coupled to ground, and the control terminal of the transistor M2 is controlled by the enable signal VEN2 to be turned on. The transistor M2 can generate a selection control signal at one end coupled to the second front-side TSV 4 to control the multiplexer circuit MUX2, so as to control the multiplexer circuit MUX2 to couple the resistance circuit 114 to the first front-side TSV 3 or the second operating voltage VSS.

[0033] When the transistor Ml is in the on state, the multiplexer circuit MUXl is controlled to select coupling the first back-side connection through silicon via TSVl to the resistance circuit 114 by the first default voltage upVDD from the back-side chip detected through the second back-side connection through silicon via TSV2 when the second back-side connection through silicon via TSV2 is coupled to the back-side chip, and is controlled to select coupling the first operating voltage VCCP to the resistance circuit 114 by the ground voltage (or floating voltage) detected when the second back-side connection through silicon via TSV2 is not coupled to the back-side chip. Similarly, when the transistor M2 is in the on state, the multiplexer circuit MUX2 is controlled to select coupling the first front-side connection through silicon via TSV3 to the resistance circuit 114 by the second default voltage dnVDD from the front-side chip detected through the second front-side connection through silicon via TSV4 when the second front-side connection through silicon via TSV4 is coupled to the front-side chip, and is controlled to select coupling the second operating voltage VSS to the resistance circuit 114 by the ground voltage (or floating voltage) detected when the second front-side connection through silicon via TSV4 is not coupled to the front-side chip. In this way, the resistance circuit of each chip outputs the reference voltage corresponding to the chip rank.

[0034] For example, Figure 3 For the embodiment of stacking 3 chips (total of 4 chips), the resistance circuit 114 of each chip includes two resistors R connected in series, and the through silicon vias between the chips (including the first back-side connection through silicon via TSVl and the first front-side connection through silicon via TSV3) have a resistance Rtsv. Taking the reference voltage Vrefl output by the detection circuit 102-3 corresponding to chip rank 2 (Rank 2) as an example, the voltage value of the reference voltage Vrefl can be shown as the following equation (1).

[0035]

[0036] where Rrank2 is the resistance corresponding to chip rank 2 (Rank 2), Rtotal is the sum of the resistance of the resistance circuit 114 of the 4 chips and the resistance of the through silicon vias between the chips, and in the case of VCCP equal to 2.9V, R equal to 10 ohm, and Rtsv equal to 0.8 ohm, Vrefl is equal to 1.82V. Similarly, the resistances RrankO, Rrankl, Rrank3 corresponding to chip ranks 0, 1, 3 can be shown as R, 3R+Rtsv, and 7R+3Rtsv respectively as shown in equation (2). Figure 4 The detection circuits 102-0~102-4 of different chip ranks can correspondingly output reference voltages Vrefl with different voltage values, so that the identification circuit 104 of each chip can determine the rank of each chip according to the reference voltage Vrefl provided by the corresponding detection circuit 102. In addition, asFigure 4 As shown, the number of chip stacks is not limited to Figure 3 In other embodiments, fewer or more chips can be stacked, such as 1 or 7 chips.

[0037] Further, the identification circuit 104 can include a voltage dividing circuit 202, a selection circuit 204, and a determination circuit 206. The voltage dividing circuit 202 is coupled to the resistance circuit 114 and the selection circuit 204. The selection circuit 204 is coupled to the resistance circuit 114 and the determination circuit 206. The voltage dividing circuit 202 can include n voltage dividing resistance circuits. A first voltage dividing resistance circuit divides the reference voltage Vref1 to generate a first voltage dividing voltage. An nth voltage dividing resistance circuit divides an (n-1)th voltage dividing voltage outputted from an (n-1)th voltage dividing resistance circuit to generate an nth voltage dividing voltage, where n is an integer greater than 1. For example, in an embodiment, the voltage dividing circuit 202 includes voltage dividing resistance circuits 210 and 212. The voltage dividing resistance circuit 210 includes resistors RD3 and RD4. The voltage dividing resistance circuit 212 includes resistors RD5 and RD6. The resistors RD3 and RD4 are connected in series between a common node of the resistors RD1 and RD2 and ground. The resistors RD5 and RD6 are connected in series between a common node of the resistors RD3 and RD4 and ground. The resistors RD3 and RD4 can have the same resistance value. The resistors RD5 and RD6 can have the same resistance value, but are not limited thereto. The voltage dividing resistance circuit 210 divides the reference voltage Vref1 provided by the resistance circuit 114 to generate a first voltage dividing voltage Vref2. The voltage dividing resistance circuit 212 divides the first voltage dividing voltage Vref2 provided by the voltage dividing resistance circuit 210 to generate a second voltage dividing voltage Vref3. Figure 2 The selection circuit 204 selects one of the reference voltage Vref1, the first voltage dividing voltage Vref2, and the second voltage dividing voltage Vref3 as an output signal VO1 according to the reference voltage Vref1, the first voltage dividing voltage Vref2, a first threshold voltage V1, and a second threshold voltage V2. For example, in an embodiment, the first threshold voltage V1 and the second threshold voltage V2 can be set to a voltage value between 0.634 and 0.816 according to a first operating voltage VCCP, a second operating voltage VSS, a resistor R, and a resistor Rtsv. For example, the first threshold voltage V1 and the second threshold voltage V2 can be set to 0.8 V, but are not limited thereto. The first threshold voltage V1 and the second threshold voltage V2 can be, for example, voltages provided by a bandgap voltage reference circuit. The determination circuit 206 determines the order of the chips according to the output signal VO1 and outputs an identification signal SC1.

[0038] Figure 3

[0039] ​​Furthermore, the selection circuit 204 may include comparator circuits CP1 and CP2 and a multiplexer circuit 208. The positive and negative input terminals of comparator circuit CP1 are coupled to a reference voltage Vref1 and a first threshold voltage V1, respectively. The positive and negative input terminals of comparator circuit CP2 are coupled to a first voltage divider voltage Vref2 and a second threshold voltage V2, respectively. The input terminals of comparator circuits CP1 and CP2 are coupled to the selection control terminal of multiplexer circuit 208. The input terminal of multiplexer circuit 208 receives the reference voltage Vref1, the first voltage divider voltage Vref2, and the second voltage divider voltage Vref3. The output terminal of multiplexer circuit 208 is coupled to judgment circuit 206.

[0040] The multiplexer circuit 208 can select one of the reference voltage Vref1, the first voltage divider Vref2, and the second voltage divider Vref3 as the output signal VO1 based on the comparison voltage VP1 output by comparator circuit CP1 comparing the reference voltage Vref1 with the first threshold voltage V1, and the comparison voltage VP2 output by comparator circuit CP2 comparing the first voltage divider Vref2 with the second threshold voltage V2. The judgment circuit 206 can determine the chip sequence based on the output signal VO1 and output the identification signal SC1 accordingly.

[0041] Furthermore, the judgment circuit 206 can, for example, be used as follows: Figure 5 The implementation method is as follows. The judgment circuit 206 may include resistors R1-R7, comparator circuits CPA-CPF, and logic circuit 502. The positive input terminals of comparator circuits CPA-CPF receive the output signal VO1 provided by the selection circuit 204, and the output terminals of comparator circuits CPA-CPF are respectively coupled to the input terminals A1-F1 of logic circuit 502. Resistors R1-R7 are connected in series between the power supply voltage VDD and ground. The common contact of two adjacent resistors is coupled to the negative input terminal of the corresponding comparator circuit CPA-CPF. Furthermore, the input terminal G1 of logic circuit 502 is coupled to the contact of the second pre-amplifier silicon via to receive the second default voltage dnVDD. In cases where there are 7 or fewer chips stacked (8 chips in total), logic circuit 502 may, for example, use a 3-bit signal as the identification signal SC1, where the bit value of identification signal SC1 is CID. <0> CID <1> CID <2> It can be shown in equations (2) to (4) below.

[0042]

[0043] Where A to G are the signals received by the input terminals A1 to G1 of the logic circuit 502. Thus, the chip sorting and identification circuit 100 of each chip provides the identification signal SC1 that indicates the chip sorting, which can effectively realize the sorting and identification of the chips.

[0044] In summary, the first control circuit of the embodiment of the application couples the resistance circuit to the first operating voltage or the first back-level connection silicon via according to the coupling situation with the back-level chip, the second control circuit couples the resistance circuit to the second operating voltage or the first front-level connection silicon via according to the coupling situation with the front-level chip, and the identification circuit can judge the sequencing of the chip according to the reference voltage provided by the resistance circuit. Since the embodiment of the application only occupies 2 silicon vias between two chips, the silicon via area can be effectively utilized, and the sequencing identification of the chip is realized.

[0045] Although the present application has been disclosed with the above embodiments, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application, so the protection scope of the present application shall be subject to the right claims.

Claims

1. A chip sorting and identification circuit, suitable for detecting the sorting of chips, characterized in that, include: A detection circuit having a first contact and a second contact, the detection circuit comprising: The first switching circuit is coupled to the first contact; A resistor circuit, coupled to the first switching circuit; and A first control circuit, coupled to the first switching circuit and the second contact, determines whether the chip is coupled to a subsequent chip based on the voltage at the second contact, and controls the first switching circuit to switch the resistor circuit to couple to the first contact, or to couple the resistor circuit to a first operating voltage; and An identification circuit, coupled to the resistor circuit, determines the order of the chips based on the reference voltage provided by the resistor circuit.

2. The chip sorting and identification circuit according to claim 1, characterized in that, The detection circuit includes: Third connection point; Fourth connection point; The second switching circuit; and The second control circuit is coupled to the second switching circuit and the fourth contact. Based on the voltage on the fourth contact, it determines whether the chip is coupled to the front-end chip, and controls the second switching circuit to switch the resistor circuit to the third contact, or to switch the resistor circuit to the second operating voltage.

3. The chip sorting and identification circuit according to claim 2, characterized in that, The identification circuit includes: The voltage divider circuit, coupled to the resistor circuit, divides the reference voltage to generate the first voltage divider voltage; The selection circuit selects either the reference voltage or the first voltage divider voltage as the output signal based on the reference voltage, the first voltage divider voltage, the first threshold voltage, and the second threshold voltage; and The judgment circuit determines the order of the chips based on the output signal.

4. The chip sorting and identification circuit according to claim 3, characterized in that, The selection circuit includes: The first comparator circuit has its positive and negative input terminals coupled to the first threshold voltage and the reference voltage; The second comparator circuit has its positive and negative input terminals coupled to the second threshold voltage and the first voltage divider voltage; and The multiplexer circuit is coupled to the output terminals of the first comparator circuit and the second comparator circuit. Based on the comparison result of the first comparator circuit and the second comparator circuit, it outputs the reference voltage or the first voltage divider voltage. The judgment circuit determines the order of the chips based on the output signal.

5. The chip sorting and identification circuit according to claim 3, characterized in that, The determination circuit includes: Multiple comparator circuits, whose positive input terminals receive the output signal; Multiple resistors are connected in series between the first threshold voltage and ground, with the nodes between adjacent resistors coupled to the negative input of the corresponding comparator circuit; and A logic circuit, coupled to the output terminals of the plurality of comparator circuits and the fourth contact, outputs an identification signal indicating the order of the chips based on the output voltage of the plurality of comparator circuits and the voltage on the fourth contact.

6. The chip sorting and identification circuit according to claim 2, characterized in that, The resistor circuit includes: First resistor; and The second resistor is connected in series with the first resistor between the first switching circuit and the second switching circuit, and the common contact of the first resistor and the second resistor generates the reference voltage.

7. The chip sorting and identification circuit according to claim 1, characterized in that, The first switching circuit is a multiplexer circuit, whose input terminal is coupled to the first operating voltage and the first contact, the output terminal of the multiplexer circuit is coupled to the resistor circuit, and the control terminal of the multiplexer circuit is coupled to the first control circuit.

8. The chip sorting and identification circuit according to claim 7, characterized in that, The first control circuit includes a transistor, the first terminal of which is coupled to the control terminal of the multiplexing circuit and the second contact, the second terminal of which is coupled to ground, the control terminal of which is turned on by an enable signal, and the transistor generates a selection control signal based on the voltage of the first terminal of the transistor to control the multiplexer circuit to couple the resistor circuit to the first contact or the first operating voltage.

9. The chip sorting and identification circuit according to claim 2, characterized in that, The second switching circuit is a multiplexer circuit, whose input terminal is coupled to the second operating voltage and the third contact, the output terminal of the multiplexer circuit is coupled to the resistor circuit, and the control terminal of the multiplexer circuit is coupled to the second control circuit.

10. The chip sorting and identification circuit according to claim 9, characterized in that, The second control circuit includes a transistor, the first terminal of which is coupled to the control terminal of the multiplexer circuit and the fourth contact, the second terminal of which is coupled to ground, the control terminal of which is turned on by an enable signal, and the transistor generates a selection control signal based on the voltage of the first terminal of the transistor to control the multiplexer circuit to couple the resistor circuit to the third contact or the second operating voltage.

11. The chip sorting and identification circuit according to claim 2, characterized in that, The third contact is directly or indirectly connected to the first front-end interconnect silicon via.

12. The chip sorting and identification circuit according to claim 11, characterized in that, The chip is coupled to the front-end chip via the first front-end connection silicon through-hole.

13. The chip sorting and identification circuit according to claim 12, characterized in that, The fourth contact is directly or indirectly connected to the second front-end connection silicon via, and the chip is coupled to the front-end chip through the second front-end connection silicon via.

14. The chip sorting and identification circuit according to claim 2, characterized in that, The first contact is directly or indirectly connected to the first downstream silicon via.

15. The chip sorting and identification circuit according to claim 14, characterized in that, The chip is coupled to the subsequent chip via the first subsequent stage connection silicon through-hole.

16. The chip sorting and identification circuit according to claim 15, characterized in that, The second contact is directly or indirectly connected to the second downstream interconnect via, and the chip is coupled to the downstream chip through the second downstream interconnect via.

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