Complementary metal oxide semiconductor (CMOS) terahertz on-chip antenna and off-chip double-layer quartz antenna

Abstract

The CMOS terahertz on-chip antenna and off-chip double-layer quartz antenna comprises a chip body, a substrate layer is arranged at the bottom of the chip body, and a metal ground layer, a feeder line layer and a radiation layer are sequentially arranged in the chip body from bottom to top at intervals; a first dielectric layer is arranged at the top of the chip body; a second dielectric layer is arranged at the top of the first dielectric layer; a first metal layer is arranged at the top of the second dielectric layer; a third dielectric layer is arranged at the top of the first metal layer; and a second metal layer is arranged at the top of the third dielectric layer. The CMOS terahertz on-chip antenna cooperates with the off-chip double-layer quartz antenna, high gain and broadband efficient radiation are achieved, and the CMOS terahertz on-chip antenna is suitable for terahertz communication, imaging and 6G application.

Description

Technical Field

[0001] This invention relates to a CMOS terahertz on-chip antenna in conjunction with an off-chip dual-layer quartz antenna, belonging to the field of antenna technology. Background Technology

[0002] Currently, the terahertz band (300GHz–3THz) has become an important research direction in fields such as non-destructive testing, materials analysis, imaging, and sixth-generation mobile communication (6G) due to its high speed and strong anti-interference capability. To reduce system costs and improve integration, the industry typically uses CMOS technology to implement circuits such as amplifier frequency multipliers, terahertz signal sources, and transceivers, and related research results have been accumulated to some extent. Meanwhile, on-chip antennas are widely used in these CMOS amplifier frequency multipliers, terahertz signal sources, and transceivers due to their small size and ease of integration with circuits. This reduces losses caused by wire bonding or flip-chip bonding and provides additional design flexibility, thereby saving costs, space, and design workload, and improving overall integration. However, existing technologies still have the following prominent problems:

[0003] 1. Insufficient gain of traditional on-chip antennas:

[0004] Traditional on-chip antennas, especially those using silicon processes, suffer from energy trapping in surface wave modes and dissipating as heat due to the high dielectric constant and low resistivity of the thick silicon substrate beneath the metal layer. Furthermore, components beneath and around the on-chip antenna (such as transistors and resistors from the active region) can also negatively impact the antenna's gain.

[0005] 2. Traditional on-chip antennas have limited bandwidth:

[0006] Traditional on-chip patch antennas use an uppermost metal layer (AP, Aluminium Pad) as the patch and lower metal layers M1 and M2 as ground layers to maximize the antenna profile and isolate it from the active region and lossy silicon. However, the thin oxide layer on top of the metal layers severely restricts the antenna's bandwidth. Traditional on-chip antennas typically have a bandwidth of less than 5% in the terahertz band and low radiation efficiency, making it difficult to meet the broadband requirements of terahertz systems. Even using a single-layer dielectric (such as quartz) to improve antenna efficiency only provides a limited increase in bandwidth, still insufficient to support wideband communication and imaging applications.

[0007] 3. Common problems existing in current technologies:

[0008] In summary, existing terahertz on-chip antennas implemented using CMOS technology generally suffer from the following common problems:

[0009] 1) The high dielectric constant and low resistivity work together to confine most of the antenna energy within the substrate rather than radiating it out, resulting in extremely low antenna radiation efficiency and gain.

[0010] 2) In CMOS technology, in order to ensure the insulation and planarization between the metal layers, the dielectric layer (SiO2) is very thin (on the order of micrometers), which fundamentally limits the impedance bandwidth of the antenna.

[0011] 3) To achieve a "system-on-a-chip" (SoC), the antenna must be integrated with active / passive components such as transistors, resistors, and capacitors at extremely close range. These components absorb the energy radiated by the antenna (near-field coupling) and alter the electromagnetic environment around the antenna, thereby adversely affecting the antenna's radiation pattern, impedance, and efficiency.

[0012] Therefore, how to implement high-performance terahertz antenna design under CMOS technology, and achieve higher antenna gain, wider antenna bandwidth and higher integration, has become an urgent technical problem to be solved. Summary of the Invention

[0013] Objective: To overcome the limitations of limited bandwidth and gain of on-chip antennas in existing technologies, this invention provides a CMOS terahertz on-chip antenna in conjunction with an off-chip dual-layer quartz antenna, thereby achieving high gain and wideband high-efficiency radiation, suitable for terahertz communication, imaging and 6G applications.

[0014] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0015] A CMOS terahertz on-chip antenna and off-chip dual-layer quartz antenna specifically includes: a chip body, a substrate layer disposed at the bottom of the chip body, and a metal ground layer, a feed layer and a radiating layer disposed sequentially from bottom to top within the chip body.

[0016] A first dielectric layer is provided on the top of the chip body.

[0017] A second dielectric layer is disposed on top of the first dielectric layer.

[0018] A first metal layer is disposed on top of the second dielectric layer.

[0019] A third dielectric layer is disposed on top of the first metal layer.

[0020] A second metal layer is disposed on top of the third dielectric layer.

[0021] Optionally, the metal layer includes an upper metal layer M1 and a lower metal layer M2.

[0022] Optionally, both the second and third dielectric layers are made of quartz.

[0023] Optionally, the second and third dielectric layers have the same length, width, and height.

[0024] Optionally, the second metal layer and the first metal layer are set as rectangles, and the size of the second metal layer is larger than the size of the first metal layer.

[0025] Optionally, the substrate layer is made of silicon, the metal ground layer and feeder layer are made of copper, the radiating layer is made of aluminum, and the chip body is made of silicon dioxide.

[0026] Optionally, the heights of the second and third dielectric layers are set to 100µm, and the heights of the second and first metal layers are set to 200nm.

[0027] Optionally, the expression for the length L of the radiation layer is as follows:

[0028] L ≈ λ0 / (2√ε r )

[0029] Where λ0 is the wavelength in vacuum, ε r It is the relative permittivity of the chip itself.

[0030] Optionally, the length and width of the second dielectric layer and the third dielectric layer are 500µm*600µm; the length and width of the first metal layer and the second metal layer are 90µm*100µm and 240µm*280µm, respectively.

[0031] Optionally, the length and width dimensions of the radiating layer are 170µm*170µm.

[0032] Beneficial effects: This invention provides a CMOS terahertz on-chip antenna combined with an off-chip dual-layer quartz antenna structure, which has the following significant advantages compared with the prior art:

[0033] 1. In terms of structural design, this invention adopts an off-chip quartz and gold-plated solution. Compared with structural optimization inside the chip or external antenna packaging, this design significantly reduces R&D costs and effectively shortens the R&D cycle, providing a feasible path for the efficient development of terahertz antennas.

[0034] 2. The collaborative working mechanism of the on-chip antenna and the off-chip double-layer quartz antenna in this invention significantly improves the overall performance of the antenna, achieving higher radiation efficiency and antenna gain, which helps to enhance signal transmission quality and system sensitivity.

[0035] 3. The antenna structure of this invention exhibits excellent frequency response, possesses a wider impedance bandwidth and gain bandwidth, and can adapt to a wider range of operating frequency band requirements, providing reliable support for broadband applications of terahertz communication and sensing systems. Attached Figure Description

[0036] Figure 1 This is a cross-sectional schematic diagram of a CMOS terahertz on-chip antenna and an off-chip double-layer quartz antenna according to the present invention.

[0037] Figure 2 This is a three-dimensional schematic diagram of a CMOS terahertz on-chip antenna and an off-chip double-layer quartz antenna according to the present invention.

[0038] Figure 3 This is a schematic diagram of the electric field distribution of a 380GHz gold-plated quartz antenna. Figure 3 (a) is a schematic diagram of the electric field distribution of the second gold-plated antenna. Figure 3 (b) is a schematic diagram of the electric field distribution of the first gold-plated antenna.

[0039] Figure 4 This is a schematic diagram of the electric field distribution of a gold-plated quartz antenna at 425 GHz. Figure 4 (a) is a schematic diagram of the electric field distribution of the second gold-plated antenna. Figure 4 (b) is a schematic diagram of the electric field distribution of the first gold-plated antenna.

[0040] Figure 5 This is a schematic diagram showing the gain and impedance bandwidth of a CMOS terahertz on-chip antenna in conjunction with an off-chip double-layer quartz antenna.

[0041] Figure 6 This diagram illustrates the impedance bandwidth of a CMOS terahertz on-chip antenna in conjunction with an off-chip dual-layer quartz antenna, comparing it to an on-chip antenna and a single-layer quartz antenna.

[0042] Figure 7 This diagram illustrates the radiation efficiency of a CMOS terahertz on-chip antenna in conjunction with an off-chip dual-layer quartz antenna, comparing the efficiency of an on-chip antenna and a single-layer quartz antenna. Detailed Implementation

[0043] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0044] The present invention will be further described below with reference to specific embodiments.

[0045] Example 1:

[0046] This embodiment describes a CMOS terahertz on-chip antenna combined with an off-chip dual-layer quartz antenna, the specific structure of which is as follows: Figure 1 and Figure 2As shown, it comprises two parts: one is an on-chip antenna structure integrated inside the chip, and the other is a double-layer quartz antenna structure stacked outside the chip. Specifically, it includes:

[0047] The chip body 100 has a base layer 1 at its bottom and a metal ground layer 2, a feed line layer 3 and a radiation layer 4 arranged sequentially from bottom to top inside the chip body 100.

[0048] A first dielectric layer 5 is provided on the top of the chip body 100.

[0049] A second dielectric layer 200 is disposed on the top of the first dielectric layer 5.

[0050] A first metal layer 6 is disposed on the top of the second dielectric layer 200.

[0051] A third dielectric layer 300 is disposed on the top of the first metal layer 6.

[0052] A second metal layer 7 is disposed on the top of the third dielectric layer 300.

[0053] Furthermore, the substrate layer 1 is made of silicon, serving as the standard substrate material for chip manufacturing. The metal ground layer 2, comprising metal layers M1 and M2, acts as the antenna's ground plane (GND), providing electromagnetic shielding and effectively isolating the substrate layer from the radiating layer, thereby improving antenna performance. The feed layer is configured as a metal layer M8. The radiating layer 4 acts as the antenna and is not directly connected to the feed layer by metal; instead, it is excited through electromagnetic coupling, which helps reduce losses and improve high-frequency performance. The first dielectric layer 5 covers the antenna structure, serving as the outermost protective dielectric layer of the chip.

[0054] The external portion consists of two stacked structures: a second dielectric layer 200 and a first metal layer 6 plated on its upper surface, and a third dielectric layer 300 and a second metal layer 7 plated on its upper surface. Both structures are fabricated using the same process, namely, depositing metal patches on a quartz dielectric substrate. The two quartz structures are stacked and fixed on top of the first dielectric layer 5, without any metal connection between them. The on-chip antenna excites the antenna elements on the external double-layer metallized quartz structure through near-field electromagnetic coupling, thereby achieving effective radiation in the terahertz band.

[0055] The on-chip antenna is manufactured along with the chip. The chip body 1 has dimensions of 650µm*1500µm, the radiating layer 4 has dimensions of 170µm*170µm, and the antenna size is half the wavelength of the operating frequency.

[0056] The dual-layer quartz antenna is fabricated separately. The thickness of the second dielectric layer 200 and the third dielectric layer 300 is 100µm; the thickness of the first metal layer 6 and the second metal layer 7 is 200nm; the length and width of the second dielectric layer 200 and the third dielectric layer 300 are 500µm*600µm, which is convenient for mounting on the chip; the metal sizes of the first metal layer 6 and the second metal layer 7 are 90µm*100µm and 240µm*280µm, respectively, which are the half-wavelength dimensions corresponding to 370GHz and 425GHz around the operating frequency band, and the antenna operating modes are excited at 380GHz and 425GHz. The two quartz layers stacked together form a broadband effect from 360GHz to 440GHz.

[0057] Example 2:

[0058] This embodiment describes the working principle of a CMOS terahertz on-chip antenna combined with an off-chip dual-layer quartz antenna. It employs a second dielectric layer made of quartz, a third dielectric layer, and a first metal layer on top of that. The second metal layer is a rectangular metal sheet, which is the core radiating part of the antenna. Its typical length (L) is approximately half the wavelength of the signal in the dielectric (λ). m / 2).

[0059] Chip: The internal radiating layer of the chip body uses a filling medium between AP and M1, M2 to separate the radiating layer from the ground plane. Its material properties (especially the dielectric constant ε) are important considerations. r This directly affects the performance and size of the antenna. Ground plane: Metal layers M1 and M2 inside the chip, whose size is larger than the radiating patch used to isolate the radiating antenna from the lossy silicon substrate of the chip.

[0060] The radiating layer, ground plane, and the dielectric layer between them together form a low-profile (very small height h) resonant cavity. The top radiating patch and the bottom ground plane are two conductive walls, and the edges of the dielectric layer can be considered magnetic walls. When a high-frequency signal near the resonant frequency is injected into the radiating layer through the feed layer, the electromagnetic energy is confined within this cavity. The electromagnetic waves reflect back and forth between the edges of the radiating layer. For the antenna to operate efficiently, these reflected waves need to be superimposed in phase (i.e., resonant). This occurs when the length L of the radiating layer is approximately equal to the wavelength in the dielectric (λ). m When the wavelength λ in the medium is half of that in the medium. m = λ0 / √ε r Where λ0 is the wavelength in vacuum, ε r It is the relative permittivity of the dielectric substrate. Therefore, L ≈ λ0 / (2√ε r When this condition is met, the electric field at both ends of the radiating layer will reach its maximum and minimum values, forming a stable standing wave mode, thereby enabling the antenna to radiate.

[0061] The present invention relates to a CMOS terahertz on-chip antenna design in conjunction with an off-chip dual-layer quartz antenna. The on-chip portion uses the top metal layer AP as the radiating layer and the bottom metal layers M1 and M2 as ground layers to maximize the antenna profile and isolate it from the active region and lossy silicon.

[0062] The thin oxide layer on the chip severely restricts the antenna bandwidth. Even with electromagnetic coupling feeding, the bandwidth is not significantly improved. Therefore, by adding a metal layer and a quartz layer on top of the on-chip antenna, the actual radiating antenna (which is now gold-plated on a quartz plate) is raised from the chip ground plane through an off-chip structure. This not only improves the radiation efficiency but also expands the antenna bandwidth from 5% to 20% through the principle of stacked patch antennas.

[0063] from Figure 3 (a) and (b) Figure 4 As shown in (a) and (b), the electric field distribution of the proposed antenna is as follows: At 380 GHz, the larger antenna (240µm*280µm) in the second metal layer is excited into operating mode, and the electric field distribution shows that the electric fields of this antenna are in the same direction and superimposed, resulting in radiation. However, the smaller antenna (90µm*100µm) in the first metal layer shows that the vector electric fields are in opposite directions, canceling each other out, and therefore does not radiate at this frequency. The situation is reversed at 425 GHz. The smaller antenna (90µm*100µm) in the first metal layer is excited into operating mode, and the electric field distribution is in the same direction. However, the larger antenna (240µm*280µm) in the second metal layer has opposite directions, canceling each other out, and therefore does not radiate at this frequency.

[0064] Finally passed Figure 5 It can be seen that the proposed CMOS terahertz on-chip antenna, in conjunction with the off-chip dual-layer quartz antenna, achieves good gain within a bandwidth of 80 GHz, while the S11 remains essentially below -10 dB, achieving a bandwidth of 20%. Figure 6 , Figure 7 As shown, traditional on-chip patch antennas have extremely low bandwidth (typically less than 5%) and poor efficiency. Therefore, to achieve high antenna efficiency, this design elevates the antenna using quartz; as the distance between the radiating patch antenna and the ground plane increases, the antenna efficiency improves. To achieve broadband performance, this design employs electromagnetic coupling feeding and stacks two layers of parasitic patch antennas. These two antenna layers excite two operating modes at frequencies of 380 GHz and 425 GHz, respectively. These two modes are superimposed in the frequency domain, ultimately achieving a bandwidth of 80 GHz (i.e., 20% relative bandwidth). Figure 6 , Figure 7It can be seen that although the efficiency of a single-layer quartz antenna is slightly higher than that of a double-layer stacked quartz antenna, its impedance bandwidth is only 5%, which is much smaller than that of a double-layer stacked quartz antenna. Compared with an on-chip antenna without quartz, the double-layer stacked quartz antenna has a great advantage in both bandwidth and radiation efficiency.

[0065] The present invention uses an on-chip patch antenna as an excitation source to excite a quartz dielectric metal layer through electromagnetic coupling. The dual-layer structure can excite two operating modes with center frequencies of 370 GHz and 425 GHz, respectively. The two modes are superimposed in the frequency domain, which extends the antenna bandwidth to about 80 GHz, or about 20%, which is much greater than the less than 5% of traditional on-chip antennas. Furthermore, while maintaining high radiation efficiency, it significantly improves the output performance of the system in the high-frequency band.

[0066] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A CMOS terahertz on-chip antenna combined with an off-chip dual-layer quartz antenna, characterized in that: include: The chip body has a base layer at its bottom and a metal ground layer, a feed line layer and a radiating layer arranged sequentially from bottom to top within the chip body. A first dielectric layer is provided on the top of the chip body; A second dielectric layer is disposed on top of the first dielectric layer; A first metal layer is disposed on top of the second dielectric layer; A third dielectric layer is disposed on top of the first metal layer; A second metal layer is disposed on top of the third dielectric layer.

2. The CMOS terahertz on-chip antenna and off-chip dual-layer quartz antenna according to claim 1, characterized in that: The metal formation includes an upper metal layer M1 and an lower metal layer M2.

3. The CMOS terahertz on-chip antenna and off-chip dual-layer quartz antenna according to claim 1, characterized in that: Both the second and third dielectric layers are made of quartz.

4. The CMOS terahertz on-chip antenna and off-chip dual-layer quartz antenna according to claim 1, characterized in that: The second and third dielectric layers have the same length, width, and height.

5. The CMOS terahertz on-chip antenna and off-chip dual-layer quartz antenna according to claim 1, characterized in that: The second metal layer and the first metal layer are both rectangular, and the size of the second metal layer is larger than the size of the first metal layer.

6. The CMOS terahertz on-chip antenna and off-chip dual-layer quartz antenna according to claim 1, characterized in that: The substrate layer is made of silicon, the metal ground layer and feeder layer are made of copper, the radiating layer is made of aluminum, and the chip body is made of silicon dioxide.

7. The CMOS terahertz on-chip antenna and off-chip dual-layer quartz antenna according to claim 1, characterized in that: The heights of the second and third dielectric layers are set to 100µm, and the heights of the second and first metal layers are set to 200nm.

8. The CMOS terahertz on-chip antenna and off-chip dual-layer quartz antenna according to claim 1, characterized in that: The expression for the length L of the radiative layer is as follows: L ≈ λ0 / (2√ε r ); Where λ0 is the wavelength in vacuum, ε r It is the relative permittivity of the chip itself.

9. The CMOS terahertz on-chip antenna and off-chip dual-layer quartz antenna according to claim 1, characterized in that: The second and third dielectric layers have dimensions of 500µm x 600µm; the first and second metal layers have dimensions of 90µm x 100µm and 240µm x 280µm, respectively.

10. A CMOS terahertz on-chip antenna combined with an off-chip dual-layer quartz antenna according to claim 1, characterized in that: The length and width dimensions of the radiation layer are 170µm*170µm.

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