A resonant cavity current control circuit and an energy storage system

Abstract

The present application relates to the technical field of energy storage power supply, and mainly provides a resonant cavity current control circuit and an energy storage system, the circuit comprising a voltage regulating module, a voltage detection module connected with the voltage regulating module and a clamping control module, the voltage detection module and the voltage regulating module are also connected with a first bus capacitor and a second bus capacitor. The voltage detection module is used for detecting the bus voltage of the two bus capacitors, and when there is a difference between the two bus voltages, the voltage regulating module is controlled to work to adjust the first bus voltage and the second bus voltage. When the voltage regulating module works, the clamping control module will control the voltage regulating module to stop working when it is determined that the current signal of the voltage regulating module does not meet the preset condition. Based on this, the bus voltage balance can be realized through the voltage regulating module, and then the two LLCs in the three-level inverter work at the same time, without the need for a single LLC to bear excessive peak current, thereby reducing the cost, improving the service life and reliability of the system.

Description

Technical Field

[0001] This invention relates to the technical field of energy storage power supplies, and in particular to a resonant cavity current control circuit and energy storage system. Background Technology

[0002] In energy storage power supplies, compared to two-level topology inverter circuits, using three-level topology inverter circuits to invert the output AC voltage has many advantages, such as lower electromagnetic interference and compatibility with both high and low voltage inputs and outputs. Currently, a typical three-level inverter circuit topology for energy storage power supplies adopts a two-stage power circuit architecture of "DC / DC + DC / AC". This architecture demonstrates outstanding advantages in cost control and energy conversion efficiency, making it one of the mainstream technical solutions. The DC / DC boost circuit consists of two relatively independent LLC resonant converters: LLC1 maintains a positive voltage, while LLC2 maintains a negative voltage. The subsequent DC / AC three-level inverter circuit is responsible for converting the stabilized DC voltage into a sinusoidal AC voltage, thus realizing the AC output function of the energy storage power supply.

[0003] In this topology, the positive half-cycle of the output AC voltage is entirely powered by LLC1 circuit alone, while the negative half-cycle is entirely powered by LLC2 circuit alone. In other words, LLC1 and LLC2 operate alternately within the AC power frequency cycle. However, compared to the simultaneous operation of both LLC circuits, this alternating operation at the power frequency significantly increases the peak and effective current of each LLC resonant cavity. Simultaneously, the peak and effective currents flowing through the LLC battery-side MOSFETs, circuit copper foil, and filter capacitors also increase accordingly. This leads to increased current stress on the circuit components, resulting in excessively high device temperatures and reduced circuit lifespan and reliability. Summary of the Invention

[0004] The present invention provides a resonant cavity current control circuit and energy storage system, which mainly solves the technical problem that the device is subjected to excessive stress when the three-level inverter circuit works alternately in the prior art, which leads to easy damage to the device, low circuit reliability and low safety.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in the embodiments of the present invention is: to provide a resonant cavity current control circuit, the circuit including a voltage detection module, a wave blocking control module and a voltage adjustment module;

[0006] The voltage regulation module is connected to the voltage detection module and the wave blocking control module respectively. The voltage detection module and the voltage regulation module are also used to connect the first bus capacitor and the second bus capacitor.

[0007] The voltage detection module is used to detect the first bus voltage of the first bus capacitor and the second bus voltage of the second bus capacitor, respectively, and outputs a first control signal when the first bus voltage is greater than the second bus voltage; and

[0008] When the voltage of the first bus is less than the voltage of the second bus, a second control signal is output;

[0009] The voltage regulation module is configured to enter a first operating state upon receiving the first control signal, to receive the first bus voltage, and to adjust the second bus voltage of the second bus capacitor based on the first bus voltage; and

[0010] Upon receiving the second control signal, the system enters a second operating state to receive the second bus voltage and adjust the first bus voltage based on the second bus voltage.

[0011] The wave blocking control module is used to collect the current signal of the voltage regulation module and control the voltage regulation module to stop working when the current signal does not meet the preset conditions.

[0012] Optionally, the blocking control module is also used to output a blocking signal when the current signal does not meet the preset conditions;

[0013] The voltage regulation module is further configured to enter a first operating state upon receiving the first control signal to receive and store the first bus voltage, and to stop operating upon receiving the blocking signal to release the stored voltage to the second bus capacitor, thereby adjusting the second bus voltage of the second bus capacitor based on the first bus voltage, so that the second bus voltage is balanced with the first bus voltage; or

[0014] Upon receiving the second control signal, the system enters a second operating state to receive and store the second bus voltage. Upon receiving the blocking signal, the system stops operating to release the stored voltage to the first bus capacitor. This allows the system to adjust the first bus voltage of the first bus capacitor based on the second bus voltage, thereby balancing the first bus voltage with the second bus voltage.

[0015] Optionally, the voltage regulation module includes a logic unit, a drive unit, and a buck-boost unit;

[0016] The logic unit is connected to the wave blocking control module and the voltage detection module respectively. The logic unit is also connected to the drive unit. The buck-boost unit is connected to the drive unit and the wave blocking control module respectively. The buck-boost unit is also used to connect to the first bus capacitor and the second bus capacitor respectively.

[0017] The logic unit is configured to output a first drive signal to the drive unit when it receives the first control signal but does not receive the blocking signal; or

[0018] When the second control signal is received but the blocking signal is not received, a second drive signal is output to the drive unit; and

[0019] Upon receiving the blocking signal, the drive unit is controlled to stop working;

[0020] The driving unit is used to drive the upper tube of the buck-boost unit to operate when the first driving signal is received; and

[0021] Upon receiving the second drive signal, the lower tube of the buck-boost unit is driven to operate.

[0022] Optionally, the buck-boost unit includes a switch Q1, a switch Q2, an inductor LD1, a resistor R8, a resistor R12, a resistor R33, and a resistor R34;

[0023] The control terminal of the switch Q1 is connected to the drive unit through the resistor R8. The control terminal of the switch Q1 is also connected to the second terminal of the switch Q1 through the resistor R33. The first terminal of the switch Q1 is connected to the first bus capacitor. The second terminal of the switch Q1 is connected to the first terminal of the inductor LD1 and the switch Q2 respectively. The control terminal of the switch Q2 is connected to the drive unit through the resistor R12. The control terminal of the switch Q2 is also connected to the switch Q2 through the resistor R34. The second terminal of the switch Q2 is also used to connect to the second bus capacitor. The inductor LD1 is also connected to the wave blocking control module. The inductor LD1 is also connected to the common terminal connected to the first bus capacitor and the second bus capacitor.

[0024] Optionally, the logic unit includes AND gate U3A, AND gate U3B, resistor R3, resistor R4, resistor R15 and resistor R16;

[0025] The first input terminal of AND gate U3A is connected to the reference power supply through resistor R3. The first input terminal of AND gate U3A is also connected to the voltage detection module. The second input terminal of AND gate U3A is connected to the reference power supply through resistor R4. The first input terminal of AND gate U3B is connected to the reference power supply through resistor R15. The first input terminal of AND gate U3B is also connected to the voltage detection module. The second input terminal of AND gate U3B is connected to the reference power supply through resistor R16. The second input terminals of both AND gate U3A and AND gate U3B are also connected to the wave blocking control module. The output terminals of both AND gate U3A and AND gate U3B are connected to the driving unit.

[0026] Optionally, the voltage detection module includes comparator U4A, comparator U4B, resistor R6, resistor R9, resistor R19 and resistor R22;

[0027] The first input terminal of comparator U4A is connected to the first bus capacitor through resistor R6, the second input terminal of comparator U4A is connected to the second bus capacitor through resistor R9, and the output terminal of comparator U4A is connected to the voltage regulation module. The first input terminal of comparator U4B is connected to the second bus capacitor through resistor R19, the second input terminal of comparator U4B is connected to the first bus capacitor through resistor R22, and the output terminal of comparator U4B is connected to the voltage regulation module.

[0028] Optionally, the wave blocking control module includes a current sampling unit and a current comparison unit;

[0029] The current sampling unit is connected to the buck-boost unit and the current comparison unit respectively, and the current comparison unit is also connected to the logic unit;

[0030] The current sampling unit is used to collect the current signal of the buck-boost unit and input the current signal to the current comparison unit;

[0031] The current comparison unit is used to receive the current signal and output a blocking signal to the logic unit when the current signal is greater than a first preset value or less than a second preset value, wherein the first preset value is greater than the second preset value.

[0032] Optionally, the current sampling unit includes a current sensor U7, a differential amplifier U6, resistors R29, R30, R31, and R32;

[0033] The first input terminal of the differential amplifier U6 is connected to the current sensor U7 through the resistor R30. The first input terminal of the differential amplifier U6 also receives the midpoint voltage through the resistor R29. The second input terminal of the differential amplifier U6 is connected to the current sensor U7 through the resistor R31. The current sensor U7 is connected to the buck-boost unit. The second input terminal of the differential amplifier U6 is also connected to the output terminal of the differential amplifier U6 through the resistor R31. The output terminal of the differential amplifier U6 is also connected to the current comparison unit.

[0034] Optionally, the current comparison unit includes comparator U5A, comparator U5B, resistor R20, resistor R23, resistor R25, resistor R26, resistor R27 and resistor R28;

[0035] The first input terminal of comparator U5A is connected to the reference power supply through resistor R20, and the first input terminal of comparator U5A is also grounded through resistor R23. The second input terminal of comparator U5A is connected to the current sampling unit through resistor R25. The first input terminal of comparator U5B is connected to the current sampling unit through resistor R26, and the second input terminal of comparator U5B is connected to the reference power supply through resistor R28. The second input terminal of comparator U5B is grounded through resistor R27. The output terminals of both comparator U5A and comparator U5B are connected to the logic unit.

[0036] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of the present invention is to provide an energy storage system, the energy storage system comprising:

[0037] A three-level inverter circuit, wherein the three-level inverter circuit includes a first bus capacitor and a second bus capacitor; and

[0038] The resonant cavity current control circuit described above is connected to the first bus capacitor and the second bus capacitor respectively.

[0039] Unlike related technologies, this invention provides a resonant cavity current control circuit and energy storage system. The circuit includes a wave blocking control module, a voltage detection module, and a voltage regulation module. The voltage regulation module is connected to both the voltage detection module and the wave blocking control module. Both the voltage detection module and the voltage regulation module are also used to connect to a first bus capacitor and a second bus capacitor. The voltage detection module detects the first bus voltage of the first bus capacitor and the second bus voltage of the second bus capacitor. When the first bus voltage is greater than or less than the second bus voltage, it determines that there is a bus voltage imbalance in the three-level inverter circuit. To avoid the influence of a single-channel LLC operation, the voltage detection module outputs a first / second control signal to the voltage regulation module, causing the voltage regulation module to start operating according to the control signal, thereby regulating the first bus voltage and the second bus voltage. During the operation of the voltage regulation module, the blocking control module continuously monitors the current signal of the voltage regulation module to avoid excessive current stress on the devices due to excessive current, and to prevent energy waste due to insufficient current. When the current signal does not meet the preset conditions, a blocking signal is output to the voltage regulation module to stop its operation. Based on this, by adjusting the voltage of the first bus and the second bus through the voltage regulation module, the voltages of the first bus capacitor and the second bus capacitor are balanced, thereby enabling both LLCs in the three-level inverter to operate simultaneously. This eliminates the need for a single LLC to bear excessive peak current, reducing costs and improving the system's lifespan and reliability. Attached Figure Description

[0040] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0041] Figure 1 This is a schematic diagram illustrating an application scenario of an energy storage system provided in an embodiment of the present invention;

[0042] Figure 2 This is a circuit diagram of a three-level inverter circuit provided in an embodiment of the present invention;

[0043] Figure 3 This is a structural block diagram of a resonant cavity current control circuit provided in an embodiment of the present invention;

[0044] Figure 4 This is a circuit diagram of a resonant cavity current control circuit provided in an embodiment of the present invention;

[0045] Figure 5This is a circuit diagram of another resonant cavity current control circuit provided in an embodiment of the present invention;

[0046] Figure 6 This is a circuit diagram of a wave blocking control module provided in an embodiment of the present invention. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0048] It should be noted that, unless otherwise specified, the various features in the embodiments of the present invention can be combined with each other, and all are within the protection scope of the present invention. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different module division or in a different order than that shown in the device schematic diagram or the flowchart.

[0049] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0050] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario of an energy storage system provided in an embodiment of the present invention, such as... Figure 1 As shown, application scenario 1 includes an energy storage system 100, a load 200, and a power supply 300; the energy storage system 100 is connected to both the load 200 and the power supply 300. Wherein, as Figure 1 As shown, the energy storage system 100 further includes a three-level inverter circuit 10, which is connected to the power supply 300 and the load 200 respectively. The three-level inverter circuit 10 is used to receive the power supply voltage output by the power supply 300, and transform the power supply voltage to output AC power to the load 200 to supply power to the load 200.

[0051] In some embodiments, please refer to Figure 2 , Figure 2 This is a circuit diagram of a three-level inverter circuit provided in an embodiment of the present invention, such as... Figure 2As shown, the three-level inverter circuit 10 includes a first bus capacitor CE1, a second bus capacitor CE2, two LLC converters (LLC1 converter and LLC2 converter), and a three-level inverter module. The two LLC converters are connected in series. The two LLC converters receive the power supply voltage from the power supply 300, and after transforming and isolating the power supply voltage, charge the first bus capacitor CE1 and the second bus capacitor CE2, respectively. The LLC1 converter maintains a positive voltage, and the LLC2 converter outputs a negative voltage. Finally, the AC power is inverted by the three-level inverter module and output to the load 200 to enable the load 200 to operate.

[0052] It is known that during the positive half-cycle of the AC output from the three-level inverter module, the LLC1 converter provides all the output power. However, during the negative half-cycle, the LLC2 converter provides all the output power. In other words, the LLC1 and LLC2 converters operate alternately within the AC power frequency cycle to ensure the three-level inverter module can normally supply power to the load 200. To meet the AC output requirements, the peak current and RMS current in the resonant cavities of the LLC1 and LLC2 converters increase significantly, leading to increased current stress on the circuit components. This results in excessively high component temperatures, reducing the circuit's lifespan and reliability. Therefore, to improve the current and temperature stress resistance of the components, a converter with higher withstand capability is needed. However, a higher withstand capability converter also increases the circuit's cost.

[0053] Therefore, in order to reduce costs while improving circuit lifespan and reliability, such as Figure 1As shown, the energy storage system 100 also includes a resonant cavity current control circuit 20, which is connected to the three-level inverter circuit 10. The resonant cavity current control circuit 20 is used to detect the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2 in real time. It starts working when the first bus voltage is greater than or less than the second bus voltage, adjusting the second bus voltage based on the first bus voltage, or adjusting the first bus voltage based on the second bus voltage. This ensures that both the first bus capacitor CE1 and the second bus capacitor CE2 are in a charging state, and both the LLC1 converter and the LLC2 converter are in a working state, thus avoiding the alternating operation of the two converters and extending the service life of the devices. Based on this, when the voltage of one bus capacitor is consumed, the resonant cavity current control circuit 20 adjusts the bus voltage of that bus capacitor to consume the voltage of the other bus capacitor, thereby enabling both LLC converters to start working. This reduces the peak current and effective current of the circuit, improving circuit reliability while reducing cost.

[0054] In some embodiments, please refer to Figure 3 , Figure 3 This is a structural block diagram of a resonant cavity current control circuit provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the resonant cavity current control circuit 20 includes a voltage detection module 21, a wave blocking control module 22, and a voltage adjustment module 23;

[0055] The voltage regulation module 23 is connected to the voltage detection module 21 and the wave blocking control module 22 respectively. The voltage detection module 21 and the voltage regulation module 23 are also used to connect the first bus capacitor CE1 and the second bus capacitor CE2.

[0056] The voltage detection module 21 is used to detect the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2 respectively, and outputs a first control signal when the first bus voltage is greater than the second bus voltage; and

[0057] When the voltage of the first bus is less than the voltage of the second bus, a second control signal is output;

[0058] The voltage regulation module 23 is configured to enter a first operating state upon receiving the first control signal, to receive the first bus voltage, and to adjust the second bus voltage of the second bus capacitor CE2 based on the first bus voltage; and

[0059] Upon receiving the second control signal, the system enters a second operating state to receive the second bus voltage and adjust the first bus voltage based on the second bus voltage.

[0060] The wave blocking control module 22 is used to collect the current signal of the voltage regulation module 23, and control the voltage regulation module 23 to stop working when the current signal does not meet the preset conditions.

[0061] Specifically, during the operation of the energy storage system 100, the voltage detection module 21 continuously monitors the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2, and determines whether the first bus voltage is greater than the second bus voltage. If the first bus voltage is greater than the second bus voltage, it is considered that the three-level inverter module outputs a negative half-cycle AC current, that is, the second bus voltage of the second bus capacitor CE2 is consumed, and the converter LLC2 starts to work. At this time, the voltage detection module 21 outputs a first control signal to the voltage regulation module 23, so that the voltage regulation module 23 enters a first working state based on the first control signal. After the voltage regulation module 23 enters the first working state, it receives the first bus voltage and adjusts the second bus voltage based on the first bus voltage, thereby causing the first bus capacitor CE1 to enter a charging state, and thus causing the converter LLC1 to also participate in the operation.

[0062] If the first bus voltage is less than the second bus voltage, the three-level inverter module is considered to output a positive half-cycle AC current, and converter LLC1 starts working. At this time, the voltage detection module 21 outputs a second control signal to the voltage regulation module 23, causing the voltage regulation module 23 to enter a second working state. After the voltage regulation module 23 enters the second working state, it receives the second bus voltage and adjusts the first bus voltage based on the second bus voltage, thereby balancing the second bus voltage with the first bus voltage, and thus allowing converter LLC2 to also participate in the operation. Based on this, by real-time detection of the bus voltages of the first bus capacitor CE1 and the second bus capacitor CE2, and adjusting the bus voltage when they are different, the voltage stored in the first bus capacitor CE1 and the second bus capacitor CE2 is consumed, thus allowing both converter LLCs to participate in the operation, avoiding the situation where the two converter LLCs work alternately, thereby saving circuit costs and improving circuit reliability.

[0063] When the voltage regulation module 23 receives the first bus voltage or the second bus voltage, the wave blocking control module 22 will collect the current signal of the voltage regulation module 23 in real time, and control the voltage regulation module 23 to stop working when the current signal does not meet the preset conditions, so that the voltage regulation module 23 releases the received voltage, thereby making the first bus voltage and the second bus voltage equal.

[0064] In another embodiment, the blocking control module 22 is further configured to output a blocking signal when the current signal does not meet the preset conditions;

[0065] The voltage regulation module 23 is further configured to enter a first operating state upon receiving the first control signal to receive and store the first bus voltage, and to stop operating upon receiving the blocking signal to release the stored voltage to the second bus capacitor CE2, thereby adjusting the second bus voltage of the second bus capacitor based on the first bus voltage, so that the second bus voltage is balanced with the first bus voltage; or

[0066] Upon receiving the second control signal, the system enters a second operating state to receive and store the second bus voltage. Upon receiving the blocking signal, the system stops operating to release the stored voltage to the first bus capacitor CE1. This allows the system to adjust the first bus voltage of the first bus capacitor CE1 based on the second bus voltage, thereby balancing the first bus voltage with the second bus voltage.

[0067] Specifically, when the voltage regulation module 23 receives the first control signal, it enters a first operating state to receive and store the first bus voltage. At this time, the blocking control module 22 collects the current signal from the voltage regulation module 23 and outputs a blocking signal to the voltage regulation module 23 when the current signal does not meet preset conditions. When the voltage regulation module 23 receives the blocking signal, it stops operating based on the blocking signal, thereby releasing the stored first bus voltage to the second bus capacitor CE2, so that the second bus capacitor CE2 is charged based on the first bus voltage, thus balancing the second bus voltage with the first bus voltage.

[0068] After the voltage regulation module 23 enters the second operating state based on the second control signal, it receives and stores the second bus voltage. If the blocking control module 22 determines that the current signal of the voltage regulation module 23 does not meet preset conditions, it outputs a blocking signal to the voltage regulation module 23 to stop it from operating, thereby releasing the stored voltage. This achieves the purpose of regulating the first bus voltage based on the second bus voltage, thus balancing the first bus voltage and the second bus voltage.

[0069] In another embodiment, such as Figure 3 As shown, the voltage regulation module 23 includes a logic unit 231, a drive unit 232, and a buck-boost unit 233;

[0070] The logic unit 231 is connected to the wave blocking control module 22 and the voltage detection module 21 respectively. The logic unit 231 is also connected to the drive unit 232. The step-up and step-down unit 233 is connected to the drive unit 232 and the wave blocking control module 22 respectively. The step-up and step-down unit 233 is also used to connect to the first bus capacitor CE1 and the second bus capacitor CE2 respectively.

[0071] The logic unit 231 is configured to output a first drive signal to the drive unit 232 when it receives the first control signal but does not receive the blocking signal; or

[0072] When the second control signal is received but the blocking signal is not received, a second drive signal is output to the drive unit 232; and

[0073] Upon receiving the blocking signal, the drive unit 232 is controlled to stop working;

[0074] The driving unit 232 is used to drive the upper tube of the buck-boost unit 233 to work when the first driving signal is received; and

[0075] When the second drive signal is received, the lower tube of the buck-boost unit 233 is driven to work.

[0076] Specifically, when the voltage detection module 21 outputs a first control signal and the blocking control module 22 does not output a blocking signal, the logic unit 231 outputs a first drive signal to the drive unit 232 based on the first control signal, so that the drive unit 232 drives the upper transistor in the buck-boost unit 233 to work, thereby enabling the buck-boost unit 233 to receive and store the first bus voltage. When the blocking control module 22 outputs the blocking signal, the logic unit 231 stops outputting the first drive signal based on the blocking signal, so that the drive unit 232 stops working, thereby turning off the upper transistor in the buck-boost unit 233. At this time, the buck-boost unit 233 releases the stored first bus voltage to the second bus capacitor CE2, so that the second bus voltage rises, thereby balancing the first bus voltage and the second bus voltage. Based on this, the converter LLC1 and the converter LLC2 can work simultaneously, thereby avoiding the situation where the two converters work alternately, thus saving costs while improving the reliability and service life of the circuit.

[0077] When the logic unit 231 receives the second control signal, it outputs a second drive signal to the drive unit 232, causing the drive unit 232 to drive the lower transistor in the buck-boost unit 233 based on the second drive signal. This allows the buck-boost unit 233 to receive and store the second bus voltage. When the blocking control module 22 outputs a blocking signal, the logic unit 231 controls the drive unit 232 to stop working, and the buck-boost unit 233 releases the stored voltage, thereby balancing the first bus voltage and the second bus voltage.

[0078] In some embodiments, please refer to Figure 4 , Figure 4 This is a circuit diagram of a resonant cavity current control circuit provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the logic unit 231 includes AND gate U3A, AND gate U3B, resistor R3, resistor R4, resistor R15 and resistor R16; the driving unit 232 is a half-bridge driving chip U1; the buck-boost unit includes switching transistor Q1, switching transistor Q2, inductor LD1, resistor R8, resistor R12, resistor R33 and resistor R34.

[0079] The first input terminal of AND gate U3A is connected to the reference power supply (VCC) through resistor R3. The first input terminal of AND gate U3A is also connected to the voltage detection module 21. The second input terminal of AND gate U3A is connected to the reference power supply through resistor R4. The first input terminal of AND gate U3B is connected to the reference power supply through resistor R15. The first input terminal of AND gate U3B is also connected to the voltage detection module 21. The second input terminal of AND gate U3B is connected to the reference power supply through resistor R16. The second input terminals of both AND gate U3A and AND gate U3B are also connected to the wave blocking control module 22. The output terminals of both AND gate U3A and AND gate U3B are connected to the drive unit 232.

[0080] The first input terminal of the half-bridge driver chip U1 is connected to the output terminal of the AND gate U3A, the second input terminal of the half-bridge driver chip U1 is connected to the output terminal of the AND gate U3B, the first output terminal of the half-bridge driver chip U1 is connected to the upper transistor of the buck-boost unit 233, and the second output terminal of the half-bridge driver chip U1 is connected to the lower transistor of the buck-boost unit 233.

[0081] The control terminal of the upper switch Q1 is connected to the drive unit 232 through the resistor R8. The control terminal of the upper switch Q1 is also connected to the second terminal of the upper switch Q1 through the resistor R33. The first terminal of the upper switch Q1 is connected to the first bus capacitor CE1. The second terminal of the upper switch Q1 is connected to the inductor LD1 and the first terminal of the lower switch Q2. The control terminal of the lower switch Q2 is connected to the drive unit 232 through the resistor R12. The control terminal of the lower switch Q2 is also connected to the upper switch Q2 through the resistor R34. The second terminal of the lower switch Q2 is also used to connect to the second bus capacitor CE2. The inductor LD1 is also connected to the wave blocking control module 22. The inductor LD1 is also connected to the common terminal connected to the first bus capacitor CE1 and the second bus capacitor CE2.

[0082] Specifically, when the blocking control module 22 does not output a blocking signal, the second input terminals of AND gate U3A and AND gate U3B are both pulled high by the reference power supply. If the voltage detection module 21 outputs a first control signal at this time, AND gate U3A will receive the first control signal and output a first drive signal to the half-bridge driver chip U1 according to the first control signal, so that the half-bridge driver chip U1 drives the switch Q1 to turn on based on the first drive signal. After the switch Q1 is turned on, the first bus voltage of the first bus capacitor CE1 will be input to the inductor LD1 through the switch Q1, and the current of the inductor LD1 will begin to rise. During the rise of the current of the inductor LD1, the blocking control module 22 will collect the current signal of the inductor LD1 in real time, and output a blocking signal to the second input terminal of AND gate U3A when the current signal does not meet the preset conditions. When AND gate U3A receives the blocking signal, it stops outputting the first drive signal to the first input terminal of the half-bridge driver chip U1 based on the blocking signal, causing the half-bridge driver chip U1 to stop driving the switch Q1, and the switch Q1 is turned off. After the switch Q1 is turned off, the energy stored in the inductor LD1 will freewheel through the body diode of the switch Q2, thereby charging the second bus capacitor CE2, so that the second bus voltage is balanced with the first bus voltage. Based on this, the two converters can work simultaneously, thereby improving the circuit's lifespan and reliability.

[0083] When the voltage detection module 21 outputs the second control signal, the AND gate U3B outputs a second drive signal to the half-bridge driver chip U1 based on the second control signal, so that the half-bridge driver chip U1 drives the switch Q2 to turn on, thereby causing the second bus capacitor CE2 to input the second bus voltage to the inductor LD1. When the current signal on the inductor LD1 does not meet the preset condition, the AND gate U3B receives the blocking signal, thereby causing the switch Q2 to turn off, and the body diode of the switch Q1 to freewheel, thereby charging the first bus capacitor CE1, and thus balancing the first bus voltage and the second bus voltage.

[0084] In some embodiments, such as Figure 4 As shown, the logic unit 231 also includes capacitors C3 and C7;

[0085] The capacitor C3 is connected to the second input terminal of the AND gate U3A, and the capacitor C3 is also used for grounding; the first terminal of the capacitor C7 is connected to the second input terminal of the AND gate U3B, and the second terminal of the capacitor C7 is used for grounding.

[0086] The capacitors C3 and C7 are used to input the first control signal or the second control signal to the logic unit 231 after the blocking control module 22 stops outputting the blocking signal, thereby slowing down the switching speed of the switching transistors Q1 and Q2, reducing the instantaneous stress impact on the switching transistors Q1 and Q2, and thus improving the service life of the switching devices.

[0087] In some embodiments, please refer to Figure 5 , Figure 5 This is a circuit diagram of another resonant cavity current control circuit provided in an embodiment of the present invention, such as... Figure 5 As shown, the voltage detection module 21 includes comparator U4A, comparator U4B, resistor R6, resistor R9, resistor R19 and resistor R22;

[0088] The first input terminal of comparator U4A is connected to the first bus capacitor CE1 through resistor R6, the second input terminal of comparator U4A is connected to the second bus capacitor CE2 through resistor R9, and the output terminal of comparator U4A is connected to the voltage regulation module 23. The first input terminal of comparator U4B is connected to the second bus capacitor CE2 through resistor R19, the second input terminal of comparator U4B is connected to the first bus capacitor CE1 through resistor R22, and the output terminal of comparator U4B is connected to the voltage regulation module 23.

[0089] Specifically, when comparators U4A and U4B detect the first bus voltage and the second bus voltage, they determine whether the first bus voltage is greater than the second bus voltage. If the first bus voltage is greater than the second bus voltage, comparator U4A outputs a first control signal to AND gate U3A, causing AND gate U3A to control drive unit 232 to drive the upper transistor of buck-boost unit 233. If the first bus voltage is less than the second bus voltage, comparator U4B outputs a second control signal to AND gate U3B, causing AND gate U3B to control drive unit 232 to drive the lower transistor of buck-boost unit 233.

[0090] It is known that when the first bus voltage is the same as the second bus voltage, both comparator U4A and comparator U4B will output a third control signal, and both AND gate U3A and AND gate U3B will receive the third control signal. At this time, regardless of whether the blocking signal is received, U3A and AND gate U3B will control the drive unit 232 to stop working based on the third control signal.

[0091] In yet another embodiment, such as Figure 3As shown, the resonant cavity current control circuit 20 further includes a voltage sampling module 24; the voltage sampling module 24 is connected to the voltage detection module 21, and the voltage sampling module 24 is also used to connect to the first bus capacitor CE1 and the second bus capacitor CE2 respectively.

[0092] The voltage sampling module 24 is used to collect the first bus voltage of the first bus capacitor CE1 and the second bus voltage of the second bus capacitor CE2 respectively, and input the collected first bus voltage and second bus voltage to the voltage detection module 21.

[0093] In another embodiment, such as Figure 5 As shown, the voltage sampling module 24 includes a differential amplifier U2A and a differential amplifier U2B;

[0094] The two input terminals of the differential amplifier U2A are respectively connected to the two ends of the first bus capacitor CE1, the output terminal of the differential amplifier U2A is connected to the voltage detection module 21, the two input terminals of the differential amplifier U2B are respectively connected to the two ends of the second bus capacitor CE2, and the output terminal of the differential amplifier U7B is connected to the voltage detection module 21.

[0095] Here, the differential amplifier refers to a device that amplifies the difference between two input signals. Therefore, differential amplifier U2A continuously samples the voltage across the first bus capacitor CE1 and outputs the first bus voltage to the first input terminal of comparator U4A and the second input terminal of comparator U4B. Simultaneously, differential amplifier U2B continuously samples the second bus voltage across the second bus capacitor CE2 and inputs the sampled second bus voltage to the second input terminal of comparator U4A and the first input terminal of comparator U4B. This allows comparators U4A and U4B to compare the magnitudes of the first bus voltage and the second bus voltage, thereby outputting a first control signal or a second control signal.

[0096] In yet another embodiment, such as Figure 3 As shown, the wave blocking control module 22 includes a current sampling unit 221 and a current comparison unit 222;

[0097] The current sampling unit 221 is connected to the buck-boost unit 233 and the current comparison unit 222 respectively, and the current comparison unit 222 is also connected to the logic unit 231;

[0098] The current sampling unit 221 is used to collect the current signal of the buck-boost unit 233 and input the current signal to the current comparison unit 222;

[0099] The current comparison unit 222 is used to receive the current signal and output a blocking signal to the logic unit 231 when the current signal is greater than a first preset value or less than a second preset value, wherein the first preset value is greater than the second preset value.

[0100] When the buck-boost unit 233 is working, the current sampling unit 221 collects the current signal of the buck-boost unit 233 in real time and transmits the current signal to the current comparison unit 222, so that the current comparison unit 222 can determine whether the current signal is greater than a first preset value or less than a second preset value. If the current signal is greater than the first preset value or less than the second preset value, it is considered that the current signal does not meet the preset conditions, and the current comparison unit 222 will output a blocking signal to the logic unit 231, so that the logic unit 231 stops outputting the first drive signal and the second drive signal, thereby causing the drive unit 232 to stop working, and both the upper and lower transistors in the buck-boost unit 233 stop working. If the current signal is less than the first preset value and greater than the second preset value, it is considered that the current signal meets the preset conditions. The current comparison unit 222 will stop outputting the blocking signal, thereby causing the logic unit 231 to output the corresponding drive signal to the drive unit 232 according to the first control signal or the second control signal, thereby causing the upper tube or the lower tube in the buck-boost unit 233 to work.

[0101] In some other embodiments, please refer to Figure 4 and Figure 6 The current sampling unit 221 includes a current sensor U7, a differential amplifier U6, resistors R29, R30, R31 and R32; the current comparison unit 222 includes comparator U5A, comparator U5B, resistors R20, R23, R25, R26, R27 and R28.

[0102] The first input terminal of the differential amplifier U6 is connected to the current sensor U7 through the resistor R30. The first input terminal of the differential amplifier U6 also receives the midpoint voltage through the resistor R29. The second input terminal of the differential amplifier U6 is connected to the current sensor U7 through the resistor R31. The current sensor U7 is connected to the buck-boost unit 233. The second input terminal of the differential amplifier U6 is also connected to the output terminal of the differential amplifier U6 through the resistor R31. The output terminal of the differential amplifier U6 is also connected to the current comparison unit 222.

[0103] The first input terminal of comparator U5A is connected to the reference power supply (VCC) through resistor R20. The first input terminal of comparator U5A is also grounded through resistor R23. The second input terminal of comparator U5A is connected to the current sampling unit 221 through resistor R25. The first input terminal of comparator U5B is connected to the current sampling unit 221 through resistor R26. The second input terminal of comparator U5B is connected to the reference power supply through resistor R28. The second input terminal of comparator U5B is grounded through resistor R27. The output terminals of comparator U5A and comparator U5B are both connected to the logic unit 231.

[0104] When the buck-boost unit 233 is operating, the current sensor U7 collects the current signal from the buck-boost unit 233 and inputs the current signal to the differential amplifier U6. Upon receiving the current signal, the differential amplifier U6 transmits the current signal to the second input terminal of comparator U5A and the first input terminal of comparator U5B. Simultaneously, the power supply voltage of the reference power supply is divided by resistors R20 and R23 and input to the first input terminal of comparator U5A, and divided by resistors R27 and R28 and input to the second input terminal of comparator U5B. At this time, if the signal at the first input terminal of comparator U5A is less than the signal at the second input terminal of comparator U5A (the current signal is greater than the first preset value), or the signal at the first input terminal of comparator U5B is less than the signal at the second input terminal of comparator U5B (the current signal is less than the second preset value), then comparator U5A or comparator U5B will output a blocking signal to the logic unit 231, so that the logic unit 231 stops outputting the first drive signal or the second drive signal. However, if the signal at the first input terminal of comparator U5A is greater than the signal at the second input terminal of comparator U5A and the signal at the first input terminal of comparator U5B is greater than the signal at the second input terminal of U5B (i.e., the current signal is less than the first preset value and greater than the second preset value), then both comparator U5A and comparator U5B will stop outputting the blocking signal. Based on this, the current signal of the buck-boost unit 233 can be detected in real time to avoid excessive current stress on the device due to excessive current, and energy waste due to insufficient current. This will make the first bus voltage and the second bus voltage balanced, and thus enable the two converters to work simultaneously, reducing the cost of the energy storage system.

[0105] It should be noted that the first preset value is determined by the resistors R20 and R23, and the second preset value is set by the resistors R27 and R28. Different preset values ​​can be set by setting appropriate resistance values.

[0106] This invention provides a resonant cavity current control circuit, which includes a wave-blocking control module, a voltage detection module, and a voltage regulation module. The voltage regulation module is connected to both the voltage detection module and the wave-blocking control module. Both the voltage detection module and the voltage regulation module are also used to connect to a first bus capacitor and a second bus capacitor. The voltage detection module detects the first bus voltage of the first bus capacitor and the second bus voltage of the second bus capacitor. When the first bus voltage is greater than or less than the second bus voltage, it determines that the bus voltage in the three-level inverter circuit is unbalanced. To avoid the influence of a single-channel LLC operation, the voltage detection module outputs a first / second control signal to the voltage regulation module, causing the voltage regulation module to start operating according to the control signal, thereby regulating the first bus voltage and the second bus voltage. During the operation of the voltage regulation module, the wave-blocking control module monitors the current signal of the voltage regulation module in real time to avoid excessive current stress on the device due to excessive current, and energy waste due to insufficient current. When it determines that the current signal does not meet preset conditions, it outputs a wave-blocking signal to the voltage regulation module to stop the voltage regulation module from operating. Based on this, the voltage of the first bus and the voltage of the second bus are adjusted by the voltage regulation module, so that the voltage of the first bus capacitor and the second bus capacitor are balanced. This allows both LLCs in the three-level inverter to work at the same time, without the need for a single LLC to bear excessive peak current, thereby reducing costs and improving the service life and reliability of the system.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A resonant cavity current control circuit, characterized in that, The circuit includes a voltage detection module, a wave blocking control module, and a voltage regulation module; The voltage regulation module is connected to the voltage detection module and the wave blocking control module respectively. The voltage detection module and the voltage regulation module are also used to connect the first bus capacitor and the second bus capacitor. The voltage detection module is used to detect the first bus voltage of the first bus capacitor and the second bus voltage of the second bus capacitor respectively, and outputs a first control signal when the first bus voltage is greater than the second bus voltage. as well as When the voltage of the first bus is less than the voltage of the second bus, a second control signal is output; The voltage regulation module is used to enter a first working state when receiving the first control signal to receive and store the first bus voltage, and to stop working when receiving the blocking signal to release the stored voltage to the second bus capacitor, thereby adjusting the second bus voltage of the second bus capacitor based on the first bus voltage so that the second bus voltage is balanced with the first bus voltage. as well as Upon receiving the second control signal, the system enters a second operating state to receive and store the second bus voltage. Upon receiving the blocking signal, the system stops operating to release the stored voltage to the first bus capacitor. This allows the system to adjust the first bus voltage of the first bus capacitor based on the second bus voltage, thereby balancing the first bus voltage with the second bus voltage. The wave blocking control module is used to acquire the current signal of the voltage regulation module and output a wave blocking signal when the current signal does not meet the preset conditions. The voltage regulation module includes a logic unit, a drive unit, and a buck-boost unit. The logic unit is connected to the wave blocking control module and the voltage detection module respectively. The logic unit is also connected to the drive unit. The buck-boost unit is connected to the drive unit and the wave blocking control module respectively. The buck-boost unit is also used to connect to the first bus capacitor and the second bus capacitor respectively. The logic unit is configured to output a first drive signal to the drive unit when it receives the first control signal but does not receive the blocking signal; or When the second control signal is received but the blocking signal is not received, a second drive signal is output to the drive unit; and Upon receiving the blocking signal, the drive unit is controlled to stop working; The driving unit is used to drive the upper tube of the buck-boost unit to operate when the first driving signal is received; and Upon receiving the second drive signal, the lower tube of the buck-boost unit is driven to operate.

2. The resonant cavity current control circuit according to claim 1, characterized in that, The buck-boost unit includes a switch Q1, a switch Q2, an inductor LD1, a resistor R8, a resistor R12, a resistor R33, and a resistor R34; The control terminal of the switch Q1 is connected to the drive unit through the resistor R8. The control terminal of the switch Q1 is also connected to the second terminal of the switch Q1 through the resistor R33. The first terminal of the switch Q1 is connected to the first bus capacitor. The second terminal of the switch Q1 is connected to the first terminal of the inductor LD1 and the switch Q2 respectively. The control terminal of the switch Q2 is connected to the drive unit through the resistor R12. The control terminal of the switch Q2 is also connected to the switch Q2 through the resistor R34. The second terminal of the switch Q2 is also used to connect to the second bus capacitor. The inductor LD1 is also connected to the wave blocking control module. The inductor LD1 is also connected to the common terminal connected to the first bus capacitor and the second bus capacitor.

3. The resonant cavity current control circuit according to claim 1, characterized in that, The logic unit includes AND gate U3A, AND gate U3B, resistor R3, resistor R4, resistor R15 and resistor R16; The first input terminal of AND gate U3A is connected to the reference power supply through resistor R3. The first input terminal of AND gate U3A is also connected to the voltage detection module. The second input terminal of AND gate U3A is connected to the reference power supply through resistor R4. The first input terminal of AND gate U3B is connected to the reference power supply through resistor R15. The first input terminal of AND gate U3B is also connected to the voltage detection module. The second input terminal of AND gate U3B is connected to the reference power supply through resistor R16. The second input terminals of both AND gate U3A and AND gate U3B are also connected to the wave blocking control module. The output terminals of both AND gate U3A and AND gate U3B are connected to the driving unit.

4. The resonant cavity current control circuit according to claim 1, characterized in that, The voltage detection module includes comparator U4A, comparator U4B, resistor R6, resistor R9, resistor R19 and resistor R22; The first input terminal of comparator U4A is connected to the first bus capacitor through resistor R6, the second input terminal of comparator U4A is connected to the second bus capacitor through resistor R9, and the output terminal of comparator U4A is connected to the voltage regulation module. The first input terminal of comparator U4B is connected to the second bus capacitor through resistor R19, the second input terminal of comparator U4B is connected to the first bus capacitor through resistor R22, and the output terminal of comparator U4B is connected to the voltage regulation module.

5. The resonant cavity current control circuit according to any one of claims 1-3, characterized in that, The wave blocking control module includes a current sampling unit and a current comparison unit; The current sampling unit is connected to the buck-boost unit and the current comparison unit respectively, and the current comparison unit is also connected to the logic unit; The current sampling unit is used to collect the current signal of the buck-boost unit and input the current signal to the current comparison unit; The current comparison unit is used to receive the current signal and output a blocking signal to the logic unit when the current signal is greater than a first preset value or less than a second preset value, wherein the first preset value is greater than the second preset value.

6. The resonant cavity current control circuit according to claim 5, characterized in that, The current sampling unit includes a current sensor U7, a differential amplifier U6, resistors R29, R30, R31, and R32; The first input terminal of the differential amplifier U6 is connected to the current sensor U7 through the resistor R30. The first input terminal of the differential amplifier U6 also receives the midpoint voltage through the resistor R29. The second input terminal of the differential amplifier U6 is connected to the current sensor U7 through the resistor R31. The current sensor U7 is connected to the buck-boost unit. The second input terminal of the differential amplifier U6 is also connected to the output terminal of the differential amplifier U6 through the resistor R31. The output terminal of the differential amplifier U6 is also connected to the current comparison unit.

7. The resonant cavity current control circuit according to claim 5, characterized in that, The current comparison unit includes comparator U5A, comparator U5B, resistor R20, resistor R23, resistor R25, resistor R26, resistor R27 and resistor R28; The first input terminal of comparator U5A is connected to the reference power supply through resistor R20, and the first input terminal of comparator U5A is also grounded through resistor R23. The second input terminal of comparator U5A is connected to the current sampling unit through resistor R25. The first input terminal of comparator U5B is connected to the current sampling unit through resistor R26, and the second input terminal of comparator U5B is connected to the reference power supply through resistor R28. The second input terminal of comparator U5B is grounded through resistor R27. The output terminals of both comparator U5A and comparator U5B are connected to the logic unit.

8. An energy storage system, characterized in that, The energy storage system includes: A three-level inverter circuit, wherein the three-level inverter circuit includes a first bus capacitor and a second bus capacitor; and The resonant cavity current control circuit according to any one of claims 1-7 is connected to the first bus capacitor and the second bus capacitor respectively.

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