Control method and control circuit of switching power supply and switching power supply

Abstract

The invention discloses a control method and a control circuit of a switching power supply and the switching power supply, the switching power supply comprises a first switching tube and a second switching tube, the first switching tube is used as a main switching tube of the switching power supply, the second switching tube and the first switching tube are alternately conducted, and the second switching tube is used as a main switching tube of the switching power supply. Controlling the turn-off of the first switching tube according to the first jitter signal so as to enable an inductive current peak value to jitter along with time; the second switching tube is controlled to be turned off according to a second jitter signal, so that an inductive current negative peak value jitters along with time at least in a part of time period, when the inductive current negative peak value jitters along with time, the jitter direction of the inductive current negative peak value is opposite to the jitter direction of the inductive current peak value, and the jitter direction of the inductive current negative peak value is opposite to the jitter direction of the inductive current peak value. Therefore, the output power fluctuation is reduced. The EMI characteristics can be optimized, and output voltage ripples can be reduced.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a control method, control circuit, and switching power supply for a switching power supply. Background Technology

[0002] The switching action of the switching transistors in a switching power supply can cause electromagnetic interference (EMI) problems. Frequency dithering is a common and effective method to improve EMI characteristics, but it can also cause output power fluctuations, resulting in large output voltage ripple. Figure 1 As shown, in the prior art, the peak value of the inductor current i is often controlled. L_pk The frequency jitters in the opposite direction to the operating frequency Fsw, optimizing EMI characteristics while offsetting output power Pout fluctuations and reducing output voltage Vout ripple. The following section combines... Figure 2This section describes how to control the operating frequency and inductor current peak jitter. The switching power supply 10 includes a power stage circuit 400 and a control circuit 100. The power stage circuit 400 includes a first switching transistor and a second switching transistor (not shown in the figure). The first switching transistor serves as the main switching transistor of the switching power supply 10. The second switching transistor alternately conducts with the first switching transistor. The control circuit 100 controls the first switching transistor to turn off according to the first jitter signal jitter1, so that the inductor current peak jitters over time. It controls the first switching transistor to turn on according to the third jitter signal jitter3, so that the operating frequency jitters over time. Specifically, the control circuit 100 includes an error compensation unit 101, a switch control unit 102, and a drive control unit 103. The error compensation unit 101 generates an error compensation signal Vcomp based on the output feedback signal FB and the reference signal REF of the switching power supply. The peak current curve setting circuit 1021 in the switch control unit 102 generates a first reference signal ipkref based on the error compensation signal Vcomp. The first superposition circuit 1022 receives the first jitter signal jitter1 and the first reference signal ipkref, superimposes them, and outputs a superimposed signal. The first comparison circuit 1023 compares the superimposed signal output by the first superposition circuit 1022 with the first sampling signal Vcs, which represents the current flowing through the first switch transistor. The first turn-off control signal off1 is output by the comparison circuit. The frequency curve setting circuit 1024 generates a frequency control signal Vfs based on the error compensation signal Vcomp. The frequency jitter processing circuit 1025 receives the third jitter signal jitter3 and the frequency control signal Vfs, processes them, and outputs a jitter frequency control signal Vfs1. The drive control unit 103 generates a first switch control signal Vg1 for controlling the switching state of the first switch and a second switch control signal Vg2 for controlling the switching state of the second switch. The first switch control signal Vg1 controls the first switch to turn off according to the first turn-off control signal off1 and controls the first switch to turn on according to the jitter frequency control signal Vfs1.

[0003] Taking a flyback switching power supply as an example, when the power supply is under light load, such as operating in Discontinuous Conduction Mode (DCM), the peak inductor current fluctuates with the jitter of the superimposed signal output by the first superimposed circuit 1022, and the switching frequency (also known as the operating frequency) of the first switching transistor fluctuates with the jitter of the jitter frequency control signal Vfs1. However, when the power supply is under heavy load, such as operating in Boundary Conduction Mode (BCM), the operating frequency is no longer controlled by the jitter frequency control signal Vfs1, but depends on the peak inductor current. At this time, the output power is proportional to the peak inductor current and is independent of the operating frequency, thus failing to offset the output power fluctuations, resulting in a large output voltage ripple. To solve this problem, the conventional approach is to reduce the jitter amplitude of the peak inductor current, but this deteriorates the EMI characteristics. Therefore, a new control method, control circuit, and power supply are needed to optimize EMI characteristics while reducing output voltage ripple. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a control method, control circuit and switching power supply for a switching power supply, so as to solve the technical problem that the optimization of EMI characteristics in the prior art leads to large output ripple.

[0005] The technical solution of the present invention is, in a first aspect, a control method for a switching power supply, the switching power supply including a first switching transistor and a second switching transistor, the first switching transistor serving as the main switching transistor of the switching power supply, the second switching transistor being alternately turned on and off with the first switching transistor, the control method including:

[0006] The first switching transistor is turned off according to a first jitter signal, so that the peak value of the inductor current jitters over time; the second switching transistor is turned off according to a second jitter signal, so that the negative peak value of the inductor current jitters over time at least for a portion of the time period.

[0007] Specifically, when the negative peak value of the inductor current fluctuates over time, the fluctuating direction of the negative peak value of the inductor current is opposite to the fluctuating direction of the peak value of the inductor current, so as to reduce the fluctuation of output power.

[0008] Optionally, the absolute value of the difference between the jitter amplitude of the negative peak of the inductor current and the jitter amplitude of the peak of the inductor current is controlled to be less than or equal to a first threshold.

[0009] Optionally, the second switch is controlled to conduct for a period of time after the inductor current decreases to zero, so that the inductor current decreases to a negative value;

[0010] The first switch is turned on after the second switch is turned off.

[0011] Optionally, the first time is controlled to jitter for at least a portion of the time period according to the second jitter signal, so that the negative peak value of the inductor current jitters with time for at least a portion of the time period, wherein the first time is the time when the second switch turns on after the inductor current decreases to zero.

[0012] Optionally, the maximum value of the negative peak of the inductor current is controlled to be less than or equal to a second threshold, so that the first switch is turned on with zero voltage.

[0013] Optionally, the negative peak of the inductor current fluctuates intermittently, wherein during the period when the negative peak of the inductor current does not fluctuate, the negative peak of the inductor current is equal to the second threshold.

[0014] Optionally, the minimum value of the first time is controlled to be greater than or equal to the third threshold, so that the maximum value of the negative peak value of the inductor current is less than or equal to the second threshold, wherein the first time is the time when the second switch turns on after the inductor current decreases to zero.

[0015] Optionally, the method for controlling the turn-off of the first switching transistor based on the first jitter signal includes:

[0016] A first reference signal is generated based on the error compensation signal, wherein the error compensation signal characterizes the error between the output feedback signal and the reference signal of the switching power supply;

[0017] The first switch is turned off based on the first jitter signal, the first reference signal, and the first sampling signal representing the current flowing through the first switch.

[0018] Optionally, the method for controlling the turn-off of the second switch based on the second jitter signal includes:

[0019] The second switch is turned off based on the second jitter signal, the second reference signal, and the first signal representing the first time or negative inductor current, wherein the first time is the time when the second switch turns on after the inductor current decreases to zero.

[0020] Optionally, the second jitter signal and the first jitter signal are positively or negatively correlated.

[0021] Secondly, the present invention also provides a control circuit for a switching power supply, the switching power supply including a first switching transistor and a second switching transistor, the first switching transistor serving as the main switching transistor of the switching power supply, and the second switching transistor alternately conducting with the first switching transistor.

[0022] The control circuit controls the first switch to turn off according to a first jitter signal, so that the peak value of the inductor current jitters over time; and controls the second switch to turn off according to a second jitter signal, so that the negative peak value of the inductor current jitters over time at least for a portion of the time period.

[0023] Specifically, when the negative peak value of the inductor current fluctuates over time, the fluctuating direction of the negative peak value of the inductor current is opposite to the fluctuating direction of the peak value of the inductor current, so as to reduce the fluctuation of output power.

[0024] Optionally, the control circuit includes an error compensation unit, a switch control unit, and a drive control unit.

[0025] The error compensation unit generates an error compensation signal based on the output feedback signal and reference signal of the switching power supply.

[0026] The switch control unit generates a first reference signal based on the error compensation signal, and generates a first turn-off control signal based on the first jitter signal, the first reference signal, and a first sampling signal characterizing the current flowing through the first switch; it generates a second turn-off control signal based on the second jitter signal, the second reference signal, and a first signal characterizing a first time or negative inductor current, wherein the first time is the time it takes for the second switch to turn on after the inductor current decreases to zero;

[0027] The drive control unit generates a first switch control signal based on the first shutdown control signal and generates a second switch control signal based on the second shutdown control signal. The first switch control signal controls the first switch transistor to turn off based on the first shutdown control signal, and the second switch control signal controls the second switch transistor to turn off based on the second shutdown control signal.

[0028] Optionally, the switch control unit includes a zero-voltage detection circuit.

[0029] The zero-voltage detection circuit is used to detect when the source-drain voltage of the first switching transistor is zero or close to zero, so as to output a zero-voltage detection signal.

[0030] The drive control unit also generates the first switch control signal based on the zero voltage detection signal, wherein the first switch control signal controls the conduction of the first switch transistor based on the zero voltage detection signal.

[0031] Thirdly, the present invention also provides a switching power supply, the switching power supply including a power stage circuit and the aforementioned control circuit.

[0032] The power stage circuit is used to convert the input voltage into the output voltage. The power stage circuit includes a first switching transistor and a second switching transistor. The first switching transistor serves as the main switching transistor of the switching power supply. The second switching transistor is alternately turned on with the first switching transistor. The control circuit is used to control the switching states of the first switching transistor and the second switching transistor.

[0033] The control method, control circuit, and switching power supply of this invention control the turn-off of the first switching transistor according to a first jitter signal, causing the peak value of the inductor current to jitter over time; and control the turn-off of the second switching transistor according to a second jitter signal, causing the negative peak value of the inductor current to jitter over time at least for a portion of the time period. When the negative peak value of the inductor current jitters over time, the jitter direction of the negative peak value is opposite to the jitter direction of the peak value of the inductor current. Compared with the prior art, the addition of controlling the turn-off of the second switching transistor according to the second jitter signal, causing the negative peak value of the inductor current to jitter over time at least for a portion of the time period, and ensuring that the jitter direction of the negative peak value is opposite to the jitter direction of the peak value of the inductor current, reduces output power fluctuations and thus reduces output ripple. This reduces output power fluctuations and output ripple without reducing the jitter amplitude of the peak value of the inductor current. Since it is not necessary to reduce the jitter amplitude of the peak value of the inductor current, excellent EMI characteristics can be guaranteed. Attached Figure Description

[0034] Figure 1 The operating frequency Fsw and peak inductor current i of the existing switching power supply in discontinuous conduction mode are given. L_pk Waveform diagrams of output power Pout and output voltage Vout;

[0035] Figure 2 This is a schematic diagram of the control circuit of a prior art switching power supply.

[0036] Figure 3 The first switching control signal Vg1, the second switching signal Vg2, and the inductor current i are given for a switching power supply in critical conduction mode. L The drain-source voltage V of the first switching transistor DS_Q1 A waveform diagram;

[0037] Figure 4 The peak inductor current i of the switching power supply of the present invention in one embodiment L_pk Inductor current negative peak value i neg_pk Waveform diagrams of output power Pout and output voltage Vout;

[0038] Figure 5In another embodiment of the switching power supply of the present invention, the peak inductor current i L_pk Inductor current negative peak value i neg_pk Waveform diagrams of output power Pout and output voltage Vout;

[0039] Figure 6 In another embodiment of the switching power supply of the present invention, the peak inductor current i L_pk Inductor current negative peak value i neg_pk Waveform diagrams of output power Pout and output voltage Vout;

[0040] Figure 7 This is a schematic circuit block diagram of one embodiment of the control circuit of the switching power supply of the present invention;

[0041] Figure 8 This is a schematic circuit block diagram of another embodiment of the control circuit of the switching power supply of the present invention;

[0042] Figure 9 This is a schematic diagram of the circuit structure of one embodiment of the power stage circuit of the switching power supply of the present invention;

[0043] Figure 10 This is a schematic diagram of the circuit structure of another embodiment of the power stage circuit of the switching power supply of the present invention. Detailed Implementation

[0044] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the present invention.

[0045] To provide the public with a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the invention, but those skilled in the art can fully understand the invention without these details.

[0046] The invention is described in more detail below by way of example with reference to the accompanying drawings. It should be noted that the drawings are in a simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0047] First, please refer to Figure 3 , Figure 3 This diagram illustrates the first switching control signal Vg1, the second switching signal Vg2, and the inductor current i in critical conduction mode of a switching power supply that does not exhibit operating frequency jitter, inductor current peak jitter, or inductor current negative peak jitter. L The drain-source voltage V of the first switching transistor DS_Q1The waveform diagram shows that the switching power supply includes a first switching transistor and a second switching transistor. The first switching transistor serves as the main switching transistor of the switching power supply, and the second switching transistor alternately conducts with the first switching transistor. A first switching control signal Vg1 is used to control the switching action of the first switching transistor, and a second switching control signal Vg2 is used to control the switching action of the second switching transistor. L_pk i represents the peak inductor current. neg_pk This represents the negative peak value of the inductor current. Further, by controlling the second switch at the inductor current i... L After the inductor current is reduced to zero, it is turned on for a period of time T1, which allows the inductor current to decrease to a negative value. The first switch is turned on after the second switch is turned off. In some embodiments, to improve efficiency, the first switch can be controlled at its drain-source voltage V. DS_Q1 At time t when the voltage is zero or near zero, ZVS On. For example, when the power stage circuit of the switching power supply has a Buck topology, the output power in BCM mode... When the power stage circuit of the switching power supply has an active clamp flyback (ACF) topology, or a flyback topology where the second switch is connected to the secondary winding or auxiliary winding, the output power in BCM mode is... When the power stage circuit of the switching power supply has an asymmetric half-bridge (AHB) flyback topology, the output power in BCM mode is... Where Vin represents the input voltage of the switching power supply, Vout represents the output voltage of the switching power supply, and N represents the primary-to-secondary turns ratio of the transformer when the switching power supply is a flyback switching power supply; it can be seen that the output power in BCM mode is related to i L_pk +i neg_pk Positive correlation; existing technology does not address the negative peak value i of the inductor current. neg_pk To perform jitter control, typically at a given input / output voltage, the negative peak value of the inductor current i... neg_pk This remains unchanged, which leads to the peak inductor current i L_pk During jitter, the output power will vary with the peak inductor current i. L_pk It vibrates and oscillates.

[0048] Based on this, the present invention proposes a control method for a switching power supply. The control method includes controlling the turn-off of a first switching transistor according to a first jitter signal, so that the peak value of the inductor current jitters over time; and controlling the turn-off of a second switching transistor according to a second jitter signal, so that the negative peak value of the inductor current jitters over time at least for a portion of the time period, wherein, reference... Figures 4 to 6 When the inductor current has a negative peak value i neg_pk When the inductor current jitters over time, the negative peak value i neg_pk The direction of the jitter and the peak value of the inductor current iL_pk The jitter direction is reversed to reduce output power fluctuations. Thus, when the switching power supply is in BCM mode, output power fluctuations and output voltage ripple can be reduced without reducing the jitter amplitude of the inductor current peak. Since there is no need to reduce the jitter amplitude of the inductor current peak, good EMI characteristics can be guaranteed. Therefore, the control method of this invention can reduce cycle-by-cycle output power fluctuations while optimizing EMI characteristics, effectively reducing output ripple problems. In other words, it can reduce output ripple without affecting the optimization of EMI characteristics. It should be noted that this application does not limit the type of switching power supply; it can be a non-isolated switching power supply or an isolated switching power supply. When it is a non-isolated switching power supply, the inductor current is the current flowing through the inductor in the switching power supply; when it is an isolated switching power supply, the inductor current is the magnetizing inductor current of the transformer.

[0049] Furthermore, the inductor current can be reduced to a negative value by controlling the second switch to conduct for a period of time after the inductor current decreases to zero; and the first switch can be controlled to conduct after the second switch is turned off. Optionally, the first time can be controlled to jitter for at least a portion of the time period based on the second jitter signal, so that the negative peak value of the inductor current jitters with time for at least a portion of the time period, where the first time period is the time when the second switch is turned on after the inductor current decreases to zero. In addition, in some embodiments, the negative peak value of the inductor current i can be controlled. neg_pk The jitter amplitude and the peak inductor current i L_pk The absolute value of the difference in jitter amplitude is less than the first threshold, meaning the jitter amplitude of the negative peak of the inductor current is matched with the jitter amplitude of the peak of the inductor current to control the output power fluctuation within a certain range. For information on jitter amplitude, please refer to... Figure 4 The peak inductor current i is shown in the diagram. L_pk The jitter amplitude Δi1 and the negative peak value of the inductor current i neg_pk In a preferred embodiment, the jitter amplitude Δi2 of the inductor current negative peak can be controlled to be equal to the jitter amplitude of the inductor current peak, so as to completely offset the output power fluctuation caused by the jitter of the inductor current peak by utilizing the jitter of the inductor current negative peak.

[0050] Figures 4 to 6 The peak inductor current i is shown in different embodiments. L_pk Inductor current negative peak value i neg_pk A waveform diagram showing the output power Pout and output voltage Vout. In some embodiments, refer to... Figure 4 and Figure 6 It can control the negative peak value of the inductor current i neg_pk Jitter over time; in other embodiments, reference Figure 5It can also control the negative peak value of the inductor current i. neg_pk The inductor current jitters over time during certain periods. Furthermore, in some embodiments, the negative peak value i of the inductor current can be controlled. neg_pk The maximum value of the inductor current is less than or equal to the second threshold Ineg_zvs, so that the first switch is turned on at zero voltage, thereby improving the efficiency of the switching power supply. Optionally, the minimum value of the first time can be controlled to be greater than or equal to the third threshold, so that the maximum value of the negative peak value of the inductor current is less than or equal to the second threshold, wherein the first time is the time when the second switch turns on after the inductor current decreases to zero. In one embodiment, see Figure 4 Control the negative peak value of the inductor current i neg_pk As the inductor current jitters over time, the maximum value of the negative peak of the inductor current is less than the second threshold Ineg_zvs. Alternatively, the maximum value of the negative peak of the inductor current can be controlled to be equal to the second threshold Ineg_zvs, so that the first switch is turned on at zero voltage. This can improve the efficiency of the switching power supply while optimizing EMI characteristics and reducing output ripple. In another embodiment, refer to... Figure 5 Control the negative peak value of the inductor current i neg_pk Intermittent jittering occurs, with the negative peak of the inductor current jittering in the opposite direction to the peak inductor current during the time interval t1-t2, and remaining constant during the time interval t2-t3. Furthermore, during the period when the negative peak of the inductor current is not jittering, the negative peak of the inductor current equals the second threshold Ineg_zvs, and during the jittering period, the negative peak of the inductor current is less than or equal to the second threshold. This allows the first switching transistor to conduct with zero voltage during both the jittering and non-jittering periods of the negative peak of the inductor current, improving the efficiency of the switching power supply. Therefore, in this embodiment, the negative peak of the inductor current i neg_pk During jitter, it can optimize EMI characteristics, reduce output ripple, and improve the efficiency of the switching power supply, especially during the negative peak of the inductor current i. neg_pk During both jittering and non-jittering periods, EMI characteristics are optimized and the efficiency of the switching power supply is improved. In other words, this embodiment sacrifices output ripple characteristics for a certain time period (e.g., t2-t3) to ensure consistently optimized EMI characteristics and improved efficiency. In yet another embodiment, see... Figure 6 It can also control the negative peak value of the inductor current i. neg_pk Jitter over time, without negative peak value of inductor current i neg_pk The maximum value is limited, specifically, such as Figure 6 As shown, the negative peak current i during the time period t4-t5 neg_pk The negative peak current i is less than the second threshold Ineg_zvs during the time period t5-t6. neg_pkThe value is greater than the second threshold Ineg_zvs; therefore, this embodiment can optimize EMI characteristics while reducing output ripple. During the t4-t5 time period, it can achieve zero-point voltage conduction of the first switching transistor, improving the efficiency of the switching power supply. However, during the t5-t6 time period, due to the large negative current peak, the efficiency of the switching power supply is relatively low. Of course, in some other embodiments, it can also be combined with... Figures 4 to 6 The scenarios shown are all different. For example, the negative peak value of the inductor current can be set to be greater than the second threshold Ineg_zvs; the negative peak value of the inductor current can be controlled to fluctuate in the opposite direction to the peak value of the inductor current for a certain period of time, and be equal to zero for a certain period of time (or, in other words, there is no negative inductor current for a certain period of time), etc.

[0051] exist Figures 4 to 6 In the embodiments shown, triangular jitter is used as an example to illustrate the peak value of the inductor current, but it is not limited to this. In other embodiments, sawtooth jitter or sine wave jitter can also be performed. Of course, in addition to deterministic jitter, random jitter or pseudo-random jitter can also be performed.

[0052] The method for controlling the turn-off of the first switch transistor based on the first jitter signal further includes: generating a first reference signal based on an error compensation signal, wherein the error compensation signal characterizes the error between the output feedback signal and the reference signal of the switching power supply; and controlling the turn-off of the first switch transistor based on the first jitter signal, the first reference signal, and a first sampling signal characterizing the current flowing through the first switch. Further, the first jitter signal can be superimposed with the first reference signal or the first sampling signal to obtain a first superimposed signal; when the first jitter signal is superimposed with the first reference signal, the turn-off of the first switch transistor is controlled based on the comparison result between the first superimposed signal and the first sampling signal; when the first jitter signal is superimposed with the first sampling signal, the turn-off of the first switch transistor is controlled based on the comparison result between the first superimposed signal and the first reference signal.

[0053] The method for controlling the turn-off of the second switch based on the second jitter signal further includes: controlling the turn-off of the second switch based on the second jitter signal, the second reference signal, and a first signal characterizing a first time or negative inductor current. Further, the second jitter signal can be superimposed with the second reference signal or the first signal to obtain a second superimposed signal; when the second jitter signal is superimposed with the second reference signal, the turn-off of the second switch is controlled based on the comparison result of the second superimposed signal and the first signal; when the second jitter signal is superimposed with the first signal, the turn-off of the second switch is controlled based on the comparison result of the superimposed signal and the second reference signal. Even further, in some embodiments, when the second jitter signal is superimposed with the second reference signal, at least one of the second superimposed signal and the second reference signal can be clamped; when the second jitter signal is superimposed with the first signal, the second reference signal can be clamped, so that the maximum value of the negative peak value of the inductor current is less than or equal to a second threshold. In other embodiments, the second switch may also be turned off according to a minimum first time control signal, wherein the first time control signal is used to control the minimum value of the first time to be greater than or equal to a third threshold, thereby making the maximum value of the negative peak value of the inductor current less than or equal to the second threshold.

[0054] The control method of this application can achieve a jitter direction opposite to the jitter direction of the negative peak value of the inductor current by setting the second jitter signal and the first jitter signal to be positively or negatively correlated. For example, when the first jitter signal is superimposed on the first reference signal and the second jitter signal is superimposed on the second reference signal, the second jitter signal and the first jitter signal can be negatively correlated; when the first jitter signal is superimposed on the first reference signal and the second jitter signal is superimposed on the first signal, the second jitter signal and the first jitter signal can be positively correlated; when the first jitter signal is superimposed on the first sampling signal and the second jitter signal is superimposed on the second reference signal, the second jitter signal and the first jitter signal can be positively correlated; when the first jitter signal is superimposed on the first sampling signal and the second jitter signal is superimposed on the first signal, the second jitter signal and the first jitter signal can be negatively correlated. In some embodiments, the second jitter signal and the first jitter signal can also be set to be the same signal.

[0055] The preceding section introduced the control method of this application, which optimizes EMI characteristics and reduces cycle-by-cycle output power fluctuations, effectively reducing output ripple, when the switching power supply is in BCM mode. The following section describes methods for optimizing EMI characteristics and reducing output ripple when the switching power supply is in discontinuous conduction mode. For example, in one embodiment, when in DCM mode, instead of controlling the negative peak jitter of the inductor current, the first switching transistor is turned on according to a third jitter signal to control the operating frequency jittering over time. Simultaneously, the peak inductor current is controlled to jitter in the opposite direction to the operating frequency, thereby optimizing EMI characteristics and reducing output ripple. In another embodiment, when in DCM mode, the output ripple can be reduced while optimizing EMI characteristics by controlling the jittering of the inductor current peak value over time and the jittering of the inductor current negative peak value over time, wherein the jittering direction of the inductor current negative peak value is opposite to that of the inductor current peak value. In other words, the control method of this application can also optimize EMI characteristics and reduce output power fluctuations while the switching power supply is in DCM mode, effectively reducing output ripple. Furthermore, compared to the previous embodiment, this embodiment does not require frequency jittering control, simplifying the control process. In yet another embodiment, when in DCM mode, the main switch can be turned on according to a third jitter signal to control the operating frequency jittering over time, and the inductor current peak value can be controlled to jitter over time, with the inductor current negative peak value jittering over time at least for a portion of the time. By reasonably controlling the jittering direction and amplitude of these three factors, the output ripple can be reduced while optimizing EMI characteristics.

[0056] Secondly, the present invention also discloses a control circuit for a switching power supply, as shown in the reference. Figure 7 and Figure 8The control circuit 200 uses the aforementioned control method to control the switching power supply 20. The switching power supply 20 includes a power stage circuit 400 and a control circuit 200. The power stage circuit 400 includes a first switching transistor and a second switching transistor (not shown in the figure). The first switching transistor serves as the main switching transistor of the switching power supply 20, and the second switching transistor alternately conducts with the first switching transistor. The control circuit 200 generates a first switching control signal Vg1 to control the switching state of the first switching transistor, and generates a second switching control signal Vg2 to control the switching state of the second switching transistor. Specifically, the control circuit 200 controls the first switching transistor to turn off according to the first jitter signal jitter1, so that the peak value of the inductor current jitters over time; and controls the second switching transistor to turn off according to the second jitter signal jitter2, so that the negative peak value of the inductor current jitters over time at least for a portion of the time period. When the negative peak value of the inductor current jitters over time, the jitter direction of the negative peak value of the inductor current is opposite to the jitter direction of the peak value of the inductor current, so as to reduce output power fluctuations, thereby reducing output ripple while optimizing EMI characteristics.

[0057] like Figure 7 As shown, in one embodiment, the control circuit 200 includes an error compensation unit 201, a switch control unit 202, and a drive control unit 203. The error compensation unit 201 generates an error compensation signal Vcomp based on the output feedback signal FB of the switching power supply and a reference signal REF. The switch control unit 202 generates a first reference signal ipkref based on the error compensation signal Vcomp, and generates a first turn-off control signal off1 based on a first jitter signal jitter1, the first reference signal ipkref, and a first sampling signal Vcs representing the current flowing through the first switch; and generates a second jitter signal jitter2, a second reference signal inegref, and a first signal S representing the first time or negative inductor current. T1 / S ineg Generate a second shutdown control signal off2. Figure 7 S in T1 S represents the first signal at the first moment. ineg The first signal represents the negative inductor current; the drive control unit 203 generates a first switch control signal Vg1 according to the first turn-off control signal off1, and generates a second switch control signal Vg2 according to the second turn-off control signal off2, wherein the first switch control signal Vg1 controls the turn-off of the first switch according to the first turn-off control signal off1, and the second switch control signal Vg2 controls the turn-off of the second switch according to the second turn-off control signal off2.

[0058] For example, the switching power supply 20 further includes a first resistor R1 and a second resistor R2 connected in series. The first terminal of the first resistor R1 receives the output voltage Vout. The second terminal of the first resistor R1 and the first terminal of the second resistor R2 are connected and output a feedback signal FB at their common terminal. The second terminal of the second resistor R2 is connected to a reference ground. Of course, in other embodiments, the output feedback signal FB can also be obtained based on the output current or output power of the switching power supply 20. For example, the switching control unit 202 includes a peak current curve setting circuit 2021, a first superposition circuit 2022, a first comparison circuit 2023, a second superposition circuit 2026, and a second comparison circuit 2027. The peak current curve setting circuit 2021 generates a first reference signal ipkref based on the error compensation signal Vcomp. In one embodiment, such as... Figure 7 As shown, the first input terminal of the first superposition circuit 2022 receives the first jitter signal jitter1, and the second input terminal receives the first reference signal ipkref. After superimposing the first jitter signal jitter1 and the first reference signal ipkref, the first superposition signal is output. The first comparison circuit 1023 compares the first superposition signal with the first sampling signal Vcs representing the current flowing through the first switch to output the first turn-off control signal off1. Since the first switch control signal Vg1 controls the turn-off of the first switch according to the first turn-off control signal off1, the first superposition signal in this embodiment is the superposition signal of the first jitter signal jitter1 and the first reference signal ipkref, thus realizing the jittering of the inductor current peak. Of course, in another embodiment, the second input terminal of the first superposition circuit 2022 can also be replaced with receiving the first sampling signal Vcs. The first superposition circuit 2022 superimposes the first jitter signal jitter1 and the first sampling signal Vcs and outputs the first superimposed signal. The first comparison circuit 2023 compares the first superimposed signal and the first reference signal ipkref to output the first turn-off control signal off1, which can also achieve the same effect of jittering the peak inductor current. In one embodiment, such as Figure 7 As shown, the first input terminal of the second superposition circuit 2026 receives the second jitter signal jitter2, and the second input terminal receives the second reference signal inegref. The second jitter signal jitter2 and the second reference signal inegref are superimposed to output a second superimposed signal. The second comparison circuit 2027 compares the second superimposed signal with the first signal S. T1 / S inegA comparison is made to output a second turn-off control signal off2. The value of the second reference signal inegref can be fixed or controlled by other parameters in the switching power supply. For example, in one embodiment, the value of the second reference signal inegref can be set to be controlled by the drain-source voltage when the first switch is turned on in the previous cycle. Since the second switch control signal Vg2 controls the turn-off of the second switch according to the second turn-off control signal off2, the second superimposed signal in this embodiment is the superposition of the second jitter signal jitter2 and the second reference signal inegref. Therefore, it is possible to achieve at least partial jitter of the negative inductor current when the second switch is turned off, thereby achieving at least partial jitter of the negative peak value of the inductor current. Of course, in another embodiment, the second input terminal of the second superimposed circuit 2026 can also be replaced by receiving the first signal S. T1 / S ineg The second superposition circuit 2026 combines the second jitter signal jitter2 and the first signal S. T1 / S ineg After superposition, a second superimposed signal is output. The second comparison circuit 2027 compares the second superimposed signal and the second reference signal inegref to output a second turn-off control signal off2, which can also achieve the same effect of the negative peak of the inductor current jittering at least for a part of the time period.

[0059] Furthermore, to control the maximum value of the negative peak of the inductor current to be less than or equal to the second threshold Ineg_zvs, in some embodiments, the switch control unit 202 further includes a clamping circuit (not shown in the figure). When the second input terminal of the second superposition circuit 2026 receives the second reference signal inegref, the clamping circuit clamps at least one of the second superposition signal and the second reference signal; when the second input terminal of the second superposition circuit 2026 receives the first signal S... T1 / S ineg At that time, the clamping circuit clamps the second reference signal. In some other embodiments, the switch control unit 202 may also be replaced by a minimum first time control circuit (not shown in the figure). The minimum first time control circuit outputs a minimum first time control signal, and the drive control unit 203 further generates a second switch control signal Vg2 according to the minimum first time control signal. The second switch control signal Vg2 controls the turn-off of the second switch tube according to the second turn-off control signal off2 and the minimum first time control signal, wherein the minimum first time control signal is used to control the minimum value of the first time to be greater than or equal to a third threshold, thereby making the maximum value of the negative peak value of the inductor current less than or equal to the second threshold.

[0060] Please continue to refer to this. Figure 7The switch control unit 202 also includes a frequency curve setting circuit 2024, which generates a frequency control signal Vfs based on the error compensation signal Vcomp. In one embodiment, the switch control unit 202 further includes a frequency jitter processing circuit 2025. The frequency jitter processing circuit 2025 receives a third jitter signal jitter3 and a frequency control signal Vfs, processes them, and outputs a jitter frequency control signal Vfs1. When the switching power supply 20 is in DCM mode, it does not control the jitter of the negative peak of the inductor current, but controls the jitter direction of the peak of the inductor current to be opposite to the jitter direction of the operating frequency, thereby optimizing EMI characteristics while reducing output ripple. For example, in DCM mode, the drive control unit 203 can be set to generate a first switch control signal Vg1 according to the first turn-off control signal off1 and the jitter frequency control signal Vfs1. The first switch control signal Vg1 controls the turn-off of the first switch transistor according to the first turn-off control signal off1 to realize the jitter of the peak of the inductor current over time, and controls the turn-on of the first switch transistor according to the jitter frequency control signal Vfs1 to realize the jitter of the operating frequency over time. In another embodiment, the switch control unit 202 may also exclude the frequency jitter processing circuit 2025. When the switching power supply 20 is in DCM mode, the drive control unit 203 generates a first switch control signal Vg1 according to the first turn-off control signal off1, and generates a second switch control signal Vg2 according to the frequency control signal Vfs and the second turn-off control signal off2. The first switch control signal Vg1 controls the turn-off of the first switch transistor according to the first turn-off control signal off1 to realize the inductor current peak value jittering over time. The second switch control signal Vg2 controls the turn-on of the second switch transistor according to the frequency control signal Vfs, and controls the turn-off of the second switch transistor according to the second turn-off control signal off2, so that the negative peak value of the inductor current jitters over time at least for a part of the time period. When the negative peak value of the inductor current jitters over time, the jittering direction of the negative peak value of the inductor current is controlled to be opposite to the jittering direction of the peak value of the inductor current, thereby optimizing EMI characteristics and reducing output ripple. It is readily understood that in another embodiment, a frequency jitter processing circuit 2025 may also be included, which controls the operating frequency to jitter over time, the peak value of the inductor current to jitter over time, and the negative peak value of the inductor current to jitter over time for at least a portion of the time period when in DCM mode, and optimizes the EMI characteristics while reducing the output ripple by reasonably controlling the jitter direction and jitter amplitude of the three.

[0061] Figure 8 A circuit block diagram of another embodiment of the control circuit 200 of the switching power supply of the present invention is shown, and... Figure 7The control circuit 200 shown is basically the same and will not be described again here. The difference is that the control circuit 200 in this embodiment also includes a zero-voltage detection circuit 2028. The zero-voltage detection circuit 2028 is used to detect when the source-drain voltage of the first switching transistor is zero or close to zero, so as to output a zero-voltage detection signal ZVS. The drive control unit 203 also generates a first switching control signal Vg1 according to the zero-voltage detection signal ZVS, wherein the first switching control signal Vg1 controls the conduction of the first switching transistor according to the zero-voltage detection signal ZVS. This embodiment can optimize EMI characteristics, reduce output ripple, and control the first switching transistor to conduct when its drain-source voltage is zero or close to zero, thereby improving the efficiency of the switching power supply. Furthermore, in some embodiments, the negative peak value of the inductor current i can be controlled. neg_pk The maximum value is less than or equal to the second threshold Ineg_zvs, so that the first switching transistor can always be turned on with zero voltage, thereby further improving the efficiency of the switching power supply.

[0062] Thirdly, the present invention also discloses a switching power supply, as referenced Figure 7 and Figure 8 The switching power supply 20 includes a power stage circuit 400 and the control circuit 200. The power stage circuit 400 converts the input voltage Vin into an output voltage Vout. This application does not limit the topology of the power stage circuit 400. When the switching power supply is a non-isolated switching power supply, in one embodiment, the power stage circuit 400 may include, for example... Figure 9 The Buck topology shown includes a first switch Q1, a second switch Q2, and an inductor L01. The first switch Q1 and the second switch Q2 are connected in series between the input terminal of the power stage circuit 400 and reference ground. The inductor L01 is connected between the common terminal of the first switch Q1 and the second switch Q2 and the output terminal of the power stage circuit 400. Of course, in other embodiments, the power stage circuit 400 may also include Boost, Buck-Boost, or other topologies. When the switching power supply is an isolated switching power supply, in one embodiment, the power stage circuit 400 may include, for example... Figure 10 The asymmetric half-bridge flyback topology shown includes a first switch Q1, a second switch Q2, and a transformer T1. Transformer T1 includes a primary winding NP and a secondary winding Ns. The first switch Q1 is connected to the primary winding NP. Here, Lk represents leakage inductance, Lm represents magnetizing inductance, and i LmRepresenting the magnetizing inductor current, the first switch Q1 and the second switch Q2 are connected in series between the input terminal of the power stage circuit 400 and the reference ground. The primary winding Np and the capacitor C1 are connected in series between the source and drain of the second switch Q2. The first switch Q1 is connected between the second switch Q2 and the reference ground. Of course, in another asymmetric half-bridge flyback topology, the first switch Q1 can also be connected between the input terminal of the power stage circuit 400 and the second switch Q2, with one end of the second switch Q2 connected to the first switch Q1 and the other end connected to the reference ground. In other embodiments, the power stage circuit 400 may also include an active clamp flyback topology, or a flyback topology in which the second switch is connected to the secondary winding or auxiliary winding, etc. In the case of an active clamp flyback topology, the second switch is an active clamp switch in the active clamp flyback topology.

[0063] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. A control method for a switching power supply, the switching power supply comprising a first switching transistor and a second switching transistor, the first switching transistor serving as the main switching transistor of the switching power supply, the second switching transistor being alternately turned on and off with the first switching transistor, characterized in that, The first switching transistor is turned off according to a first jitter signal, so that the peak value of the inductor current jitters over time; the second switching transistor is turned off according to a second jitter signal, so that the negative peak value of the inductor current jitters over time at least for a portion of the time period. Specifically, when the negative peak value of the inductor current fluctuates over time, the fluctuating direction of the negative peak value of the inductor current is opposite to the fluctuating direction of the peak value of the inductor current, so as to reduce the fluctuation of output power.

2. The control method according to claim 1, characterized in that, The absolute value of the difference between the jitter amplitude of the negative peak value of the inductor current and the jitter amplitude of the peak value of the inductor current is less than or equal to a first threshold.

3. The control method according to claim 1, characterized in that, The second switch is controlled to conduct for a period of time after the inductor current decreases to zero, so that the inductor current decreases to a negative value; The first switch is turned on after the second switch is turned off.

4. The control method according to claim 1, characterized in that, The first time is controlled to jitter for at least a portion of the time period according to the second jitter signal, so that the negative peak value of the inductor current jitters with time for at least a portion of the time period, wherein the first time is the time when the second switch turns on after the inductor current decreases to zero.

5. The control method according to claim 1, characterized in that, The maximum value of the negative peak of the inductor current is controlled to be less than or equal to a second threshold so that the first switch is turned on with zero voltage.

6. The control method according to claim 5, characterized in that, The negative peak value of the inductor current fluctuates intermittently, wherein during the period when the negative peak value of the inductor current does not fluctuate, the negative peak value of the inductor current is equal to the second threshold.

7. The control method according to claim 5, characterized in that, The minimum value of the first time is controlled to be greater than or equal to the third threshold, so that the maximum value of the negative peak value of the inductor current is less than or equal to the second threshold, wherein the first time is the time when the second switch turns on after the inductor current decreases to zero.

8. The control method according to claim 1, characterized in that, The method for controlling the turn-off of the first switching transistor based on the first jitter signal includes: A first reference signal is generated based on the error compensation signal, wherein the error compensation signal characterizes the error between the output feedback signal and the reference signal of the switching power supply; The first switch is turned off based on the first jitter signal, the first reference signal, and the first sampling signal representing the current flowing through the first switch.

9. The control method according to claim 1, characterized in that, The method for controlling the turn-off of the second switching transistor based on the second jitter signal includes: The second switch is turned off based on the second jitter signal, the second reference signal, and the first signal representing the first time or negative inductor current, wherein the first time is the time when the second switch turns on after the inductor current decreases to zero.

10. The control method according to any one of claims 1, 8-9, characterized in that, The second jitter signal is positively or negatively correlated with the first jitter signal.

11. A control circuit for a switching power supply, the switching power supply including a first switching transistor and a second switching transistor, the first switching transistor serving as the main switching transistor of the switching power supply, the second switching transistor being alternately turned on and off with the first switching transistor, characterized in that, The control circuit controls the first switch to turn off according to a first jitter signal, so that the peak value of the inductor current jitters over time; and controls the second switch to turn off according to a second jitter signal, so that the negative peak value of the inductor current jitters over time at least for a portion of the time period. Specifically, when the negative peak value of the inductor current fluctuates over time, the fluctuating direction of the negative peak value of the inductor current is opposite to the fluctuating direction of the peak value of the inductor current, so as to reduce the fluctuation of output power.

12. The control circuit according to claim 11, characterized in that, The control circuit includes an error compensation unit, a switch control unit, and a drive control unit. The error compensation unit generates an error compensation signal based on the output feedback signal and reference signal of the switching power supply. The switch control unit generates a first reference signal based on the error compensation signal, and generates a first shutdown control signal based on the first jitter signal, the first reference signal, and a first sampling signal characterizing the current flowing through the first switch. A second turn-off control signal is generated based on the second jitter signal, the second reference signal and the first signal characterizing the first time or negative inductor current, wherein the first time is the time when the second switch turns on after the inductor current decreases to zero. The drive control unit generates a first switch control signal based on the first shutdown control signal and generates a second switch control signal based on the second shutdown control signal. The first switch control signal controls the first switch transistor to turn off based on the first shutdown control signal, and the second switch control signal controls the second switch transistor to turn off based on the second shutdown control signal.

13. The control circuit according to claim 12, characterized in that, The switch control unit includes a zero-voltage detection circuit. The zero-voltage detection circuit is used to detect when the source-drain voltage of the first switching transistor is zero or close to zero, so as to output a zero-voltage detection signal. The drive control unit also generates the first switch control signal based on the zero voltage detection signal, wherein the first switch control signal controls the conduction of the first switch transistor based on the zero voltage detection signal.

14. A switching power supply, characterized in that, The switching power supply includes a power stage circuit and a control circuit as described in any one of claims 11-13. The power stage circuit is used to convert the input voltage into the output voltage. The power stage circuit includes a first switching transistor and a second switching transistor. The first switching transistor serves as the main switching transistor of the switching power supply. The second switching transistor is alternately turned on with the first switching transistor. The control circuit is used to control the switching states of the first switching transistor and the second switching transistor.

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