Circuit for making boost current limit value not change with duty ratio by dynamic clamping

Abstract

The circuit of dynamic clamping makes the current limit value of BOOST not change with duty ratio. The slope compensation superimposed quantity formed by slope compensation current is superimposed on the original upper clamping voltage to form dynamic clamping, which is beneficial to guarantee the maximum peak current of BOOST and realize the effect that the effective current limit value of BOOST converter does not change with duty ratio.

Description

Technical Field

[0001] This invention relates to current loop slope compensation technology for BOOST converters, and in particular to a circuit that uses dynamic clamping to prevent the BOOST current limit value from changing with the duty cycle. Background Technology

[0002] Figure 2 This is a schematic diagram of a traditional superimposed slope compensation current-limiting comparator circuit. (Example) Figure 2 As shown, the conventional superimposed slope-compensated current-limiting comparator circuit includes a first PMOS transistor MP0 and a third PMOS transistor MP2 (with a mirror ratio of 1:1) with a common source and common gate. The source of MP2 is connected to the power supply voltage VDD. The gate and drain of MP0 are interconnected and then connected to the drain of the first NMOS transistor MN1. The gate of MN1 is connected to the sawtooth wave voltage terminal VRAMP generated by the internal clock. The source of MN1 is grounded through the first resistor R1. The drain of MP2 is connected to the sampling node sum. sum is connected to VDD through the current sampling terminal Ics of the lower transistor. The sampling current Ics of the BOOST lower transistor flows into the sampling node sum. sum is grounded through the third resistor R3. sum is connected to the positive input terminal of the pulse width modulation comparator PWM_COMP. +), the negative input terminal (-) of PWM_COMP is connected to the clamping node eaout, which is the output terminal of error amplifier EA. The output terminal of PWM_COMP is connected to the main flip signal terminal MAIN_TRIP (or output the main flip signal MAIN_TRIP). The positive input terminal (+) of error amplifier EA is connected to the reference voltage terminal VREF. The negative input terminal (-) of error amplifier EA is connected to the feedback voltage terminal FB. The clamping node eaout is connected to the source of the fourth PMOS transistor MP3 and the negative input terminal (-) of the first operational amplifier AMP1. The positive input terminal (+) of AMP1 is connected to the upper clamping voltage terminal. The output terminal of AMP1 is connected to the gate of MP3. The drain of MP3 is grounded.

[0003] For peak current-mode boost converters, when the duty cycle is greater than 50%, slope compensation is needed in the current loop to eliminate subharmonic oscillations. However, adding slope compensation reduces the peak inductor current, resulting in a lower effective boost current limit. A common solution is to change the slope compensation gradient, transforming the fixed-slope compensation current into a segmented-slope compensation current; the larger the duty cycle, the larger the slope. This approach mitigates the reduction in maximum peak current caused by slope compensation, but it cannot completely eliminate it. Figure 2The conventional superimposed slope-compensated current-limiting comparator circuit shown uses a sawtooth wave generated by the internal clock of the VRAMP to produce a current with a fixed slope across resistor R1. This slope-compensated current is superimposed on the sampling current Ics of the lower transistor through the mirror image of the MP2 transistor, and converted into a sum-point voltage across R3. This voltage is compared with the output eaout of the error amplifier, thereby controlling the switching of the PWM comparator. The operational amplifiers AMP1 and MP3 transistors form an upper clamping circuit for eaout through negative feedback. When the load is light or medium, the eaout voltage is low and insufficient to turn on the MP3 transistor, therefore the upper clamping circuit does not operate. As the load increases, the eaout voltage gradually rises. When the load increases to the point where the inductor current reaches its maximum peak current, the MP3 transistor turns on, and the upper clamping circuit begins to function. At this time, the negative feedback clamps the eaout voltage to the Clamp_H value. Only when the inductor current increases to satisfy (Ics + Islope) * R3 = Clamp_H, where Islope is the slope compensation current (flowing from the drain of MP2 into sum and flowing through R3 together with Ics), will the PWM comparator flip and turn off the lower transistor. Analysis shows that the larger the duty cycle, the larger the slope compensation current Islope, thus the smaller the effective maximum peak current Ics, and the smaller the effective current limit value of BOOST. Summary of the Invention

[0004] This invention addresses the defects or deficiencies in existing technologies by providing a circuit that uses dynamic clamping to ensure that the BOOST current limit value does not change with the duty cycle.

[0005] The technical solution of the present invention is as follows:

[0006] A circuit employing dynamic clamping to prevent the BOOST current limit value from changing with the duty cycle is characterized by comprising a sampling node and a clamping node for controlling the switching of a pulse width modulation comparator. The clamping node has a first path connected to the negative input terminal of the pulse width modulation comparator, a second path connected to the output terminal of an error amplifier, and a third path connected to the source of a fourth PMOS transistor and the negative input terminal of a first operational amplifier. The drain of the fourth PMOS transistor is grounded, and its gate is connected to the output terminal of the first operational amplifier. The positive input terminal of the first operational amplifier is connected to a second node. The second node has a first path connected to a ramp compensation current circuit, and a second path connected via a second resistor R2 to the positive input terminal of a second operational amplifier and the drain of a second NMOS transistor. The source of the second NMOS transistor is grounded, and its gate is connected to the output terminal of the second operational amplifier. The negative input terminal of the second operational amplifier is connected to a clamping voltage terminal.

[0007] The sampling node has a first path connected to the positive input terminal of the pulse width modulation comparator, a second path connected to the power supply voltage terminal through the current sampling terminal of the lower transistor, with the sampling current of the BOOST lower transistor flowing into the sampling node, a third path connected to the slope compensation current circuit, with the slope compensation current flowing into the sampling node, and a fourth path grounded through the third resistor R3.

[0008] The slope compensation current circuit includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor with a common source and common gate. The drain of the third PMOS transistor is connected to the sampling node, and the source of the third PMOS transistor is connected to the power supply voltage terminal. The drain of the second PMOS transistor is connected to the second node.

[0009] The gate and drain of the first PMOS transistor are interconnected and then connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the sawtooth wave voltage terminal generated by the internal clock. The source of the first NMOS transistor is connected to the first node, and the first node is grounded through the first resistor R1.

[0010] The mirror ratio of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor is 1:1:1.

[0011] The resistance values ​​of R1, R2, and R3 are equal, R1 = R2 = R3 = R.

[0012] Let the slope compensation current be Islope, the sampling current of the lower BOOST transistor be Ics, the voltage at the upper clamping voltage terminal be Clamp_H, and the clamping node voltage be eaout. Then, when the load on the BOOST converter increases to the point that the fourth PMOS transistor turns on, eaout = Clamp_H + Islope*R, where Islope*R is equal to the slope compensation superposition amount Islope*R3, so that the maximum peak current of the BOOST converter does not change with the duty cycle.

[0013] The output of the pulse width modulation comparator is connected to the master flip signal terminal to output the master flip signal MAIN_TRIP.

[0014] The technical effects of this invention are as follows: This invention uses a dynamic clamping circuit to ensure that the BOOST current limiting value does not change with the duty cycle. By superimposing a slope compensation superposition amount formed by the slope compensation current on the original upper clamping voltage, a dynamic clamping is formed together with the original upper clamping voltage and applied to the clamping node. This helps to ensure that the maximum peak current of BOOST is not affected, and achieves the effect that the effective current limiting value of the BOOST converter does not change with the duty cycle.

[0015] The present invention has the following characteristics: 1. With the help of the clamp detection circuit at the output of the error amplifier, the slope recovery circuit does not affect the normal slope compensation operation when the inductor current has not reached the maximum peak current. 2. Based on the traditional operational amplifier slope compensation circuit, when the inductor current reaches the maximum peak current, the slope compensation amount in the inductor current is completely canceled out by superimposing the clamp value at the output of the error amplifier with the slope compensation voltage, thus creating a dynamic clamping form.

[0016] The advantages of this invention compared to the prior art are: simple circuit structure, ingenious design, and the maximum peak current of BOOST does not change with slope compensation. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure of the present invention, which uses dynamic clamping to prevent the BOOST current limit value from changing with the duty cycle.

[0018] Figure 2 This is a schematic diagram of a current-limiting comparator circuit with traditional superimposed slope compensation.

[0019] The reference numerals in the attached diagram are listed below: VDD - Power supply voltage terminal; PWM_COMP - Pulse width modulation comparator; EA - Error amplifier; AMP1~AMP2 - First operational amplifier to second operational amplifier; MAIN_TRIP - Main flip signal terminal; sum - Sampling node; VREF - Reference voltage terminal; FB - Feedback voltage terminal; eaout - Clamping node; Clamp_H - Upper clamping voltage terminal; Ics - Lower transistor current sampling terminal or BOOST lower transistor sampling current (BOOST is a boost converter, and the lower transistor is also called the lower switching transistor); R1~R3 - First resistor to third resistor; MP0~MP3 - First PMOS transistor to fourth PMOS transistor; MN1~MN2 - First NMOS transistor to second NMOS transistor; VRAMP - Internal clock generation sawtooth wave voltage terminal; A~B - First node to second node; 1:1:1 - Mirror ratio. Detailed Implementation

[0020] The following is in conjunction with the attached diagram ( Figure 1 The present invention will be described below.

[0021] Figure 1 This is a schematic diagram illustrating the structural principle of the circuit that implements the present invention, using dynamic clamping to ensure that the BOOST current limiting value does not change with the duty cycle. (Reference) Figure 1As shown, the circuit employs dynamic clamping to prevent the BOOST current limit value from changing with the duty cycle. It includes a sampling node `sum` and a clamping node `eaout` that control the switching of the pulse width modulation comparator. The clamping node `eaout` has a first path connected to the negative input (-) of the pulse width modulation comparator `PWM_COMP`, a second path connected to the output of the error amplifier `EA`, and a third path connected to the source of the fourth PMOS transistor `MP3` and the negative input (-) of the first operational amplifier `AMP1`. The drain of the fourth PMOS transistor `MP3` is grounded, and the gate of the fourth PMOS transistor `MP3` is connected to the first operational amplifier `AMP1`. The output terminal of the first operational amplifier AMP1 is connected to the positive input terminal (+) of the first operational amplifier AMP1, which is connected to the second node B. The first path of the second node B is connected to the ramp compensation current circuit, and the second path is connected to the positive input terminal (+) of the second operational amplifier AMP2 and the drain of the second NMOS transistor MN2 through the second resistor R2. The source of the second NMOS transistor MN2 is grounded, and the gate of the second NMOS transistor MN2 is connected to the output terminal of the second operational amplifier AMP2. The negative input terminal (-) of the second operational amplifier AMP2 is connected to the clamping voltage terminal Clamp_H.

[0022] The sampling node sum has four paths: a first path connected to the positive input (+) of the pulse width modulation comparator PWM_COMP; a second path connected to the power supply voltage VDD via the lower transistor current sampling terminal Ics, with the BOOST lower transistor sampling current Ics flowing into the sampling node sum; a third path connected to the slope compensation current circuit, with the slope compensation current flowing into the sampling node sum; and a fourth path grounded via the third resistor R3. The slope compensation current circuit includes a common-source common-gate PMOS transistor MP0, a second PMOS transistor MP1, and a third PMOS transistor MP2. The drain of the third PMOS transistor MP2 is connected to the sampling node sum, and its source is connected to the power supply voltage VDD. The drain of the second PMOS transistor MP1 is connected to the second node B. The gate and drain of the first PMOS transistor MP0 are interconnected and then connected to the drain of the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is connected to the internal clock sawtooth wave voltage terminal VRAMP, and its source is connected to the first node A. The first node A is grounded via the first resistor R1.

[0023] The mirror ratio of the first PMOS transistor MP0, the second PMOS transistor MP1, and the third PMOS transistor MP2 is 1:1:1. The resistance values ​​of R1, R2, and R3 are equal, R1 = R2 = R3 = R. Let the slope compensation current be Islope, the sampling current of the lower BOOST transistor be Ics, the upper clamping voltage terminal voltage be Clamp_H, and the clamping node voltage be eaout. Then, when the load on the BOOST converter increases to the point that the fourth PMOS transistor MP3 turns on, eaout = Clamp_H + Islope*R, where Islope*R is equal to the slope compensation superposition amount Islope*R3, thus ensuring that the maximum peak current of the BOOST converter does not change with the duty cycle. The output terminal of the pulse width modulation comparator PWM_COMP is connected to the main switching signal terminal to output the main switching signal MAIN_TRIP.

[0024] Peak current mode BOOST converters are widely used in BOOST converter architectures due to their relatively simple loop compensation method. When the duty cycle is greater than 50%, slope compensation needs to be added to the current loop to eliminate subharmonic oscillations. However, after adding slope compensation, the peak inductor current decreases, resulting in a lower BOOST load capacity. This invention proposes a circuit that uses dynamic clamping to ensure that the BOOST current limit value does not change with the duty cycle. This invention belongs to a slope compensation recovery technique, which cancels out the slope compensation current when current limiting occurs, thereby ensuring that the maximum peak current of the BOOST remains unaffected. This achieves the effect that the effective current limit value of the BOOST converter does not change with the duty cycle, while simultaneously preventing a decrease in the BOOST load capacity.

[0025] The circuit designed in this invention is as follows: Figure 1 As shown, the resistance values ​​R1 = R2 = R3. The current of MP2 is compensated by the mirror slope of MP1, so that the voltage drop across resistor R2 is equal to the voltage drop across resistor R3 of the slope compensation current. This raises the clamping value Islope*R2 on the error amplifier, thereby achieving the purpose of dynamic clamping.

[0026] When under medium load, eaout is low, and the upper clamping circuit composed of AMP1 and MP3 does not work. At this time, the slope compensation current is normally added to resistor R3 through MP2. Although the upper clamping voltage of EA at point B is also superimposed with the slope compensation information, it will not cancel the slope compensation current because MP3 has not reached the turn-on point.

[0027] When the load increases to a level sufficient to turn on MP3, the upper clamping circuit of EA starts to function. Through the negative feedback formed by AMP1 and MP3, eaout is clamped to a voltage equal to that at point B. Since the voltage at point B has already been superimposed with the slope compensation current across resistor R2, the upper clamping voltage of eaout becomes (Clamp_H + Islope*R2), meaning the upper clamping voltage is increased by Islope*R2. If we set resistors R2 and R3 to be equal, we know that the increase in the upper clamping voltage is equal to the slope compensation superposition amount Islope*R3. This completely cancels out the slope compensation amount of the peak current mode. Therefore, under this condition, the slope compensation will not change the magnitude of the maximum peak current, thus ensuring that the maximum peak current of BOOST does not change with the duty cycle.

[0028] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A circuit that employs dynamic clamping to ensure that the BOOST current limiting value does not change with the duty cycle, characterized in that, The system includes a sampling node and a clamping node for controlling the switching of a pulse width modulation comparator. The clamping node has a first path connected to the negative input of the pulse width modulation comparator, a second path connected to the output of an error amplifier, and a third path connected to the source of a fourth PMOS transistor and the negative input of a first operational amplifier. The drain of the fourth PMOS transistor is grounded, and the gate of the fourth PMOS transistor is connected to the output of the first operational amplifier. The positive input of the first operational amplifier is connected to a second node. The second node has a first path connected to a ramp compensation current circuit, and a second path connected through a second resistor R2 to the positive input of a second operational amplifier and the drain of a second NMOS transistor. The source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to the output of the second operational amplifier. The negative input of the second operational amplifier is connected to the clamping voltage terminal. The sampling node has a first path connected to the positive input terminal of the pulse width modulation comparator, a second path connected to the power supply voltage terminal through the current sampling terminal of the lower transistor, with the sampling current of the BOOST lower transistor flowing into the sampling node, a third path connected to the slope compensation current circuit, with the slope compensation current flowing into the sampling node, and a fourth path grounded through the third resistor R3.

2. The circuit according to claim 1, which uses dynamic clamping to prevent the BOOST current limiting value from changing with the duty cycle, is characterized in that... The slope compensation current circuit includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor with a common source and common gate. The drain of the third PMOS transistor is connected to the sampling node, and the source of the third PMOS transistor is connected to the power supply voltage terminal. The drain of the second PMOS transistor is connected to the second node.

3. The circuit according to claim 2, which uses dynamic clamping to prevent the BOOST current limiting value from changing with the duty cycle, is characterized in that... The gate and drain of the first PMOS transistor are interconnected and then connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the sawtooth wave voltage terminal generated by the internal clock. The source of the first NMOS transistor is connected to the first node, and the first node is grounded through the first resistor R1.

4. The circuit according to claim 3, which uses dynamic clamping to prevent the BOOST current limiting value from changing with the duty cycle, is characterized in that... The mirror ratio of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor is 1:1:

1.

5. The circuit according to claim 4, which uses dynamic clamping to prevent the BOOST current limiting value from changing with the duty cycle, is characterized in that... The resistance values ​​of R1, R2, and R3 are equal, R1=R2=R3=R.

6. The circuit according to claim 5, which uses dynamic clamping to prevent the BOOST current limiting value from changing with the duty cycle, is characterized in that... Let the slope compensation current be Islope, the sampling current of the lower BOOST transistor be Ics, the upper clamping voltage terminal voltage be Clamp_H, and the clamping node voltage be eaout. Then, when the load on the BOOST converter increases to the point that the fourth PMOS transistor turns on, eaout = Clamp_H + Islope. R2, where Islope R2 and slope compensation superposition amount Islope R3 is equal, so that the maximum peak current of the BOOST converter does not change with the duty cycle.

7. The circuit according to claim 1, which uses dynamic clamping to prevent the BOOST current limiting value from changing with the duty cycle, is characterized in that... The output of the pulse width modulation comparator is connected to the master flip signal terminal to output the master flip signal MAIN_TRIP.

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