EDMA and McBSP-based inter-DSP communication method for satellite receiver

Abstract

The application provides a kind of communication method between DSPs of satellite-borne receiver based on EDMA and McBSP, which utilizes EDMA to control real-time data communication between DSPs through McBSP interface, and does not need CPU to allocate receiving and sending, so as to ensure that DSP has sufficient machine time to complete navigation text processing, observation calculation, positioning / orbit determination and real-time processing of inter-satellite measurement, etc.; flexible multi-channel buffer serial port McBSP interface is used for communication between DSPs, which reduces the complexity of hardware interface design under the premise of meeting the real-time data communication rate between DSPs; reasonable embedded software design realizes full-duplex communication of McBSP by querying EDMA event completion flag in one interrupt (timer interrupt), which meets the real-time requirement of interface data communication while reducing software complexity; the method simplifies the hardware interface design of data communication between DSPs of each receiving board in current dual-satellite measurement receiver, and greatly improves the reliability and real-time performance of data transmission between DSPs of multi-system and multi-functional dual-satellite measurement receiver.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and specifically to a communication method between satellite receiver DSPs based on EDMA and McBSP. Background Technology

[0002] Based on the requirements for receiving navigation signals, the business processing of the navigation receiver needs to adopt a dual-threaded processing method of main loop combined with timer interrupt. The communication of the DSP chip is mostly implemented by the CPU controlling various interfaces.

[0003] The operating environment of spaceborne navigation receivers contains a large number of single-event events, which can cause receiver malfunctions. To reduce the impact of single-event events, spaceborne navigation receivers need to use aerospace-grade DSP chips, but these DSP chips have relatively limited performance and resources.

[0004] With the development of global satellite navigation systems and technologies, the functions of spaceborne receivers are becoming increasingly complex. For example, some spaceborne receivers use dual DSPs to implement single-point positioning, absolute orbit determination, dual-satellite relative orbit determination, and relative positioning functions using GPS L1C / A and L2P dual-frequency, BD2 B1I and B3I dual-frequency, and BD3 B1C and B2a dual-frequency signals. The DSPs operate at a clock frequency of 372MHz, which puts increasing strain on the DSP chip's clock resources, necessitating the search for a communication solution that does not require CPU control. The EDMA function of the DSP chip is a good choice. EDMA can handle data transfer between all memory units and peripherals on the DSP chip without consuming CPU clock cycles.

[0005] TEXAS INSTRUMENTS' C64x series DSP chips feature 64 EDMA channels and three independent McBSP interfaces (McBSP0, McBSP1, and McBSP2). EDMA provides synchronization events for McBSPs, facilitating data transmission control. In the C64+ series, EDMA channels 12 and 13 handle the transmit and receive events for McBSP0, respectively. Configuration allows for one-dimensional data transmission of elements or arrays, as well as two-dimensional data transmission of frames or blocks. Two-dimensional data transmission is typically used in image processing.

[0006] The EDMA controller of the TEXAS INSTRUMENTS C64x series DSP chips consists of four parts: event and interrupt handling registers, an event decoder, parameter RAM, and address generation hardware. An event is a synchronization signal that triggers the start of transmission on the EDMA channel. The event register is responsible for capturing all EDMA events. If events occur simultaneously, the event decoder resolves the conflict. The transmission parameters (PaRAM) of the EDMA event are stored in the EDMA's parameter RAM and are passed to the address generation hardware after the event is triggered for read / write addressing. The event and interrupt handling registers and PaRAM are user-programmable.

[0007] Each EDMA event's PaRAM contains 6 parameters, each occupying 32 bits, as detailed in the table below.

[0008]

[0009] The relevant input parameters are explained below:

[0010] The list of control registers involved is as follows:

[0011] EDMA transfer events have three triggering modes: CPU-triggered, event-triggered, and chain-triggered. CPU-triggered EDMA transfer is initiated by the CPU by writing to the Event Set Register (ESR). CPU-triggered EDMA transfer is a real-time event that does not require an external trigger signal; therefore, it is asynchronous data transfer. Event-triggered EDMA transfer is initiated by an external event trigger signal. Each EDMA channel has a dedicated Event Register (ER) responsible for monitoring all transfer events on that channel. When the CPU enables the EER by writing a "1", the EDMA channel can automatically complete data transfer based on an external trigger signal. Chain-triggered EDMA transfer builds upon event-triggered EDMA transfer by establishing an event chain, allowing the completion of one EDMA transfer to trigger another.

[0012] The conventional implementation of EDMA communication in DSP chips is a dual-threaded mode using a main program and EDMA interrupts. The control flow is shown below. Figure 1 , Figure 2The main program is responsible for initiating the initial data transmission and reception, as well as data packaging and parsing. EDMA uses an event-triggered mode. Each time a receive / transmit event is detected, only one data unit (determined by the transmitted data dimension and synchronization mode configuration) is transmitted. The data count value (ELECNT, FRMCNT) is automatically decremented by 1. When all count values ​​are 0, the transmission is considered complete, and a receive / transmit interrupt is generated. The EDMA interrupt service routine checks the CIPR. If an McBSP transmit channel interrupt is detected, the next data transmission is initiated as needed, and then the system checks for an McBSP receive channel interrupt. If no transmit interrupt is detected, the system directly checks for an McBSP receive channel interrupt. If an interrupt is detected, the data is copied, the CIPR is cleared, and the EDMA interrupt service routine ends. If no interrupt is detected, the CIPR is cleared, and the EDMA interrupt service routine ends.

[0013] If the navigation receiver's EDMA communication adopts the conventional method described above, namely the EDMA interrupt mode, the final receiver design becomes a three-threaded approach of "main loop + timer interrupt + EDMA interrupt". This not only increases the design complexity but also reduces its reliability.

[0014] Therefore, a communication method is needed to enable navigation receivers that achieve real-time communication between DSPs based on EDMA and McBSP functions, balancing complexity and reliability. Summary of the Invention

[0015] This invention addresses the problems of complex hardware interfaces and insufficient service processing capabilities in dual-satellite measurement and navigation receivers by providing a communication method between the onboard receiver's DSPs based on EDMA and McBSP. By utilizing the EDMA and McBSP functions of the DSP chip, the complexity of the dual-satellite measurement and navigation receiver interface hardware design is reduced. Simultaneously, the use of EDMA significantly reduces the CPU time consumed by communication on the receiver's DSP chip, thereby improving the service processing capabilities of the dual-satellite measurement and navigation receiver. Furthermore, it reduces software complexity while ensuring reliability.

[0016] This invention provides a communication method between DSPs of a satellite receiver based on EDMA and McBSP. The satellite receiver is a dual-satellite measurement receiver, including DSP1 and DSP2. Real-time data communication is achieved by using only the McBSP interface of DSP1 and DSP2 controlled by EDMA, without the need for CPU to manage data reception and transmission. The McBSP interface is a multi-channel buffered serial port. When communicating between DSPs of the onboard receiver, only the main loop and timer interrupts are used in a dual-threaded manner. Full-duplex communication between McBSP interfaces is achieved by querying the EDMA event completion flag in the timer interrupt service routine. When the timer interrupt is triggered, the execution of the main loop program is interrupted by the DSP timer interrupt and enters the interrupt service routine to trigger the EDMA receive and transmit. After the interrupt routine finishes execution, it returns to the interrupt point of the main loop program to continue the execution of the main loop. EDMA's receive and transmit triggers use an event-triggered mode that combines event triggering and CPU triggering. When there is a program to be received or a program to be transmitted and the last receive or transmit time has been completed, the EDMA transmit interrupt or receive interrupt is cleared, and a CPU-triggered EDMA is started to execute data transmission and / or reception between DSP1 and DSP2. EDMA event completion flags include a transmission completion flag and a reception completion flag.

[0017] The present invention provides a preferred method for communication between DSPs of a spaceborne receiver based on EDMA and McBSP, comprising the following steps: S1. Initialize the McBSP interface transceiver channels of DSP1 and DSP2, configure the EDMA channel entry parameters PaRAM, event enable register EER, channel interrupt pending register CIPR and event setting register ESR corresponding to the transceiver channels of DSP1 and DSP2, and start the first data reception and data transmission. S2. Configure the DSP timer interrupt period and enable the DSP timer interrupt; S3, Enter the loop body step; Step S3 includes the following steps: S31. Determine if there is data to be sent. If yes, proceed to step S32; otherwise, proceed to step S38. S32. Pack the data to be sent and determine whether the previous sending was completed based on the sending completion flag. If yes, proceed to step S33; otherwise, proceed to step S38. S33. Disable DSP timer interrupts; S34. Clear the EDMA transmit interrupt by sending a 1 to the CIPR register channel bit; S35. Configure the EDMA transmission channel entry parameter PaRAM according to the transmission requirements; S36. Initiate a CPU-triggered EDMA transmission by sending a 1 to the channel bit of the ESR register; S37. Enable DSP timer interrupt; S38. Determine whether the previous reception was completed based on the reception completion flag. If yes, proceed to step S39; otherwise, return to step S31. S39. Update the in pointer of the receive circular buffer; S3a, Disable DSP timer interrupts; S3b: Clear the EDMA receive interrupt by writing 1 to the receive channel bit of the CIPR register; S3c. Configure the EDMA receive channel entry parameter PaRAM according to the reception requirements; S3d: By writing 1 to the receive channel bit of the ESR register, a CPU-triggered EDMA receive is initiated. S3e. Based on the current reception requirements, reconfigure the EDMA receive channel entry parameter PaRAM; S3f: Enable DSP timer interrupt; S3g: Execute the business processing within the main loop and return to step S31.

[0018] The present invention discloses a communication method between satellite receiver DSPs based on EDMA and McBSP. In a preferred embodiment, step S1 of the McBSP interface transceiver channel initialization includes: McBSP0 pin configuration, McBSP receive / transmit configuration, and sampling rate generator configuration. Then, the sampling rate generator, frame synchronization signal generator, and transceiver are enabled sequentially through the serial port control register.

[0019] In the preferred embodiment of the communication method between DSPs of a spaceborne receiver based on EDMA and McBSP, the McBSP0 pins are configured such that the transmit / receive related pins operate in non-GPIO mode, the transmit frame synchronization signal and clock signal are generated internally, the receive frame synchronization signal and clock signal are provided externally, the transmit and receive frame synchronization pulses are active high, the transmit data is driven on the rising edge of the transmit clock, and the receive data is sampled on the rising edge of the receive clock.

[0020] The present invention discloses a communication method between satellite receiver DSPs based on EDMA and McBSP. In a preferred embodiment, when the McBSP is configured to receive / transmit, it receives / transmits 32-bit data in a single phase, receiving one word per phase; the data is not compressed, the most significant bit is transmitted first, there is a 1-bit data delay, and unexpected receive / transmit frame synchronization pulses are ignored.

[0021] In the preferred embodiment of the communication method between DSPs of a spaceborne receiver based on EDMA and McBSP described in this invention, the sampling rate generator clock is a 2-division of the internal clock.

[0022] The present invention discloses a communication method between DSPs of a spaceborne receiver based on EDMA and McBSP. In a preferred embodiment, when configuring the DSP1 / DSP2 transmission channels, the data synchronization method is Element synchronization. Element is a one-dimensional to one-dimensional data transmission of 32-bit data. The source address is incremented and the destination address is fixed. Channel 12 writes 1 to indicate enable. The enable indication includes enabling CPU trigger, enabling event trigger, and enabling transmission completion interrupt. One frame of data to be transmitted from DSP1 contains 512 element data, and one frame of data to be transmitted from DSP2 contains 1024 element data. When configuring the DSP1 / DSP2 receiving channels, the data synchronization method is Element synchronization. Element is a one-to-one data transmission of 32-bit data. The source address is fixed and the destination address is incremented. Channel 13 writes 1 to indicate enable. One frame of data to be received by DSP1 contains 1024 elements, while one frame of data to be received by DSP2 contains 512 elements.

[0023] In the preferred embodiment of the communication method between satellite receiver DSPs based on EDMA and McBSP described in this invention, in steps S34 and S3b, the CIPRx identifier is used to send a channel bit of 1 to the CIPR register. In steps S36 and S3d, the channel bit is written to the ESR register using the ESRx identifier.

[0024] In the preferred embodiment of the communication method between DSPs of a spaceborne receiver based on EDMA and McBSP described in this invention, the DSP timer interrupt period is 500 microseconds.

[0025] The present invention discloses a communication method between satellite receivers and DSPs based on EDMA and McBSP. As a preferred embodiment, the satellite receiver can receive signals from 72 channels at 6 frequency points (6 frequencies, L1C / A and L2P of GPS and B1I, B3I, B1C, and B2a of BDS), perform message parsing, pseudorange and carrier phase calculation, navigation calculation, real-time orbit determination, inter-satellite relative positioning, and external communication.

[0026] This invention relates to embedded EDMA communication, and is applicable to various embedded devices that implement full-duplex communication between DSPs using C64x series DSP chips based on TEXAS INSTRUMENTS.

[0027] The present invention has the following advantages: (1) This invention utilizes EDMA to control real-time data communication between DSPs via the McBSP interface, eliminating the need for CPU to allocate sending and receiving, thereby ensuring that the DSP has sufficient time to complete business processing functions such as navigation message processing, observation calculation, positioning / orbit determination calculation, and real-time inter-satellite measurement processing. (2) The DSPs use a flexibly configurable multi-channel buffered serial port McBSP interface for communication, which reduces the complexity of hardware interface design while meeting the real-time data communication rate between DSPs. (3) Reasonable embedded software design, which realizes full-duplex communication of McBSP by querying the EDMA event completion flag in only one interrupt (timer interrupt), meets the real-time requirements of interface data communication while reducing software complexity; this method simplifies the hardware interface design of data communication between DSPs of various receiving boards in the current dual-star measurement receiver, the use of EDMA function greatly improves the efficiency of DSP use, improves the embedded software data receiving and transmitting design, and greatly improves the reliability and real-time performance of data transmission between DSPs of multi-system, multi-functional dual-star measurement receiver. Attached Figure Description

[0028] Figure 1 A flowchart illustrating the communication transmission and reception process for EDMA functionality based on a DSP. Figure 2 An EDMA interrupt flowchart for communication implementation based on DSP's EDMA function; Figure 3 This is a schematic diagram of the interface connection relationship between DSP chips in a spaceborne receiver DSP communication method based on EDMA and McBSP. Figure 4 A software workflow diagram for a communication method between spaceborne receiver DSPs based on EDMA and McBSP. Figure 5 This is an interrupt workflow diagram for a communication method between DSPs of an onboard receiver based on EDMA and McBSP. Figure 6 This is a time-sharing diagram of the main loop and the timer interrupt thread for a spaceborne receiver DSP communication method based on EDMA and McBSP. Figure 7 This is a timeline of the main loop and the timer interrupt thread when inter-DSP communication is not enabled. Detailed Implementation

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Example 1

[0030] like Figure 4 , Figure 5 As shown, a communication method between DSPs of a spaceborne receiver is proposed, based on EDMA and McBSP. This method is implemented using the TI Q-level DSP chip SMJ320C6415DGADW60, and the hardware connections are as follows: Figure 3 As shown, the software implementation uses a dual-threaded approach with a main loop and timer interrupts. The real-time communication processing flow between the DSP in the main loop and the interrupt is as follows: Figure 3 As shown. When the timer interrupt is enabled, the execution of the main loop program can be interrupted by the timer interrupt and enter the interrupt routine. After the interrupt routine finishes execution, the main loop program returns to continue execution.

[0031] The main loop includes the following steps: S1. Initialize the McBSP receive and transmit channels, configure the corresponding EDMA channel entry parameters PaRAM, event enable register EER, channel interrupt suspension register CIPR and event setting register ESR, and proceed to step (2) after starting the first receive and transmit. McBSP0 initialization includes the following steps: 1) McBSP0 Pin Configuration: The receive / transmit related pins operate in non-GPIO mode. The transmit frame synchronization signal and clock signal are generated internally, while the receive frame synchronization signal and clock signal are provided externally. The transmit / receive frame synchronization pulse is active high. Transmit data is driven on the rising edge of the transmit clock, and receive data is sampled on the rising edge of the receive clock.

[0032] 2) McBSP Receive / Transmit Configuration: Single-phase 32-bit data reception / transmission, one word is received per phase. Data is not compressed, most significant bit is transmitted first, 1-bit data delay, and unexpected receive / transmit frame synchronization pulses are ignored.

[0033] 3) Sampling rate generator configuration: The sampling rate generator clock is a division of the internal clock by 2.

[0034] 4) Enable the sampling rate generator, frame synchronization signal generator, and transceiver sequentially through the serial port control register.

[0035] Next, initialize the EDMA channel, which includes the following two steps: 1) DSP1 / DSP2 Transmit Channel Configuration:

[0036] 2) DSP1 / DSP2 Receiver Channel Configuration

[0037] S2. Configure the DSP timer interrupt period to 500 microseconds. After enabling the interrupt, proceed to the loop body steps: S31. Determine if there is data to be sent. If there is, proceed to step S32; otherwise, proceed to step S38. S32. Determine the sending completion flag and whether the previous sending was completed. If completed, proceed to step S33; otherwise, proceed to step S38. S33. Disable DSP timer interrupt and proceed to step S34; S34. Clear the EDMA transmit interrupt by writing 1 to the channel bit (identified by CIPRx) in the CIPR register, and proceed to step S35. S35. Configure the EDMA transmission channel entry parameter PaRAM according to the transmission requirements, and proceed to step S36. S36. By sending a 1 to the channel bit (identified by ESRx) in the ESR register, a CPU-triggered EDMA transmission is initiated, and the process proceeds to step S37. S37. Enable DSP timer interrupt and proceed to step S38; S38. Determine the reception completion flag and whether the previous reception was completed. If completed, proceed to step S39; otherwise, proceed to step S31. S39. Update the in pointer of the receive circular buffer and proceed to step S3a; S3a. Disable DSP timer interrupt and proceed to step S3b; S3b: Clear the EDMA receive interrupt by writing 1 to the receive channel bit (identified by CIPRr) in the CIPR register, and proceed to step S3c; S3c. Configure the EDMA receive channel entry parameter PaRAM according to the receiving requirements, and proceed to step S3d. S3d: By writing 1 to the receive channel bit (identified by ESRr) in the ESR register, the CPU triggers EDMA reception once, and proceeds to step S3e; S3e. Based on the current reception requirements, reconfigure the EDMA receive channel entry parameter PaRAM and proceed to step S3f. S3f: Enable DSP timer interrupt and proceed to step S3g; S3g, Execute the business processing within the main loop, and proceed to step S31; The interrupt procedure includes the following steps: Sb1: Read CIPRr to update the receive completion flag, then proceed to step Sb2; Sb2, Read the CIPRx update send completion flag, proceed to step Sb3; Sb3. After the business processing task within the interrupt is completed, exit the interrupt service routine and return to the interrupt point of the main program.

[0038] The dual-satellite measurement and navigation receiver based on this invention realizes complex functions such as receiving signals from 72 channels across 6 frequency points (GPS L1C / A, L2P, BDS B1I, B3I, B1C, B2a), message parsing, pseudorange and carrier phase calculation, navigation calculation, real-time orbit determination, inter-satellite relative positioning, and external communication. The execution time margin for the main loop thread and timer interrupt thread is tight. Actual testing shows that after adopting this invention, all receiver functions normally, data communication is continuous, and inter-DSP communication does not incur additional overhead on the execution time of the main loop thread and timer interrupt thread. The execution time diagrams of the main loop and timer interrupt thread with and without inter-DSP communication are shown below. Figure 6 and Figure 7 The statistical results are shown in the table below.

[0039]

[0040] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A communication method between DSPs of a spaceborne receiver based on EDMA and McBSP, characterized in that: The onboard receiver is a dual-satellite measurement receiver, consisting of DSP1 and DSP2; Real-time data communication is achieved by using only the McBSP interface of DSP1 and DSP2 controlled by EDMA, without the need for CPU to allocate data reception and transmission. The McBSP interface is a multi-channel buffered serial port. When communicating between the spaceborne receiver DSPs, only the main loop and timer interrupts are used in a dual-threaded manner. Full-duplex communication between the McBSP interfaces is carried out by querying the EDMA event completion flag in the timer interrupt service routine. When the timer interrupt is triggered, the execution of the main loop program is interrupted by the DSP timer interrupt and enters the interrupt service routine to trigger the EDMA receive and transmit. After the interrupt routine finishes execution, it returns to the interrupt point of the main loop program to continue the execution of the main loop. EDMA's receive and transmit triggers use an event-triggered mode that combines event triggering and CPU triggering. When there is a program to be received or a program to be sent and the previous receive or send event is completed, the EDMA transmit interrupt or receive interrupt is cleared, and a CPU-triggered EDMA is started to execute data transmission and / or reception between DSP1 and DSP2. The EDMA event completion flags include a transmission completion flag and a reception completion flag.

2. The communication method between spaceborne receiver DSPs based on EDMA and McBSP according to claim 1, characterized in that: Includes the following steps: S1. Initialize the McBSP interface transceiver channels of DSP1 and DSP2, configure the EDMA channel entry parameters PaRAM, event enable register EER, channel interrupt pending register CIPR and event setting register ESR corresponding to the transceiver channels of DSP1 and DSP2, and start the first data reception and data transmission. S2. Configure the DSP timer interrupt period and enable the DSP timer interrupt; S3, Enter the loop body step; Step S3 includes the following steps: S31. Determine if there is data to be sent. If yes, proceed to step S32; otherwise, proceed to step S38. S32. Pack the data to be sent and determine whether the previous sending was completed according to the sending completion flag. If yes, proceed to step S33; otherwise, proceed to step S38. S33. Disable DSP timer interrupts; S34. Clear the EDMA transmit interrupt by sending a 1 to the CIPR register channel bit; S35. Configure the EDMA transmission channel entry parameter PaRAM according to the transmission requirements; S36. Initiate a CPU-triggered EDMA transmission by sending a 1 to the channel bit of the ESR register; S37. Enable DSP timer interrupt; S38. Determine whether the previous reception was completed based on the reception completion flag. If yes, proceed to step S39; otherwise, return to step S31. S39. Update the in pointer of the receive circular buffer; S3a, Disable DSP timer interrupts; S3b: Clear the EDMA receive interrupt by writing 1 to the receive channel bit of the CIPR register; S3c. Configure the EDMA receive channel entry parameter PaRAM according to the reception requirements; S3d: By writing 1 to the receive channel bit of the ESR register, a CPU-triggered EDMA receive is initiated. S3e. Based on the current reception requirements, reconfigure the EDMA receive channel entry parameter PaRAM; S3f: Enable DSP timer interrupt; S3g: Execute the business processing within the main loop and return to step S31.

3. The communication method between satellite receiver DSPs based on EDMA and McBSP according to claim 2, characterized in that: In step S1, the initialization of the McBSP interface transceiver channel includes: McBSP0 pin configuration, McBSP receive / transmit configuration, sampling rate generator configuration, and then the sampling rate generator, frame synchronization signal generator and transceiver are enabled sequentially through the serial port control register.

4. The communication method between satellite receiver DSPs based on EDMA and McBSP according to claim 3, characterized in that: When configuring the McBSP0 pins, the receive / transmit related pins operate in non-GPIO mode. The transmit frame synchronization signal and clock signal are generated internally, while the receive frame synchronization signal and clock signal are provided externally. The transmit and receive frame synchronization pulses are active high. The transmit data is driven on the rising edge of the transmit clock, and the receive data is sampled on the rising edge of the receive clock.

5. The communication method between satellite receiver DSPs based on EDMA and McBSP according to claim 3, characterized in that: When McBSP is configured to receive / transmit, it receives / transmits single-phase 32-bit data, receiving one word per phase; the data is not compressed, the most significant bit is transmitted first, there is a 1-bit data delay, and unexpected receive / transmit frame synchronization pulses are ignored.

6. The communication method between spaceborne receiver DSPs based on EDMA and McBSP according to claim 3, characterized in that: The sampling rate generator clock is a 2-fold division of the internal clock.

7. The communication method between satellite receiver DSPs based on EDMA and McBSP according to claim 2, characterized in that: When configuring the DSP1 / DSP2 transmission channels, the data synchronization method is Element synchronization. Element is a one-to-one data transmission of 32-bit data. The source address is incremented and the destination address is fixed. Channel 12 write 1 indicator is enabled. The indicator enable includes enabling CPU trigger, enabling event trigger, and enabling transmission completion interrupt. One frame of data to be transmitted from DSP1 contains 512 element data, and one frame of data to be transmitted from DSP2 contains 1024 element data. When configuring the DSP1 / DSP2 receiving channels, the data synchronization method is Element synchronization. Element is a one-to-one data transmission of 32-bit data. The source address is fixed and the destination address is incremented. Channel 13 writes 1 to enable the indication. One frame of data to be received by DSP1 contains 1024 elements, while one frame of data to be received by DSP2 contains 512 elements.

8. The communication method between satellite receiver DSPs based on EDMA and McBSP according to claim 2, characterized in that: In steps S34 and S3b, the CIPRx identifier is used to send a 1 to the channel bit of the CIPR register; In steps S36 and S3d, the channel bit is written to the ESR register using the ESRx identifier.

9. The communication method between satellite receiver DSPs based on EDMA and McBSP according to claim 2, characterized in that: The DSP timer interrupt cycle is 500 microseconds.

10. The communication method between satellite receiver DSPs based on EDMA and McBSP according to claim 1, characterized in that: The satellite receiver can receive signals from 72 channels across 6 frequency points (GPS L1C / A, L2P, BDS B1I, B3I, B1C, B2a), perform message parsing, pseudorange and carrier phase calculation, navigation calculation, real-time orbit determination, inter-satellite relative positioning, and external communication.

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