FDSOI NMOS source drain structure and manufacturing method thereof
By designing a gradient-up source-drain structure in FDSOI NMOS, and utilizing double-layer epitaxy and stress memory film, the problem of stress memory technology being difficult to apply to the channel was solved, thereby improving electron mobility, reducing leakage current, and optimizing device performance.
Patent Information
- Application Number
- CN202511577188.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-02-06
AI Technical Summary
In existing FDSOI technology, it is difficult to improve the performance of NMOS devices, especially because stress memory technology is difficult to apply effectively to the channel, resulting in insufficient electron mobility.
A gradient-raised source-drain structure design is adopted, and a double-layer epitaxial structure is formed through two epitaxys. The region near the channel is a pure silicon epitaxial layer, and the region away from the channel is a phosphorus-doped epitaxial silicon layer. A stress memory film layer is formed on the latter to increase the contact area and distance between the stress memory film layer and the channel.
This significantly improves the electron mobility of FDSOI NMOS, reduces leakage current issues, and optimizes the overall performance of the device.
Smart Images
Figure CN121487322A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and in particular to an FDSOI NMOS source-drain structure and its manufacturing method. Background Technology
[0002] FDSOI (Fully Depletion Silicon on Insulator) technology is an advanced semiconductor manufacturing technique. Its core structural feature is the presence of an ultra-thin insulating layer above the substrate, commonly known as a buried oxide layer (BOX). A very thin silicon film is used to fabricate the transistor channel. Because the channel is extremely thin, no channel doping process is required, and the depletion layer can fill the entire channel region, thus forming a fully depletion transistor, such as... Figure 1 As shown. Structurally, FD-SOI transistors exhibit superior electrostatic characteristics compared to traditional bulk silicon technology. The buried oxide layer significantly reduces parasitic capacitance between the source and drain, and effectively suppresses electron flow from the source to the drain, thereby drastically reducing leakage current that leads to performance degradation. Furthermore, FD-SOI offers numerous unique advantages, including back-side bias capability, excellent transistor matching characteristics, the ability to operate at near-threshold low supply voltages, ultra-low sensitivity to radiation, and very high intrinsic transistor operating speed. These advantages enable its application in millimeter-wave bands and other fields.
[0003] Despite the numerous advantages of FDSOI technology, several challenges remain in performance optimization. Due to the thin silicon layer in FDSOI, traditional ion implantation methods struggle to effectively adjust and optimize its performance, primarily relying on material manipulation. Currently, in FDSOI devices, PMOS typically uses a germanium-silicon channel (SiGe channel), achieving stable performance improvements; while NMOS uses a silicon phosphorus channel (SiP channel) to enhance performance, but due to the poor stability of SiP, achieving stable channel performance improvements is difficult. Furthermore, FDSOI employs raised source / drain to reduce resistance, such as... Figure 2 As shown, the source / drain and gate are very close in height, which makes it difficult for traditional stress-improvement engineering (such as stress memory technology for NMOS) films to be directly applied to the channel, thus failing to achieve the same effect as bulk silicon MOSFETs. Therefore, how to improve the performance of NMOS in FDSOI has always been a problem that needs to be continuously explored. Summary of the Invention
[0004] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0005] The technical problem to be solved by the present invention is to provide an FDSOI NMOS source-drain structure and its manufacturing method that can provide more tensile stress, improve the electron mobility in the channel, and improve the device performance compared with the prior art.
[0006] To solve the above-mentioned technical problems, the FDSOI NMOS source-drain structure provided by the present invention is formed as a raised source-drain structure with a gradient increasing outward from both sides of the gate structure.
[0007] Preferably, the FDSOI NMOS source-drain structure is further improved such that the distance between the stress memory film layer and the channel is the minimum distance allowed by the current process.
[0008] To solve the above technical problems, the present invention provides a method for manufacturing an FDSOI NMOS source-drain structure, comprising the following steps:
[0009] S1, using existing technology to manufacture the FDSOI NMOS gate structure;
[0010] S2, form the first sidewall and trim its shape, retaining only the first sidewall of the preset thickness on both sides of the grid structure;
[0011] S3, form the second sidewall and refine its shape;
[0012] S4, the first extension, the first increase in the height of the source and drain structure;
[0013] S5, remove the second side wall;
[0014] S6, second extension, second elevation of source-drain structure height;
[0015] S7, forming the third sidewall and refining its shape;
[0016] S8 forms a stress memory film layer.
[0017] Preferably, the FDSOI NMOS source-drain structure manufacturing method is further improved by first epitaxial pure silicon.
[0018] Preferably, the FDSOI NMOS source / drain structure manufacturing method is further improved by a second phosphorus-doped epitaxial silicon.
[0019] Preferably, in the further improved FDSOI NMOS source-drain structure manufacturing method, the height of the source-drain structure is raised by the first epitaxial growth to H, and the height of the source-drain structure is raised by the second epitaxial growth to h, where h < H.
[0020] Preferably, in a further improved method for manufacturing the FDSOI NMOS source-drain structure, the first sidewall is formed using silicon carbonitride.
[0021] Preferably, in a further improved method for manufacturing the FDSOI NMOS source-drain structure, the second sidewall is formed using silicon oxide.
[0022] Preferably, in a further improved method for manufacturing the FDSOI NMOS source-drain structure, the third sidewall is formed using silicon nitride.
[0023] Preferably, in a further improved method for manufacturing the FDSOI NMOS source-drain structure, the stress memory film layer is formed using silicon oxide and silicon nitride.
[0024] The working principle of this invention is explained below;
[0025] This invention utilizes a two-stage epitaxial source / drain process to create a gradient-driven source / drain. The region near the channel employs a double-layer epitaxy: a lower silicon epitaxial layer and an upper phosphorus-doped epitaxial silicon layer. The source / drain region further from the channel uses a fully phosphorus-doped epitaxial silicon film. This structural design allows the stress memory film to be positioned closer to the channel and provides a longer film length, thereby providing more tensile stress to the FDSOI NMOS. Tensile stress increases electron mobility in the channel, thus improving the performance of the FDSOI NMOS. Simultaneously, the pure silicon epitaxial layer near the channel effectively blocks phosphorus diffusion, preventing leakage current issues.
[0026] This invention can achieve at least the following technical effects;
[0027] 1. Improved device performance: Due to the gradient source-drain structure design, the stress memory film layer of the present invention is closer to the channel and the film layer length is increased. By increasing the contact area and distance between the stress memory film layer and the channel, more tensile stress is provided, so that the tensile stress can act on the channel more effectively, improve electron mobility, and significantly improve the performance of FDSOI NMOS.
[0028] 2. Reduced device leakage current: The double-layer epitaxial structure near the channel in this invention effectively blocks the diffusion of phosphorus doping in the lower pure silicon epitaxial layer, avoiding leakage current problems, while the upper phosphorus-doped epitaxial silicon layer provides excellent electrical performance.
[0029] 3. Optimize device stress: This invention achieves a gradient-lifted source-drain structure through a two-stage source-drain lifting process, which allows the stress memory film layer to function better, while reducing resistance and improving overall performance. Attached Figure Description
[0030] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
[0031] Figure 1 This is a schematic diagram of a fully depleted transistor structure.
[0032] Figure 2 This is a schematic diagram of an existing FDSOI NMOS structure.
[0033] Figure 3 This is a schematic diagram of the FDSOI NMOS source-drain structure of the present invention.
[0034] Figure 4 This is a schematic diagram of the manufacturing method of the present invention.
[0035] Figure 5 This is a schematic diagram of the intermediate mechanism in the manufacturing method of the present invention. Figure 1 .
[0036] Figure 6 This is a schematic diagram of the intermediate mechanism in the manufacturing method of the present invention. Figure 2 .
[0037] Figure 7 This is a schematic diagram of the intermediate mechanism in the manufacturing method of the present invention. Figure 3 .
[0038] Figure 8 This is a schematic diagram of the intermediate mechanism in the manufacturing method of the present invention. Figure 4 .
[0039] Figure 9 This is a schematic diagram of the intermediate mechanism in the manufacturing method of the present invention. Figure 5 .
[0040] Figure 10 This is a schematic diagram of the intermediate mechanism in the manufacturing method of the present invention. Figure 6 . Detailed Implementation
[0041] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.
[0042] First embodiment;
[0043] refer to Figure 3 As shown, the present invention provides an FDSOI NMOS source-drain structure, which is formed as a raised source-drain structure with a gradient increasing outward from both sides of the gate structure.
[0044] A further improvement to the first embodiment is that the distance between the stress memory film layer and the channel is the minimum distance allowed by the current process.
[0045] Second embodiment;
[0046] refer to Figure 4 As shown, the present invention provides a method for manufacturing an FDSOI NMOS source-drain structure, comprising the following steps:
[0047] S1, using existing technology to manufacture the FDSOI NMOS gate structure;
[0048] S2, using carbon-nitrogen-oxide-silicon to form the first sidewall, the first sidewall covers the gate structure and the bulk silicon region, then the morphology is modified, retaining only the first sidewalls on both sides of the gate structure with a predetermined thickness, ranging from 8 nm to 15 nm, with an optimal thickness of 10 nm, as referenced. Figure 5 As shown;
[0049] S3, using silicon oxide to form the second sidewall, after morphology modification, exposes the silicon in the two bulk regions on both sides of the gate structure, reference. Figure 6 As shown;
[0050] S4, first epitaxial silicon, first increase in source / drain structure height, reference. Figure 7 As shown;
[0051] S5, remove the second side wall;
[0052] S6, second phosphorus-doped silicon epitaxial growth, second increase in source / drain structure height, reference. Figure 8 As shown;
[0053] S7 uses silicon nitride to form the third sidewalls and modifies their shape, retaining only the third sidewalls on both sides of the grid structure, as shown in the reference. Figure 9 As shown, there is a gap between the third sidewall and the second epitaxial phosphorus-doped silicon on both sides in the horizontal direction. A stress memory film layer will be formed in this gap, which extends the length of the stress memory film layer.
[0054] S8 uses silicon oxide + silicon nitride to form a stress memory film layer, reference. Figure 10 As shown;
[0055] The height of the source-drain structure is H for the first epitaxial lift and h for the second epitaxial lift, where h < H.
[0056] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.
[0057] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. An FDSOI NMOS source-drain structure, characterized in that: It is formed as a raised source-drain structure with a gradient that extends outward from both sides of the gate structure.
2. The FDSOI NMOS source / drain structure as described in claim 1, characterized in that: The distance between its stress memory film layer and the channel is the minimum distance allowed by the current process.
3. A method for manufacturing an FDSOI NMOS source / drain structure, characterized in that, Includes the following steps: S1, using existing technology to manufacture the FDSOI NMOS gate structure; S2, form the first sidewall and trim its shape, retaining only the first sidewall of the preset thickness on both sides of the grid structure; S3, form the second sidewall and refine its shape; S4, the first extension, the first increase in the height of the source and drain structure; S5, remove the second side wall; S6, second extension, second elevation of source-drain structure height; S7, forming the third sidewall and refining its shape; S8 forms a stress memory film layer.
4. The method for manufacturing the FDSOI NMOS source / drain structure as described in claim 3, characterized in that: The first epitaxial pure silicon.
5. The method for manufacturing the FDSOI NMOS source / drain structure as described in claim 4, characterized in that: Second phosphorus-doped epitaxial silicon.
6. The method for manufacturing the FDSOI NMOS source / drain structure as described in claim 3, characterized in that: The height of the source-drain structure is H during the first epitaxial lift, and the height of the source-drain structure is h during the second epitaxial lift, where h < H.
7. The method for manufacturing the FDSOI NMOS source / drain structure as described in claim 3, characterized in that: The first sidewall is made of carbon nitride silicon oxide.
8. The method for manufacturing the FDSOI NMOS source / drain structure as described in claim 3, characterized in that: The second sidewall is made of silicon dioxide.
9. The method for manufacturing the FDSOI NMOS source / drain structure as described in claim 3, characterized in that: The third sidewall is made of silicon nitride.
10. The method for manufacturing the FDSOI NMOS source / drain structure as described in claim 3, characterized in that: The stress memory film is formed using silicon oxide and silicon nitride.