Semiconductor device

Abstract

A semiconductor device includes: a substrate; a first active pattern and a second active pattern, the first active pattern and the second active pattern being spaced apart, a second width of the second active pattern being greater than a first width of the first active pattern; a first plurality of nanosheets stacked on the first active pattern and spaced apart from each other; a second plurality of nanosheets stacked on the second active pattern and spaced apart from each other, the second plurality of nanosheets having a second width greater than the first width of the first plurality of nanosheets; a gate electrode surrounding the first plurality of nanosheets and the second plurality of nanosheets; first internal spacers located on both sidewalls of the gate electrode between adjacent first plurality of nanosheets; and a second internal spacer on both sidewalls of the gate electrode between adjacent second plurality of nanosheets, the second internal spacer having a thickness less than a thickness of the first internal spacer.

Description

Technical Field

[0001] Various exemplary embodiments of this disclosure relate to semiconductor devices. Specifically, this disclosure relates to devices including MBCFETs. TM Semiconductor devices (multi-bridge channel field-effect transistors). Background Technology

[0002] As one of the scaling technologies to increase the density of integrated circuit devices, multi-gate transistors have been proposed. Fin-shaped or nanowire-shaped silicon bodies are formed on the substrate of the multi-gate transistor, and gates are formed on the surface of the silicon bodies.

[0003] Because these multi-gate transistors utilize three-dimensional channels, they are easily scalable. Furthermore, current control capabilities can be improved without increasing the gate length of the multi-gate transistor. Additionally, the short-channel effect (SCE), where the channel region potential is affected by the drain voltage, can be effectively suppressed. Summary of the Invention

[0004] This disclosure provides a semiconductor device that improves reliability by forming internal spacers formed on NMOS (N-type metal-oxide-semiconductor) transistors and internal spacers formed on PMOS (P-channel metal-oxide-semiconductor) transistors with different widths.

[0005] The aspects of this disclosure are not limited to those mentioned herein, and those skilled in the art will clearly understand from the following description another aspect not mentioned.

[0006] According to some embodiments of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate; a first active pattern extending on the substrate along a first horizontal direction; a second active pattern extending on the substrate along the first horizontal direction and spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction, the second active pattern having a second width in the second horizontal direction greater than a first width of the first active pattern in the second horizontal direction; a first plurality of nanosheets, each of the first plurality of nanosheets stacked in a vertical direction and spaced apart from each other on the first active pattern; and a second plurality of nanosheets, each of the second plurality of nanosheets stacked in a vertical direction and spaced apart from each other on the second active pattern, each of the second plurality of nanosheets in the second horizontal direction... The upward second width is greater than the first width of each of the first plurality of nanosheets in the second horizontal direction; the gate electrode extends along the second horizontal direction on the first active pattern and the second active pattern, the gate electrode extends around each of the first plurality of nanosheets and the second plurality of nanosheets, the gate electrode has two sidewalls; the first internal spacer is disposed between adjacent nanosheets of the first plurality of nanosheets on both of the two sidewalls of the gate electrode in the first horizontal direction; and the second internal spacer is disposed between adjacent nanosheets of the second plurality of nanosheets on both of the two sidewalls of the gate electrode in the first horizontal direction, the second thickness of the second internal spacer in the first horizontal direction is less than the first thickness of the first internal spacer in the first horizontal direction.

[0007] According to some embodiments of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate; a first active pattern extending on the substrate along a first horizontal direction; a second active pattern extending on the substrate along the first horizontal direction and spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction; a first plurality of nanosheets, each of the first plurality of nanosheets stacked vertically on the first active pattern and spaced apart from each other, each of the first plurality of nanosheets having two sidewalls; a second plurality of nanosheets, each of the second plurality of nanosheets stacked vertically on the second active pattern and spaced apart from each other, each of the second plurality of nanosheets having a second width in the second horizontal direction greater than the first width of each of the first plurality of nanosheets in the second horizontal direction, each of the second plurality of nanosheets having two sidewalls; and a gate electrode. Extending along a second horizontal direction on a first active pattern and a second active pattern, surrounding each of the first plurality of nanosheets and each of the second plurality of nanosheets, and having two sidewalls; a first source / drain region, the first source / drain region contacting both of the two sidewalls of each of the first plurality of nanosheets in the first horizontal direction on the first active pattern; a second source / drain region, the second source / drain region contacting both of the two sidewalls of each of the second plurality of nanosheets in the first horizontal direction on the second active pattern; a first internal spacer, the first internal spacer disposed between the gate electrode and the first source / drain region; and a second internal spacer, the second internal spacer disposed between the gate electrode and the second source / drain region, wherein a first portion of the first internal spacer overlaps with the second internal spacer in the second horizontal direction, and a second portion of the first internal spacer does not overlap with the second internal spacer in the second horizontal direction.

[0008] According to some embodiments of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate; a first active pattern extending on the substrate along a first horizontal direction; a second active pattern extending on the substrate along the first horizontal direction and spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction, the second width of the second active pattern in the second horizontal direction being greater than the first width of the first active pattern in the second horizontal direction; and a first plurality of nanosheets, each of the first plurality of nanosheets being stacked in a vertical direction on the first active pattern and spaced apart from each other, each of the first plurality of nanosheets having two sidewalls; A second plurality of nanosheets, each nanosheet stacked vertically and spaced apart from each other on a second active pattern, each nanosheet having a second width in a second horizontal direction greater than the first width in a second horizontal direction of each of the first plurality of nanosheets, and each nanosheet having two sidewalls; a gate electrode extending along a second horizontal direction on both the first and second active patterns, surrounding each of the first and second plurality of nanosheets; and a first source / drain region on the first active pattern and adjacent to the first plurality of nanosheets. Each nanosheet in the second active pattern is in contact with two of its two sidewalls in the first horizontal direction; a second source / drain region is in contact with two of the two sidewalls of each nanosheet in the second plurality of nanosheets in the first horizontal direction; a first internal spacer is disposed between the gate electrode and the first source / drain region; a second internal spacer is disposed between the gate electrode and the second source / drain region, the second thickness of the second internal spacer in the first horizontal direction is less than the first thickness of the first internal spacer in the first horizontal direction, and the second width of the second internal spacer in the second horizontal direction is greater than the second width of the first internal spacer in the second horizontal direction. A first width in the horizontal direction; and gate spacers, the gate spacers being disposed on both the first upper surface of the uppermost nanosheet and the second upper surface of the uppermost nanosheet in the first plurality of nanosheets on both sidewalls of the gate electrode in the first horizontal direction, wherein a first thickness of the first internal spacer and a second thickness of the second internal spacer in the first horizontal direction are each less than the thickness of the gate spacer in the first horizontal direction, and wherein a first portion of the first internal spacer overlaps with the second internal spacer in the second horizontal direction, and a second portion of the first internal spacer does not overlap with the second internal spacer in the second horizontal direction. Attached Figure Description

[0009] The above and other aspects and features of this disclosure will become clearer from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which: Figure 1 It is a layout diagram used to illustrate some exemplary embodiments of a semiconductor device according to this disclosure; Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'; Figure 3 It is along Figure 1 A cross-sectional view taken from line B-B'; Figure 4 It is along Figure 1 A cross-sectional view taken from line C-C'; Figures 5 to 22 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure; Figure 23 It is a layout diagram used to illustrate some exemplary embodiments of a semiconductor device according to this disclosure; Figure 24 It is along Figure 23 A cross-sectional view taken from line D-D'; Figure 25 It is along Figure 23 A cross-sectional view taken from line E-E'; Figure 26 It is a layout diagram used to illustrate some other exemplary embodiments of a semiconductor device according to this disclosure; Figure 27 It is along Figure 26 A cross-sectional view taken by line F-F'; Figure 28 It is along Figure 26 A cross-sectional view taken from line G-G'; Figure 29 It is a layout diagram used to illustrate a semiconductor device according to another exemplary embodiment of the present disclosure; Figure 30 It is along Figure 29 A cross-sectional view taken by line H-H'; Figure 31 It is along Figure 29 A cross-sectional view taken from line I-I'; Figure 32 It is a layout diagram used to illustrate a semiconductor device according to another exemplary embodiment of the present disclosure; Figure 33 It is along Figure 32 The cross-sectional view taken by line J-J'; and Figure 34 It is along Figure 32 The cross-sectional view taken by line K-K'. Detailed Implementation

[0010] In the following text, reference will be made to Figures 1 to 34 This disclosure describes semiconductor devices according to some exemplary embodiments.

[0011] This invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments described herein. These exemplary embodiments are merely examples, and various implementations and variations are possible, which need not be detailed herein. This disclosure provides details of alternative examples, but such a list of alternatives is not exhaustive.

[0012] Terms described in the singular form herein may be provided in the plural form, as can be seen, for example, in the accompanying figures. Therefore, unless the context otherwise indicates, the description of a single term provided in the plural form should be understood to apply to the remaining multiple terms.

[0013] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it should be understood that, unless the context otherwise indicates, the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with other elements to form the component.

[0014] For ease of description, this document may use spatial relative terms, such as “above,” “bottom,” “vertical,” and “horizontal,” to describe positional relationships, as shown, for example, in the accompanying figures. It should be understood that spatial relative terms also include different orientations in addition to those depicted in the figures.

[0015] Numbers such as "first," "second," and "third" can simply be used as labels to distinguish certain elements, steps, etc., from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific number (e.g., "first") in a particular claim may be described with a different number (e.g., "second") elsewhere in the specification or another claim.

[0016] As used herein, the terms “surround,” “surrounding,” and “surrounded” are intended to mean that one element is outside another element. These elements may or may not be in contact. A surrounding element may surround an inner element or may not completely surround the inner element. However, a surrounding element does not need to completely enclose the inner element. As used herein, the term “adjacent” can be used to mean that one element is close to another element. The two elements do not need to be in contact or in direct contact with each other. As used herein, the terms “on,” “above,” “cover,” or “overlap” are intended to mean that one element is on or next to another element. These elements may or may not be in contact. For example, there may be layers on top of each other between layers. An element “on” another element, or “above” another element, or “stacked” on another element, or “covered” another element, or “overlapped” with another element does not need to cover the entire top surface of the underlying element in order to be considered “on”, or “above”, or “stacked” on, or “covered” by, or “overlapped” with. These terms are intended to cover an element “on” all or any part of the element below it, or “above” all or any part of the element below it, or “stacked” on all or any part of the element below it, or “covering” all or any part of the element below it, or “overlapping” all or any part of the element below it.

[0017] Figure 1 This is a layout diagram used to illustrate a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 3 It is along Figure 1 The cross-sectional view taken by line B-B'. Figure 4 It is along Figure 1 The cross-sectional view taken from line C-C'.

[0018] Semiconductor devices can be semiconductor chips (i.e., semiconductor dies that are monolithized from wafers, such as those cut from wafers).

[0019] refer to Figures 1 to 4A semiconductor device according to some exemplary embodiments of the present disclosure includes a substrate 100, a first active pattern 101 and a second active pattern 102, a field insulating layer 105, a first plurality of nanosheets NW1 and a second plurality of nanosheets NW2, a gate electrode G1, a gate spacer 111, a gate insulating layer 112, a cover pattern 113, a first source / drain region SD1 and a second source / drain region SD2, a first internal spacer 121 and a second internal spacer 122, a first etch stop layer 130, a first interlayer insulating layer 140, a gate contact CB, a second etch stop layer 150, a second interlayer insulating layer 160, and a path V1.

[0020] Substrate 100 may be a silicon substrate or SOI (silicon-on-insulator). Alternatively, substrate 100 may include silicon germanium, SGOI (silicon-germanium-on-insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but this disclosure is not limited thereto. In the following, each of the first horizontal direction DR1 and the second horizontal direction DR2 may be defined as a direction parallel to the upper surface of substrate 100. The second horizontal direction DR2 may be defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 may be defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. The vertical direction DR3 may be defined as a direction perpendicular to the upper surface of substrate 100.

[0021] Each of the first active pattern 101 and the second active pattern 102 may extend along a first horizontal direction DR1 on the upper surface of the substrate 100. The second active pattern 102 may be spaced apart from the first active pattern 101 in a second horizontal direction DR2. In some examples, the second width AW2 of the second active pattern 102 in the second horizontal direction DR2 may be greater than the first width AW1 of the first active pattern 101 in the second horizontal direction DR2. Each of the first active pattern 101 and the second active pattern 102 may protrude from the upper surface of the substrate 100 in a vertical direction DR3. In some examples, each of the first active pattern 101 and the second active pattern 102 may be a portion of the substrate 100, or may include an epitaxial layer grown from the substrate 100.

[0022] A field insulating layer 105 may be disposed on the upper surface of the substrate 100. The field insulating layer 105 may surround the sidewalls of each of the first active pattern 101 and the second active pattern 102. In some examples, the upper surface of each of the first active pattern 101 and the second active pattern 102 may protrude beyond the upper surface of the field insulating layer 105 in the vertical direction DR3. However, this disclosure is not limited thereto. In some exemplary embodiments, the upper surface of each of the first active pattern 101 and the second active pattern 102 may be formed on the same plane as the upper surface of the field insulating layer 105. The field insulating layer 105 may include, for example, an oxide layer, a nitride layer, an oxide oxynitride layer, or a combination thereof.

[0023] A first plurality of nanosheets NW1 may be disposed on a first active pattern 101. The first plurality of nanosheets NW1 may include a plurality of nanosheets stacked and spaced apart from each other in the vertical direction DR3 on the first active pattern 101. A second plurality of nanosheets NW2 may be disposed on a second active pattern 102. The second plurality of nanosheets NW2 may be spaced apart from the first plurality of nanosheets NW1 in the second horizontal direction DR2. In some examples, the second width W2 of the second plurality of nanosheets NW2 in the second horizontal direction DR2 may be greater than the first width W1 of the first plurality of nanosheets NW1 in the second horizontal direction DR2. The second plurality of nanosheets NW2 may include a plurality of nanosheets stacked and spaced apart from each other in the vertical direction DR3 on the second active pattern 102. In some examples, each nanosheet included in the second plurality of nanosheets NW2 may be disposed at the same vertical height as each nanosheet included in the first plurality of nanosheets NW1.

[0024] exist Figures 2 to 4 In this embodiment, each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 is shown as comprising three nanosheets stacked and spaced apart from each other in a vertical direction DR3, but this is for illustrative purposes and the present disclosure is not limited thereto. In some other exemplary embodiments, each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 may comprise four or more nanosheets stacked and spaced apart from each other in a vertical direction DR3. In some examples, each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 may comprise silicon (Si). However, the present disclosure is not limited thereto. In some other exemplary embodiments, each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 may be silicon germanium (SiGe).

[0025] The gate electrode G1 may extend along a second horizontal direction DR2 over the first active pattern 101, the second active pattern 102, and the field insulating layer 105. The gate electrode G1 may surround a first plurality of nanosheets NW1 and a second plurality of nanosheets NW2, and optionally surround one or more additional nanosheets provided herein. In some examples, the width of the gate electrode G1 in the first horizontal direction DR1 between the uppermost surface of the second active pattern 102 and the bottom surface of the lowermost nanosheet of the second plurality of nanosheets NW2 may be larger than the width of the gate electrode G1 in the first horizontal direction DR1 between the uppermost surface of the first active pattern 101 and the bottom surface of the lowermost nanosheet of the first plurality of nanosheets NW1. Furthermore, the width of the gate electrode G1 between adjacent second plurality of nanosheets NW2 in the first horizontal direction DR1 may be larger than the width of the gate electrode G1 between adjacent first plurality of nanosheets NW1 in the first horizontal direction DR1.

[0026] In some examples, the gate electrode G1 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (TaCN). The gate electrode G1 may include at least one or a combination of the following: tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), and vanadium (V). The gate electrode G1 may include conductive metal oxides, conductive metal nitrides, etc., and may include oxide forms of the aforementioned materials.

[0027] The gate electrode G1 may include, for example, two sidewalls. A gate spacer 111 may be disposed on the upper surfaces of the uppermost nanosheets of each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2, and on the upper surface of the field insulating layer 105, on both of the two sidewalls of the gate electrode G1 in the first horizontal direction DR1. The gate spacer 111 may extend along the two sidewalls of the gate electrode G1 in the first horizontal direction DR1 in the second horizontal direction DR2. In some examples, the gate spacer 111 may contact the upper surfaces of the uppermost nanosheets of each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2. In some examples, the gate spacer 111 may include at least one or a combination of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride oxynitride (SiOBN), and silicon oxycarbonate (SiOC). However, this disclosure is not limited thereto.

[0028] A first source / drain region SD1 may be disposed on the first active pattern 101 on both of the two sidewalls of the gate electrode G1 in the first horizontal direction DR1. In some examples, the first plurality of nanosheets NW1 may include two sidewalls for each nanosheet in the first plurality of nanosheets NW1, and the first source / drain region SD1 may be in contact with both of the two sidewalls of each nanosheet in the first plurality of nanosheets NW1 in the first horizontal direction DR1. A second source / drain region SD2 may be disposed on the second active pattern 102 on both of the two sidewalls of the gate electrode G1 in the first horizontal direction DR1. In some examples, the second plurality of nanosheets NW2 may include two sidewalls for each nanosheet in the second plurality of nanosheets NW2, and the second source / drain region SD2 may be in contact with both of the two sidewalls of each nanosheet in the second plurality of nanosheets NW2 in the first horizontal direction DR1.

[0029] In some examples, the upper surface of the first source / drain region SD1 may be formed higher than the upper surface of the uppermost nanosheet in the first plurality of nanosheets NW1. Additionally, the upper surface of the second source / drain region SD2 may be formed higher than the upper surface of the uppermost nanosheet in the second plurality of nanosheets NW2. Although not shown, the second source / drain region SD2 may be spaced apart from the first source / drain region SD1 in the second horizontal direction DR2. In some examples, the second width of the second source / drain region SD2 in the second horizontal direction DR2 may be greater than the first width of the first source / drain region SD1 in the second horizontal direction DR2.

[0030] In some exemplary embodiments, the first plurality of nanosheets NW1, the gate electrode G1, and the first source / drain region SD1 can form an NMOS transistor. Additionally, the second plurality of nanosheets NW2, the gate electrode G1, and the second source / drain region SD2 can form a PMOS transistor. In some other exemplary embodiments, the first plurality of nanosheets NW1, the gate electrode G1, and the first source / drain region SD1 can form a PMOS transistor. Additionally, the second plurality of nanosheets NW2, the gate electrode G1, and the second source / drain region SD2 can form an NMOS transistor.

[0031] The first internal spacer 121 may be disposed between the gate electrode G1 and the first source / drain region SD1. In some examples, the first internal spacer 121 may be in contact with the first source / drain region SD1. The first internal spacer 121 may be disposed between the uppermost surface of the first active pattern 101 and the bottom surface of the lowermost nanosheet among the first plurality of nanosheets NW1 on both sides of the two sidewalls of the gate electrode G1 in the first horizontal direction DR1. The first internal spacer 121 may be disposed between adjacent first plurality of nanosheets NW1 on both sides of the two sidewalls of the gate electrode G1 in the first horizontal direction DR1.

[0032] In some examples, the sidewall of the first internal spacer 121 facing the gate electrode G1 in the first horizontal direction DR1 can be recessed toward the first source / drain region SD1. Figure 2 The diagram shows the sidewall of the first internal spacer 121 in contact with the first source / drain region SD1 in the first horizontal direction DR1 aligned with the sidewall of the first plurality of nanosheets NW1 in the first horizontal direction DR1, but this disclosure is not limited thereto. In some other exemplary embodiments, the sidewall of the first internal spacer 121 in contact with the first source / drain region SD1 in the first horizontal direction DR1 may be formed recessed toward the gate electrode G1.

[0033] The second internal spacer 122 may be disposed between the gate electrode G1 and the second source / drain region SD2. In some examples, the second internal spacer 122 may be in contact with the second source / drain region SD2. The second internal spacer 122 may be disposed between the uppermost surface of the second active pattern 102 and the bottom surface of the lowermost nanosheet in the second plurality of nanosheets NW2, on both sides of the two sidewalls of the gate electrode G1 in the first horizontal direction DR1. The second internal spacer 122 may be disposed between the two sidewalls of the gate electrode G1 in the first horizontal direction DR1 between adjacent first plurality of nanosheets NW2.

[0034] In some examples, the second internal spacer 122 may be recessed toward the second source / drain region SD2 on the sidewall facing the gate electrode G1 in the first horizontal direction DR1. Figure 3The diagram shows the sidewall of the second internal spacer 122 in contact with the second source / drain region SD2 in the first horizontal direction DR1 aligned with the sidewall of the second plurality of nanosheets NW2 in the first horizontal direction DR1, but this disclosure is not limited thereto. In some other exemplary embodiments, the sidewall of the second internal spacer 122 in contact with the second source / drain region SD2 in the first horizontal direction DR1 may be formed recessed toward the gate electrode G1.

[0035] In some examples, the first thickness t2 of the first internal spacer 121 in the first horizontal direction DR1 may be less than the thickness t1 of the gate spacer 111 disposed on one side of the gate electrode G1 in the first horizontal direction DR1. In some examples, the second thickness t3 of the second internal spacer 122 in the first horizontal direction DR1 may be less than the thickness t1 of the gate spacer 111 disposed on one side of the gate electrode G1 in the first horizontal direction DR1. In some examples, the second thickness t3 of the second internal spacer 122 in the first horizontal direction DR1 may be less than the first thickness t2 of the first internal spacer 121 in the first horizontal direction DR1. In some examples, the second width of the second internal spacer 122 in the second horizontal direction DR2 may be greater than the first width of the first internal spacer 121 in the second horizontal direction DR2.

[0036] In some examples, there may be multiple first internal spacers, and multiple second internal spacers. In some examples, the second width between the second internal spacers 122 in the first horizontal direction DR1 may be greater than the first width between the first internal spacers 121 in the first horizontal direction DR1. In some examples, the first portion of the first internal spacer 121 may overlap with the second internal spacer 122 in the second horizontal direction DR2. In some examples, the second portion of the first internal spacer 121 may not overlap with the second internal spacer 122 in the second horizontal direction DR2. This is because the second thickness t3 of the second internal spacer 122 in the first horizontal direction DR1 is less than the first thickness t2 of the first internal spacer 121 in the first horizontal direction DR1. In some examples, each of the first internal spacer 121 and the second internal spacer 122 may include at least one or a combination of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride oxynitride (SiOBN), and silicon oxycarbonate (SiOC). However, this disclosure is not limited thereto.

[0037] A gate insulating layer 112 may be disposed between the gate electrode G1 and the gate spacer 111. A gate insulating layer 112 may be disposed between the gate electrode G1 and the first active pattern 101. A gate insulating layer 112 may be disposed between the gate electrode G1 and the second active pattern 102. A gate insulating layer 112 may be disposed between the gate electrode G1 and the field insulating layer 105. A gate insulating layer 112 may be disposed between the gate electrode G1 and the first plurality of nanosheets NW1. A gate insulating layer 112 may be disposed between the gate electrode G1 and the second plurality of nanosheets NW2. A gate insulating layer 112 may be disposed between the gate electrode G1 and the first internal spacer 121. A gate insulating layer 112 may be disposed between the gate electrode G1 and the second internal spacer 122. In some examples, the gate insulating layer 112 may contact each of the first internal spacer 121 and the second internal spacer 122. In some examples, the gate insulating layer 112 may be spaced apart from each of the first source / drain region SD1 and the second source / drain region SD2 on the first horizontal direction DR1.

[0038] In some examples, the gate insulating layer 112 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high-k dielectric material with a dielectric constant greater than that of silicon oxide. The high-k dielectric material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0039] Semiconductor devices according to some exemplary embodiments may include NC (negative capacitance) FETs utilizing negative capacitors. In some examples, gate insulating layer 112 may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties.

[0040] Ferroelectric material layers can have negative capacitance, while paraelectric material layers can have positive capacitance. In some examples, the total capacitance decreases when two or more capacitors are connected in series and each of their capacitances is positive, compared to the capacitance of each individual capacitor. On the other hand, the total capacitance can be positive and can be greater than the absolute value of each individual capacitor when at least one of the capacitances of the two or more capacitors connected in series has a negative value.

[0041] When a ferroelectric material layer with negative capacitance and a paraelectric material layer with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric materials can be increased. By utilizing the increase in total capacitance, a transistor including a ferroelectric material layer can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0042] The ferroelectric material layer can possess ferroelectric properties. The ferroelectric material layer can include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, or lead zirconium titanium oxide. As another example, hafnium zirconium oxide can be a material in which zirconium (Zr) is doped into hafnium oxide. In yet another example, hafnium zirconium oxide can be a compound of hafnium (Hf) and zirconium (Zr) with oxygen (O).

[0043] The ferroelectric material layer may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn). The type of dopants included in the ferroelectric material layer may vary depending on the specific ferroelectric material included in the ferroelectric material layer.

[0044] When the ferroelectric material layer includes hafnium oxide, the dopants included in the ferroelectric material layer may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) or yttrium (Y).

[0045] When the dopant is aluminum (Al), the ferroelectric material layer may include 3 at% to 8 at% (atomic %) aluminum. Here, the percentage of dopant can be the ratio of aluminum to the sum of hafnium and aluminum.

[0046] When the dopant is silicon (Si), the ferroelectric material layer may include 2 at% to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may include 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may include 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may include 50 at% to 80 at% zirconium.

[0047] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include at least one of, for example, silicon oxide or a high-k metal oxide. The metal oxide included in the paraelectric material layer may include, for example, at least one of, hafnium oxide, zirconium oxide, or aluminum oxide, but is not limited thereto.

[0048] The ferroelectric and paraelectric material layers can comprise the same material. The ferroelectric material layer may have ferroelectric properties, while the paraelectric material layer may not. In some examples, when both the ferroelectric and paraelectric material layers comprise hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric material layer differs from that in the paraelectric material layer.

[0049] The ferroelectric material layer can have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material layer can be, for example, from 0.5 nm to 10 nm, but is not limited to this. Since each ferroelectric material can have a different critical thickness to exhibit ferroelectric properties, the thickness of the ferroelectric material layer can vary depending on the specific ferroelectric material.

[0050] In some examples, gate insulating layer 112 may include a single ferroelectric material layer. In another example, gate insulating layer 112 may include multiple ferroelectric material layers spaced apart from each other. Gate insulating layer 112 may include a stacked layer structure in which multiple ferroelectric material layers and multiple paraelectric material layers are stacked alternately.

[0051] The first etch stop layer 130 may be disposed on the sidewall of the gate spacer 111 in the first horizontal direction DR1. The first etch stop layer 130 may be disposed on the upper surface of each of the first source / drain region SD1 and the second source / drain region SD2. Although not shown, the first etch stop layer 130 may be disposed on the upper surface of the field insulating layer 105. Furthermore, although not shown, the first etch stop layer 130 may be disposed on both sidewalls of the first source / drain region SD1 and the second source / drain region SD2 in the second horizontal direction DR2. In some examples, the first etch stop layer 130 may be conformally formed. The first etch stop layer 130 may, for example, comprise at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0052] The overlay pattern 113 may extend along a second horizontal direction DR2 over each of the gate spacer 111, the gate insulating layer 112, the gate electrode G1, and the first etch stop layer 130. In some examples, the bottom surface of the overlay pattern 113 may contact the first etch stop layer 130. However, this disclosure is not limited thereto. In some other exemplary embodiments, the sidewalls of the overlay pattern 113 may contact the first etch stop layer 130. The overlay pattern 113 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), or combinations thereof. However, this disclosure is not limited thereto.

[0053] A first interlayer insulating layer 140 may be disposed on the first etch stop layer 130. The first interlayer insulating layer 140 may surround the sidewalls of the cover pattern 113. In some examples, the upper surface of the first interlayer insulating layer 140 may be formed on the same plane as the upper surface of the cover pattern 113. The first interlayer insulating layer 140 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric materials. Low-k dielectric materials may include, for example, fluorinated tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetraethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilylborate (TMSB), diacyloxyditert-butoxysiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (toninsilazole), FSG (fluorosilicate glass), polyimide nanofoams (such as polypropylene oxide), CDO (carbon-doped silicon dioxide), OSG (organosilicon glass), SiLKTM, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof, but this disclosure is not limited thereto.

[0054] The gate contact CB can penetrate the cover pattern 113 in the vertical direction DR3 and connect to the gate electrode G1. Figure 4 In the illustration, the gate contact CB is shown disposed between the first active pattern 101 and the second active pattern 102, but this disclosure is not limited thereto. In some other exemplary embodiments, the gate contact CB may overlap with the first active pattern 101 or the second active pattern 102 in the vertical direction DR3. The gate contact CB may comprise a conductive material.

[0055] A second etch stop layer 150 may be disposed on the upper surface of each of the first interlayer insulating layer 140, the cover pattern 113, and the gate contact CB. Figures 2 to 4 In this embodiment, the second etch stop layer 150 is shown as a single layer, but this disclosure is not limited thereto. In some other exemplary embodiments, the second etch stop layer 150 may be formed as a multilayer. In some examples, the second etch stop layer 150 may be or include at least one of alumina, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0056] The second interlayer insulating layer 160 may be disposed on the second etch stop layer 150. The second interlayer insulating layer 160 may be or include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric materials. The passage V1 may penetrate the second interlayer insulating layer 160 and the second etch stop layer 150 in the vertical direction DR3 to connect to the gate contact CB. The passage V1 may be or include a conductive material.

[0057] In a semiconductor device according to some exemplary embodiments of the present disclosure, a plurality of first nanosheets NW1 and a plurality of second nanosheets NW2 spaced apart on a second horizontal direction DR2 can be surrounded by a gate electrode G1, wherein one of the first plurality of nanosheets NW1 and the plurality of second nanosheets NW2 can be used as a channel layer of an NMOS transistor, and the other of the first plurality of nanosheets NW1 and the plurality of second nanosheets NW2 can be used as a channel layer of a PMOS transistor. In a semiconductor device according to some exemplary embodiments of the present disclosure, the second width W2 of the second plurality of nanosheets NW2 on the second horizontal direction DR2 can be greater than the first width W1 of the first plurality of nanosheets NW1 on the second horizontal direction DR2, and the second thickness t3 of the second internal spacer 122 on the first horizontal direction DR1 can be less than the first thickness t2 of the first internal spacer 121 on the first horizontal direction DR1. In a semiconductor device according to some exemplary embodiments of the present disclosure, the first thickness t2 and the second thickness t3 of the first internal spacer 121 and the second internal spacer 122 disposed on the NMOS transistor and the PMOS transistor can be formed differently, which can improve the reliability of the semiconductor device.

[0058] In the following text, reference will be made to Figures 2 to 22 A method for manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure is described.

[0059] Figures 5 to 22 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure.

[0060] refer to Figures 5 to 7 A stacked structure 10 can be formed on a substrate 100. The stacked structure 10 may include a sacrificial layer 11 and a semiconductor layer 12 alternately stacked on the substrate 100. In some examples, the sacrificial layer 11 may be formed at the bottom of the stacked structure 10, and the semiconductor layer 12 may be formed at the top of the stacked structure 10. However, this disclosure is not limited thereto. In some other exemplary embodiments, the sacrificial layer 11 may also be formed at the top of the stacked structure 10. The sacrificial layer 11 may be, for example, silicon germanium (SiGe). The sacrificial layer 12 may be, for example, silicon (Si).

[0061] Subsequently, a portion of the stacked structure 10 may be etched. Simultaneously with etching the stacked structure 10, a portion of the substrate 100 may also be etched. This etching process defines each of a first active pattern 101 and a second active pattern 102 below the stacked structure 10 on the upper surface of the substrate 100. Each of the first active pattern 101 and the second active pattern 102 may extend along a first horizontal direction DR1. The second active pattern 102 may be spaced apart from the first active pattern 101 along a second horizontal direction DR2. In some examples, the second width of the second active pattern 102 along the second horizontal direction DR2 may be greater than the first width of the first active pattern 101 along the second horizontal direction DR2.

[0062] Subsequently, a field insulating layer 105 may be formed on the upper surface of the substrate 100. The field insulating layer 105 may surround the sidewalls of each of the first active pattern 101 and the second active pattern 102. In some examples, the upper surfaces of each of the first active pattern 101 and the second active pattern 102 may be formed higher than the upper surface of the field insulating layer 105. Subsequently, a pad oxide layer 20 may be formed to cover the upper surface of the field insulating layer 105, the exposed sidewalls of each of the first active pattern 101 and the second active pattern 102, and the sidewalls and upper surface of the stacked structure 10. In some examples, the pad oxide layer 20 may be formed conformally. The pad oxide layer 20 may be, for example, silicon oxide (SiO2).

[0063] refer to Figures 8 to 10 A dummy gate DG and a dummy overlay pattern DC extending along the second horizontal direction DR2 can be formed on the pad oxide layer 20 on the stacked structure 10 and the field insulating layer 105. The dummy overlay pattern DC can be disposed on the dummy gate DG. While the dummy gate DG and the dummy overlay pattern DC are being formed, the remaining pad oxide layer 20 on the substrate 100, except for the portion that overlaps with the dummy gate DG in the vertical direction DR3, can be removed.

[0064] Subsequently, a spacer material layer SM can be formed to cover the sidewalls of the dummy gate DG, the sidewalls and top surface of the dummy cover pattern DC, the exposed sidewalls and top surface of the stacked structure 10, and the top surface of the field insulating layer 105. In some examples, the spacer material layer SM can be formed conformally. The spacer material layer SM can be or include at least one or a combination of silicon nitride (SiN), silicon carbonitride oxynitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON).

[0065] refer to Figures 11 to 13 The stacked structure 10 can be etched using a dummy gate (DG) and a dummy overlay pattern (DC) as a mask (see [link]). Figure 8 and Figure 9 To form a first source / drain trench ST1 and a second source / drain trench ST2. In some examples, the first source / drain trench ST1 may be formed on a first active pattern 101. The second source / drain trench ST2 may be formed on a second active pattern 102. While forming each of the first source / drain trench ST1 and the second source / drain trench ST2, a spacer material layer SM (see [reference]) is formed on the upper surface of the dummy overlay pattern DC. Figure 8 and Figure 9 The portions of the ) and the portions of the dummy overlay pattern DC can be etched.

[0066] In some examples, after forming each of the first source / drain trench ST1 and the second source / drain trench ST2, a spacer material layer SM can be retained on the sidewalls of each of the dummy overlay pattern DC and the dummy gate DG (see [reference]). Figure 8 and Figure 9 The gate spacer 111 is defined as such. In some examples, after the formation of the first source / drain trench ST1, a semiconductor layer 12 remains below the dummy gate DG on the first active pattern 101 (see [reference]). Figure 8 The first plurality of nanosheets NW1 can be defined. Additionally, after forming the second source / drain trench ST2, a semiconductor layer 12 remains below the dummy gate DG on the second active pattern 102 (see...). Figure 9 It can be defined as a second or more nanosheets NW2.

[0067] refer to Figure 13 and Figure 14 It can be done in the first source / drain trench ST1 (see...) Figure 11 A first source / drain region SD1 is formed within the first active pattern 101. In some examples, the first source / drain region SD1 may contact both of the two sidewalls of each of the first plurality of nanosheets NW1 in the first horizontal direction DR1. Alternatively, the first source / drain region SD1 may contact the two sidewalls of the sacrificial layer 11 formed on the first active pattern 101 in the first horizontal direction DR1. A second source / drain trench ST2 (see...) can be formed within the first active pattern 101. Figure 12 A second source / drain region SD2 is formed within the active pattern 102. In some examples, the second source / drain region SD2 may contact both of the two sidewalls of each of the second plurality of nanosheets NW2 in the first horizontal direction DR1. Alternatively, the second source / drain region SD2 may contact the two sidewalls of the sacrificial layer 11 formed on the second active pattern 102 in the first horizontal direction DR1.

[0068] Subsequently, a first etch stop layer 130 may be formed on the surface of each of the first source / drain region SD1 and the second source / drain region SD2, as well as on the sidewall of the gate spacer 111. Although not shown, the first etch stop layer 130 may also be formed on the upper surface of the field insulating layer 105. In some examples, the first etch stop layer 130 may be formed conformally. Subsequently, a first interlayer insulating layer 140 may be formed on the first etch stop layer 130. Subsequently, the upper surface of the dummy gate DG may be exposed by a planarization process.

[0069] refer to Figures 15 to 17 This can be used for dummy gate DG (see Figure 13 and Figure 14 ), Pad oxide layer 20 (see Figure 13 and Figure 14 ) and sacrificial layer 11 (see Figure 13 and Figure 14 Each is etched individually. In some examples, a dummy gate DG (see...) Figure 13 and Figure 14 ), Pad oxide layer 20 (see Figure 13 and Figure 14 ) and sacrificial layer 11 (see Figure 13 and Figure 14 The portion of each of the removed elements in the first gate trench GT1 can be defined as the first gate trench GT1.

[0070] refer to Figure 18 and Figure 19 It can be in the first gate trench GT1 (see Figure 15 and Figure 16 A first internal spacer 121 is formed within the first gate trench GT1 to contact the first source / drain region SD1. Additionally, a first internal spacer 121 may be formed within the first gate trench GT1 (see [link to gate trench]). Figure 15 and Figure 16 A second internal spacer 122 is formed within the first gate trench GT1 to contact the second source / drain region SD2. In some examples, the second thickness t3 of the second internal spacer 122 on the first horizontal direction DR1 can be formed to be smaller than the first thickness t2 of the first internal spacer 121 on the first horizontal direction DR1. In some examples, within the first gate trench GT1 (see...), Figure 15 and 16 The remaining area, except for the portions forming the first internal spacer 121 and the second internal spacer 122, can be defined as the second gate trench GT2.

[0071] refer to Figures 20 to 22 It can be done in the second gate trench GT2 (see Figure 18 and Figure 19A gate insulating layer 112, a gate electrode G1, and a cover pattern 113 are sequentially formed within the structure. In some examples, the gate insulating layer 112 may contact the inner sidewalls of the first internal spacer 121 and the second internal spacer 122 in the first horizontal direction DR1.

[0072] refer to Figures 2 to 4 A gate contact CB can be formed that penetrates the cover pattern 113 in the vertical direction DR3 and connects to the gate electrode G1. Subsequently, a second etch stop layer 150 and a second interlayer insulating layer 160 can be sequentially formed on the upper surfaces of each of the first interlayer insulating layer 140, the cover pattern 113, and the gate contact CB. A path V1 can then be formed that penetrates the second interlayer insulating layer 160 and the second etch stop layer 150 in the vertical direction DR3 and connects to the gate contact CB. Through this manufacturing process, a fabrication can be completed. Figures 2 to 4 The semiconductor device shown.

[0073] refer to Figures 23 to 25 The following will describe semiconductor devices according to some other embodiments of the present disclosure. The description will focus on those related to... Figures 1 to 4 The differences shown are in the semiconductor devices.

[0074] Figure 23 This is a layout diagram used to illustrate a semiconductor device according to some other exemplary embodiments of the present disclosure. Figure 24 It is along Figure 23 The cross-sectional view taken by line D-D'. Figure 25 It is along Figure 23 The cross-sectional view taken from line E-E'.

[0075] Now for reference Figures 23 to 25 The semiconductor device according to some other exemplary embodiments of the present disclosure may include a third active pattern 203, a third plurality of nanosheets NW23, a third source / drain region SD23 and a third internal spacer 223.

[0076] In some examples, the third active pattern 203 may extend in the first horizontal direction DR1. In some examples, the third active pattern 203 may be spaced apart from the second active pattern 102 in the second horizontal direction DR2. The second active pattern 102 may be disposed between the first active pattern 101 and the third active pattern 203. The third active pattern 203 may protrude from the upper surface of the substrate 100 in the vertical direction DR3. In some examples, the third active pattern 203 may be part of the substrate 100, or may include an epitaxial layer grown from the substrate 100.

[0077] In some examples, the distance between the third active pattern 203 and the second active pattern 102 in the second horizontal direction DR2 may be the same as the distance between the first active pattern 101 and the second active pattern 102 in the second horizontal direction DR2. In some examples, the third width AW23 of the third active pattern 203 in the second horizontal direction DR2 may be smaller than the second width AW2 of the second active pattern 102 in the second horizontal direction DR2. In some examples, the third width AW23 of the third active pattern 203 in the second horizontal direction DR2 may be the same as the first width AW1 of the first active pattern 101 in the second horizontal direction DR2. The field insulating layer 205 may surround the sidewalls of each of the first to third active patterns 101, 102 and 203.

[0078] In some examples, the third plurality of nanosheets NW23 may include a plurality of nanosheets stacked and spaced apart from each other in the vertical direction DR3 on the third active pattern 203. The third plurality of nanosheets NW23 may be spaced apart from the second plurality of nanosheets NW2 in the second horizontal direction DR2. In some examples, the third width W23 of the third plurality of nanosheets NW23 in the second horizontal direction DR2 may be smaller than the second width W2 of the second plurality of nanosheets NW2 in the second horizontal direction DR2. In some examples, the third width W23 of the third plurality of nanosheets NW23 in the second horizontal direction DR2 may be the same as the first width W1 of the first plurality of nanosheets NW1 in the second horizontal direction DR2. In some examples, each nanosheet included in the third plurality of nanosheets NW23 may be set at the same vertical height as each nanosheet included in each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2.

[0079] In some examples, the gate electrode G2 may extend along a second horizontal direction DR2 on the first to third active patterns 101, 102, 203 and the field insulating layer 205. The gate electrode G2 may surround each of the plurality of first to third nanosheets NW1, NW2, NW3. In some examples, the gate spacer 211 may extend along the second horizontal direction DR2 on the upper surface of the uppermost nanosheet of each of the plurality of first to third nanosheets NW1, NW2, NW23 and on the upper surface of the field insulating layer 205, along the two sidewalls of the gate electrode G2 in the first horizontal direction DR1. In some examples, a third source / drain region SD23 may be disposed on both of the two sidewalls of the gate electrode G2 in the first horizontal direction DR1 on the third active pattern 203. The third source / drain region SD23 may contact both of the two sidewalls of each of the third plurality of nanosheets NW23 in the first horizontal direction DR1.

[0080] In some exemplary embodiments, a first plurality of nanosheets NW1, a gate electrode G2, and a first source / drain region SD1 can form an NMOS transistor; a second plurality of nanosheets NW2, a gate electrode G2, and a second source / drain region SD2 can form a PMOS transistor; and a third plurality of nanosheets NW23, a gate electrode G2, and a third source / drain region SD23 can form an NMOS transistor. In some other exemplary embodiments, the first plurality of nanosheets NW1, a gate electrode G2, and a first source / drain region SD1 can form a PMOS transistor; the second plurality of nanosheets NW2, a gate electrode G2, and a second source / drain region SD2 can form an NMOS transistor; and the third plurality of nanosheets NW23, a gate electrode G2, and a third source / drain region SD23 can form a PMOS transistor.

[0081] In some examples, a third internal spacer 223 may be disposed between the gate electrode G2 and the third source / drain region SD23. In some examples, the third internal spacer 223 may be in contact with the third source / drain region SD23. The third internal spacer 223 may be disposed on both sides of the two sidewalls of the gate electrode G2 in the first horizontal direction DR1 between the uppermost surface of the third active pattern 203 and the bottom surface of the lowermost nanosheet among the third plurality of nanosheets NW23. The third internal spacer 223 may be disposed on both sides of the two sidewalls of the gate electrode G2 in the first horizontal direction DR1 between adjacent third plurality of nanosheets NW23.

[0082] In some examples, the third thickness t24 of the third internal spacer 223 on the first horizontal direction DR1 may be less than the thickness t1 of the gate spacer 211 disposed on one side of the gate electrode G2 on the first horizontal direction DR1. The thickness t used in this specification refers to the thickness of each of the gate spacers (e.g., gate spacers 111, 211, or 311 on one side of the gate electrodes G1, G2, or G3) in different embodiments. In some examples, the third thickness t24 of the third internal spacer 223 on the first horizontal direction DR1 may be greater than the second thickness t3 of the second internal spacer 122 on the first horizontal direction DR1 (see...). Figure 3 In some examples, the third thickness t24 of the third internal spacer 223 on the first horizontal direction DR1 can be the same as the first thickness t2 of the first internal spacer 121 on the first horizontal direction DR1 (see [reference]). Figure 2 The same. In some examples, the third width of the third inner spacer 223 in the second horizontal direction DR2 may be less than the second width of the second inner spacer 122 in the second horizontal direction DR2. In some examples, the third width of the third inner spacer 223 in the second horizontal direction DR2 may be the same as the first width of the first inner spacer 121 in the second horizontal direction DR2.

[0083] In some examples, a first portion of the third internal spacer 223 may overlap with the second internal spacer 122 in the second horizontal direction DR2. In some examples, a second portion of the third internal spacer 223 may not overlap with the second internal spacer 122 in the second horizontal direction DR2. In some examples, the third internal spacer 223 may be made of the same material as each of the first internal spacer 121 and the second internal spacer 122. In some examples, a gate insulating layer 212 may be additionally disposed between the gate electrode G2 and the third active pattern 203. A gate insulating layer 212 may be additionally disposed between the gate electrode G2 and the third plurality of nanosheets NW23. A gate insulating layer 212 may be additionally disposed between the gate electrode G2 and the third internal spacer 223.

[0084] refer to Figures 26 to 28 The following will describe semiconductor devices according to some other exemplary embodiments of the present disclosure. The description will focus on those related to... Figures 1 to 4 The differences shown are in the semiconductor devices.

[0085] Figure 26 This is a layout diagram used to illustrate semiconductor devices according to other exemplary embodiments of this disclosure. Figure 27 It is along Figure 26 The cross-sectional view taken by line F-F'. Figure 28 It is along Figure 26 A cross-sectional view taken from line G-G'.

[0086] refer to Figures 26 to 28 The semiconductor device according to other exemplary embodiments of the present disclosure may include a fourth active pattern 303, a fourth plurality of nanosheets NW33, a fourth source / drain region SD33 and a fourth internal spacer 323.

[0087] In some examples, the fourth active pattern 303 may extend in the first horizontal direction DR1. In some examples, the fourth active pattern 303 may be spaced apart from the first active pattern 101 in the opposite direction to the second horizontal direction DR2. The first active pattern 101 may be disposed between the fourth active pattern 303 and the second active pattern 102. The fourth active pattern 303 may protrude from the upper surface of the substrate 100 in the vertical direction DR3. In some examples, the fourth active pattern 303 may be part of the substrate 100, or may include an epitaxial layer grown from the substrate 100.

[0088] In some examples, the distance between the fourth active pattern 303 and the first active pattern 102 in the second horizontal direction DR2 may be the same as the distance between the first active pattern 101 and the second active pattern 102 in the second horizontal direction DR2. In some examples, the fourth width AW33 of the fourth active pattern 303 in the second horizontal direction DR2 may be greater than the first width AW1 of the first active pattern 101 in the second horizontal direction DR2. In some examples, the fourth width AW33 of the fourth active pattern 303 in the second horizontal direction DR2 may be the same as the second width AW2 of the second active pattern 102 in the second horizontal direction DR2. The field insulating layer 305 may surround the sidewalls of each of the first active pattern 101, the second active pattern 102, and the fourth active pattern 303.

[0089] For example, a fourth plurality of nanosheets NW33 may include a plurality of nanosheets stacked and spaced apart from each other in the vertical direction DR3 on a fourth active pattern 303. The fourth plurality of nanosheets NW33 may be spaced apart from the first plurality of nanosheets NW1 in the opposite direction to the second horizontal direction DR2. In some examples, the fourth width AW33 of the fourth plurality of nanosheets NW33 in the second horizontal direction DR2 may be greater than the first width AW1 of the first plurality of nanosheets NW1 in the second horizontal direction DR2. In some examples, the fourth width AW33 of the fourth plurality of nanosheets NW33 in the second horizontal direction DR2 may be the same as the second width AW2 of the second plurality of nanosheets NW2 in the second horizontal direction DR2. In some examples, each nanosheet included in the fourth plurality of nanosheets NW33 may be set at the same vertical height as each nanosheet included in each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2.

[0090] In some examples, the gate electrode G3 may extend along a second horizontal direction DR2 on the first active pattern 101, the second active pattern 102, the third active pattern 303, and the field insulating layer 305. The gate electrode G3 may surround each of the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the fourth plurality of nanosheets NW33. In some examples, the gate spacer 311 may extend along both of the two sidewalls of the gate electrode G3 in the first horizontal direction DR1 on the upper surface of the uppermost nanosheet of each of the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the fourth plurality of nanosheets NW33 and on the upper surface of the field insulating layer 305 in the second horizontal direction DR2. In some examples, a fourth source / drain region SD33 may be disposed on the fourth active pattern 303 and located on both of the two sidewalls of the gate electrode G3 in the first horizontal direction DR1. The fourth source / drain region SD33 may contact both of the two sidewalls of each of the fourth plurality of nanosheets NW33 in the first horizontal direction DR1.

[0091] In some embodiments, a first plurality of nanosheets NW1, a gate electrode G3, and a first source / drain region SD1 form an NMOS transistor; a second plurality of nanosheets NW2, a gate electrode G3, and a second source / drain region SD2 can form a PMOS transistor; and a fourth plurality of nanosheets NW33, a gate electrode G3, and a fourth source / drain region SD33 can form an NMOS transistor. In some other exemplary embodiments, the first plurality of nanosheets NW1, a gate electrode G3, and a first source / drain region SD1 form a PMOS transistor; the second plurality of nanosheets NW2, a gate electrode G3, and a second source / drain region SD2 can form an NMOS transistor; and the fourth plurality of nanosheets NW33, a gate electrode G3, and a fourth source / drain region SD33 can form a PMOS transistor.

[0092] In some examples, a fourth internal spacer 323 may be disposed between the gate electrode G3 and the fourth source / drain region SD33. In some examples, the fourth internal spacer 323 may be in contact with the fourth source / drain region SD33. The fourth internal spacer 323 may be disposed on both sides of the two sidewalls of the gate electrode G3 in the first horizontal direction DR1 between the uppermost surface of the fourth active pattern 303 and the bottom surface of the lowermost nanosheet among the fourth plurality of nanosheets NW33. The fourth internal spacer 323 may be disposed on both sides of the two sidewalls of the gate electrode G3 in the first horizontal direction DR1 between adjacent fourth plurality of nanosheets NW33.

[0093] In some examples, the fourth thickness t34 of the fourth internal spacer 323 on the first horizontal direction DR1 can be less than the thickness t1 of the gate spacer 311 disposed on one side of the gate electrode G3 on the first horizontal direction DR1. In some examples, the fourth thickness t34 of the fourth internal spacer 323 on the first horizontal direction DR1 can be less than the first thickness t2 of the first internal spacer 121 on the first horizontal direction DR1 (see...). Figure 2 In some examples, the fourth thickness t34 of the fourth internal spacer 323 on the first horizontal direction DR1 can be the same as the second thickness t3 of the second internal spacer 122 on the first horizontal direction DR1 (see...). Figure 3 The same applies. In some examples, the fourth width of the fourth internal spacer 323 in the second horizontal direction DR2 may be greater than the first width of the first internal spacer 121 in the second horizontal direction DR2. In some examples, the fourth width of the fourth internal spacer 323 in the second horizontal direction DR2 may be the same as the second width of the second internal spacer 122 in the second horizontal direction DR2.

[0094] In some examples, a portion of the first internal spacer 121 may overlap with the fourth internal spacer 323 in the second horizontal direction DR2. In some examples, another portion of the first internal spacer 121 may not overlap with the fourth internal spacer 323 in the second horizontal direction DR2. In some examples, the fourth internal spacer 323 may be made of the same material as each of the first internal spacer 121 and the second internal spacer 122. In some examples, the gate insulating layer 312 may be additionally disposed between the gate electrode G3 and the fourth active pattern 303. The gate insulating layer 312 may be additionally disposed between the gate electrode G3 and the fourth plurality of nanosheets NW33. The gate insulating layer 312 may be additionally disposed between the gate electrode G3 and the fourth internal spacer 323.

[0095] In the following text, reference will be made to Figures 29 to 31 The description focuses on semiconductor devices according to some other embodiments of the present disclosure. Figures 1 to 4 The differences shown are in the semiconductor devices.

[0096] Figure 29 This is a layout diagram used to illustrate semiconductor devices according to other exemplary embodiments of this disclosure. Figure 30 It is along Figure 29 A cross-sectional view taken from line H-H'. Figure 31 It is along Figure 29 The cross-sectional view taken from line I-I'.

[0097] refer to Figures 29 to 31The semiconductor device according to some other exemplary embodiments of the present disclosure may include a fifth internal spacer 421, the fifth internal spacer 421 having a fifth thickness t42 in the first horizontal direction DR1 greater than the thickness t1 of the gate spacer 111 in the first horizontal direction DR1.

[0098] In some examples, the fifth thickness t42 of the fifth internal spacer 421 on the first horizontal direction DR1 can be greater than the sixth thickness t43 of the sixth internal spacer 422 on the first horizontal direction DR1. In some examples, the sixth thickness t43 of the sixth internal spacer 422 on the first horizontal direction DR1 can be less than the first thickness t1 of the gate spacer 111 on the first horizontal direction DR1.

[0099] In the following text, reference will be made to Figures 32 to 34 The description describes semiconductor devices according to some other exemplary embodiments of the present disclosure. The description will focus on those related to... Figures 1 to 4 The differences shown are in the semiconductor devices.

[0100] Figure 32 This is a layout diagram used to illustrate semiconductor devices according to other exemplary embodiments of this disclosure. Figure 33 It is along Figure 32 The cross-sectional view taken from line J-J'. Figure 34 It is along Figure 32 The cross-sectional view taken by line K-K'.

[0101] refer to Figures 32 to 34 The semiconductor device according to some other exemplary embodiments of the present disclosure may include a seventh internal spacer 522, the seventh internal spacer 522 having a seventh thickness t53 in the first horizontal direction DR1 greater than the thickness t1 of the gate spacer 111 in the first horizontal direction DR1.

[0102] In some examples, the eighth thickness t52 of the eighth internal spacer 521 on the first horizontal direction DR1 can be greater than the seventh thickness t53 of the seventh internal spacer 522 on the first horizontal direction DR1. In some examples, the eighth thickness t52 of the eighth internal spacer 521 on the first horizontal direction DR1 can be greater than the thickness t1 of the gate spacer 111 on the first horizontal direction DR1.

[0103] While exemplary embodiments according to the present disclosure have been described above with reference to the accompanying drawings, it should be understood that the present disclosure is not limited to the above embodiments and can be made in various different forms. Those skilled in the art will recognize that the present disclosure can be implemented in other specific forms without altering the technical concept or essential characteristics of the present disclosure. Therefore, it should be understood that the above embodiments are exemplary in all respects and not restrictive.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate; A first active pattern extends on the substrate along a first horizontal direction; The second active pattern extends on the substrate along the first horizontal direction and is spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction. The second width of the second active pattern in the second horizontal direction is greater than the first width of the first active pattern in the second horizontal direction. The first plurality of nanosheets, each of the first plurality of nanosheets being stacked in a vertical direction and spaced apart from each other on the first active pattern; The second plurality of nanosheets, each of the second plurality of nanosheets being stacked on the second active pattern in the vertical direction and spaced apart from each other, wherein the second width of each of the second plurality of nanosheets in the second horizontal direction is greater than the first width of each of the first plurality of nanosheets in the second horizontal direction; A gate electrode extending along a second horizontal direction on the first active pattern and the second active pattern, the gate electrode extending around each of the first plurality of nanosheets and each of the second plurality of nanosheets, the gate electrode having two sidewalls; A first internal spacer is disposed between adjacent nanosheets in the first plurality of nanosheets on both sides of the two sidewalls of the gate electrode in the first horizontal direction. as well as The second internal spacer is disposed between adjacent nanosheets in the second plurality of nanosheets on both sides of the two sidewalls of the gate electrode in the first horizontal direction, and the second thickness of the second internal spacer in the first horizontal direction is less than the first thickness of the first internal spacer in the first horizontal direction.

2. The semiconductor device according to claim 1, wherein, A portion of the first internal spacer overlaps with the second internal spacer in the second horizontal direction, and another portion of the first internal spacer does not overlap with the two internal spacers in the second horizontal direction.

3. The semiconductor device according to claim 1, wherein, The second width of the second internal spacer in the second horizontal direction is greater than the first width of the first internal spacer in the second horizontal direction.

4. The semiconductor device according to claim 1, wherein, The second width of the gate electrode between adjacent nanosheets in the first horizontal direction is greater than the first width of the gate electrode between adjacent nanosheets in the first horizontal direction.

5. The semiconductor device according to claim 1, wherein, The second internal spacer includes a plurality of second internal spacers, and the first internal spacer includes a plurality of first internal spacers, wherein the second width between the second internal spacers in the first horizontal direction is greater than the first width between the first internal spacers in the first horizontal direction.

6. The semiconductor device according to claim 1, further comprising: A gate spacer is disposed on both the first upper surface of the uppermost nanosheet of the first plurality of nanosheets and the second upper surface of the uppermost nanosheet of the second plurality of nanosheets on both sidewalls of the gate electrode in the first horizontal direction. Wherein, the second thickness of the second internal spacer in the first horizontal direction is less than the thickness of the gate spacer in the first horizontal direction.

7. The semiconductor device according to claim 1, further comprising: A gate spacer is disposed on both the first upper surface of the uppermost nanosheet of the first plurality of nanosheets and the second upper surface of the uppermost nanosheet of the second plurality of nanosheets on both sidewalls of the gate electrode in the first horizontal direction. Wherein, the first thickness of the first internal spacer in the first horizontal direction is less than the thickness of the gate spacer in the first horizontal direction.

8. The semiconductor device according to claim 1, wherein, The first plurality of nanosheets and the gate electrode form an NMOS transistor, and the second plurality of nanosheets and the gate electrode form a PMOS transistor.

9. The semiconductor device according to claim 1, further comprising: A third active pattern extends on the substrate along the first horizontal direction and is spaced apart from the second active pattern in the second horizontal direction. The third width of the third active pattern in the second horizontal direction is smaller than the second width of the second active pattern in the second horizontal direction. A third plurality of nanosheets, each of which is stacked on the third active pattern in the vertical direction and spaced apart from each other, wherein the third width of each of the third plurality of nanosheets in the second horizontal direction is smaller than the second width of each of the second plurality of nanosheets in the second horizontal direction, and the third plurality of nanosheets are surrounded by the gate electrode. as well as A third internal spacer is disposed between adjacent nanosheets in the third plurality of nanosheets on both sides of the two sidewalls of the gate electrode in the first horizontal direction, and the third thickness of the third internal spacer in the first horizontal direction is greater than the second thickness of the second internal spacer in the first horizontal direction.

10. The semiconductor device according to claim 9, wherein, The third width of the third active pattern in the second horizontal direction is the same as the first width of the first active pattern in the second horizontal direction. Wherein, the third width of each of the third plurality of nanosheets in the second horizontal direction is the same as the first width of each of the first plurality of nanosheets in the second horizontal direction, and Wherein, the third thickness of the third internal spacer in the first horizontal direction is the same as the first thickness of the first internal spacer in the first horizontal direction.

11. The semiconductor device according to claim 1, further comprising: A third active pattern extends on the substrate along the first horizontal direction and is spaced apart from the first active pattern in the opposite direction of the second horizontal direction. The third width of the third active pattern in the second horizontal direction is greater than the first width of the first active pattern in the second horizontal direction. A third plurality of nanosheets, each of which is stacked on the third active pattern in the vertical direction and spaced apart from each other, wherein the third width of each of the third plurality of nanosheets in the second horizontal direction is greater than the first width of each of the first plurality of nanosheets in the second horizontal direction, and the third plurality of nanosheets are surrounded by the gate electrode. as well as A third internal spacer is disposed between adjacent nanosheets in the third plurality of nanosheets on both sides of the two sidewalls of the gate electrode in the first horizontal direction, and the third thickness of the third internal spacer in the first horizontal direction is less than the first thickness of the first internal spacer in the first horizontal direction.

12. The semiconductor device according to claim 11, wherein, The third width of the third active pattern in the second horizontal direction is the same as the second width of the second active pattern in the second horizontal direction. Wherein, the third width of each of the third plurality of nanosheets in the second horizontal direction is the same as the second width of each of the second plurality of nanosheets in the second horizontal direction, and The third thickness of the third internal spacer in the first horizontal direction is the same as the second thickness of the second internal spacer in the first horizontal direction.

13. A semiconductor device, said semiconductor device comprising: Substrate; A first active pattern extends on the substrate along a first horizontal direction; The second active pattern extends on the substrate along the first horizontal direction and is spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction; The first plurality of nanosheets, each of the first plurality of nanosheets being stacked vertically and spaced apart from each other on the first active pattern, each of the first plurality of nanosheets having two sidewalls; The second plurality of nanosheets, each of the second plurality of nanosheets being stacked on the second active pattern in the vertical direction and spaced apart from each other, each of the second plurality of nanosheets having a second width in the second horizontal direction greater than the first width in the second horizontal direction of each of the first plurality of nanosheets, each of the second plurality of nanosheets having two sidewalls. A gate electrode extending along a second horizontal direction on the first active pattern and the second active pattern, the gate electrode surrounding each of the first plurality of nanosheets and each of the second plurality of nanosheets, the gate electrode having two sidewalls; The first source / drain region is in contact with both of the two sidewalls of each of the first plurality of nanosheets in the first horizontal direction on the first active pattern. The second source / drain region is in contact with both of the two sidewalls of each of the second plurality of nanosheets in the first horizontal direction on the second active pattern. A first internal spacer is disposed between the gate electrode and the first source / drain region; as well as A second internal spacer is disposed between the gate electrode and the second source / drain region. Wherein, a first portion of the first internal spacer overlaps with the second internal spacer in the second horizontal direction, and a second portion of the first internal spacer does not overlap with the two internal spacers in the second horizontal direction.

14. The semiconductor device according to claim 13, wherein, The second thickness of the second internal spacer in the first horizontal direction is less than the first thickness of the first internal spacer in the first horizontal direction.

15. The semiconductor device according to claim 13, wherein, The second width of the second source / drain region in the second horizontal direction is greater than the first width of the first source / drain region in the second horizontal direction.

16. The semiconductor device according to claim 13, wherein, The first plurality of nanosheets and the gate electrode form a PMOS transistor, and the second plurality of nanosheets and the gate electrode form an NMOS transistor.

17. The semiconductor device of claim 13, further comprising: A third active pattern extends on the substrate along the first horizontal direction and is spaced apart from the second active pattern in the second horizontal direction; A third plurality of nanosheets, each of which is stacked on the third active pattern in the vertical direction and spaced apart from each other, wherein the third width of each of the third plurality of nanosheets in the second horizontal direction is smaller than the second width of each of the second plurality of nanosheets in the second horizontal direction, each of the third plurality of nanosheets is surrounded by the gate electrode, and each of the third plurality of nanosheets has two sidewalls. The third source / drain region is in contact with both of the two sidewalls of each of the third plurality of nanosheets in the first horizontal direction on the third active pattern. as well as A third internal spacer is disposed between the gate electrode and the third source / drain region. Wherein, the first portion of the third internal spacer overlaps with the second internal spacer in the second horizontal direction, and the second portion of the third internal spacer does not overlap with the second internal spacer in the second horizontal direction.

18. The semiconductor device of claim 13, further comprising: A third active pattern extends on the substrate along the first horizontal direction and is spaced apart from the first active pattern in the opposite direction to the second horizontal direction. A third plurality of nanosheets, each of which is stacked on the third active pattern in the vertical direction and spaced apart from each other, wherein the third width of each of the third plurality of nanosheets in the second horizontal direction is greater than the first width of each of the first plurality of nanosheets in the second horizontal direction, each of the third plurality of nanosheets is surrounded by the gate electrode, and each of the third plurality of nanosheets has two sidewalls. The third source / drain region is in contact with both of the two sidewalls of each of the third plurality of nanosheets in the first horizontal direction on the third active pattern. as well as A third internal spacer is disposed between the gate electrode and the third source / drain region. Wherein, the third portion of the first internal spacer overlaps with the third internal spacer in the second horizontal direction, and the fourth portion of the first internal spacer does not overlap with the third internal spacer in the second horizontal direction.

19. The semiconductor device of claim 13, further comprising: A gate spacer is disposed on both the first upper surface of the uppermost nanosheet of the first plurality of nanosheets and the second upper surface of the uppermost nanosheet of the second plurality of nanosheets on both sidewalls of the gate electrode in the first horizontal direction. Wherein, the second thickness of the second internal spacer in the first horizontal direction is greater than the thickness of the gate spacer in the first horizontal direction.

20. A semiconductor device, the semiconductor device comprising: Substrate; A first active pattern extends on the substrate along a first horizontal direction; The second active pattern extends on the substrate along the first horizontal direction and is spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction. The second width of the second active pattern in the second horizontal direction is greater than the first width of the first active pattern in the second horizontal direction. The first plurality of nanosheets, each of the first plurality of nanosheets being stacked vertically and spaced apart from each other on the first active pattern, each of the first plurality of nanosheets having two sidewalls; The second plurality of nanosheets, each of the second plurality of nanosheets being stacked on the second active pattern in the vertical direction and spaced apart from each other, each of the second plurality of nanosheets having a second width in the second horizontal direction greater than the first width in the second horizontal direction of each of the first plurality of nanosheets, each of the second plurality of nanosheets having two sidewalls. A gate electrode extending along a second horizontal direction on the first active pattern and the second active pattern, the gate electrode surrounding each of the first plurality of nanosheets and each of the second plurality of nanosheets; The first source / drain region is in contact with both of the two sidewalls of each of the first plurality of nanosheets in the first horizontal direction on the first active pattern. The second source / drain region is in contact with both of the two sidewalls of each of the second plurality of nanosheets in the first horizontal direction on the second active pattern. A first internal spacer is disposed between the gate electrode and the first source / drain region; The second internal spacer is disposed between the gate electrode and the second source / drain region. The second thickness of the second internal spacer in the first horizontal direction is less than the first thickness of the first internal spacer in the first horizontal direction, and the second width of the second internal spacer in the second horizontal direction is greater than the first width of the first internal spacer in the second horizontal direction. as well as A gate spacer is disposed on both the first upper surface of the uppermost nanosheet of the first plurality of nanosheets and the second upper surface of the uppermost nanosheet of the second plurality of nanosheets on both sidewalls of the gate electrode in the first horizontal direction. Wherein, the first thickness of the first internal spacer in the first horizontal direction and the second thickness of the second internal spacer in the first horizontal direction are each smaller than the thickness of the gate spacer in the first horizontal direction, and Wherein, a first portion of the first internal spacer overlaps with the second internal spacer in the second horizontal direction, and a second portion of the first internal spacer does not overlap with the second internal spacer in the second horizontal direction.

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