Overlay mark and overlay measurement method of semiconductor structure

Abstract

The invention discloses an overlay mark and an overlay measurement method of a semiconductor structure, the overlay mark comprises four sub-marks which jointly form the overlay mark, each sub-mark comprises a substrate, an inner area and an outer area are defined, a plurality of first mandrel structures are located in the inner area, and a plurality of second mandrel structures are located in the outer area. Wherein the first axis structures are arranged in parallel, the second axis structures are also arranged in parallel, the strip-shaped mask layers are located in the inner area, and the strip-shaped mask layers are arranged on the two sides of any first axis structure respectively.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing processes, and more particularly to a semiconductor overlay mark and a method for performing overlay measurement steps using the overlay mark. This invention can reduce the number of overlay marks, thereby reducing the area occupied by the dicing trace. Background Technology

[0002] In semiconductor manufacturing, overlay and alignment marking are two crucial technical concepts. These technologies ensure that each layer of a wafer in a multilayer structure is precisely overlaid, thereby guaranteeing the functionality and performance of the circuit. As manufacturing technology continues to advance, the importance of these technologies continues to grow.

[0003] In semiconductor manufacturing, the alignment of different photolithographic layers on a wafer refers to the relative positions of these layers. Each photolithographic pattern must be precisely aligned with the previous one to ensure correct circuit functionality. Alignment error is a measure of this misalignment, typically measured in nanometers. At advanced manufacturing nodes (such as 7 nanometers and below), the requirements for alignment precision become even higher, as any minute error can lead to performance degradation or even circuit failure. Alignment errors can be categorized into systematic errors and random errors. Systematic errors, caused by equipment calibration or design flaws, are predictable and can be reduced through correction methods. Random errors, on the other hand, are caused by defects in the manufacturing process or materials and are unpredictable, requiring control through improved manufacturing process stability.

[0004] In measuring overlap errors, modern semiconductor manufacturing processes primarily utilize optical or electron microscopy techniques. Optical overlap systems use optical overlap marks for measurement, offering advantages such as high speed and ease of operation, with accuracy down to tens of nanometers. However, advancements in manufacturing technology have led to the demand for even higher precision, prompting the emergence of electron beam overlap systems. Electron beam overlap systems use an electron beam to scan overlap marks, achieving even higher accuracy, but their measurement speed is slower, making them suitable for manufacturing processes with extremely high precision requirements. In actual manufacturing processes, various correction methods are employed to reduce overlap errors. Pre-correction involves photomask overlap before exposure to reduce errors; dynamic correction is performed in real-time during exposure to improve overlap accuracy; and post-correction corrects errors through subsequent processes, such as ion implantation or chemical mechanical polishing (CMP).

[0005] Alignment marks are reference marks used for photolithography alignment in semiconductor manufacturing processes. These marks are typically placed at specific locations on the wafer, serving as reference points for identification and alignment by the photolithography equipment. The accurate fabrication and identification of alignment marks are fundamental to achieving high-precision overlay. Alignment marks are usually composed of specific geometric shapes, such as crosses, rings, or other high-contrast patterns, to facilitate identification and positioning by the photolithography equipment. These marks need to be fabricated early in the manufacturing process and checked and corrected during each photolithography layer to ensure the alignment accuracy of all photolithography layers.

[0006] In the photolithography process of semiconductor manufacturing, the role of alignment marks is crucial. Photolithography is a technique that uses photoresist and a photomask to form patterns on the surface of a wafer. First, photoresist is coated onto the wafer surface. Then, ultraviolet or extreme ultraviolet light is used to transfer the pattern onto the photoresist through the photomask. This process requires precise alignment to ensure that each layer of pattern accurately overlaps with the previous layer. Alignment marks provide reference points for this precise alignment. The photolithography equipment identifies these marks to perform positional corrections, thereby ensuring accurate pattern transfer.

[0007] With the continuous advancement of manufacturing technology, the requirements for alignment accuracy and alignment marking are becoming increasingly stringent. At advanced manufacturing nodes, alignment errors need to be controlled within a few nanometers, placing extremely high demands on manufacturing equipment and technology. To address these challenges, manufacturing technologies are constantly introducing new alignment and correction techniques. However, the application of these techniques also brings new challenges, such as more stringent requirements for photoresist materials and photomask design. Summary of the Invention

[0008] This invention provides a stacked marker comprising four sub-markers, each sub-marker containing a substrate, defining an inner region and an outer region, a plurality of first mandrel structures located in the inner region, and a plurality of second mandrel structures located in the outer region, wherein the first mandrel structures are arranged in parallel to each other, and the second mandrel structures are also arranged in parallel to each other, and a plurality of strip mask layers are located in the inner region, wherein each of the first mandrel structures contains a strip mask layer on each side.

[0009] The present invention further provides a method for measuring the stacking of semiconductor structures, comprising: a substrate having four sub-markers on a diced path, each sub-marker including an inner region and an outer region; a plurality of first axial structures located on the substrate of the inner region; a plurality of second axial structures located on the substrate of the outer region; forming a mask layer covering the first axial structures and the second axial structures; forming a first patterned photoresist layer on the mask layer; performing a first stacking measurement step on the first patterned photoresist layer with the first axial structures and the second axial structures; forming a second patterned photoresist layer on the mask layer; and performing a second stacking measurement step on the second patterned photoresist layer with the first axial structures and the second axial structures.

[0010] In current technologies, several different overlay methods may be used to improve the accuracy of overlay measurement steps, including IBO (Image-Based Overlay) and DBO (Diffraction-Based Overlay). However, in current technologies, each overlay measurement step requires the formation of a separate overlay mark. As the number of stacked material layers increases, each material layer needs to be overlaid with the others, resulting in a corresponding increase in the number of overlay marks. Since the size of components is becoming increasingly smaller, too many overlay marks may not be able to fit within the limited space of the cutting channel. The concept of this invention is to divide the same overlay mark into different regions, such as an inner region and an outer region, and then apply different overlay measurement steps to the inner and outer regions respectively, such as image overlay measurement steps (i.e., IBO overlay) and diffraction overlay measurement steps (i.e., DBO overlay). In other words, different regions of the same overlay mark can be used for different overlay measurement steps. Therefore, the number of overlay marks originally required can be reduced to only a few overlay marks to complete the same overlay measurement steps. In this way, the space of the cutting track can be greatly saved, thereby saving component space. This invention conforms to the development trend of component miniaturization and is also conducive to technological progress. Attached Figure Description

[0011] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0012] Figure 1 This is a top view schematic diagram of the overlapping marks within the cutting channel in one embodiment;

[0013] Figure 2 This is a top view of the overlapping markings of the present invention;

[0014] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 To form Figure 2 The diagram shows a top view and a cross-sectional view of the overlapping markings.

[0015] Symbol Explanation

[0016] 10: First stack pair marker

[0017] 20: Second stack pair marker

[0018] 30: Third stack pair mark

[0019] 40: Fourth stack pair mark

[0020] 50: Fifth stack pair mark

[0021] 100: Overlapping mark

[0022] 101: Sub-tag

[0023] 101A: Inner Zone

[0024] 101B: Outer Zone

[0025] 102: Sub-tag

[0026] 102A: Inner Zone

[0027] 102B: Outer Zone

[0028] 103: Sub-tags

[0029] 103A: Inner Zone

[0030] 103B: Outer Zone

[0031] 104: Sub-tags

[0032] 104A: Inner Zone

[0033] 104B: Outer Zone

[0034] 105: Signage Area

[0035] 110: First axis structure

[0036] 120: Second axis structure

[0037] 130: Strip-shaped mask layer

[0038] 140: Insulation layer

[0039] 150: Mask layer

[0040] 152: First patterned photoresist layer

[0041] 160: Second patterned photoresist layer

[0042] DBO1: First diffraction stacking measurement step

[0043] DBO2: Second diffraction stacking measurement steps

[0044] IBO1: First Image Overlay Measurement Procedure

[0045] IBO2: Second Image Overlay Measurement Procedure

[0046] O: Center point

[0047] OP1: Opening

[0048] R1: Groove

[0049] S: Substrate

[0050] SL: Cutting Track

[0051] X1: Distance

[0052] X2: Distance

[0053] X3: Distance

[0054] X4: Distance Detailed Implementation

[0055] To enable those skilled in the art to further understand the present invention, preferred embodiments of the invention are described below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings.

[0056] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0057] Although the present invention uses terms such as first, second, third, etc., to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0058] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, such as within 10%, 5%, 3%, 2%, 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate, meaning that the meaning of "about" or "substantially" may be implied even without specific mention of it.

[0059] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0060] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details are within the scope of knowledge of those skilled in the art.

[0061] First, this invention relates primarily to an overlay mark and a method for performing overlay measurements using this overlay mark. Before describing the steps and structure of this invention, the basic principles of this invention will be described to better understand its features.

[0062] This invention is primarily applied in semiconductor manufacturing processes, specifically in the stacking measurement steps during the formation of fin structures and gate patterns. The steps generally include first forming a mandrel pattern on a substrate, then transferring the pattern into the substrate using mandrel pattern and sidewall pattern transfer (SIT) technology to form multiple arranged fin structures, followed by forming a gate pattern on top of the fin structures, and finally cutting the gate pattern.

[0063] In semiconductor fabrication, a mandrel is a temporary structure typically used as a template or support during patterning. Its primary function is to facilitate the formation of fine structures, particularly in multi-patterning techniques such as Self-Stacked Double Patterning (SADP) and Self-Stacked Quad Patterning (SAQP). These techniques aim to overcome the resolution limitations of photolithography and achieve smaller feature sizes. In the manufacturing process, the mandrel is first patterned, then spacers are deposited, and finally the mandrel is removed, leaving the fine pattern formed by the spacers. Thus, the mandrel acts as a transitional structure, facilitating high-precision pattern transfer, resulting in smaller linewidths and higher pattern densities.

[0064] The fin structure is the core component of a FinFET structure, representing one or more elongated structures protruding from the substrate that form the channel region of the transistor. Current flows through these fins and is controlled by the gate surrounding them. The three-dimensional design of the fin structure increases the gate's control area over the channel, resulting in significant improvements in leakage current control and switching performance compared to traditional planar transistors. Using multiple fins in parallel can further enhance current capability and improve the overall performance of the transistor. The fabrication of fin structures typically involves first creating a fin pattern, followed by a series of etching and deposition steps to ensure precision and consistency.

[0065] The gate is a fin-shaped switching element that controls the flow of current. In a FinFET, the gate surrounds the sidewalls and top of the fin structure, forming a three-dimensional enclosure structure. This design provides better electric field control. The gate is typically made of polysilicon or other metallic materials and covered with an insulating layer, such as a high-dielectric-constant material, to ensure effective control of the channel current during switching. The fabrication of the gate involves fine photolithography and etching processes to ensure that the gate precisely surrounds each fin structure and provides the required electrical characteristics.

[0066] In addition, from a top view, the gate usually presents multiple elongated strip patterns that are separate from each other. In the actual manufacturing process, in order to avoid the pattern from rounding after etching, multiple elongated gate continuous patterns are usually formed first, and then a cutting step (also known as a slot cut step) is used to divide these elongated gate continuous patterns into multiple gate structure patterns that are separate from each other. In this way, the corner shape of the cut gate pattern will be close to the original design pattern (e.g., right angle), thus reducing the problem of rounding.

[0067] As described above, in the sequential steps of forming the axial structure, forming a continuous gate pattern, and dicing the continuous gate pattern, different photomasks are used for photolithography etching to transfer the pattern on the photomask to the substrate or material layer. However, in the above steps, different material layers need to be overlapped to prevent misalignment of the components, which could lead to component damage. Therefore, when the components are formed in the component area on the substrate, it is preferable to also form corresponding overlap marks in the peripheral area of ​​the components (such as dicing lines).

[0068] In current technology, during the formation of each pattern layer, an overlay pattern is simultaneously formed within the cutting kerf for overlay measurement with the overlay marks of other material layers above and below. That is, each material layer corresponds to at least one overlay pattern in the cutting kerf region. Furthermore, to improve the accuracy of the overlay fabrication process, current technology may use multiple different overlay fabrication processes to perform separate overlays, obtaining multiple sets of data, and then selecting one set as the primary data for subsequent measurements. For example, if a material layer is expected to be overlaid with other material layers above and below using two different overlay measurement steps, current technology will form two overlay marks in the cutting kerf, each used for one of the two overlay measurement steps for that layer.

[0069] Figure 1 A top view schematic diagram illustrating overlapping marks within a cutting channel according to one embodiment is shown. Figure 1For example, the cutting path SL contains multiple overlapping marks, namely the first overlapping mark 10, the second overlapping mark 20, the third overlapping mark 30, the fourth overlapping mark 40, and the fifth overlapping mark 50. Each overlapping mark is formed by overlapping two layers of patterns, that is, by overlapping the patterns of the upper and lower overlapping marks respectively. For example, the first stacking mark 10 contains an overlapping pattern of the mandrel stacking mark and the gate pattern stacking mark, and will be used in subsequent stacking measurement steps using the IBO (Image Based Overlay) step; the second stacking mark 20 contains an overlapping pattern of the mandrel stacking mark and the gate pattern stacking mark, and will be used in subsequent stacking measurement steps using the DBO (Diffraction Based Overlay) step; the third stacking mark 30 contains an overlapping pattern of the mandrel stacking mark and the gate slot stacking mark, and will be used in subsequent stacking measurement steps using the IBO (Image Based Overlay) step; the fourth stacking mark 40 contains an overlapping pattern of the mandrel stacking mark and the gate slot stacking mark, and will be used in subsequent stacking measurement steps using the IBO (Image Based Overlay) step; The overlapping pattern of the overlapping marks (slot) will be used in the DBO (Diffraction Based Overlay) step for subsequent overlapping measurement steps; the fifth overlapping mark 50 contains the overlap of the gate pattern and the gate slot, and will be subject to the AEICD (After Etch Inspection Critical Dimension) step.

[0070] The IBO, DBO, and AEICD stacking measurement steps mentioned here can be understood as different stacking measurement steps, and more detailed features will be described in subsequent paragraphs. Therefore, as mentioned above, when there are multiple material layers and different stacking measurement steps are required for stacking, multiple stacking marks need to be formed within the cleaving trace SL. However, as the size of semiconductor devices becomes smaller and smaller, the space in the cleaving trace is becoming increasingly insufficient. Figure 1 Each stacking pair mark occupies a certain area. Furthermore, to easily distinguish the material layer corresponding to each stacking pair mark, the material layer's code is usually indicated next to the stacking pair mark, for example... Figure 1The markings such as 30 and 4D below each stack pair mark are understandable, as these markings may change depending on the manufacturer. In short, with current technology, multiple stack pairs mark will occupy more cutting space, thus hindering component miniaturization.

[0071] To address the above problems, the present invention provides an improved stacking mark and a method for performing semiconductor stacking measurement steps using the stacking mark. Figure 2 A top view schematic diagram illustrating the overlapping markings of the present invention is shown. For example... Figure 2 As shown, the overlapping marker 100 provided in this embodiment is formed by arranging four sub-markers, namely sub-marker 101, sub-marker 102, sub-marker 103, and sub-marker 104. Each sub-marker further includes an inner area and an outer area. Figure 2 As can be seen, the inner and outer regions contain different patterns. The patterns in the inner region and the patterns in the outer region will undergo different overlay measurement steps in subsequent steps. For example, the pattern in the inner region and the pattern in the outer region will be subjected to an IBO overlay measurement step, or the pattern in the inner region will be subjected to a DBO overlay measurement step with the pattern in other inner regions of the other layers. Therefore, in the concept of this invention, different areas of the same overlay mark can be used for different overlay measurement steps. That is to say, only one or a few overlay marks are needed to achieve the overlay measurement steps that originally required multiple overlay marks. In this way, the space occupied by the overlay mark in the cutting channel can be reduced, which is beneficial to the miniaturization of the component.

[0072] More specifically, such as Figure 2 As shown, taking sub-marker 101 in overlapping mark 100 as an example, sub-marker 101 includes an inner region 101A and an outer region 101B. The inner region 101A contains a plurality of first axial structures 110 arranged in an array, while the outer region 101B contains a plurality of second axial structures 120 arranged in an array. The length, width, or area of ​​each first axial structure 110 and each second axial structure 120 is different. For example, each first axial structure 110 is rectangular with its major axis extending along the Y-axis, while each second axial structure 120 is rectangular with its major axis extending along the X-axis. In this embodiment, the lengths and widths of the first axial structures 110 and the second axial structures 120 are different from each other. In addition, the inner region 101A also includes multiple strip-shaped mask layers 130, wherein each strip-shaped mask layer 130 is preferably rectangular, and each of the first axial structure 110 includes a strip-shaped mask pattern 130 on each side. Figure 2 In this case, the first axial structure 110 has strip-shaped mask layers 130 on both sides of the Y-axis, and the strip-shaped mask layers 130 are rectangular with their long axis extending along the X-axis.

[0073] Additionally, from the top view, an insulating layer 140 is located around each of the first axial structures 110 and each of the second axial structures 120, exposing each of the first axial structures 110 and each of the second axial structures 120, and the aforementioned strip-shaped mask layer 130 is located above the insulating layer 140 (this part will be explained more clearly when discussing the cross-sectional structure later). Similarly, except for sub-marker 101 which includes an inner region 101A and an outer region 101B, other sub-markers also include inner and outer regions, such as... Figure 2 As shown, sub-marker 102 includes an inner region 102A and an outer region 102B, sub-marker 103 includes an inner region 103A and an outer region 103B, and sub-marker 104 includes an inner region 104A and an outer region 104B. The four sub-markers are arranged in a pinwheel shape, as described here... Figure 2 As shown, the entire overlapping marker 100 is divided into four regions: upper right, lower right, upper left, and lower left. Sub-markers 101 and 103 are located at opposite ends of one diagonal, for example, in the lower right and upper left regions respectively. The inner and outer regions of sub-markers 101 and 103 are arranged along the Y-direction, and sub-markers 101 and 103 are 180-degree flipped patterns. Similarly, sub-markers 102 and 104 are located at opposite ends of the other diagonal, for example, in the lower left and upper right regions respectively. The inner and outer regions of sub-markers 102 and 104 are arranged along the X-direction, and sub-markers 102 and 104 are 180-degree flipped patterns. Furthermore, the four inner regions 101A, 102A, 103A, and 104A are all located in the area near the center (inner region) of the overlapping mark 100, that is, near the center point O, while the four outer regions 101B, 102B, 103B, and 104B are all located in the area near the edge (outer region) of the overlapping mark 100, that is, far from the center point O. Other features related to the windmill shape include... Figure 2 As shown.

[0074] also, Figure 2 The overlap mark 100 may also include a marking area 105, which can be used to annotate information, such as the corresponding material layer number, to facilitate the manufacturer in quickly identifying the material layer to which the overlap mark belongs during the overlap measurement step. However, it is understood that the marking area 105 is not a necessary element in this invention, and in some embodiments, the marking area 105 may be omitted, which is also within the scope of this invention.

[0075] Figure 2 The diagram shown is a top view of the overlapping markings within the dicing path after the core structure fabrication, gate fabrication, and gate dicing processes are completed within the core region of the semiconductor structure. The following... Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The description will be formed Figure 2 The diagram shows a partial top view and a partial cross-sectional view of the overlapping markings. For simplicity, only a portion of the overlapping markings is shown in the accompanying drawings, for example... Figure 2 The sub-marked 101 region and its corresponding cross-sectional view.

[0076] Figure 3 The left side shows a top view of the overlapping markings. Figure 3 The right side shows the corresponding cross-sectional structural diagram, below. Figures 4 to 8 The left side shows a top view of the overlapping marked sections, while the right side shows the corresponding cross-sectional structure. For example... Figure 3 As shown, multiple first axial structures 110 and multiple second axial structures 120 are formed within the cleavage path SL on the substrate S. The first axial structures 110 are located in the inner region 101A, while the second axial structures 120 are located in the outer region 101B. The first axial structures 110 and second axial structures 120 are formed together with the axial structure (mandrel) of the semiconductor device core region. As mentioned above, the axial structure within the core region will be fabricated into a fin-like structure after a subsequent sidewall pattern transfer step. For the sake of simplicity, the axial structure within the core region is not shown in the accompanying drawings.

[0077] In this embodiment, the lengths and widths of the first axial structure 110 and the second axial structure 120 in the inner region 101A and the outer region 101B are designed to be different, to facilitate identification of the first axial structure 110 and the second axial structure 120. Furthermore, after the first axial structure 110 and the second axial structure 120 are formed, an insulating layer 140 is formed to cover the substrate S, wherein the insulating layer 140 corresponds to the shallow trench isolation (STI) in the core region of the semiconductor device, that is, it is formed together with the shallow trench isolation. Figure 3 As shown, the insulating layer 140 is located around the first axial structure 110 and the second axial structure 120, and the insulating layer 140 exposes the first axial structure 110 and the second axial structure 120. In this embodiment, the material of the insulating layer 140 is, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., but is not limited to these.

[0078] In this step, after forming the first axial structure 110 and the second axial structure 120, their positions can be recorded in a system (e.g., a computer) to facilitate subsequent overlay measurement steps. Details will be explained in later paragraphs.

[0079] Then as Figure 4As shown, a mask layer 150 is formed to cover the insulating layer 140, the first axial structure 110, and the second axial structure 120. The material of the mask layer 150 is, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., and the material of the mask layer 150 is preferably different from the material of the insulating layer 140.

[0080] like Figure 5 As shown, a first patterned photoresist layer 152 is formed above the mask layer 150. The first patterned photoresist layer 152 includes a plurality of openings OP1, wherein the openings OP1 are located within the inner region 101A, not within the outer region 101B, and preferably, the openings OP1 are located directly above the first axial structure 110. The openings OP1 mentioned here may be formed simultaneously with the gate dicing pattern in the gate dicing step of the core region in the semiconductor fabrication process. That is, in this step, a gate dicing pattern is defined in the core region of the semiconductor device. When the subsequent gate structure pattern is formed, the overlapping portion of the gate structure pattern and the gate dicing pattern will be removed, and the remaining gate pattern is the gate pattern that needs to be retained in the core region.

[0081] It is worth noting that in the above steps, the position of the gate dicing pattern is defined first, and then the position of the gate pattern is defined. The overlapping portion of the two will be removed, leaving the desired gate pattern. However, in other embodiments of the present invention, the gate pattern can be formed first, and then the gate dicing pattern can be formed. Similarly, the overlapping portion of the gate pattern and the gate dicing pattern will be removed, leaving the desired gate pattern. This variation is also within the scope of the present invention. Therefore, although in this embodiment, the opening OP1 is formed simultaneously with the gate dicing pattern of the core region, in other embodiments of the present invention, if the gate pattern is formed first, the opening OP1 can also be formed simultaneously with the gate pattern.

[0082] In this embodiment, when opening OP1 is formed, the position of the gate dicing pattern within the core region is defined. Therefore, the position of opening OP1 can be used for stacking measurement steps with other material layers to determine whether the gate dicing pattern is formed in the expected position without offset. As mentioned above ( Figure 1 In current technology, if two overlapping measurement steps are used, such as IBO overlapping and DBO overlapping, two overlapping marks need to be formed in the cutting path respectively. However, in this embodiment, the inner and outer areas of a single overlapping mark can be used for both overlapping measurement steps respectively. For more details, please refer to... Figure 5The opening OP1 in the inner region 101A is located directly above the first axial structure 110, so the two overlap when viewed from the top view. A first diffraction overlay measurement step DBO1 can be performed on the opening OP1 and the first axial structure 110, i.e., the so-called DBO overlay measurement step. On the other hand, a first image overlay measurement step IBO1 can be performed on the position of the opening OP1 observed in the top view and the position of the second axial structure 120 located in the outer region 101B, i.e., the so-called IBO step. Therefore, for the pattern of the first patterned photoresist layer 152, that is, the position of the opening OP1 located in the inner region 101A, it can be used to perform the first diffraction overlay measurement step DBO1 with the first axial structure 110 in the lower layer, which is also located in the inner region 101A, and at the same time, it can be used to perform the first image overlay measurement step IBO1 with the second axial structure 120 in the lower layer located in the outer region 101B.

[0083] This section provides supplementary details regarding the IBO and DBO stacking measurement steps described above. IBO stacking is an image-based stacking technique used to ensure precise alignment of photolithographic patterns onto previously formed patterns in semiconductor fabrication. IBO stacking uses a high-resolution optical or electron microscope to photograph the stacking mark patterns on the wafer and employs image processing techniques to calculate and correct the relative positional errors between layers. This method offers very high stacking accuracy because it directly analyzes the actual features in the image, rather than relying on optical diffraction patterns. Its advantages include high precision and ease of observation; however, it is computationally expensive. DBO stacking, on the other hand, is a diffraction-based stacking technique used to align photolithographic patterns with existing patterns in semiconductor fabrication. DBO stacking utilizes the principle of diffraction to measure the relative position of the stacking marks. When a beam of light illuminates the stacking marks on the wafer, the resulting diffraction pattern is captured by a detector. By analyzing these diffraction patterns, the relative positional errors between the stacking marks can be calculated and corrected. The advantages of DBO overlay include fast analysis speed, suitability for large-scale production, and high precision. However, its disadvantages include technical complexity and susceptibility to limitations imposed by material structure, such as the ability to overlay only vertically overlapping patterns. In summary, both of these overlay measurement steps are the overlay measurement steps used in this invention. However, this invention is not limited to these two overlay measurement steps; other overlay measurement steps may also be included within the scope of this invention.

[0084] Therefore, from the above Figure 5 From the concept shown, the inner region 101A and outer region 101B of the same material layer (first patterned photoresist layer 152) can be used to perform IBO and DBO overlay measurement steps with the pattern of the underlying layer, respectively. This can form fewer overlay marks and save space occupied by the cutting path.

[0085] In the above embodiments, IBO and DBO overlay measurement steps were performed respectively, and two sets of calibration data were obtained after the overlay measurement steps were completed. The manufacturer can then select one set of data as the actual calibration data based on the results. However, in other embodiments of the present invention, to save manufacturing process steps, only one type of overlay measurement step may be performed, such as either the IBO or DBO overlay measurement step, and the obtained result may be directly used as the calibration data for that layer. This variation also falls within the scope of the present invention.

[0086] Please refer to the following. Figure 6 An etching step is performed using the first patterned photoresist layer 152 as a mask. After etching, a groove R1 is formed in the mask layer 150, and then the first patterned photoresist layer 152 is removed. The etching step can be performed simultaneously with the gate cutting step of the semiconductor core region, but is not limited to this.

[0087] Next, as Figure 7 As shown, a second patterned photoresist layer 160 is formed on the mask layer 150, wherein the second patterned photoresist layer 160 can be formed simultaneously with the gate pattern in the core region. In this embodiment, the second patterned photoresist layer 160 can be used to align the position of the gate pattern, and the second patterned photoresist layer 160 is formed in the inner region 101A. Similar to the above, the second patterned photoresist layer 160 located in the inner region 101A can undergo a second diffraction overlay measurement step DBO2 with the first axial structure 110 also located in the inner region 101A below, and simultaneously, the second patterned photoresist layer 160 located in the inner region 101A can undergo a second image overlay measurement step IBO2 with the second axial structure 120 located in the outer region 101B below. The steps are similar to those described above. Figure 5 As shown, further details are omitted here. Therefore, similar to the steps described above, when forming the second patterned photoresist layer 160, it can be used for different overlay measurement steps to overlay the second patterned photoresist layer 160 with the core structure in different regions. In this way, it is not necessary to make additional overlay marks, saving space for the cutting path.

[0088] Finally, as Figure 8 As shown, one or more photolithography etching steps are performed. Here, the overlapping portion of the pattern of the first patterned photoresist layer 152 (i.e., the location of the opening OP1) and the second patterned photoresist layer 160 is removed, and the remaining pattern is transferred to the mask layer 150 below. The final mask layer 150 is as shown. Figure 8 As shown. It is worth noting that the mask layer 150 here is... Figure 2 The strip-shaped mask layer 130 is the same. After completion... Figure 8 After the mask layer 150 shown, the gate pattern that has been cut is also formed in the core area of ​​the semiconductor device.

[0089] In addition Figure 8 After the etching step shown is completed, an After-Etch Inspection Critical Dimension (AEICD) step can be performed. The AEICD step is commonly used in semiconductor manufacturing processes to measure and inspect the dimensions of critical structures on the chip after the etching step, ensuring that each dimension is within the expected range, i.e., within the critical dimension (CD), to guarantee the functionality and performance of the components. In this embodiment, the AEICD step can also measure whether there is a positional offset between the gate pattern and the corresponding axial structure below the gate cut pattern. More specifically, since the outer boundary of the etched strip mask layer 130 corresponds to the outer boundary of the second patterned photoresist layer 160, i.e., the boundary of the gate pattern, the horizontal distance from the outer side of the remaining mask layer 150 (i.e., the strip mask layer 130) to the side of the first axial structure 110 can be measured, such as... Figure 8 The distances X1 and X2 are then subtracted from each other and divided by 2 to obtain the positional offset between the gate pattern and the first axial structure 110 below.

[0090] It is worth noting that, since the inner boundary of the etched strip mask layer 130 corresponds to the opening OP1 of the first patterned photoresist layer 152, which is the boundary of the gate dicing pattern, the horizontal distance from the inner side of the remaining mask layer 150 (i.e., the strip mask layer 130) to the side of the first axial structure 110 can be measured, such as... Figure 8 The distances X3 and X4 are then subtracted from each other and divided by 2 to obtain the positional offset between the gate cutting pattern and the first axial structure 110 below.

[0091] In other words, if the positional offset between the gate pattern and the underlying first axial structure 110 obtained above is almost zero, it means that no offset has occurred in the position of the gate pattern or gate cut pattern relative to the underlying first axial structure during the fabrication process. Conversely, if the above values ​​exceed an allowable range, an offset will occur during the post-etching inspection step, which also indicates that a positional error may occur between the gate pattern, gate cut pattern, and the underlying fin structure within the semiconductor core region. In this case, an inspection and fabrication process adjustment step is required to detect and correct the error in a timely manner.

[0092] In current technology, performing AEICD and concurrent overlay measurement also requires creating corresponding overlay marks on the cutting path, i.e., as shown below. Figure 1 The fifth overlapping mark 50 in the present invention. However, the overlapping mark 100 in this embodiment of the invention has undergone multiple overlapping measurement steps during its formation, including the first image overlapping measurement step IBO1, the first diffraction overlapping measurement step DBO1, the second image overlapping measurement step IBO2, and the second diffraction overlapping measurement step DBO2. In addition, after etching is completed, an AEICD step of overlapping measurement is performed. That is to say, the same overlapping mark 100 of the present invention can undergo a total of five overlapping measurement steps from the start of its formation to the completion of etching. In actual manufacturing process, only the overlapping mark 100 needs to be formed, which can replace the previous method. Figure 1 The five stacking pairs in the middle can significantly reduce the number of stacking pairs.

[0093] Furthermore, in the above embodiments, the gate dicing pattern is formed first, followed by the gate pattern. Therefore, the first patterned photoresist layer 152 corresponds to the gate dicing pattern, and the subsequently formed second patterned photoresist layer 160 corresponds to the gate pattern. The overlapping portion of the two patterns will be removed, and the final remaining pattern is the desired gate pattern. However, in other embodiments of the present invention, the gate pattern can be formed first, followed by the gate dicing pattern. That is, the aforementioned first patterned photoresist layer 152 can correspond to the gate pattern. Figure 6 The etching step shown can be performed simultaneously with the etching step of etching the gate pattern in the core region, and then the second patterned photoresist layer 160 can correspond to the gate cutting pattern, therefore Figure 8 The etching step shown corresponds to the etching step in the gate cutting step (i.e., the etching step that removes part of the gate pattern). This variation is also within the scope of this invention.

[0094] Based on the above description and figures, the present invention provides a stacking mark comprising four sub-markers 101, 102, 103, and 104, which together form a stacking mark 100. Each sub-marker includes a substrate S, defining an inner region 101A and an outer region 101B. A plurality of first mandrel structures 110 are located in the inner region 101A, and a plurality of second mandrel structures 120 are located in the outer region 101B. The first mandrel structures 110 are arranged in parallel with each other, and the second mandrel structures 120 are also arranged in parallel with each other. A plurality of strip mask layers 130 are located in the inner region 101A, wherein each of the first mandrel structures 110 has a strip mask layer 130 on each side.

[0095] In some embodiments of the present invention, the lengths of the first axial structure 110 and the second axial structure 120 are different from each other, and their widths are also different from each other (e.g., ...). Figure 3 (As shown).

[0096] In some embodiments of the present invention, an insulating layer 140 is further included on the substrate S, and each of the first axial structures 110 and each of the second axial structures 120 are exposed.

[0097] In some embodiments of the present invention, the insulating layer 140 is located on both sides of the first axial structure 110 and each of the second axial structures 120, and the strip mask layer 130 is located on the insulating layer 140.

[0098] In some embodiments of the present invention, the first axial structure 110 is directly connected to the substrate S with each of the second axial structures 120.

[0099] In some embodiments of the present invention, two of the four sub-markers (e.g., sub-markers 102 and 104) are arranged along an X-axis, and the other two sub-markers (e.g., sub-markers 101 and 103) are arranged along a Y-axis, and the four sub-markers are arranged in a windmill shape.

[0100] The present invention further provides a method for measuring the stacking of semiconductor structures, comprising a substrate S having four sub-markers (sub-markers 101, 102, 103, 104) on a diced path SL, wherein each sub-marker includes an inner region 101A and an outer region 101B, and a plurality of first axial structures 110 located on the substrate S of the inner region 101A, and a plurality of second axial structures 120 located on the substrate S of the outer region 101B, forming a mask layer 150 covering the first axial structures 110 and the second axial structures 120, and forming a first patterned photoresist layer 152 on the mask layer. On the mask layer 150, a first patterned photoresist layer 152 is subjected to a first overlay measurement step (including a first image overlay measurement step IBO1 and a first diffraction overlay measurement step DBO1) to form a second patterned photoresist layer 160 on the mask layer 150, and a second overlay measurement step (including a second image overlay measurement step IBO2 and a second diffraction overlay measurement step DBO2) is performed on the second patterned photoresist layer 160 and the first axial structure 110 and the second axial structure 120.

[0101] In some embodiments of the present invention, the first overlay measurement step includes a first image overlay measurement step IBO1 and a first diffraction overlay measurement step DBO1.

[0102] In some embodiments of the present invention, the first image overlay measurement step is to perform an image overlay between the pattern (opening OP1) of the first patterned photoresist layer 152 located in the inner region 101A and the pattern of the second axial structure 120 in the outer region 101B.

[0103] In some embodiments of the present invention, the first diffraction overlay measurement step is to perform a diffraction overlay of the pattern (opening OP1) of the first patterned photoresist layer 152 located in the inner region 101A with the pattern of the first axial structure 110 in the inner region 101A.

[0104] In some embodiments of the present invention, the second overlay measurement step includes a second image overlay measurement step IBO2 and a second diffraction overlay measurement step DBO2.

[0105] In some embodiments of the present invention, the second image overlay measurement step is to perform an image overlay between the pattern of the second patterned photoresist layer 160 located in the inner region 101A and the pattern of the second axial structure 120 in the outer region.

[0106] In some embodiments of the present invention, the second diffraction overlay measurement step is to perform a diffraction overlay of the pattern of the second patterned photoresist layer 160 located in the inner region 101A with the pattern of the first axial structure 110 in the inner region 101A.

[0107] In some embodiments of the present invention, an insulating layer 140 is further formed on the substrate S, wherein the insulating layer 140 is located next to each of the first axial structures 110 and each of the second axial structures 120.

[0108] In some embodiments of the present invention, after the formation of the first patterned photoresist layer 152, a first etching step is further included (e.g., ...). Figure 6 (The steps are as follows), a portion of the mask layer 150 is removed, and then a second patterned photoresist layer 160 is formed on the remaining mask layer 150 (e.g., ...). Figure 7 (Steps).

[0109] In some embodiments of the present invention, a second etching step is further included after the formation of the second patterned photoresist layer 160. Figure 8 (Steps) Remove part of the mask layer 150, and the remaining mask layer 150 is defined as a plurality of strip mask layers 130, wherein the strip mask layers 130 are located on the insulating layer 140.

[0110] In some embodiments of the invention, a post-etching critical dimension (AEICD) step is further included after the second etching step. Figure 8 (as shown in the steps), measure the distance from the strip mask layer 130 to the first axial structure 110.

[0111] In some embodiments of the present invention, the lengths of the first axial structure 110 and the second axial structure 120 are different from each other, and their widths are also different from each other.

[0112] In some embodiments of the present invention, the first axial structure 110 is directly connected to the substrate with each of the second axial structures 120.

[0113] In some embodiments of the present invention, two of the four sub-markers 101, 102, 103, and 104 (e.g., sub-marker 102 and sub-marker 104) are arranged along an X-axis, and the other two sub-markers (e.g., sub-marker 101 and sub-marker 103) are arranged along a Y-axis, and the four sub-markers are arranged in a windmill shape.

[0114] In summary, current technologies employ several different overlay methods to improve the accuracy of overlay measurement steps, including IBO (Image-Based Overlay) and DBO (Diffraction-Based Overlay). However, each overlay measurement step requires a separate overlay marker. As the number of stacked material layers increases, each layer needs to be overlaid, leading to a corresponding increase in the number of overlay markers. With increasingly smaller component sizes, excessive overlay markers may not be adequately accommodated within the limited space of the cutting channel. The concept of this invention is to divide the same overlay marker into different regions, such as an inner and outer region, and then apply these regions to different overlay measurement steps, such as image overlay measurement (IBO) and diffraction overlay measurement (DBO). In other words, different regions of the same overlay mark can be used for different overlay measurement steps. Therefore, the number of overlay marks originally required can be reduced to only a few overlay marks to complete the same overlay measurement steps. In this way, the space of the cutting track can be greatly saved, thereby saving component space. This invention conforms to the development trend of component miniaturization and is also conducive to technological progress.

[0115] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A pairing tag, comprising: The four sub-tags together form the stacked pair, where each sub-tag contains: A basis is defined by having an inner region and an outer region. Multiple first mandrel structures are located in the inner region, and multiple second mandrel structures are located in the outer region, wherein each of the first mandrel structures is arranged in parallel with each other, and each of the second mandrel structures is also arranged in parallel with each other; Multiple strip-shaped mask layers are located in the inner region, wherein each of the first axial structures contains one of the strip-shaped mask layers on each side.

2. The overlapping mark as claimed in claim 1, wherein the lengths of the first axial structure and the second axial structure are different from each other, and their widths are also different from each other.

3. The overlapping mark as claimed in claim 1, further comprising an insulating layer located on the substrate and exposing each of the first axial structures and each of the second axial structures.

4. The overlapping mark as claimed in claim 3, wherein the insulating layer is located on both sides of the first axial structure and each of the second axial structures, and the strip mask layer is located on the insulating layer.

5. The overlapping mark as claimed in claim 1, wherein the first axial structure and each of the second axial structures are directly connected to the substrate.

6. The overlapping marker as claimed in claim 1, wherein two of the four sub-markers are arranged along the X-axis, the other two are arranged along the Y-axis, and the four sub-markers are arranged in a pinwheel shape.

7. A method for measuring the stacking of semiconductor structures, comprising: Four sub-marks are formed on the cutting path of the substrate, wherein each sub-mark contains an inner region and an outer region, and a plurality of first axial structures are located on the substrate in the inner region, and a plurality of second axial structures are located on the substrate in the outer region; A mask layer is formed to cover the first axial structure and the second axial structure; A first patterned photoresist layer is formed on the mask layer; A first stacking measurement step is performed on the first patterned photoresist layer, the first axial structure, and the second axial structure; A second patterned photoresist layer is formed on the mask layer; as well as A second stacking measurement step is performed on the second patterned photoresist layer, the first axial structure, and the second axial structure.

8. The method for measuring the stacking of a semiconductor structure as described in claim 7, wherein the first stacking measurement step includes a first image stacking measurement step and a first diffraction stacking measurement step.

9. The semiconductor structure overlay measurement method as claimed in claim 8, wherein the first image overlay measurement step is to perform image overlay between the pattern of the first patterned photoresist layer located in the inner region and the pattern of the second axial structure in the outer region.

10. The method for measuring the superposition of a semiconductor structure as claimed in claim 8, wherein the first diffraction superposition measurement step is to perform diffraction superposition of the pattern of the first patterned photoresist layer located in the inner region with the pattern of the first axial structure in the inner region.

11. The method for measuring the stacking of a semiconductor structure as described in claim 7, wherein the second stacking measurement step includes a second image stacking measurement step and a second diffraction stacking measurement step.

12. The semiconductor structure overlay measurement method of claim 11, wherein the second image overlay measurement step is to perform image overlay between the pattern of the second patterned photoresist layer located in the inner region and the pattern of the second axial structure in the outer region.

13. The semiconductor structure stacking measurement method of claim 11, wherein the second diffraction stacking measurement step is to perform diffraction stacking of the pattern of the second patterned photoresist layer located in the inner region with the pattern of the first axial structure in the inner region.

14. The method for measuring the stacking of semiconductor structures as claimed in claim 7, further comprising forming an insulating layer on the substrate, wherein the insulating layer is located adjacent to each of the first axial structures and each of the second axial structures.

15. The method for measuring the stacking of a semiconductor structure as claimed in claim 14, wherein after the formation of the first patterned photoresist layer, the method further comprises performing a first etching step to remove a portion of the mask layer, and then forming the second patterned photoresist layer on the remaining mask layer.

16. The method for measuring the stacking of a semiconductor structure as claimed in claim 15, wherein after the formation of the second patterned photoresist layer, a second etching step is further included to remove a portion of the mask layer, wherein the remaining mask layer is defined as a plurality of strip mask layers, wherein the strip mask layers are located on the insulating layer.

17. The method for measuring the stacking of a semiconductor structure as claimed in claim 16, wherein after the second etching step, it further includes performing an etch-after critical dimension (AEICD) step to measure the distance from the strip mask layer to the first axial structure.

18. The method for measuring the stacking of semiconductor structures as claimed in claim 7, wherein the lengths of the first axial structure and the second axial structure are different from each other, and their widths are also different from each other.

19. The method for measuring the stacking of semiconductor structures as claimed in claim 7, wherein the first axial structure and each of the second axial structures are directly connected to the substrate.

20. The method for measuring the stacking of a semiconductor structure as described in claim 7, wherein two of the four sub-markers are arranged along the X-axis, the other two are arranged along the Y-axis, and the four sub-markers are arranged in a pinwheel shape.

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