Test element and method of manufacturing same

Abstract

A test element and a method of manufacturing the same are disclosed. The test element may include: a base layer; a bank on a portion of the base layer; a first layer on the base layer and on the bank; a photoresist layer on the first layer, the photoresist layer including a patterned region; and a second layer on the photoresist layer. A height of a first region of the first layer on the bank may be higher than a height of a second region of the first layer on the base layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0102086, filed on July 31, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a test element and a method for manufacturing the same. Background Technology

[0004] Display devices are being used in a variety of electronic devices such as televisions, mobile phones, laptops, and tablets. Examples of display devices include self-emissive organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require a separate light source.

[0005] Recently, display devices that include light-emitting elements such as light-emitting diodes (LEDs) have attracted attention as next-generation display devices. Because light-emitting elements are made of inorganic materials rather than organic materials, such display devices that include light-emitting elements have faster light emission speeds, higher luminous efficiency, and higher brightness compared to liquid crystal displays and organic light-emitting displays. Summary of the Invention

[0006] When manufacturing semiconductor devices by forming integrated circuits on semiconductor wafers, it is necessary to measure the electrical characteristics of the integrated circuits to determine any defects or reliability issues.

[0007] Therefore, embodiments of this disclosure relate to test elements and methods of manufacturing such test elements, which substantially eliminate one or more problems caused by limitations and disadvantages of related technologies.

[0008] One aspect of this disclosure is to provide a test element capable of determining reliability and a method for manufacturing the test element.

[0009] Additional features and aspects will be set forth in the description which follows, and will become partly apparent from the description, or may be learned by practice of the inventive concept provided herein. Other features and aspects of the inventive concept may be realized and obtained by means of structures particularly pointed out in the written description, or structures from which they may be derived, the claims thereof, and the accompanying drawings.

[0010] To achieve these and other aspects of the inventive concept, as embodied and broadly described herein, a test element can include a base layer, a bank on a portion of the base layer, a first layer on the base layer and the bank, a photoresist layer on the first layer, the photoresist layer including a patterned region, and a second layer on the photoresist layer, wherein a height of a first region of the first layer on the bank is higher than a height of a second region of the first layer on the base layer.

[0011] In another aspect, a method of manufacturing a test element can include forming a bank on a base layer, forming a first layer including a first region on the bank and a second region on the base layer, forming a photoresist layer on the first layer, forming a patterned region in the photoresist layer by exposure, and forming a second layer on the photoresist layer and in the patterned region, wherein a height of the first region of the first layer on the bank is higher than a height of the second region of the first layer on the base layer.

[0012] In addition to means for solving the above-described problems, specific details according to various examples of the present disclosure are also included in the following description and the accompanying drawings.

[0013] According to one or more embodiments of the present disclosure, a contact resistance between the first layer and the second layer can be measured through the patterned region. Accordingly, a reliability of a micro LED in a display device can be determined.

[0014] According to one or more embodiments of the present disclosure, by configuring a test element, defects in a display device can be detected. This can enable optimization of a process of the display device and reduction of greenhouse gas emissions from production of the display device.

[0015] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concept as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain various principles.

[0017] Figure 1 FIG. 1 is a perspective view illustrating a display device according to an embodiment of the present disclosure.

[0018] Figure 2 FIG. 2 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0019] Figure 3 FIG. 3 is an enlarged view illustrating a display device according to an embodiment of the present disclosure.

[0020] Figure 4 is a diagram showing a circuit structure according to an embodiment of the present disclosure.

[0021] Figure 5 is an enlarged plan view of a display region including a plurality of pixels.

[0022] Figure 6 is a plan view of a display device according to an embodiment of the present disclosure.

[0023] Figure 7 is a plan view of a display device according to an embodiment of the present disclosure.

[0024] Figure 8 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0025] Figure 9 is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0026] Figures 10 to 13 is a diagram showing an apparatus to which a display device according to an embodiment of the present disclosure is applied.

[0027] Figure 14 is a plan view of a semiconductor device according to an embodiment of the present disclosure.

[0028] Figure 15 is an enlarged view of a region A of Figure 14

[0029] Figure 16 is a cross-sectional view showing an example of a test element in which contact resistance between a first layer and a second layer is not measured.

[0030] Figure 17 is a diagram showing an example mask pattern for generating a test element of Figure 16

[0031] Figure 18 is a cross-sectional view showing a test element or a group of test elements according to an embodiment of the present disclosure.

[0032] Figure 19 is a diagram showing a mask pattern for forming a test element or a group of test elements of Figure 18

[0033] Figure 20 is a plan view of a test element of Figure 18

[0034] Figure 21 is a diagram showing an embodiment of a test element or a group of test elements according to an embodiment of the present disclosure. DETAILED DESCRIPTION​​​​

[0035] The advantages and features of the present disclosure and a method of achieving the advantages and features of the present disclosure will become apparent from the detailed description of the embodiments given below with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments described below and can be implemented by various modifications. The embodiments are provided merely to enable those skilled in the art to completely understand the scope of the present disclosure.

[0036] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely illustrative and are not limited to the matters indicated in the present disclosure. Throughout the disclosure, like reference numerals refer to like elements. Also, in describing the present disclosure, detailed descriptions of known technical functions or constitutions incorporated herein can be omitted when it is determined that such detailed description can unnecessarily obscure the subject matter of the present disclosure. Unless the terms such as "include" and "have" are used together with the term "only" or the like, these terms are intended to enable addition of other elements. Unless otherwise explicitly stated, any reference to a singular can include a plural.

[0037] Even if such a margin is not explicitly stated, components are interpreted to include ordinary error ranges.

[0038] In describing positional relationships, for example, in the case of using the terms "on", "above", "below", "next to", etc. to describe the positional relationship between two parts, one or more parts can be inserted therebetween unless the terms "just", "directly", or "adjacent" are used in the expression.

[0039] In order to describe temporal relationships, when a temporal relationship is described as "after", "subsequently", "next", "before", etc., a non-continuous case can be included unless the term "immediately" or "directly" is used in the expression.

[0040] Although the terms "first", "second", etc. can be used herein to describe various components, the components are not limited by the terms. The terms are used only to distinguish one component from another component. Therefore, within the technical scope of the present disclosure, the first component described below can be a second component.

[0041] When describing the components of the present disclosure, the terms first, second, A, B, (a), (b), etc. can be used herein. Such terms are used only to distinguish one component from another component, and do not limit the nature, sequence, order, number, etc. of the components.

[0042] It should be understood that when a component is referred to as being "connected", "coupled", "linked", or "attached" to another component, it can be directly connected, coupled, linked, or attached to the other component, but it can also be indirectly connected, coupled, linked, or attached to the other component through yet another component, unless specifically stated otherwise.

[0043] It should also be understood that when a component or layer is referred to as being "in contact" or "overlapping" another component or layer, it can be in direct contact or directly overlapping the other component or layer, but unless specifically stated otherwise, yet another component or layer can be interposed between the two components or layers such that they are in indirect contact or indirect overlapping with each other.

[0044] The term "at least one of" shall be construed as including any and all combinations of one or more associated listed components. For example, the meaning of "at least one of a first component, a second component, and a third component" indicates all combinations including two or more of the first component, the second component, and the third component, as well as the first component, the second component, or the third component alone.

[0045] The terms "first direction", "second direction", "third direction", "X-axis direction", "Y-axis direction", and "Z-axis direction" shall not be construed as referring only to a geometric relationship of being perpendicular to each other, but can indicate a wider range of directions within the functional range of the configuration described in the present disclosure.

[0046] Features of various embodiments of the present disclosure can be partially or wholly combined with each other. Embodiments can be technically associated and operate in various ways, and can be executed independently or in association with each other.

[0047] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0048] Figure 1 is a perspective view illustrating a display apparatus according to an embodiment of the present disclosure; Figure 2 is a plan view illustrating a display apparatus according to an embodiment of the present disclosure; Figure 3 is an enlarged view illustrating a display apparatus according to an embodiment of the present disclosure.

[0049] As Figures 1 to 3As illustrated, the display apparatus 1000 according to an embodiment of the disclosure can include a display panel 100, a polarizing layer 293, an adhesive layer 295, a cover member 120, a support substrate 170, a flexible circuit board CB, and a printed circuit board 160. For example, the display apparatus 1000 can include a substrate 110. The substrate 110 can be a member that supports other components of the display apparatus 1000. The substrate 110 can be made of an insulating material. For example, the substrate 110 can be made of glass, resin, or the like. The substrate 110 can also be made of a material having flexibility. For example, the substrate 110 can be made of a plastic material having flexibility, such as polyimide (PI). However, embodiments of the disclosure are not limited thereto.

[0050] The display panel 100 can implement display of information, video, and / or image intended for a user. For example, the display panel 100 can include a display area AA and a non-display area NA. For example, the substrate 110 can include the display area AA and the non-display area NA. The terms of the display area AA and the non-display area NA can not be limited to the substrate 110, but can be applied to the entire display apparatus.

[0051] The display area AA can be an area in which an image is displayed. The display area AA can include a plurality of pixels PX. Each of the plurality of pixels PX can be composed of a plurality of sub-pixels. A plurality of light emitting elements can be arranged in each of the plurality of sub-pixels. The plurality of light emitting elements can be variously configured according to a type of the display apparatus 1000. For example, if the display apparatus 1000 is an inorganic light emitting display apparatus, the light emitting element can be a light emitting diode (LED), a micro light emitting diode (micro LED), or a mini light emitting diode (mini LED), but embodiments of the disclosure are not limited thereto.

[0052] The non-display area NA can be an area in which an image is not displayed. Various wirings and circuits for driving the plurality of light emitting elements PX of the display area AA can be arranged in the non-display area NA. For example, in the non-display area NA, various wirings and driving circuits can be mounted, and a pad portion PAD connecting an integrated circuit, a printed circuit, or the like can be arranged, but embodiments of the disclosure are not limited thereto.

[0053] For example, the driving circuit can be a data driving circuit and / or a gate driving circuit, but embodiments of the present disclosure are not limited thereto. Wires to which control signals for controlling the driving circuit are supplied can be arranged. For example, the control signals can include various timing signals including a clock signal, an input data enable signal, and a synchronization signal, but embodiments of the present disclosure are not limited thereto. The control signals can be received through the pad portion PAD. For example, link wires LL for transmitting signals can be arranged in the non-display area NA. For example, a driving component such as a flexible circuit board CB and a printed circuit board 160 can be connected to the pad portion PAD.

[0054] According to an example of the present disclosure, the non-display area NA can include a first non-display area NA1, a bending area BA, and a second non-display area NA2. For example, the first non-display area NA1 can be an area surrounding at least a portion of the display area AA. The bending area BA can be an area extending from at least one of the plurality of sides of the first non-display area NA1, and can be a bendable area. The second non-display area NA2 is an area extending from the bending area BA, in which the pad portion PAD can be arranged. For example, the bending area BA can be in a bent state, and the remaining area of the substrate 110 other than the bending area BA can be in a flat state. In this structure, when the bending area BA is bent, the second non-display area NA2 can be located on the rear surface of the display area AA. However, embodiments of the present disclosure are not limited thereto.

[0055] According to the design of the display apparatus 1000, the substrate 110 or the display area AA of the display apparatus 1000 can be configured in various shapes. For example, the display area AA can be configured in a rectangular shape having four rounded corners, but embodiments of the present disclosure are not limited thereto. As another example, the display area AA can be configured in a rectangular shape having four right-angled corners, a circular shape, or the like, but embodiments of the present disclosure are not limited thereto.

[0056] According to an example of the present disclosure, a width of the second non-display area NA2 in which the plurality of pad electrodes PE are arranged can be wider than a width of the bending area BA in which only the plurality of link wires LL are arranged. Further, a width of the display area AA in which the plurality of sub-pixels are arranged can be wider than the width of the bending area BA in which only the plurality of link wires LL are arranged. Although the width of the bending area BA is shown to be narrower than the width of the other area of the substrate 110 in this drawing, the shape of the substrate 110 including the bending area BA is exemplary, and embodiments of the present disclosure are not limited thereto.

[0057] Referring to Figure 3Multiple pixel driving circuits (PDs) can be arranged in the display area AA. The multiple pixel driving circuits (PDs) can be circuits for driving light-emitting elements of multiple sub-pixels. Each of the multiple pixel driving circuits (PDs) includes multiple transistors with driving transistors and storage capacitors, etc., and can supply control signals, power, and driving current to the light-emitting elements of the multiple sub-pixels to control the light-emitting operation of the multiple light-emitting elements. For example, the pixel driving circuit (PD) can include power supply wiring and signal wiring for controlling the emission on / off and / or emission time of the light-emitting elements. For example, the multiple pixel driving circuits (PDs) can be drive drivers fabricated on a semiconductor substrate using a metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication process, but embodiments of this disclosure are not limited thereto. The drive driver can include multiple pixel driving circuits (PDs) and can drive multiple sub-pixels.

[0058] like Figure 1 As shown, the flexible circuit board CB and the printed circuit board 160 can be arranged on the lower portion of the display panel 100. The flexible circuit board CB and the printed circuit board 160 can be arranged on at least one side edge of the display panel 100, but embodiments of this disclosure are not limited thereto. One side of the flexible circuit board CB can be attached to the display panel 100, and the other side can be attached to the printed circuit board 160, but embodiments of this disclosure are not limited thereto. The flexible circuit board CB can be a flexible film, but embodiments of this disclosure are not limited thereto.

[0059] A pad portion PAD, including multiple pad electrodes PE, can be arranged in a second non-display area NA2. A driving component, including one or more flexible circuit boards (or flexible films) CB and a printed circuit board 160, can be attached to or combined with the pad portion PAD. The multiple pad electrodes PE of the pad portion PAD are electrically connected to one or more flexible circuit boards (or flexible films) CB, and can transmit various signals (or power) from the printed circuit board 160 and the flexible circuit boards (or flexible films) CB to multiple pixel driving circuits PD in the display area AA.

[0060] The flexible circuit board (or flexible film) CB can be a film having various components placed on a flexible base film. For example, a driver IC, such as a gate driver IC or a data driver IC, can be located on the flexible circuit board (or flexible film) CB, but embodiments of this disclosure are not limited thereto. The driver IC can be a component that processes data and drive signals for displaying images. The driver IC can be arranged in a manner such as chip on glass (COG), chip on thin film (COF), or tape-on-carrier (TCP), depending on how it is mounted, but embodiments of this disclosure are not limited thereto. The flexible circuit board (or flexible film) CB can be attached or bonded to multiple pad electrodes PE by a conductive adhesive layer, but embodiments of this disclosure are not limited thereto. For example, the flexible circuit board CB can include control circuitry as a timing controller (TCON) 151.

[0061] Printed circuit board 160 can be electrically connected to one or more flexible circuit boards (or flexible films) CB, and can be a component that supplies signals to a driver IC. Printed circuit board 160 can be disposed on one side of the flexible circuit board (or flexible film) CB and electrically connected to the flexible circuit board (or flexible film) CB.

[0062] Various components for supplying different signals to the driver IC can be arranged on the printed circuit board 160. For example, various components such as timing controllers, power supplies, memory, or processors can be arranged on the printed circuit board 160. For example, the printed circuit board 160 may include a power management integrated circuit (PMIC) 161, but embodiments of this disclosure are not limited thereto.

[0063] The printed circuit board 160 may include at least one hole 180, but embodiments of this disclosure are not limited thereto. Internal components for sensing ambient light or temperature, which may be provided to multiple sensors, may be arranged in the area corresponding to at least one hole 180. For example, the internal components may include an ambient light sensor (ALS) or a temperature sensor, but embodiments of this disclosure are not limited thereto. For example, the hole 180 may be a transmission hole, etc., but embodiments of this disclosure are not limited thereto.

[0064] like Figure 1 As shown, the polarization layer 293 can be located on the display panel 100. The polarization layer 293 can prevent or reduce the entry of light generated by external light sources into the interior of the display panel 100 and affect the light-emitting elements, etc.

[0065] Cover member 120 may be disposed on polarizing layer 293. Cover member 120 may be a component for protecting display panel 100. Adhesive layer 295 may be disposed between polarizing layer 293 and cover member 120. Cover member 120 may be attached to display panel 100 via adhesive layer 295. Adhesive layer 295 may include, but is not limited to, optically clear adhesive (OCA), optically clear resin (OCR), or pressure-sensitive adhesive (PSA).

[0066] A support substrate 170 may be disposed between the display panel 100 and the printed circuit board 160. The support substrate 170 may enhance the rigidity of the display panel 100. The support substrate 170 may be a back plate, but the embodiments of this disclosure are not limited thereto.

[0067] Reference Figures 1 to 3 Multiple link wirings LL can be arranged in the non-display area NA. These link wirings LL can be wirings that transmit various signals from one or more flexible circuit boards (or flexible films) CB and printed circuit boards 160 to the display area AA. The multiple link wirings LL can extend from multiple pad electrodes PE in the second non-display area NA2 toward the curved area BA and the first non-display area NA1, and can be electrically connected to multiple drive wirings VL in the display area AA. Multiple pixel drive circuits PD can be driven by signals received from one or more flexible circuit boards (or flexible films) CB and printed circuit boards 160 via the drive wirings VL in the display area AA and the link wirings LL in the non-display area NA.

[0068] For example, multiple drive wirings VL can be used, together with multiple link wirings LL, to transmit signals output from the flexible circuit board (or flexible film) CB and printed circuit board 160 to multiple pixel driving circuits PD. The multiple drive wirings VL can be arranged in the display area AA and electrically connected to each of the multiple pixel driving circuits PD. The multiple drive wirings VL can extend from the display area AA towards the non-display area NA and can be electrically connected to the multiple link wirings LL. Therefore, signals output from the flexible circuit board (or flexible film) CB and printed circuit board 160 can be transmitted to each of the multiple pixel driving circuits PD through the multiple link wirings LL and the multiple drive wirings VL.

[0069] When the bending region BA bends, portions of the multiple link wirings LL may bend accordingly. Stress concentrates in the bent portions of the link wirings LL, which may cause the link wirings LL to crack. Therefore, the multiple link wirings LL can be formed of a conductive material with excellent ductility to reduce cracking of the bending region BA during bending. For example, the multiple link wirings LL can be formed of conductive materials with excellent ductility such as gold (Au), silver (Ag), aluminum (Al), etc., but embodiments of the present disclosure are not limited thereto. The multiple link wirings LL can also be formed of one of a variety of conductive materials used in the display region AA. For example, the multiple link wirings LL can be formed of an alloy of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and silver (Ag) and magnesium (Mg), or alloys thereof, but embodiments of the present disclosure are not limited thereto. The multiple link wirings LL can be formed of a multilayer structure comprising various conductive materials. For example, the multiple link wirings LL can be formed of a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but embodiments of the present disclosure are not limited thereto.

[0070] Multiple link wirings LL can be configured in various shapes to reduce stress. At least a portion of the multiple link wirings LL arranged in the curved region BA can extend in the same direction as the extension of the curved region BA, or in a different direction to reduce stress. For example, if the curved region BA extends in one direction from the first non-display region NA1 toward the second non-display region NA2, at least a portion of the link wirings LL arranged in the curved region BA can extend in a direction inclined relative to that direction. As another example, at least a portion of the multiple link wirings LL can be configured in various shaped patterns. For example, at least a portion of the multiple link wirings LL arranged in the curved region BA can be a shape in which a conductive pattern having at least one of rhombuses, oblique squares, trapezoids, triangular waveforms, sawtooth waveforms, sine waves, circles, and ω shapes is repeatedly arranged, but embodiments of this disclosure are not limited thereto. Therefore, in order to minimize or at least reduce the stress concentrated in the multiple link wirings LL and the resulting cracking, the shape of the multiple link wirings LL can be various shapes including the shapes described above, but embodiments of this disclosure are not limited thereto.

[0071] Figure 4 This is a diagram illustrating the circuit structure according to an embodiment of the present disclosure.

[0072] Although Figure 4A single light-emitting element (ED) connected to a micro-driver (μDriver) is shown, but this disclosure is not limited thereto. For example, eight EDs can be connected to a single micro-driver (μDriver). As another example, 16 EDs can be connected to a single micro-driver, or 32 or 64 EDs can be connected simultaneously to a single micro-driver. The EDs can be micro-LEDs.

[0073] A micro-driver μDriver may include a driving transistor T DR and light-emitting transistor T EM However, the implementation of this disclosure is not limited thereto. For example, driving transistor T DR It can have a first electrode to which a high-potential power voltage VDD is applied and connected to a light-emitting transistor T. EM The first electrode, the second electrode, and the gate electrode to which the scan signal SC is applied are applied to the driving transistor T. DR The scan signal SC of the gate electrode can be a DC voltage applied as a fixed reference voltage (Vref) for each frame, but the embodiments of this disclosure are not limited thereto.

[0074] Light-emitting transistor T EM It can have a connection to the driving transistor T DR The second electrode is connected to the first electrode of the second electrode, the second electrode is connected to the light-emitting element ED, and the gate electrode to which the emission signal EM is applied is applied to the light-emitting transistor T. EM The transmit signal EM of the gate electrode can be a pulse width modulated signal that varies with each frame, but the embodiments of this disclosure are not limited thereto.

[0075] The light-emitting element ED can have a connection to the light-emitting transistor T EM The second electrode is the first electrode and the grounded second electrode. For example, the first electrode of the light-emitting element ED can be the anode electrode, and the second electrode of the light-emitting element ED can be the cathode electrode, but the embodiments of this disclosure are not limited thereto. Driving transistor T DR and light-emitting transistor T EM Each of them can be an n-type transistor or a p-type transistor.

[0076] In the micro-driver μDriver, the driving transistor T DR The LED can be turned on by the scan signal SC applied from the timing controller TCON, and the LED T... EM It can be turned on by transmitting a signal EM. Therefore, by applying a signal to the driving transistor T... DR The high potential power voltage VDD of the first electrode drives the current through the driving transistor T. DR and light-emitting transistor TEM An application is made to the light-emitting element ED, causing the light-emitting element ED to emit light.

[0077] Figures 5 to 7 This is a plan view of a display device according to an embodiment of the present disclosure. For example, Figure 5 It is a magnified planar view of a display area that includes multiple pixels. For example, Figure 6 It is a magnified planar view of a display area including one pixel. For example, Figure 7 It is a magnified planar view of a display area that includes multiple pixels. Although Figure 5 and Figure 6 Only multiple signal wirings TL, multiple communication wirings NL, multiple first electrodes CE1, multiple dams BNK, and multiple light-emitting elements ED are shown, but the embodiments of this disclosure are not limited thereto. Figure 7 Is Figure 5 An enlarged planar view showing multiple second electrodes CE2 arranged in the middle.

[0078] like Figures 5 to 6 As shown, multiple pixels PX, consisting of multiple sub-pixels, can be arranged in the display area AA. Each sub-pixel can include a light-emitting element ED, which can emit light independently. The multiple sub-pixels can be arranged in a matrix to form multiple rows and columns, but the embodiments of this disclosure are not limited thereto.

[0079] The plurality of sub-pixels may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be a red sub-pixel, another may be a green sub-pixel, and the remainder may be a blue sub-pixel. The type of the plurality of sub-pixels is exemplary, and the implementation of this disclosure is not limited thereto.

[0080] Each pixel in a plurality of pixels PX may include one or more first sub-pixels SP1, one or more second sub-pixels SP2, and one or more third sub-pixels SP3. For example, a pixel PX may include a pair of first sub-pixels SP1, a pair of second sub-pixels SP2, and a pair of third sub-pixels SP3. The pair of first sub-pixels SP1 may consist of a first-first sub-pixel SP1a and a first-second sub-pixel SP1b. The pair of second sub-pixels SP2 may consist of a second-first sub-pixel SP2a and a second-second sub-pixel SP2b. The pair of third sub-pixels SP3 may consist of a third-first sub-pixel SP3a and a third-second sub-pixel SP3b. For example, a pixel PX may include first-first sub-pixels SP1a and first-second sub-pixels SP1b, second-first sub-pixels SP2a and second-second sub-pixels SP2b, and third-first sub-pixels SP3a and third-second sub-pixels SP3b, but the embodiments of this disclosure are not limited thereto.

[0081] The subpixels constituting a pixel PX can be arranged in various ways. For example, in a pixel PX, a pair of first subpixels SP1 can be arranged in the same column, a pair of second subpixels SP2 can be arranged in the same column, and a pair of third subpixels SP3 can be arranged in the same column. The first subpixels SP1, second subpixels SP2, and third subpixels SP3 can be arranged in the same row. The number and arrangement of the subpixels constituting a pixel PX are examples, and the implementation of this disclosure is not limited thereto.

[0082] Multiple signal wirings TL can be arranged in the area between multiple sub-pixels. Multiple signal wirings TL can extend along the column direction between multiple sub-pixels. Multiple signal wirings TL can be wiring that transmits the anode voltage from the pixel driving circuit PD to the multiple sub-pixels. For example, multiple signal wirings TL can be electrically connected to the multiple pixel driving circuits PD and the first electrode CE1 of the multiple sub-pixels. The anode voltage output from the pixel driving circuit PD can be transmitted to the first electrode CE1 of the multiple sub-pixels through the multiple signal wirings TL. For example, the first electrode CE1 can be the anode electrode 134 electrically connected to the light-emitting element ED (in...). Figure 9 The electrodes are shown in the diagram. Therefore, the anode voltage from the signal wiring TL can be transmitted through the first electrode CE1 to the anode electrode 134 of the light-emitting element ED.

[0083] Therefore, instead of forming multiple transistors and storage capacitors for each of the multiple sub-pixels, the structure of the display device 1000 can be simplified by using a pixel driving circuit PD with integrated multiple pixel circuits. Furthermore, by integrating the circuitry arranged for each of the multiple sub-pixels into a single pixel driving circuit PD, high-efficiency, low-power operation can be achieved.

[0084] Multiple signal wirings TL may include a first signal wiring TL1, a second signal wiring TL2, a third signal wiring TL3, a fourth signal wiring TL4, a fifth signal wiring TL5, and a sixth signal wiring TL6. Each of the first signal wiring TL1 and the second signal wiring TL2 can be electrically connected to each of a pair of first sub-pixels SP1. Each of the third signal wiring TL3 and the fourth signal wiring TL4 can be electrically connected to each of a pair of second sub-pixels SP2. Each of the fifth signal wiring TL5 and the sixth signal wiring TL6 can be electrically connected to each of a pair of third sub-pixels SP3.

[0085] A first signal wiring TL1 can be arranged on one side of a pair of first sub-pixels SP1, and a second signal wiring TL2 can be arranged on the other side of the pair of first sub-pixels SP1. The first signal wiring TL1 can be electrically connected to one of the pair of first sub-pixels SP1, such as the first electrode CE1 of the first sub-pixel SP1a. The second signal wiring TL2 can be electrically connected to the remaining pair of first sub-pixels SP1, such as the first electrode CE1 of the first sub-pixel SP1b.

[0086] A third signal wiring TL3 can be arranged on one side of a pair of second sub-pixels SP2, and a fourth signal wiring TL4 can be arranged on the other side of the pair of second sub-pixels SP2. For example, the third signal wiring TL3 can be arranged adjacent to the second signal wiring TL2. The third signal wiring TL3 can be electrically connected to one of the pair of second sub-pixels SP2, such as the first electrode CE1 of the second-first sub-pixel SP2a. The fourth signal wiring TL4 can be electrically connected to the remaining pair of second sub-pixels SP2, such as the first electrode CE1 of the second-second sub-pixel SP2b.

[0087] A fifth signal wiring TL5 can be arranged on one side of a pair of third sub-pixels SP3, and a sixth signal wiring TL6 can be arranged on the other side of the pair of third sub-pixels SP3. For example, the fifth signal wiring TL5 can be arranged adjacent to a fourth signal wiring TL4. The sixth signal wiring TL6 can be arranged adjacent to a first signal wiring TL1 connected to its adjacent pixel PX. The fifth signal wiring TL5 can be electrically connected to one of the pair of third sub-pixels SP3, such as the first electrode CE1 of the third-first sub-pixel SP3a. The sixth signal wiring TL6 can be electrically connected to the first electrode CE1 of the remaining pair of third sub-pixels SP3, such as the first electrode CE1 of the third-second sub-pixel SP3b.

[0088] Multiple signal wiring layers (TLs) can be made of conductive materials. For example, multiple signal wiring layers (TLs) can be formed from conductive materials such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the embodiments of this disclosure are not limited thereto. As another example, multiple signal wiring layers (TLs) can be formed from a multilayer structure of conductive materials. For example, multiple signal wiring layers (TLs) can be formed from a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) / indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto.

[0089] Multiple communication wirings NL can be arranged in the region between multiple pixels PX. Multiple communication wirings NL can extend along the row direction in the region between multiple pixels PX. Multiple communication wirings NL can be arranged in the region between multiple second electrodes CE2, and may not overlap with the multiple second electrodes CE2. For example, multiple communication wirings NL can be wiring for short-range communication such as near field communication (NFC). Multiple communication wirings NL can be used as antennas. For example, multiple communication wirings NL can be multiple connection wirings, etc., but embodiments of this disclosure are not limited thereto.

[0090] According to an example embodiment of this disclosure, a dam BNK can be located in each of a plurality of sub-pixels. The plurality of dam BNKs can be structures in which a plurality of light-emitting elements (EDs) are disposed. The plurality of dam BNKs can be used to guide the positioning of the plurality of light-emitting elements (EDs) during a transfer process of transferring the plurality of light-emitting elements (EDs) to the display device 1000. During the transfer of the plurality of light-emitting elements (EDs), the plurality of light-emitting elements (EDs) can be transferred onto the plurality of dam BNKs. The plurality of dam BNKs can be dam patterns or structures, etc., but embodiments of this disclosure are not limited thereto.

[0091] The BNKs of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be arranged to be spaced apart from each other. Therefore, the BNKs of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be easily identified to transfer different types of light-emitting elements (EDs).

[0092] The dam BNK of the first-first sub-pixel SP1a and the dam BNK of the first-second sub-pixel SP1b can be connected to each other, or they can be spaced apart from each other. For example, considering design requirements such as transfer process requirements, the dam BNK of the first-first sub-pixel SP1a and the dam BNK of the first-second sub-pixel SP1b, in which light-emitting elements ED of the same type are arranged, can be connected, spaced apart, or separated from each other. The dam BNK of the second-first sub-pixel SP2a and the dam BNK of the second-second sub-pixel SP2b can also be connected to each other, or they can be spaced apart from each other. The dam BNK of the third-first sub-pixel SP3a and the dam BNK of the third-second sub-pixel SP3b can also be connected to each other, or they can be spaced apart from each other. Therefore, a pair of dam BNK of first sub-pixels SP1, a pair of dam BNK of second sub-pixels SP2, and a pair of dam BNK of third sub-pixels SP3 can be formed in various ways, and the embodiments of this disclosure are not limited thereto.

[0093] For example, multiple dammed BNKs can be made of organic insulating materials. Multiple dammed BNKs can be formed from single or multiple layers of organic insulating materials. For example, multiple dammed BNKs can be formed from photoresist, polyimide (PI) or acrylic-based materials, but embodiments of this disclosure are not limited thereto.

[0094] A first electrode CE1 may be located on each of a plurality of sub-pixels. The first electrode CE1 may be located on a dam BNK. The first electrode CE1 may be electrically connected to one of a plurality of signal wirings TL. At least a portion of the first electrode CE1 may extend outward from the dam BNK and may be electrically connected to the signal wiring TL closest to the first electrode CE1. For example, a portion of the first electrode CE1 of the first-first sub-pixel SP1a may extend to one side of the first-first sub-pixel SP1a and be electrically connected to the first signal wiring TL1, and a portion of the first electrode CE1 of the first-second sub-pixel SP1b may extend to the other side of the first-second sub-pixel SP1b and be electrically connected to the second signal wiring TL2. A portion of the first electrode CE1 of the second-first sub-pixel SP2a may extend to one side of the second-first sub-pixel SP2a and be electrically connected to the third signal wiring TL3, and a portion of the first electrode CE1 of the second-second sub-pixel SP2b may extend to the other side of the second-second sub-pixel SP2b and be electrically connected to the fourth signal wiring TL4. A portion of the first electrode CE1 of the third-first sub-pixel SP3a may extend to one side of the third-first sub-pixel SP3a and be electrically connected to the fifth signal wiring TL5, and a portion of the first electrode CE1 of the third-second sub-pixel SP3b may extend to the other side of the third-second sub-pixel SP3b and be electrically connected to the sixth signal wiring TL6.

[0095] The first electrode CE1 is electrically connected to the anode electrode 134 of the light-emitting element ED, and the anode voltage can be transmitted from the pixel driving circuit PD to the light-emitting element ED via signal wiring TL. Depending on the image being displayed, a different voltage can be applied to the first electrode CE1 of each of the plurality of sub-pixels. For example, a different voltage can be applied to the first electrode CE1 of each of the plurality of sub-pixels. The first electrode CE1 can be a pixel electrode, and embodiments of this disclosure are not limited thereto.

[0096] The first electrode CE1 can be formed of a conductive material. For example, the first electrode CE1 can be integrally configured with multiple signal wirings TL. For example, the first electrode CE1 can be formed of the same conductive material as the multiple signal wirings TL, but the embodiments of this disclosure are not limited thereto. For example, the first electrode CE1 can be formed of conductive materials such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the embodiments of this disclosure are not limited thereto. As another example, the first electrode CE1 can be formed of a multilayer structure of conductive material. For example, multiple first electrodes CE1 can be made of a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) / indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto.

[0097] The light-emitting elements (EDs) can be arranged in each of the multiple sub-pixels. The multiple EDs can be light-emitting diodes (LEDs) or micro-LEDs, but embodiments of this disclosure are not limited thereto. The multiple EDs can be arranged on the diaphragm BNK and the first electrode CE1. The multiple EDs can be arranged on and electrically connected to the first electrode CE1. Therefore, the EDs can emit light by receiving an anode voltage from the pixel driving circuit PD via signal wiring TL and the first electrode CE1.

[0098] Multiple light-emitting elements (EDs) may include a first light-emitting element 130, a second light-emitting element 140, and a third light-emitting element 150. The first light-emitting element 130 may be arranged in a first sub-pixel SP1. The second light-emitting element 140 may be arranged in a second sub-pixel SP2. The third light-emitting element 150 may be arranged in a third sub-pixel SP3. For example, one of the first light-emitting element 130, the second light-emitting element 140, and the third light-emitting element 150 may be a red light-emitting element, another may be a green light-emitting element, and the remainder may be a blue light-emitting element; however, embodiments of this disclosure are not limited thereto. Therefore, various colors of light, including white, can be achieved by combining red, green, and blue light emitted by multiple light-emitting elements (EDs). The type of multiple light-emitting elements (EDs) is merely an example, and embodiments of this disclosure are not limited thereto.

[0099] The first light-emitting element 130 may include a first-first light-emitting element 130a disposed in the first-first sub-pixel SP1a and a first-second light-emitting element 130b disposed in the first-second sub-pixel SP1b. The second light-emitting element 140 may include a second-first light-emitting element 140a disposed in the second-first sub-pixel SP2a and a second-second light-emitting element 140b disposed in the second-second sub-pixel SP2b. The third light-emitting element 150 may include a third-first light-emitting element 150a disposed in the third-first sub-pixel SP3a and a third-second light-emitting element 150b disposed in the third-second sub-pixel SP3b.

[0100] like Figure 5 and Figure 6 as well as Figure 7 As shown, the second electrode CE2 can be arranged on each of the multiple sub-pixels. The second electrode CE2 can be located on the light-emitting element ED. The second electrode CE2 can be electrically connected to the pixel driving circuit PD through multiple contact electrodes CCE.

[0101] For example, the second electrode CE2 can be electrically connected to the cathode electrode 135 of the light-emitting element ED (in Figure 9 (As shown in the diagram), a cathode voltage from the pixel driving circuit PD is sent to the light-emitting element ED. The same cathode voltage can be applied to the second electrode CE2 of each of the plurality of sub-pixels. For example, the same voltage can be applied to the second electrode CE2 of each of the plurality of sub-pixels and the cathode electrode 135 of the light-emitting element ED. Therefore, the second electrode CE2 can be a common electrode, but embodiments of the present disclosure are not limited thereto.

[0102] At least some of the sub-pixels in a plurality of sub-pixels can share the second electrode CE2. At least some of the second electrodes CE2 in a plurality of sub-pixels can be electrically connected to each other. Because the same voltage is applied to the second electrodes CE2, at least some of the second electrodes CE2 in the sub-pixels can be shared and used. For example, the second electrodes CE2 of at least some of the pixels PX arranged in the same row can be connected to each other. For example, one second electrode CE2 can be arranged on multiple pixels PX. One second electrode CE2 can be arranged for each of n sub-pixels.

[0103] For example, some of the second electrodes CE2 of the plurality of sub-pixels may be spaced apart or separated from each other. For example, the second electrode CE2 connected to the nth row pixel PX and the second electrode CE2 connected to the (n+1)th row pixel PX may be spaced apart or separated from each other. For example, the plurality of second electrodes CE2 may be spaced apart from each other by a plurality of communication wirings NL extending in the row direction and inserted therebetween. Therefore, the number of the plurality of sub-pixels may be greater than the number of the plurality of second electrodes CE2. In another example, the second electrodes CE2 of the plurality of sub-pixels may all be connected to each other, such that only one second electrode CE2 is arranged on the substrate 110, and the embodiments of the present disclosure are not limited thereto.

[0104] Multiple second electrodes CE2 can be formed of a transparent conductive material, but embodiments of the present disclosure are not limited thereto. The multiple second electrodes CE2 can be made of a transparent conductive material such that light emitted from the light-emitting element ED is guided to the upper portion of the second electrodes CE2. For example, the second electrodes CE2 can be made of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but embodiments of the present disclosure are not limited thereto.

[0105] Multiple contact electrodes CCE may be located on the substrate 110. For example, the multiple contact electrodes CCE may be positioned to be spaced apart from multiple BNKs and multiple signal traces TL. Each of the multiple second electrodes CE2 may overlap with at least one contact electrode CCE. For example, one second electrode CE2 may overlap with multiple contact electrodes CCE.

[0106] For example, multiple contact electrodes CCE can be electrically connected to multiple second electrodes CE2. The multiple contact electrodes CCE are arranged between the substrate 110 and the multiple second electrodes CE2 to supply the cathode voltage from the pixel driving circuit PD to the second electrodes CE2.

[0107] For example, when using micro-LEDs as light-emitting elements (EDs), the display device 1000 can be manufactured by forming multiple micro-LEDs on a wafer and transferring them onto the substrate 110 of the display device 1000. During the process of transferring multiple light-emitting elements (EDs) with fine dimensions from the wafer to the substrate 110, various defects may occur. For example, in some sub-pixels, there may be non-transfer defects where the light-emitting element (ED) is not transferred, and in other sub-pixels, there may be defects caused by alignment errors where the light-emitting element (ED) is transferred out of position. Furthermore, even if the transfer process is completed normally, the transferred light-emitting element (ED) itself may be defective. Therefore, taking into account the defects during the transfer process of multiple light-emitting element (EDs), multiple light-emitting element (EDs) of the same type can be transferred to a single sub-pixel. Illumination tests are performed on the multiple light-emitting element (EDs), and only one light-emitting element (ED) that is ultimately determined to be normal can be used.

[0108] For example, first-first light-emitting element 130a and first-second light-emitting element 130b can be transferred together onto a single pixel PX and defects can be checked. If both first-first light-emitting element 130a and first-second light-emitting element 130b are determined to be normal, only first-first light-emitting element 130a can be used, but not first-second light-emitting element 130b. In another example, if only first-second light-emitting element 130b is determined to be normal, then first-first light-emitting element 130a cannot be used, but only first-second light-emitting element 130b can be used. Therefore, even if multiple light-emitting elements ED of the same type are transferred onto a single pixel PX, ultimately only one light-emitting element ED can be used.

[0109] Therefore, in a pair of light-emitting elements (EDs), one ED can be a primary ED or a secondary ED, and the other ED can be a redundant ED. The redundant ED can be a backup ED, prepared in case of defects in the primary ED. The redundant ED can be used as a substitute in case the primary ED is defective. Therefore, transferring both the primary and redundant EDs together onto a single pixel (PX) can minimize or at least reduce the degradation in display quality caused by defects in both the primary and redundant EDs.

[0110] For example, the first-first light-emitting element 130a, the second-first light-emitting element 140a, and the third-first light-emitting element 150a transferred to a pixel PX can be used as the main light-emitting element ED, while the first-second light-emitting element 130b, the second-second light-emitting element 140b, and the third-second light-emitting element 150b can be used as redundant light-emitting elements ED.

[0111] Figure 8 This is a cross-sectional view of a display device according to an embodiment of the present disclosure. Figure 9 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure. For example, Figure 8 It is a cross-sectional view of the display area AA, the first non-display area NA1, the curved area BA, and the second non-display area NA2.

[0112] like Figure 8 As shown, the first buffer layer 111a and the second buffer layer 111b can be disposed on the remaining area of ​​the substrate 110 excluding the bent region BA. The first buffer layer 111a and the second buffer layer 111b can be disposed in the display area AA, the first non-display area NA1, and the second non-display area NA2. The first buffer layer 111a and the second buffer layer 111b can reduce the penetration of moisture or impurities through the substrate 110. The first buffer layer 111a and the second buffer layer 111b can be made of an inorganic insulating material. For example, the first buffer layer 111a and the second buffer layer 111b can be formed from a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but the embodiments of this disclosure are not limited thereto.

[0113] For example, portions of the first buffer layer 111a and the second buffer layer 111b on the bending region BA can be removed. The top surface of the substrate 110 located in the bending region BA can be exposed from the first buffer layer 111a and the second buffer layer 111b. By removing the first buffer layer 111a and the second buffer layer 111b, which are made of inorganic insulating material, from the bending region BA, cracks in the first buffer layer 111a and the second buffer layer 111b that may occur during bending can be minimized or at least reduced.

[0114] Multiple alignment keys MK can be located between the first buffer layer 111a and the second buffer layer 111b. The multiple alignment keys MK can be configured to identify the position of the pixel driving circuit PD during the manufacturing process of the display device 1000. For example, the multiple alignment keys MK can be configured to align with the position of the pixel driving circuit PD transferred onto the adhesive layer 112. In another example, the multiple alignment keys MK can be omitted.

[0115] Adhesive layer 112 may be disposed on second buffer layer 111b. Adhesive layer 112 may be disposed in display area AA, first non-display area NA1, curved area BA, and second non-display area NA2. In another example, at least a portion of adhesive layer 112 may be removed from non-display area NA, including curved area BA. For example, adhesive layer 112 may be made of any of polymers, epoxy resins, UV-curable resins, polyimide-based, acrylate-based, polyurethane-based, and polydimethylsiloxane (PDMS), but embodiments of this disclosure are not limited thereto.

[0116] In the display area AA, the pixel driving circuit PD can be disposed on the adhesive layer 112. If the pixel driving circuit PD is implemented as a drive driver, the drive driver can be mounted on the adhesive layer 112 by a transfer process, but the embodiments of this disclosure are not limited thereto.

[0117] A first protective layer 113a and a second protective layer 113b can be disposed on the adhesive layer 112 and the pixel driving circuit PD. The first protective layer 113a and the second protective layer 113b can be disposed around the side surface of the pixel driving circuit PD, but embodiments of this disclosure are not limited thereto. For example, the second protective layer 113b can be disposed to cover at least a portion of the top surface of the pixel driving circuit PD. For example, at least one of the first protective layer 113a and the second protective layer 113b disposed on the curved region BA can be omitted. For example, the first protective layer 113a can be disposed entirely in the display area AA and the non-display area NA, and the second protective layer 113b can be disposed partially in the display area AA, the first non-display area NA1, and the second non-display area NA2. For example, a portion of the second protective layer 113b in the curved region BA can be removed. However, embodiments of this disclosure are not limited thereto.

[0118] The first protective layer 113a and the second protective layer 113b may be formed of organic insulating materials, but the embodiments of this disclosure are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b may be formed of photoresist, polyimide (PI), or photoacrylic-based materials, but the embodiments of this disclosure are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b may be an outer coating or an insulating layer, but the embodiments of this disclosure are not limited thereto.

[0119] According to this disclosure, a plurality of first connection wirings 121 can be arranged on the second protective layer 113b in the display area AA. The plurality of first connection wirings 121 can be wirings used to electrically connect a pixel driving circuit PD to other components. For example, the pixel driving circuit PD can be electrically connected to a plurality of signal wirings TL and a plurality of contact electrodes CCE, etc., through the plurality of first connection wirings 121. For example, the plurality of first connection wirings 121 may include a first-first connection wiring 121a, a first-second connection wiring 121b, a first-third connection wiring 121c, and a first-fourth connection wiring 121d, but the embodiments of this disclosure are not limited thereto.

[0120] For example, multiple first-to-first connection lines 121a can be arranged on the second protective layer 113b. The multiple first-to-first connection lines 121a can be electrically connected to the pixel driving circuit PD. The multiple first-to-first connection lines 121a can transmit the voltage output from the pixel driving circuit PD to the first electrode CE1 or the second electrode CE2.

[0121] For example, a third protective layer 114 may be disposed on the second protective layer 113b. The third protective layer 114 may be completely disposed in the display area AA and the non-display area NA. In the curved area BA, the third protective layer 114 may cover the side surface of the second protective layer 113b and the top surface of the first protective layer 113a. The third protective layer 114 may be formed of an organic insulating material. For example, the third protective layer 114 may be formed of a photoresist, polyimide (PI), or photoacrylic-based material, but embodiments of this disclosure are not limited thereto. For example, the first protective layer 113a, the second protective layer 113b, and the third protective layer 114 may be formed of the same material, but embodiments of this disclosure are not limited thereto. Embodiments of this disclosure are not limited to those described above. A first insulating layer 115a may be disposed on the third protective layer 114. The first insulating layer 115a may be completely disposed in the display area AA and the non-display area NA, but embodiments of this disclosure are not limited thereto. The first insulating layer 115a may be formed of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the first insulating layer 115a may be formed of a photoresist, polyimide (PI) or photoacrylic-based material, but the embodiments of this disclosure are not limited thereto.

[0122] Multiple first-second connection wires 121b can be arranged on the first insulating layer 115a. These multiple first-second connection wires 121b can be connected to or directly connected to the pixel driving circuit PD. For example, some of the first-second connection wires 121b can be directly connected to the pixel driving circuit PD through contact holes in the first insulating layer 115a and the third protective layer 114. Other first-second connection wires 121b can be electrically connected to the first-first connection wire 121a through contact holes in the first insulating layer 115a and the third protective layer 114. However, embodiments of this disclosure are not limited thereto. The voltage output from the pixel driving circuit PD can be sent to the first electrode CE1 or the second electrode CE2 through connection wires other than the multiple first-second connection wires 121b.

[0123] The second insulating layer 115b can be formed on a plurality of first-second connection wirings 121b. The second insulating layer 115b can be completely disposed in the display area AA and the non-display area NA, but embodiments of the present disclosure are not limited thereto. The second insulating layer 115b can be formed of an organic insulating material, but embodiments of the present disclosure are not limited thereto. For example, the second insulating layer 115b can be formed of a photoresist, polyimide (PI), or photoacrylic acid-based material, but embodiments of the present disclosure are not limited thereto.

[0124] Multiple first-third connection wires 121c can be arranged on the second insulating layer 115b. The first-third connection wires 121c can be electrically connected to multiple first-second connection wires 121b. For example, the first-third connection wires 121c can be electrically connected to the first-second connection wires 121b through contact holes in the second insulating layer 115b.

[0125] The third insulating layer 115c can be disposed on a plurality of first-third connecting wires 121c. The third insulating layer 115c can be disposed in the remaining areas except for the curved region BA, but embodiments of this disclosure are not limited thereto. The third insulating layer 115c can be disposed in the display region AA, the first non-display region NA1, and the second non-display region NA2, but embodiments of this disclosure are not limited thereto. For example, a portion of the third insulating layer 115c in the curved region BA can be removed. The third insulating layer 115c can be formed of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the third insulating layer 115c can be formed of a photoresist, polyimide (PI), or photoacrylic acid-based material, but embodiments of this disclosure are not limited thereto.

[0126] Multiple first-fourth connection wires 121d can be arranged on the third insulating layer 115c. The multiple first-fourth connection wires 121d can be electrically connected to multiple first-third connection wires 121c. For example, the first-fourth connection wires 121d can be electrically connected to the first-third connection wires 121c via contact holes in the third insulating layer 115c.

[0127] According to the example of this disclosure, a plurality of second connection wires 122 may be arranged on a second protective layer 113b in the display area NA. The plurality of second connection wires 122 are for connecting the flexible circuit board (or flexible film) CB and the printed circuit board (…). Figure 1 The signal sent to the pad portion PAD (160) is transmitted to the pixel driving circuit PD of the display area AA via wiring. For example, multiple second connection wirings 122 can be electrically connected to multiple pad electrodes PE to receive signals from the flexible circuit board (or flexible film) CB and the printed circuit board.

[0128] For example, a plurality of second connection lines 122 may extend from the pad portion PAD toward the display area AA to send signals to the wiring in the display area AA. In this case, the plurality of second connection lines 122 may be used as link lines LL. The plurality of second connection lines 122 may include a second-first connection line 122a, a second-second connection line 122b, a second-third connection line 122c, and a second-fourth connection line 122d.

[0129] Multiple second-first connection wirings 122a can be arranged on the second protective layer 113b. These multiple second-first connection wirings 122a can extend from the second non-display area NA2 to the curved area BA and the first non-display area NA1. The multiple second-first connection wirings 122a can transmit signals already sent from the flexible circuit board (or flexible film) CB and the printed circuit board to the pad portion PAD to the pixel driving circuit PD in the display area AA.

[0130] Multiple second-to-second connection wires 122b can be arranged on the first insulating layer 115a. Multiple second-to-second connection wires 122b can be arranged on the second non-display area NA2. The second-to-second connection wires 122b can be electrically connected to the second-to-first connection wire 122a through contact holes in the first insulating layer 115a and the third protective layer 114. Therefore, signals from the flexible circuit board (or flexible film) (CB) and the printed circuit board can be transmitted to the second-to-first connection wire 122a through the second-to-second connection wires 122b.

[0131] Multiple second-third connection wires 122c can be arranged on the second insulating layer 115b. The second-third connection wires 122c can be arranged in the second non-display area NA2. The second-third connection wires 122c can be electrically connected to the second-second connection wire 122b through contact holes in the second insulating layer 115b. Therefore, signals from the flexible circuit board (or flexible film) (CB) and the printed circuit board can be transmitted to the second-first connection wire 122a through the second-third connection wires 122c and the second-second connection wires 122b.

[0132] Multiple second-fourth connection wires 122d can be arranged on the third insulating layer 115c. The second-fourth connection wires 122d can be arranged in the second non-display area NA2. The second-fourth connection wires 122d can be electrically connected to the second-third connection wire 122c through contact holes in the third insulating layer 115c. Therefore, signals from the flexible film (FF) and the printed circuit board can be transmitted to the second-first connection wire 122a through the second-fourth connection wires 122d, the second-third connection wire 122c, and the second-second connection wire 122b.

[0133] The plurality of first connection wires 121 and the plurality of second connection wires 122 may be formed of any of a conductive material with excellent ductility or a variety of conductive materials used in the display area AA. For example, a portion of the second connection wires 122 disposed in the curved area BA may be made of a conductive material with excellent ductility such as gold (Au), silver (Ag), or aluminum (Al), but embodiments of the present disclosure are not limited thereto. As another example, the plurality of first connection wires 121 and the plurality of second connection wires 122 may be formed of an alloy of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and silver (Ag) and magnesium (Mg), or an alloy thereof, but embodiments of the present disclosure are not limited thereto.

[0134] The fourth insulating layer 115d can be disposed on a plurality of first connecting wires 121 and a plurality of second connecting wires 122. The fourth insulating layer 115d can be disposed in the remaining areas except for the curved region BA, but embodiments of this disclosure are not limited thereto. The fourth insulating layer 115d can be disposed in the display region AA, the first non-display region NA1, and the second non-display region NA2. A portion of the fourth insulating layer 115d in the curved region BA can be removed. The fourth insulating layer 115d can be formed of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the fourth insulating layer 115d can be formed of a photoresist, polyimide (PI), or photoacrylic-based material, but embodiments of this disclosure are not limited thereto.

[0135] In the display area AA, multiple dams BNK can be arranged on the fourth insulating layer 115d. The multiple dams BNK can be arranged to overlap with each of the multiple sub-pixels. One or more light-emitting elements ED of the same type can be arranged in the upper portion of each dam of the multiple dams BNK.

[0136] In the display area AA, multiple signal traces TL can be arranged on the fourth insulating layer 115d. Multiple signal traces TL can be arranged in the area between multiple dams BNK. For example, multiple signal traces TL can be arranged adjacent to any one of the multiple dams BNK.

[0137] Multiple contact electrodes CCE can be arranged on the fourth insulating layer 115d in the display area AA. The multiple contact electrodes CCE can supply the cathode voltage from the pixel driving circuit PD to the second electrode CE2.

[0138] The first electrode CE1 can be disposed on the dam BNK. For example, the first electrode CE1 can be disposed extending from the adjacent signal wiring TL toward the upper portion of the dam BNK. The first electrode CE1 can be disposed on the top surface and side surface of the dam BNK. For example, the first electrode CE1 can be disposed extending from the signal wiring TL on the top surface of the fourth insulating layer 115d to the side surface and top surface of the dam BNK.

[0139] Reference Figure 9 The first electrode CE1 may be composed of multiple conductive layers. For example, the first electrode CE1 may include a first conductive layer CE1a, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d, but the embodiments of this disclosure are not limited thereto.

[0140] The first conductive layer CE1a can be disposed on the embankment BNK. The second conductive layer CE1b can be disposed on the first conductive layer CE1a. The third conductive layer CE1c can be disposed on the second conductive layer CE1b. The fourth conductive layer CE1d can be disposed on the third conductive layer CE1c. For example, each of the first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can be formed of titanium (Ti), molybdenum (Mo), aluminum (Al), or titanium (Ti) and indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto.

[0141] According to an exemplary embodiment of this disclosure, some of the conductive layers constituting the first electrode CE1 and having good reflectivity can be configured as alignment keys and / or reflectors for aligning the light-emitting element ED. For example, the second conductive layer CE1b of the plurality of conductive layers of the first electrode CE1 may include a reflective material. For example, the second conductive layer CE1b may include aluminum (Al), but embodiments of this disclosure are not limited thereto. In this way, the second conductive layer CE1b can be configured as a reflector. Furthermore, the high reflectivity of the second conductive layer CE1b can facilitate easy identification during the manufacturing process, allowing the light-emitting element ED or the transfer position of the light-emitting element ED to be aligned relative to the second conductive layer CE1b.

[0142] For example, to configure the second conductive layer CE1b as a reflector, the third conductive layer CE1c and the fourth conductive layer CE1d covering the second conductive layer CE1b can be partially removed or etched away. For example, portions of the third conductive layer CE1c and the fourth conductive layer CE1d disposed on the embankment BNK can be partially removed or etched away to expose the top surface of the second conductive layer CE1b. For example, the third conductive layer CE1c and the fourth conductive layer CE1d can be removed except for the central and boundary (or edge) portions of these layers on which the solder pattern SDP is placed. For example, the boundary (or edge) portions of each of the third conductive layer CE1c made of titanium (Ti) and the fourth conductive layer CE1d made of indium tin oxide (ITO) can be left unetched. Therefore, the other conductive layers of the first electrode CE1 can be prevented from being etched by the TMAH (tetramethylammonium hydroxide) solution used in the masking process of the first electrode CE1.

[0143] According to this disclosure, the first conductive layer CE1a and the third conductive layer CE1c may comprise titanium (Ti) or molybdenum (Mo). The second conductive layer CE1b may comprise aluminum (Al). The fourth conductive layer CE1d may comprise a transparent conductive oxide layer, such as indium tin oxide (ITO) or indium zinc oxide (IZO), which has good adhesion to the solder pattern SDP and is corrosion-resistant and acid-resistant. However, embodiments of this disclosure are not limited thereto.

[0144] The first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can be deposited sequentially and then patterned by photolithography and etching processes, but the embodiments of this disclosure are not limited thereto.

[0145] According to this disclosure, the signal wiring TL, contact electrode CCE, and pad electrode PE, which are disposed in the same layer as the first electrode CE1, can be formed of multilayer conductive materials; however, the embodiments of this disclosure are not limited thereto. For example, the signal wiring TL, contact electrode CCE, and pad electrode PE can be made of a multilayer of indium tin oxide (ITO) / titanium (Ti) / aluminum (Al) / titanium (Ti); however, the embodiments of this disclosure are not limited thereto.

[0146] According to this disclosure, a solder pattern SDP can be disposed on a first electrode CE1 in each of a plurality of sub-pixels. The solder pattern SDP can bond a light-emitting element ED to the first electrode CE1. The first electrode CE1 and the light-emitting element ED can be electrically connected to each other via eutectic bonding using the solder pattern SDP, but embodiments of this disclosure are not limited thereto. For example, the first electrode CE1 and the anode electrode 134 of the light-emitting element ED can be electrically connected via eutectic bonding using the solder pattern SDP, but embodiments of this disclosure are not limited thereto. For example, if the solder pattern SDP is formed of indium (In) and the anode electrode 134 of the light-emitting element ED is formed of gold (Au), the solder pattern SDP and the anode electrode 134 can be bonded by applying heat and pressure during the transfer process of the light-emitting element ED. Eutectic bonding allows the light-emitting element ED to be bonded to the solder pattern SDP and the first electrode CE1 without a separate adhesive. For example, the solder pattern SDP can be formed of indium (In), tin (Sn), or alloys thereof, but embodiments of this disclosure are not limited thereto. For example, the solder pattern SDP can be a bonding pad or an adhesive pad, but the embodiments of this disclosure are not limited thereto.

[0147] According to examples of this disclosure, passivation layer 116 can be disposed on multiple signal traces TL, multiple first electrodes CE1, multiple contact electrodes CCE, and a fourth insulating layer 115d. For example, passivation layer 116 can be disposed in display area AA, first non-display area NA1, and second non-display area NA2. A portion of passivation layer 116 disposed in curved area BA can be removed. A portion of passivation layer 116 covering multiple pad electrodes PE in second non-display area NA2 can be removed. Passivation layer 116 can be disposed to cover the remaining area except for the area where curved area BA, multiple pad electrodes PE, and solder pattern SDP are disposed, thereby reducing the penetration of moisture or impurities into light-emitting element ED. For example, passivation layer 116 can be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but embodiments of this disclosure are not limited thereto. For example, passivation layer 116 can be a protective layer, insulating layer, etc., but embodiments of this disclosure are not limited thereto. For example, passivation layer 116 may include holes exposing solder pattern SDP.

[0148] The light-emitting elements ED can be arranged on the welding pattern SDP in each of the multiple sub-pixels. The first light-emitting element 130 can be arranged in the first sub-pixel SP1. The second light-emitting element 140 can be arranged in the second sub-pixel SP2. The third light-emitting element 150 can be arranged in the third sub-pixel SP3.

[0149] Light-emitting elements (EDs) can be formed on silicon wafers by methods such as metal-organic vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam growth (MBE), hydride vapor deposition (HVPE), or sputtering, but the embodiments of this disclosure are not limited thereto.

[0150] Reference Figure 9 The first light-emitting element 130 may include an anode electrode 134, a first semiconductor layer 131, an active layer 132, a second semiconductor layer 133, a cathode electrode 135, and an encapsulation film 136, but the embodiments of this disclosure are not limited thereto. For example, the encapsulation film 136 may not be included in the first light-emitting element 130.

[0151] The first semiconductor layer 131 can be disposed on the solder pattern SDP. The second semiconductor layer 133 can be disposed on the first semiconductor layer 131. For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 can be implemented as a compound semiconductor such as a III-V group, II-VI group, etc., and can be doped with impurities (or dopants). For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 can be a semiconductor layer doped with n-type impurities, and the other can be a semiconductor layer doped with p-type impurities, but the embodiments of this disclosure are not limited thereto. For example, one or more of the first semiconductor layer 131 and the second semiconductor layer 133 can be layers doped with n-type or p-type impurities on materials such as gallium nitride (GaN), gallium phosphide (GaP), aluminum gallium indium phosphide (AlGaInP), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs), or gallium arsenide (GaAs), but the embodiments of this disclosure are not limited thereto. For example, n-type impurities can be silicon (Si), germanium (Ge), selenium (Se), carbon (C), tellurium (Te), or tin (Sn), but the embodiments of this disclosure are not limited thereto. For example, p-type impurities can be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or beryllium (Be), but the embodiments of this disclosure are not limited thereto.

[0152] For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be a nitride semiconductor containing n-type impurities and a nitride semiconductor containing p-type impurities, respectively, but the embodiments of this disclosure are not limited thereto. For example, the first semiconductor layer 131 may be a nitride semiconductor containing p-type impurities, and the second semiconductor layer 133 may be a nitride semiconductor containing n-type impurities, but the embodiments of this disclosure are not limited thereto.

[0153] The active layer 132 may be disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The active layer 132 can emit light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. For example, the active layer 132 may be composed of one of a single-well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but the embodiments of this disclosure are not limited thereto. For example, the active layer 132 may be formed of indium gallium nitride (InGaN) or gallium nitride (GaN), but the embodiments of this disclosure are not limited thereto.

[0154] For another example, the active layer 132 may comprise a multiple quantum well (MQW) structure having a well layer and a barrier layer with a higher bandgap than the well layer. For instance, the active layer 132 may be formed of an InGaN layer as the well layer and an AlGaN layer as the barrier layer, but embodiments of this disclosure are not limited thereto.

[0155] An anode electrode 134 may be disposed between the first semiconductor layer 131 and the solder pattern SDP. For example, the anode electrode 134 may be electrically connected to the first semiconductor layer 131 and the first electrode CE1. The anode voltage output from the pixel driving circuit PD may be applied to the first semiconductor layer 131 through signal wiring TL, the first electrode CE1, and the anode electrode 134. For example, the anode electrode 134 may be formed of a conductive material that can be eutecticly bonded to the solder pattern SDP, but embodiments of the present disclosure are not limited thereto. For example, the anode electrode 134 may be formed of gold (Au), tin (Sn), tungsten (W), silicon (Si), silver (Ag), titanium (Ti), iridium (Ir), chromium (Cr), indium (In), zinc (Zn), lead (Pb), nickel (Ni), platinum (Pt), and copper (Cu), or alloys thereof, but embodiments of the present disclosure are not limited thereto.

[0156] The cathode electrode 135 may be disposed on the second semiconductor layer 133. For example, the cathode electrode 135 may be electrically connected to the second semiconductor layer 133 and the second electrode CE2. The cathode voltage output from the pixel driving circuit PD may be applied to the second semiconductor layer 133 through the contact electrode CCE, the second electrode CE2, and the cathode electrode 135. The cathode electrode 135 may be formed of a transparent conductive material to allow light emitted from the ED to be guided to the upper portion of the ED, but embodiments of this disclosure are not limited thereto. For example, the cathode electrode 135 may be formed of a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), but embodiments of this disclosure are not limited thereto.

[0157] The encapsulation film 136 may be disposed on at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135. For example, the encapsulation film 136 may surround at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135.

[0158] For example, the encapsulation film 136 can protect the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. For example, the encapsulation film 136 can be disposed on the side surface of the first semiconductor layer 131, the side surface of the active layer 132, and the side surface of the second semiconductor layer 133.

[0159] For example, the encapsulation film 136 may be disposed on at least a portion of the anode electrode 134 and the cathode electrode 135, such as the edge portion (or one side) of the anode electrode 134 and the edge portion (or one side) of the cathode electrode 135. At least a portion of the anode electrode 134 may be exposed from the encapsulation film 136, thereby enabling the anode electrode 134 and the solder pattern SDP to be connected. For example, at least a portion of the cathode electrode 135 may be exposed from the encapsulation film 136, thereby enabling the cathode electrode 135 and the second electrode CE2 to be connected. For example, the encapsulation film 136 may be formed of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), but embodiments of this disclosure are not limited thereto.

[0160] For another example, the encapsulation film 136 may have a structure in which reflective material is dispersed in a resin layer, but embodiments of the present disclosure are not limited thereto. For example, the encapsulation film 136 may be manufactured as a reflector with various structures, but embodiments of the present disclosure are not limited thereto. Light excited from the active layer 132 is reflected upward by the encapsulation film 136 to improve light extraction efficiency. For example, the encapsulation film 136 may be a reflective layer, but embodiments of the present disclosure are not limited thereto.

[0161] Although the light-emitting element (ED) is described herein as having a vertical structure, embodiments of this disclosure are not limited thereto. For example, the ED may have a horizontal structure or a flip-chip structure.

[0162] Although it has been referenced Figure 9 The first light-emitting element 130 has been described, but the second light-emitting element 140 and the third light-emitting element 150 may have substantially the same structure as the first light-emitting element 130. For example, the second light-emitting element 140 and the third light-emitting element 150 may be substantially the same as the first light-emitting element 130 having a first semiconductor layer 131, an active layer 132, a second semiconductor layer 133, an anode electrode 134, a cathode electrode 135, and an encapsulation film 136.

[0163] According to an exemplary embodiment of this disclosure, the first optical layer 117a can be arranged to surround a plurality of light-emitting elements ED in a display area AA. For example, the first optical layer 117a can be arranged in a plurality of sub-pixel regions to cover a plurality of light-emitting elements ED and a dam BNK. For example, the first optical layer 117a can cover the dam BNK, a portion of the passivation layer 116, and the plurality of light-emitting elements ED. The first optical layer 117a can be arranged between or cover a plurality of light-emitting elements ED included in a pixel PX, and arranged between a plurality of dam BNK. For example, the first optical layer 117a can extend in a first direction (X-axis direction) and can be spaced apart in a second direction (Y-axis direction). For example, the first optical layer 117a can be arranged between the passivation layer 116 and the second electrode CE2 to surround the sides of the light-emitting elements ED and the dam BNK, but the embodiments of this disclosure are not limited thereto. For example, the first optical layer 117a can be a diffusion layer, a sidewall diffusion layer, etc., but the embodiments of this disclosure are not limited thereto.

[0164] The first optical layer 117a may include an organic insulating material in which fine particles are dispersed, but embodiments of the present disclosure are not limited thereto. For example, the first optical layer 117a may be formed of a siloxane in which fine metal particles, such as titanium dioxide (TiO2) particles, are dispersed, but embodiments of the present disclosure are not limited thereto. Light from the multiple light-emitting elements (EDs) can be scattered by the fine particles dispersed in the first optical layer 117a and emitted to the outside of the display device 1000. This ensures that the first optical layer 117a improves the extraction efficiency of light emitted from the multiple light-emitting elements (EDs).

[0165] For example, the first optical layer 117a may be arranged in each of the plurality of pixels PX, or may be arranged together in some of the pixels PX arranged in the same row, but the embodiments of the present disclosure are not limited thereto. For example, the first optical layer 117a may be arranged in each of the plurality of pixels PX, or a first optical layer 117a may be shared by the plurality of pixels PX. For another example, each of the plurality of sub-pixels may each include the first optical layer 117a, but the embodiments of the present disclosure are not limited thereto.

[0166] The second optical layer 117b can be disposed on the passivation layer 116 in the display area AA. For example, the second optical layer 117b can be disposed around the first optical layer 117a. For example, the second optical layer 117b can be adjacent to the side surface of the first optical layer 117a. For example, the second optical layer 117b can be disposed in the area between a plurality of pixels PX. However, the embodiments of the present disclosure are not limited thereto. For example, the second optical layer 117b can be a diffusion layer, a diffusion layer window, or a window diffusion layer, but the embodiments of the present disclosure are not limited thereto.

[0167] The second optical layer 117b may be formed of an organic insulating material, but embodiments of the present disclosure are not limited thereto. The second optical layer 117b may be formed of the same material as the first optical layer 117a, but embodiments of the present disclosure are not limited thereto. For example, the first optical layer 117a may include fine particles, and the second optical layer 117b may not include fine particles. For example, the second optical layer 117b may be made of siloxane, but embodiments of the present disclosure are not limited thereto.

[0168] For example, the thickness of the first optical layer 117a may be less than the thickness of the second optical layer 117b, but the embodiments of this disclosure are not limited thereto. Therefore, when viewed from a plane, the area in which the first optical layer 117a is disposed may include a recessed portion recessed inward from the upper surface of the second optical layer 117b.

[0169] The second electrode CE2 can be disposed on the first optical layer 117a and the second optical layer 117b. For example, the second electrode CE2 can be electrically connected to multiple contact electrodes CCE through contact holes in the second optical layer 117b. For example, the second electrode CE2 can be disposed on multiple light-emitting elements ED. For example, the second electrode CE2 can include a transparent conductive oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of this disclosure are not limited thereto. For example, the second electrode CE2 can be disposed in contact with the cathode electrode 135. For example, the second electrode CE2 can overlap with the first optical layer 117a. For example, the second electrode CE2 can cover the outer plane of the first optical layer 117a.

[0170] The second electrode CE2 can extend continuously in the first direction (X-axis direction) of the substrate 110. Therefore, it can be commonly connected to a plurality of pixels PX arranged in the first direction (X-axis direction) of the substrate 110. For example, the second electrode CE2 can be commonly connected to a plurality of pixels PX.

[0171] The second electrode CE2 can extend continuously over the first optical layer 117a, the second optical layer 117b, and the light-emitting element ED. The region where the first optical layer 117a is disposed may include a recessed portion that is recessed inward from the upper surface of the second optical layer 117b. Therefore, the first portion of the second electrode CE2 disposed on the first optical layer 117a is arranged along the recessed portion, such that it can be located at a lower position than the second portion of the second electrode CE2 disposed on the second optical layer 117b.

[0172] The third optical layer 117c can be disposed on the second electrode CE2. The third optical layer 117c can be arranged to overlap with the plurality of light-emitting elements ED and the first optical layer 117a. The third optical layer 117c can be disposed on the upper portion of the second electrode CE2 and the plurality of light-emitting elements ED, thereby improving the mura that may occur in some of the plurality of light-emitting elements ED. For example, when the plurality of light-emitting elements ED are transferred to the substrate 110 of the display device 1000, regions with uneven spacing between the plurality of light-emitting elements ED may appear due to process variations. If the spacing between the plurality of light-emitting elements ED is uneven, the emission areas of the plurality of light-emitting elements ED may be unevenly arranged, causing the unevenness to be visible to the user. Because the third optical layer 117c can be formed to uniformly diffuse light onto the plurality of light-emitting elements ED, the visual perception of unevenness of light emitted from some of the light-emitting elements ED can be reduced. Therefore, the light emitted from the multiple light-emitting elements ED is uniformly diffused through the third optical layer 117c and extracted to the outside of the display device 1000, which can improve the brightness uniformity of the display device 1000.

[0173] The third optical layer 117c can be formed from an organic insulating material in which fine particles are dispersed, but the embodiments of this disclosure are not limited thereto. For example, the third optical layer 117c can be formed from a siloxane in which fine metal particles, such as titanium dioxide (TiO2) particles, are dispersed, but the embodiments of this disclosure are not limited thereto. For example, the third optical layer 117c can be formed from the same material as the first optical layer 117a, but the embodiments of this disclosure are not limited thereto. For example, the third optical layer 117c can be a diffusion layer, a top surface diffusion layer, etc., but the embodiments of this disclosure are not limited thereto.

[0174] Light from multiple light-emitting elements (EDs) can be scattered by fine particles dispersed in the third optical layer 117c and emitted to the outside of the display device 1000. The third optical layer 117c can further improve the brightness uniformity of the display device 1000 by uniformly mixing the light emitted from the multiple light-emitting elements (EDs). In addition, the light scattered from the multiple fine particles can improve the light extraction efficiency of the display device 1000, thereby enabling the display device 1000 to be driven with low power.

[0175] The black matrix BM can be disposed on the second electrode CE2, the first optical layer 117a, the second optical layer 117b, and the third optical layer 117c in the display area AA. For example, the black matrix BM can fill the contact holes in the second optical layer 117b. The black matrix BM can be configured to cover the display area AA, thereby reducing color mixing of light from multiple sub-pixels and reflection of external light. For example, the black matrix BM can also be disposed within the contact holes connecting the second electrode CE2 and the contact electrode CCE, which can prevent light leakage between multiple adjacent sub-pixels.

[0176] For example, the black matrix BM can be formed of an opaque material, but embodiments of the present disclosure are not limited thereto. For example, the black matrix BM can be a black pigment or an organic insulating material to which a black dye has been added, but embodiments of the present disclosure are not limited thereto.

[0177] In the display area AA, a cover layer 119 may be disposed on the black matrix BM. The cover layer 119 may protect the configuration beneath it. For example, the cover layer 119 may be formed of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the cover layer 119 may be formed of a photoresist, polyimide (PI), or photopropylene-based material, but embodiments of this disclosure are not limited thereto. For example, the cover layer 119 may be an outer coating or an insulating layer, but embodiments of this disclosure are not limited thereto.

[0178] The polarizing layer 293 can be disposed on the cover layer 119 via the first adhesive layer 291. The cover member 120 can be disposed on the polarizing layer 293 via the second adhesive layer 295. For example, the first adhesive layer 291 and the second adhesive layer 295 may include optically transparent adhesive (OCA), optically transparent resin (OCR), or pressure-sensitive adhesive (PSA), but embodiments of this disclosure are not limited thereto.

[0179] Multiple pad electrodes PE can be disposed on the fourth insulating layer 115d in the second non-display area NA2. For example, at least a portion of the multiple pad electrodes PE can be exposed from the passivation layer 116. For example, the multiple pad electrodes PE can be electrically connected to the second-fourth connection wiring 122d through contact holes in the fourth insulating layer 115d.

[0180] An adhesive layer ACF can be disposed on multiple pad electrodes PE. The adhesive layer ACF may be an adhesive layer in which conductive spheres are dispersed in an insulating material, but embodiments of this disclosure are not limited thereto. When heat or pressure is applied to the adhesive layer ACF, the conductive spheres can become electrically connected and exhibit conductive properties at the points where heat or pressure is applied. The adhesive layer ACF can be disposed between multiple pad electrodes PE and a flexible circuit board (or flexible film) CB to attach or bond the flexible circuit board (or flexible film) CB to the multiple pad electrodes PE. For example, the adhesive layer ACF may be an anisotropic conductive film (ACF), but embodiments of this disclosure are not limited thereto.

[0181] The flexible circuit board (or flexible film) CB can be disposed on the adhesive layer ACF. The flexible circuit board (or flexible film) CB can be electrically connected to multiple pad electrodes PE through the adhesive layer ACF. Therefore, signals output from the flexible circuit board (or flexible film) CB and the printed circuit board can be transmitted to the pixel driving circuit PD of the display area AA through the multiple pad electrodes PE, the second-fourth connection wiring 122d, the second-third connection wiring 122c, the second-second connection wiring 122b, and the second-first connection wiring 122a.

[0182] Figures 10 to 13 This is a diagram illustrating an apparatus for using a display device according to an embodiment of the present disclosure.

[0183] like Figures 10 to 13 As shown, the display device 1000 can be included in various devices or electronic components. For example, various electronic devices may include wearable device 1100, mobile device 1200, laptop computer 1300, and monitor or television (TV) 1400, but embodiments of this disclosure are not limited thereto.

[0184] Wearable device 1100, mobile device 1200, laptop computer 1300, and monitor or TV 1400 may include their respective housing portions 1005, 1010, 1015, and 1020, as well as display panel 100 and display device 1000 according to the above embodiments. Display devices according to exemplary embodiments of this disclosure may include mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation systems, vehicle display devices, cinema display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, camera devices, camcorders, and motherboards of consumer electronic devices.

[0185] The following will describe a test element according to an embodiment of the present disclosure and a method for manufacturing the test element. Figure 14 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure, and Figure 15 yes Figure 14 A magnified view of region A.

[0186] A semiconductor device or device 1 according to one embodiment of the present disclosure may include a plurality of chip regions CA in which an integrated circuit chip is formed and a separating region SL between the plurality of chip regions CA. The plurality of chip regions CA may be arranged on a wafer along multiple rows and columns, but embodiments of the present disclosure are not limited thereto.

[0187] Each of the multiple chip regions CA may include an integrated circuit region and a dummy region. Within the integrated circuit region, semiconductor elements may be provided, and various circuit elements such as resistors, capacitors, transistors, diodes, etc., may be formed. In one embodiment of this disclosure, the semiconductor element may be a display device using miniature LEDs, but embodiments of this disclosure are not limited thereto.

[0188] Multiple semiconductor processes can be performed to form semiconductor elements in an integrated circuit region with multiple chip regions (CA). If semiconductor processes are not performed properly, defects such as open circuits or short circuits may occur, which may degrade the performance of semiconductor elements (or inorganic light-emitting elements).

[0189] Multiple test elements or test element groups (TEGs) can be provided on the wafer to identify defects in integrated circuit regions during semiconductor processing. In an example embodiment, test elements may be formed in test regions TA located within a partition region SL. In another embodiment, test elements may be formed in dummy regions within multiple chip regions CA, where no semiconductor elements or inorganic light-emitting elements are formed. The dummy region may be a region outside the integrated circuit region (or display region). Alternatively, test elements may be placed in both test regions TA and dummy regions within the partition region SL, but embodiments of this disclosure are not limited thereto. Test elements placed in dummy regions may remain in the final manufactured chip or display device, while test elements placed in test regions TA within the partition region SL may not remain in the final manufactured chip or display device, but embodiments of this disclosure are not limited thereto.

[0190] Test elements or groups of test elements may be formed simultaneously with semiconductor elements or inorganic light-emitting elements in the integrated circuit region, but the embodiments of this disclosure are not limited thereto. By inspecting the electrical characteristics of the test elements or groups of test elements during the manufacturing of the semiconductor elements, it can be determined whether the semiconductor elements or inorganic light-emitting elements have been formed correctly.

[0191] The separator region SL can be a region used to separate multiple chip regions CA from each other by scribing or trimming processes, such as scribing lines. Alternatively, semiconductor elements or inorganic light-emitting elements intended to be formed in the integrated circuit region may not be placed in the separator region SL. Considering the efficiency and reliability of the scribing process, the separator region SL can be multiple straight lines between multiple chip regions CA arranged in multiple rows and columns, but embodiments of this disclosure are not limited to this.

[0192] The test area TA can be a region in which a test structure is formed for testing the physical or electrical characteristics of various components constituting the semiconductor device 1 or the display device. For example, by testing the physical or electrical characteristics of test elements or groups of test elements formed within the test area TA, the reliability of integrated circuits (e.g., inorganic light-emitting elements) contained within multiple chip areas CA or display areas can be determined.

[0193] Figure 16 This is a cross-sectional view showing an example of a test element in which the contact resistance between the first and second layers was not measured, and Figure 17 This shows the method used to generate Figure 16 A diagram of an example mask pattern for a test element.

[0194] like Figure 16 and Figure 17As shown, for example, a test element or group of test elements in which the contact resistance between the first layer L1 and the second layer L2 cannot be measured can be created as follows: The first layer L1 can be formed on the base layer BL, and the photoresist layer PR can be formed on the first layer L1. A pattern is formed on the photoresist layer PR by an exposure process, and the second layer L2 can be formed or deposited on the photoresist layer PR having a patterned region PA. The patterned region PA thus formed has an inverted tapered profile, such as... Figure 16 As shown, the photoresist layer PR defining the patterned region PA has sidewalls with an inverted conical profile. Therefore, the second layer L2 is formed or deposited in a discontinuous state within the patterned region PA, making it impossible to measure the contact resistance between the first layer L1 and the second layer L2.

[0195] As an example of adjusting the cone angle of the patterned area PA, it can be achieved in the exposure process by having a cone angle such as... Figure 17 The mask illustrating the slit pattern illuminates the photoresist layer PR, thereby adjusting the exposure. Because the continuity of the second layer L2 in the patterned region PA is not maintained even using the above method, it may still be impossible to measure the contact resistance between the first layer L1 and the second layer L2.

[0196] Figure 18 This is a cross-sectional view showing a test element or group of test elements according to an embodiment of the present disclosure. Figure 19 It shows the formation Figure 18 A diagram of the mask pattern of the test element or test element group, and Figure 20 yes Figure 18 A plan view of the test component. (Refer to...) Figure 18 The method for manufacturing a test element or test element group according to one embodiment of the present disclosure is as follows.

[0197] The embankment BNK can be formed on the base layer BL. A first layer L1 can be disposed on the base layer BL, and the first layer L1 can be formed to cover the sloping side surfaces and the top surface of the embankment BNK. Therefore, the first region L1a of the first layer L1 formed on the top surface of the embankment BNK can be located at a higher position than the second region L1b of the first layer L1 formed on the base layer BL. For example, the first region L1a of the first layer L1 can be positioned at the same height as the embankment BNK relative to the second region L1b.

[0198] A photoresist layer PR is formed on the first layer L1 thus formed, and a pattern is formed on the photoresist layer PR by an exposure process, allowing a second layer L2 to be formed or deposited on the photoresist layer PR with patterned regions PA. For example, the patterned regions PA can be constructed by a stripping process. To adjust the cone angle of the patterned regions PA, the pattern can be formed by irradiating the photoresist layer PR with light through a mask including full-tone (FT) slits and half-tone (HT) slits, as shown. Figure 19 As shown in the figure.

[0199] The patterned region PA thus formed has a positive conical profile, such as Figure 18 As shown, the photoresist layer PR defining the patterned region PA has, for example, positively tapered sidewalls. Therefore, a second layer L2 can be formed or deposited to maintain continuity even within the patterned region PA, and the entire second layer is connected through the patterned region PA, thereby enabling the measurement of the contact resistance between the first layer L1 and the second layer L2.

[0200] Even if the patterned region PA has a positive conical profile, if the patterned region PA is deep, the continuity of the second layer L2 may be disrupted during the formation or deposition of the second layer L2. In an exemplary embodiment of this disclosure, the embankment BNK may be located below the first layer L1 to allow the first layer L1 and the second layer L2 to contact each other at a relatively high position (or point), thereby reducing the depth of the patterned region PA and maintaining the continuity of the second layer L2 in the patterned region PA. In one embodiment, refer to Figure 20 The first layer, L1, can be electrically connected to the pads (PADs). Here, Figure 20 The pads (PADs) can be components on which micro-LEDs are formed, such as chip circuitry (e.g., pixel driver circuitry) electrically connected to another external medium.

[0201] A mask according to an example embodiment of this disclosure may include a second slit within a first slit that is reduced in size by a predetermined ratio from the first slit, or a second slit with a different size from the first slit. For example, but not limited to, the first slit may be full-tone (FT) and the second slit may be half-tone (HT). For example, the full-tone (FT) slit and the half-tone (HT) slit may have different sizes. For example, the size of the full-tone (FT) slit may increase from the inside of the mask to the outside. The size of the full-tone (FT) slit may increase by 0.2 μm from the inside of the mask to the outside, but is not limited to this. For example, the size of the half-tone (HT) slit may decrease from the inside of the mask to the outside, but is not limited to this. The size of the half-tone (HT) slit may decrease by about 0.3 μm from the inside of the mask to the outside, but is not limited to this. For example, the mask may be, but is not limited to, as shown in the example. Figure 19The mask shown has a repeating pattern of full-tone (FT) slits and half-tone (HT) slits. For example, the mask can have, but is not limited to, a rectangular shape. Other forms of masks can also be used; for example, a pattern can be formed on a photoresist layer PR such that the patterned region PA has a positive conical profile.

[0202] Figure 21 This is a diagram illustrating an implementation of a test element or group of test elements according to an embodiment of this disclosure.

[0203] Reference Figure 21 The first layer L1 can be located on the embankment BNK, and the second layer L2 can be formed or deposited on the photoresist layer PR, which includes the patterned region PA. Therefore, the first layer L1 and the second layer L2 can contact each other at the bottom portion CP of the patterned region PA. The first layer L1 can be connected to... Figure 20 The pads (PADs).

[0204] In one example embodiment of this disclosure, the first layer L1 may be a metal layer, and the second layer L2 may be an indium layer. For example, the metal layer may be aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), etc., but embodiments of this disclosure are not limited thereto. For example, a test element or group of test elements may have a structure where current flows through the metal layer to the indium layer. For example, because the metal layer can be used as various signal wirings and the indium layer can be used as various electrodes, the contact resistance for a specific structure in a display device using micro-LEDs (or micro-light-emitting elements) can be determined by measuring the contact resistance between the metal layer and the indium layer. In one embodiment, the contact resistance of a micro-LED with a vertical structure can be determined. For example, the metal layer may be the first connection wiring 121, but embodiments of this disclosure are not limited thereto; for example, the indium layer may be the layer to which the light-emitting element (e.g., a micro-LED) is bonded in a subsequent process, but embodiments of this disclosure are not limited thereto.

[0205] According to one embodiment of this disclosure, a test element or group of test elements can measure the contact resistance between a first layer and a second layer by the following steps: depositing a dike beneath the first layer; forming a patterned area with a positive conical profile using a mask; and bringing the first layer and the second layer into contact through the patterned area above the dike. Therefore, the reliability of a display device using micro-LEDs can be determined.

[0206] A test element according to one or more embodiments of this disclosure and a method for manufacturing the test element can be described as follows.

[0207] A test element according to one or more embodiments of the present disclosure may include: a base layer; a dam on a portion of the base layer; a first layer on the base layer and the dam; a photoresist layer on the first layer, the photoresist layer including patterned areas; and a second layer on the photoresist layer, wherein the height of a first region of the first layer on the dam is higher than the height of a second region of the first layer on the base layer.

[0208] According to one or more embodiments of this disclosure, the patterned region may have a positive conical profile.

[0209] According to one or more embodiments of this disclosure, there is no photoresist layer on a first region of a first layer in the patterned region.

[0210] According to one or more embodiments of this disclosure, the first region and the patterned region of the first layer may contact each other above the dike.

[0211] According to one or more embodiments of this disclosure, the inclined region of the first layer may be located on the side surface of the dike, and the first region and the second region of the first layer may be connected to each other through the inclined region of the first layer.

[0212] According to one or more embodiments of this disclosure, the entire second layer can be connected by patterned regions.

[0213] According to one or more embodiments of this disclosure, a mask including full-tone slits and half-tone slits can be used to form patterned areas.

[0214] According to one or more embodiments of this disclosure, the sizes of the full-tone slits and half-tone slits in the mask are different from each other, and the full-tone slits and half-tone slits may be repeated.

[0215] According to one or more embodiments of this disclosure, the contact resistance between the first layer and the second layer can be measured through the portion where the first region of the first layer and the patterned region are in contact.

[0216] According to one or more embodiments of this disclosure, the contact resistance of a micro light-emitting element can be determined based on the measured contact resistance.

[0217] According to one or more embodiments of this disclosure, the micro light-emitting element may have a vertical structure.

[0218] According to one or more embodiments of this disclosure, the first layer may include a metal, and the second layer may include indium.

[0219] A method of manufacturing a test element according to one or more embodiments of the present disclosure may include: forming a dam on a substrate; forming a first layer including a first region on the dam and a second region on the substrate; forming a photoresist layer on the first layer; forming a patterned region in the photoresist layer by exposure; and forming a second layer on the photoresist layer and in the patterned region, wherein the height of the first region of the first layer on the dam is higher than the height of the second region of the first layer on the substrate.

[0220] According to one or more embodiments of this disclosure, the patterned region may have a positive conical profile.

[0221] According to one or more embodiments of this disclosure, the first region of the first layer and the second layer can be in direct contact within the patterned region.

[0222] According to one or more embodiments of this disclosure, there is no photoresist layer on a first region of a first layer in the patterned region.

[0223] According to one or more embodiments of this disclosure, the inclined region of the first layer may be located on the side surface of the dike, and the first region and the second region of the first layer may be connected to each other through the inclined region of the first layer.

[0224] According to one or more embodiments of this disclosure, the entire second layer can be connected by patterned regions.

[0225] According to one or more embodiments of this disclosure, the formation of patterned regions may include irradiating a photoresist layer with light through a mask including full-tone slits and half-tone slits.

[0226] According to one or more embodiments of this disclosure, the sizes of the full-tone slits and half-tone slits in the mask are different from each other, and the full-tone slits and half-tone slits may be repeated.

[0227] According to one or more embodiments of this disclosure, the contact resistance between the first layer and the second layer can be measured through the portion where the first region of the first layer and the patterned region are in contact.

[0228] According to one or more embodiments of this disclosure, the contact resistance of a micro light-emitting element can be determined based on the measured contact resistance.

[0229] According to one or more embodiments of this disclosure, the micro light-emitting element may have a vertical structure.

[0230] According to one or more embodiments of this disclosure, the first layer may include a metal, and the second layer may include indium.

[0231] It will be apparent to those skilled in the art that various modifications and variations can be made to the test element and the method of manufacturing the test element of this disclosure without departing from the technical concept or scope of this disclosure. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

[0232] [List of reference numerals]

[0233] 100: Display panel

[0234] 110: Substrate

[0235] 120: Covering component

[0236] 140: Support base plate

[0237] CB: Flexible Circuit Board

[0238] 160: Printed Circuit Board

[0239] 1000: Display device

Claims

1. A test element, comprising: grassroots level; The dike is built on a portion of the base layer; The first layer is on the base layer and the embankment; A photoresist layer, the photoresist layer being on the first layer, the photoresist layer including patterned regions; as well as The second layer is located on top of the photoresist layer. Wherein, the height of the first region of the first layer on the embankment is higher than the height of the second region of the first layer on the base layer.

2. The test element according to claim 1, wherein, The patterned region has a conical profile.

3. The test element according to claim 1, wherein, The first region of the first layer and the second layer are in direct contact in the patterned region.

4. The test element according to claim 1, wherein, The photoresist layer is not present in the first region of the first layer within the patterned region.

5. The test element according to claim 1, wherein, The first region of the first layer and the second region of the first layer are connected by an inclined region of the first layer on the side surface of the dike.

6. The test element according to claim 1, wherein, The entire second layer is connected through the patterned areas.

7. The test element according to claim 1, wherein, The patterned area is formed using a mask comprising a full-tone slit and a half-tone slit, wherein the full-tone slit and the half-tone slit in the mask are of different sizes and are repeating.

8. The test element according to claim 3, wherein, The contact resistance between the first layer and the second layer is measured through the portion where the first region of the first layer and the patterned region contact each other, wherein the contact resistance of the micro-light-emitting element is determined based on the measured contact resistance, and wherein the micro-light-emitting element has a vertical structure.

9. The test element according to claim 1, wherein, The first layer comprises a metal, and the second layer comprises indium.

10. A method for manufacturing a test element, comprising: A dike was formed at the grassroots level; A first layer is formed, comprising a first region on the embankment and a second region on the base layer; A photoresist layer is formed on the first layer; Patterned regions are formed in the photoresist layer by exposure; as well as A second layer is formed on the photoresist layer and in the patterned region. Wherein, the height of the first region of the first layer on the embankment is higher than the height of the second region of the first layer on the base layer.

11. The method according to claim 10, wherein, The patterned region has a conical profile.

12. The method according to claim 10, wherein, The first region of the first layer and the second layer are in direct contact in the patterned region.

13. The method according to claim 10, wherein, The photoresist layer is not present in the first region of the first layer within the patterned region.

14. The method of claim 10, wherein, The first region of the first layer and the second region of the first layer are connected by an inclined region of the first layer on the side surface of the dike.

15. The method according to claim 10, wherein, The entire second layer is connected through the patterned areas.

16. The method of claim 10, wherein forming the patterned region comprises irradiating the photoresist layer with light through a mask comprising full-tone slits and half-tone slits.

17. The method according to claim 16, wherein, The full-tone slits and half-tone slits in the mask are different in size from each other, and the full-tone slits and half-tone slits are repeated.

18. The method according to claim 12, wherein, The contact resistance between the first layer and the second layer is measured through the portion where the first region of the first layer and the patterned region contact each other.

19. The method according to claim 18, wherein, The contact resistance of the micro light-emitting element is determined based on the measured contact resistance, wherein the micro light-emitting element has a vertical structure.

20. The method of claim 10, wherein, The first layer comprises a metal, and the second layer comprises indium.

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