Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device includes: a base chip including a first base pad, a second base pad, and a third base pad; and a core chip including a first path, a second path, and a third path, the first path including a first plurality of core pads, the second path including a second plurality of core pads, and the third path including a third plurality of core pads. The first base pad is electrically connected to one of the first plurality of core pads. The second base pad is electrically connected to one of the second plurality of core pads. The third base pad is electrically connected to one of the third plurality of core pads. The base chip and the core chip are stacked.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0102588, filed on August 1, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices, including but not limited to electrical connections in semiconductor devices comprising multiple pads and a core chip. Background Technology

[0003] With the development of semiconductor device manufacturing technology, packaging technologies for core chips in semiconductor devices are increasingly achieving higher integration and performance. As packaging technologies for semiconductor devices have evolved, the technologies associated with three-dimensional structures where core chips are vertically stacked are gradually diverging from those associated with two-dimensional structures where multiple core chips are arranged in a planar layout on a printed circuit board (PCB). Semiconductor devices with three-dimensional structures are implemented by stacking multiple core chips using at least one through-silicon via (TSV) called a "through electrode," or by stacking multiple core chips and utilizing wire bonding (e.g., wire bonding used in high-bandwidth memory (HBM)). Summary of the Invention

[0004] In one embodiment, a semiconductor device may include: a base chip including a first base pad, a second base pad, and a third base pad; and a core chip including a first path, a second path, and a third path, wherein the first path includes a first plurality of core pads, the second path includes a second plurality of core pads, and the third path includes a third plurality of core pads. The first base pad is electrically connected to one of the first plurality of core pads. The second base pad is electrically connected to one of the second plurality of core pads. The third base pad is electrically connected to one of the third plurality of core pads. The base chip and the core chip are stacked.

[0005] In one embodiment, a semiconductor device may include: a base chip including base pads disposed between interface circuitry and a memory controller and configured to receive a power supply voltage; a first core chip including a first path including a first plurality of core pads disposed between a first channel region and a second channel region; and a second core chip including a second path including a second plurality of core pads disposed between a third channel region and a fourth channel region. The base pads are electrically connected to one of the first plurality of core pads and electrically connected to one of the second plurality of core pads. The base chip, the first core chip, and the second core chip are stacked.

[0006] In one embodiment, a semiconductor device may include: a base chip including base pads disposed along a first direction along with interface circuitry and a memory controller; a first core chip including a first path including a first plurality of core pads disposed along the first direction along with a first channel region and a second channel region; and a second core chip including a second path including a second plurality of core pads disposed along the first direction along with a third channel region and a fourth channel region. The base pads are electrically connected to one of the first plurality of core pads and to one of the second plurality of core pads. The base chip, the first core chip, and the second core chip are stacked.

[0007] In one embodiment, a semiconductor device may include: a base chip including base pads disposed in a region between the surface of the base chip and interface circuitry and a memory controller of the base chip; a first core chip including a first path including a first plurality of core pads disposed in a region between the surface of the first core chip and a first channel region and a second channel region of the first core chip; and a second core chip including a second path including a second plurality of core pads disposed in a region between the surface of the second core chip and a third channel region and a fourth channel region. The base pads are electrically connected to one of the first plurality of core pads and electrically connected to one of the second plurality of core pads. The base chip, the first core chip, and the second core chip are stacked.

[0008] In one embodiment, a semiconductor device may include: a base chip including a base pad at a first location of a plurality of locations; and a core chip including a first path including a plurality of core pads. The base pad is electrically connected to one of the plurality of core pads located at a location corresponding to the first location, and the base chip and the core chip are stacked. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a perspective view showing the connection between the pads of the base chip and the pads of the core chip of a semiconductor device according to an embodiment.

[0011] Figure 3 This is a perspective view showing the connection between the pads of the base chip and the pads of the core chip of a semiconductor device according to an embodiment.

[0012] Figure 4 This is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 5 This is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 6 and Figure 7 This is a diagram illustrating an embodiment of a stacked storage system according to the present disclosure. Detailed Implementation

[0015] Terms such as “vertical,” “horizontal,” “above,” “over,” “left,” “right,” “upward,” “downward,” and other terms that imply relative spatial relationships or orientations are used only for the purpose of facilitating description or reference to diagrams and are not otherwise restrictive.

[0016] Terms such as “first” and “second” are used to distinguish multiple components and do not imply the size, order, priority, number, or importance of the components. For example, in one example, the first component may be referred to as the second component, while in another example, the second element may be referred to as the first element.

[0017] When a component is marked as "connected" to another component, these components can be directly connected or connected via an intermediate component between them. When two components are marked as "directly connected," one component is directly connected to the other without any intermediate component between them.

[0018] Crosshairs in the diagram represent corresponding or similar areas between diagrams, rather than representing material related to those areas.

[0019] Embodiments of this disclosure have been described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. The scope of this disclosure is not limited to the examples or embodiments described herein, as examples or embodiments of the concepts may be implemented in various forms.

[0020] like Figure 1 As shown, the semiconductor device 1 according to an embodiment of the present disclosure includes a base chip 10, a first core chip 20, and a second core chip 30. For ease of explanation, Figure 1 It is a block diagram showing the through electrodes T11 to T13, T21 to T29 and T31 to T39, as well as the bumps 111 to 119 and 211 to 219 and their interconnections and other components, rather than a top view or three-dimensional diagram of these components.

[0021] The base chip 10 includes an interface circuit PHY 11, a memory controller MC 12, and a pad area 13.

[0022] Interface circuit 11 receives control signals (not shown) and external data (not shown) from an external device (not shown) to control the operation of the first core chip 20 and the second core chip 30. Interface circuit 11 outputs the received control signals and external data to memory controller 12. Interface circuit 11 receives data DATA from memory controller 12. Interface circuit 11 outputs the received data DATA to the external device. The external device may be a processor, host, or test device that controls the operation of the first core chip 20 and the second core chip 30. The control signals may include commands (CMD) and addresses (ADD) used to perform write and read operations on the first core chip 20 and the second core chip 30. The control signals may be request signals including multiple bits. The external data may be common data or normal data stored after the start of write operations on the first core chip 20 and the second core chip 30.

[0023] The storage controller 12 applies the power supply voltage VDD supplied to the first core chip 20 and the second core chip 30 to the pad area 13. The storage controller 12 also applies the power supply voltage VDD supplied to the first core chip 20 and the second core chip 30 to the first base pad BP11. The storage controller 12 receives control signals and external data from the interface circuit 11. Based on the control signals and external data received by the storage controller 12, the storage controller 12 generates a command CMD, an address ADD, and data DATA used to perform write and read operations on the first core chip 20 and the second core chip 30. After the write and read operations begin, the storage controller 12 applies the command CMD and the address ADD to the pad area 13. The storage controller 12 applies the command CMD and the address ADD to the second base pad BP12. After the write operation begins, the storage controller 12 applies the data DATA to the pad area 13. After the write operation begins, the storage controller 12 applies the data DATA to the third base pad BP13. After the read operation begins, the storage controller 12 receives the data DATA from the pad area 13. After the read operation begins, the storage controller 12 receives data DATA from the third base pad BP13. The storage controller 12 then outputs the data DATA received after the read operation begins to the interface circuit 11.

[0024] The pad area 13 includes a first base pad BP11, a second base pad BP12, a third base pad BP13, a first base through electrode T11, a second base through electrode T12, and a third base through electrode T13.

[0025] The pad area 13 is located between the interface circuit 11 and the storage controller 12.

[0026] The first base pad BP11 is electrically connected to the first base through electrode T11. The first base pad BP11 receives the power supply voltage VDD and outputs the power supply voltage VDD to the first base through electrode T11. The term "output" when used for a base pad or core pad includes the transmission of received voltage or signal.

[0027] Based on the position of the first base pad BP11 relative to the corresponding core pad, the first base pad BP11 is electrically connected to one of the first bump 111, the second bump 112, and the third bump 113. When the first base pad BP11 is positioned corresponding to the first core pad CP21, the first base pad BP11 is electrically connected to the first bump 111. When the first chip and the second chip are arranged consecutively, the corresponding position of the pad on the first chip includes the position directly above or directly below the pad on the second chip. For example, the corresponding position of the first base pad BP11 includes the first core pad CP21 on the first core chip 20 located directly above the first base pad BP11, such as... Figure 2 As shown. The corresponding positions include similar physical coordinates on different chips in the chip stack. When the first base pad BP11 is set at the position corresponding to the second core pad CP22, the first base pad BP11 is electrically connected to the second bump 112. When the first base pad BP11 is set at the position corresponding to the third core pad CP23, the first base pad BP11 is electrically connected to the third bump 113.

[0028] The second base pad BP12 is electrically connected to the second base through electrode T12. The second base pad BP12 receives and outputs commands CMD and addresses ADD through the second base through electrode T12.

[0029] Depending on its position relative to the corresponding core pad, the second base pad BP12 is electrically connected to one of the fourth bump 114, the fifth bump 115, and the sixth bump 116. When the second base pad BP12 is positioned corresponding to the fourth core pad CP24, it is electrically connected to the fourth bump 114. When the second base pad BP12 is positioned corresponding to the fifth core pad CP25, it is electrically connected to the fifth bump 115. When the second base pad BP12 is positioned corresponding to the sixth core pad CP26, it is electrically connected to the sixth bump 116.

[0030] The third base pad BP13 is electrically connected to the third base through electrode T13. After a write operation begins, the third base pad BP13 receives and outputs data DATA through the third base through electrode T13. After a read operation begins, the third base pad BP13 outputs data DATA to the storage controller 12.

[0031] Depending on its position relative to the corresponding core pad, the third base pad BP13 is electrically connected to one of the seventh bump 117, the eighth bump 118, and the ninth bump 119. When the third base pad BP13 is positioned corresponding to the seventh core pad CP27, it is electrically connected to the seventh bump 117. When the third base pad BP13 is positioned corresponding to the eighth core pad CP28, it is electrically connected to the eighth bump 118. When the third base pad BP13 is positioned corresponding to the ninth core pad CP29, it is electrically connected to the ninth bump 119.

[0032] The first base pad BP11, the second base pad BP12, and the third base pad BP13 can be configured to be spaced equidistant from each other. The first base through electrode T11, the second base through electrode T12, and the third base through electrode T13 can also be configured to be spaced equidistant from each other. The first base pad BP11, the second base pad BP12, and the third base pad BP13 can be positioned between the interface circuit 11 and the storage controller 12.

[0033] The first core chip 20 is vertically stacked on or above the base chip 10 using bumps 111 to 119.

[0034] The first core chip 20 includes a first path 21, a second path 22, a third path 23, a first channel region CH 24, and a second channel region CH 25.

[0035] The first path 21 includes a first core through electrode T21, a second core through electrode T22, a third core through electrode T23, a first core pad CP21, a second core pad CP22, and a third core pad CP23.

[0036] The first core through electrode T21 is electrically connected to the first bump 111. The first core pad CP21 is electrically connected to the first core through electrode T21. The first core pad CP21 can receive the power supply voltage VDD and output the power supply voltage VDD to the first channel region 24 and the second channel region 25. When the first base pad BP11 is electrically connected to the first bump 111, the first core pad CP21 receives the power supply voltage VDD from the first base pad BP11 and outputs the power supply voltage VDD to the first channel region 24 and the second channel region 25.

[0037] The second core through electrode T22 is electrically connected to the second bump 112. The second core pad CP22 is electrically connected to the second core through electrode T22. The second core pad CP22 can receive the power supply voltage VDD and output the power supply voltage VDD to the first channel region 24 and the second channel region 25. When the first base pad BP11 is electrically connected to the second bump 112, the second core pad CP22 receives the power supply voltage VDD from the first base pad BP11 and outputs the power supply voltage VDD to the first channel region 24 and the second channel region 25.

[0038] The third core through electrode T23 is electrically connected to the third bump 113. The third core pad CP23 is electrically connected to the third core through electrode T23. The third core pad CP23 can receive the power supply voltage VDD and output the power supply voltage VDD to the first channel region 24 and the second channel region 25. When the first base pad BP11 is electrically connected to the third bump 113, the third core pad CP23 receives the power supply voltage VDD from the first base pad BP11 and outputs the power supply voltage VDD to the first channel region 24 and the second channel region 25.

[0039] The first core through electrode T21, the second core through electrode T22, and the third core through electrode T23 can be set to be spaced apart from each other by an equal distance. The first core pad CP21, the second core pad CP22, and the third core pad CP23 can be set to be spaced apart from each other by an equal distance.

[0040] The first core pad CP21, the second core pad CP22, and the third core pad CP23 included in the first path 21 can be implemented using a redistribution layer RDL and electrically connected.

[0041] The second path 22 includes the fourth core through electrode T24, the fifth core through electrode T25, the sixth core through electrode T26, the fourth core pad CP24, the fifth core pad CP25, and the sixth core pad CP26.

[0042] The fourth core through electrode T24 is electrically connected to the fourth bump 114. The fourth core pad CP24 is electrically connected to the fourth core through electrode T24. The fourth core pad CP24 can receive commands CMD and addresses ADD, and output commands CMD and addresses ADD to the first channel region 24 and the second channel region 25. When the second base pad BP12 is electrically connected to the fourth bump 114, the fourth core pad CP24 receives commands CMD and addresses ADD from the second base pad BP12, and outputs commands CMD and addresses ADD to the first channel region 24 and the second channel region 25.

[0043] The fifth core through electrode T25 is electrically connected to the fifth bump 115. The fifth core pad CP25 is electrically connected to the fifth core through electrode T25. The fifth core pad CP25 can receive commands CMD and addresses ADD, and output commands CMD and addresses ADD to the first channel region 24 and the second channel region 25. When the second base pad BP12 is electrically connected to the fifth bump 115, the fifth core pad CP25 receives commands CMD and addresses ADD from the second base pad BP12, and outputs commands CMD and addresses ADD to the first channel region 24 and the second channel region 25.

[0044] The sixth core through electrode T26 is electrically connected to the sixth bump 116. The sixth core pad CP26 is electrically connected to the sixth core through electrode T26. The sixth core pad CP26 can receive commands CMD and addresses ADD, and output commands CMD and addresses ADD to the first channel region 24 and the second channel region 25. When the second base pad BP12 is electrically connected to the sixth bump 116, the sixth core pad CP26 receives commands CMD and addresses ADD from the second base pad BP12, and outputs commands CMD and addresses ADD to the first channel region 24 and the second channel region 25.

[0045] The fourth core through electrode T24, the fifth core through electrode T25, and the sixth core through electrode T26 can be set to be spaced equally apart from each other. The fourth core pad CP24, the fifth core pad CP25, and the sixth core pad CP26 can also be set to be spaced equally apart from each other.

[0046] The fourth core pad CP24, the fifth core pad CP25, and the first core pad CP26 included in the second path 22 can be implemented using a redistribution layer RDL and electrically connected.

[0047] The third path 23 includes the seventh core through electrode T27, the eighth core through electrode T28, the ninth core through electrode T29, the seventh core pad CP27, the eighth core pad CP28, and the ninth core pad CP29.

[0048] The seventh core through electrode T27 is electrically connected to the seventh bump 117. The seventh core pad CP27 is electrically connected to the seventh core through electrode T27. After a write operation begins, the seventh core pad CP27 can receive data DATA and output data DATA to the first channel region 24 and the second channel region 25. After a write operation begins, when the third base pad BP13 is electrically connected to the seventh bump 117, the seventh core pad CP27 receives data DATA from the third base pad BP13 and outputs data DATA to the first channel region 24 and the second channel region 25. After a read operation begins, the seventh core pad CP27 can receive data DATA from the first channel region 24 and the second channel region 25 and output data DATA. After a read operation begins, when the third base pad BP13 is electrically connected to the seventh bump 117, the seventh core pad CP27 receives data DATA from the first channel region 24 and the second channel region 25 and outputs data DATA to the third base pad BP13.

[0049] The eighth core through electrode T28 is electrically connected to the eighth bump 118. The eighth core pad CP28 is electrically connected to the eighth core through electrode T28. After a write operation begins, the eighth core pad CP28 can receive data DATA and output data DATA to the first channel region 24 and the second channel region 25. After a write operation begins, when the third base pad BP13 is electrically connected to the eighth bump 118, the eighth core pad CP28 receives data DATA from the third base pad BP13 and outputs data DATA to the first channel region 24 and the second channel region 25. After a read operation begins, the eighth core pad CP28 can receive data DATA from the first channel region 24 and the second channel region 25 and output data DATA. After a read operation begins, when the third base pad BP13 is electrically connected to the eighth bump 118, the eighth core pad CP28 receives data DATA from the first channel region 24 and the second channel region 25 and outputs data DATA to the third base pad BP13.

[0050] The ninth core through electrode T29 is electrically connected to the ninth bump 119. The ninth core pad CP29 is electrically connected to the ninth core through electrode T29. After a write operation begins, the ninth core pad CP29 can receive data DATA and output data DATA to the first channel region 24 and the second channel region 25. After a write operation begins, when the third base pad BP13 is electrically connected to the ninth bump 119, the ninth core pad CP29 receives data DATA from the third base pad BP13 and outputs data DATA to the first channel region 24 and the second channel region 25. After a read operation begins, the ninth core pad CP29 can receive data DATA from the first channel region 24 and the second channel region 25 and output data DATA. After a read operation begins, when the third base pad BP13 is electrically connected to the ninth bump 119, the ninth core pad CP29 receives data DATA from the first channel region 24 and the second channel region 25 and outputs data DATA to the third base pad BP13.

[0051] The seventh core through electrode T27, the eighth core through electrode T28, and the ninth core through electrode T29 can be set to be spaced apart from each other by the same distance. The seventh core pad CP27, the eighth core pad CP28, and the ninth core pad CP29 can be set to be spaced apart from each other by the same distance.

[0052] The seventh core pad CP27, the eighth core pad CP28, and the ninth core pad CP29 included in the third path 23 can be implemented using a redistribution layer RDL and electrically connected.

[0053] Both the first channel region 24 and the second channel region 25 include multiple channels. Each of the multiple channels included in each of the first channel region 24 and the second channel region 25 stores data DATA by performing an independent write operation. Each of the multiple channels included in each of the first channel region 24 and the second channel region 25 outputs the data DATA stored in each channel by performing an independent read operation. According to one embodiment, the multiple channels included in each of the first channel region 24 and the second channel region 25 may include four channels or eight channels.

[0054] The first path 21, the second path 22, and the third path 23 are located between the first channel region 24 and the second channel region 25. Core pads CP21 to CP29 are located between the first channel region 24 and the second channel region 25.

[0055] The second core chip 30 is vertically stacked on or above the first core chip 20 using bumps 211 to 219.

[0056] The second core chip 30 includes a fourth path 31, a fifth path 32, a sixth path 33, a third channel region CH 34, and a fourth channel region CH 35.

[0057] The fourth path 31 includes the tenth core through electrode T31, the eleventh core through electrode T32, the twelfth core through electrode T33, the tenth core pad CP31, the eleventh core pad CP32, and the twelfth core pad CP33.

[0058] The tenth core through electrode T31 is electrically connected to the tenth bump 211. The tenth core pad CP31 is electrically connected to the tenth core through electrode T31. The tenth core pad CP31 can receive the power supply voltage VDD and output the power supply voltage VDD to the third channel region 34 and the fourth channel region 35. When the first base pad BP11 is electrically connected to the first bump 111, the tenth core pad CP31 receives the power supply voltage VDD from the first base pad BP11 and outputs the power supply voltage VDD to the third channel region 34 and the fourth channel region 35.

[0059] The eleventh core through electrode T32 is electrically connected to the eleventh bump 212. The eleventh core pad CP32 is electrically connected to the eleventh core through electrode T32. The eleventh core pad CP32 can receive the power supply voltage VDD and output the power supply voltage VDD to the third channel region 34 and the fourth channel region 35. When the first base pad BP11 is electrically connected to the second bump 112, the eleventh core pad CP32 receives the power supply voltage VDD from the first base pad BP11 and outputs the power supply voltage VDD to the third channel region 34 and the fourth channel region 35.

[0060] The twelfth core through electrode T33 is electrically connected to the twelfth bump 213. The twelfth core pad CP33 is electrically connected to the twelfth core through electrode T33. The twelfth core pad CP33 can receive the power supply voltage VDD and output the power supply voltage VDD to the third channel region 34 and the fourth channel region 35. When the first base pad BP11 is electrically connected to the third bump 113, the twelfth core pad CP33 receives the power supply voltage VDD from the first base pad BP11 and outputs the power supply voltage VDD to the third channel region 34 and the fourth channel region 35.

[0061] The tenth core through electrode T31, the eleventh core through electrode T32, and the twelfth core through electrode T33 can be set to be spaced apart by the same distance. The tenth core pad CP31, the eleventh core pad CP32, and the twelfth core pad CP33 can also be set to be spaced apart by the same distance.

[0062] The tenth core pad CP31, eleventh core pad CP32, and twelfth core pad CP33 included in the fourth path 31 can be implemented using a redistribution layer (RDL) and electrically connected. The tenth core pad CP31, eleventh core pad CP32, and twelfth core pad CP33 of the fourth path 31 are respectively located at positions corresponding to the first core pad CP21, second core pad CP22, and third core pad CP23 of the first path 21.

[0063] The fifth path 32 includes the thirteenth core through electrode T34, the fourteenth core through electrode T35, the fifteenth core through electrode T36, the thirteenth core pad CP34, the fourteenth core pad CP35, and the fifteenth core pad CP36.

[0064] The thirteenth core through electrode T34 is electrically connected to the thirteenth bump 214. The thirteenth core pad CP34 is electrically connected to the thirteenth core through electrode T34. The thirteenth core pad CP34 can receive commands CMD and addresses ADD, and output commands CMD and addresses ADD to the third channel region 34 and the fourth channel region 35. When the second base pad BP12 is electrically connected to the fourth bump 114, the thirteenth core pad CP34 receives commands CMD and addresses ADD from the second base pad BP12, and outputs commands CMD and addresses ADD to the third channel region 34 and the fourth channel region 35.

[0065] The fourteenth core through electrode T35 is electrically connected to the fourteenth bump 215. The fourteenth core pad CP35 is electrically connected to the fourteenth core through electrode T35. The fourteenth core pad CP35 can receive commands CMD and addresses ADD, and output commands CMD and addresses ADD to the third channel region 34 and the fourth channel region 35. When the second base pad BP12 is electrically connected to the fifth bump 115, the fourteenth core pad CP35 receives commands CMD and addresses ADD from the second base pad BP12, and outputs commands CMD and addresses ADD to the third channel region 34 and the fourth channel region 35.

[0066] The fifteenth core through electrode T36 is electrically connected to the fifteenth bump 216. The fifteenth core pad CP36 is electrically connected to the fifteenth core through electrode T36. The fifteenth core pad CP36 can receive commands (CMD) and addresses (ADD) and output commands (CMD) and addresses (ADD) to the third channel region 34 and the fourth channel region 35. When the second base pad BP12 is electrically connected to the sixth bump 116, the fifteenth core pad CP36 receives commands (CMD) and addresses (ADD) from the second base pad BP12 and outputs commands (CMD) and addresses (ADD) to the third channel region 34 and the fourth channel region 35.

[0067] The thirteenth core through electrode T34, the fourteenth core through electrode T35, and the fifteenth core through electrode T36 can be set to be spaced apart from each other by the same distance. The thirteenth core pad CP34, the fourteenth core pad CP35, and the fifteenth core pad CP36 can also be set to be spaced apart from each other by the same distance.

[0068] The thirteenth core pad CP34, fourteenth core pad CP35, and fifteenth core pad CP36 included in the fifth path 32 can be implemented using a redistribution layer (RDL) and electrically connected. The thirteenth core pad CP34, fourteenth core pad CP35, and fifteenth core pad CP36 of the fifth path 32 are respectively located at positions corresponding to the fourth core pad CP24, fifth core pad CP25, and sixth core pad CP26 of the second path 22.

[0069] The sixth path 33 includes the sixteenth core through electrode T37, the seventeenth core through electrode T38, the eighteenth core through electrode T39, the sixteenth core pad CP37, the seventeenth core pad CP38, and the eighteenth core pad CP39.

[0070] The sixteenth core through electrode T37 is electrically connected to the sixteenth bump 217. The sixteenth core pad CP37 is electrically connected to the sixteenth core through electrode T37. After a write operation begins, the sixteenth core pad CP37 can receive data DATA and output data DATA to the third channel region 34 and the fourth channel region 35. After a write operation begins, when the third base pad BP13 is electrically connected to the seventh bump 117, the sixteenth core pad CP37 receives data DATA from the third base pad BP13 and outputs data DATA to the third channel region 34 and the fourth channel region 35. After a read operation begins, the sixteenth core pad CP37 can receive data DATA from the third channel region 34 and the fourth channel region 35 and output data DATA. After a read operation begins, when the third base pad BP13 is electrically connected to the seventh bump 117, the sixteenth core pad CP37 receives data DATA from the third channel region 34 and the fourth channel region 35 and outputs data DATA to the third base pad BP13.

[0071] The seventeenth core through electrode T38 is electrically connected to the seventeenth bump 218. The seventeenth core pad CP38 is electrically connected to the seventeenth core through electrode T38. After a write operation begins, the seventeenth core pad CP38 can receive data DATA and output data DATA to the third channel region 34 and the fourth channel region 35. After a write operation begins, when the third base pad BP13 is electrically connected to the eighth bump 118, the seventeenth core pad CP38 receives data DATA from the third base pad BP13 and outputs data DATA to the third channel region 34 and the fourth channel region 35. After a read operation begins, the seventeenth core pad CP38 can receive data DATA from the third channel region 34 and the fourth channel region 35 and output data DATA. After a read operation begins, when the third base pad BP13 is electrically connected to the eighth bump 118, the seventeenth core pad CP38 receives data DATA from the third channel region 34 and the fourth channel region 35 and outputs data DATA to the third base pad BP13.

[0072] The eighteenth core through electrode T39 is electrically connected to the eighteenth bump 219. The eighteenth core pad CP39 is electrically connected to the eighteenth core through electrode T39. After a write operation begins, the eighteenth core pad CP39 can receive data DATA and output data DATA to the third channel region 34 and the fourth channel region 35. After a write operation begins, when the third base pad BP13 is electrically connected to the ninth bump 119, the eighteenth core pad CP39 receives data DATA from the third base pad BP13 and outputs data DATA to the third channel region 34 and the fourth channel region 35. After a read operation begins, the eighteenth core pad CP39 can receive data DATA from the third channel region 34 and the fourth channel region 35 and output data DATA. After a read operation begins, when the third base pad BP13 is electrically connected to the ninth bump 119, the eighteenth core pad CP39 receives data DATA from the third channel region 34 and the fourth channel region 35 and outputs data DATA to the third base pad BP13.

[0073] The sixteenth core through electrode T37, the seventeenth core through electrode T38, and the eighteenth core through electrode T39 can be set to be spaced at the same distance from each other. The sixteenth core pad CP37, the seventeenth core pad CP38, and the eighteenth core pad CP39 can also be set to be spaced at the same distance from each other.

[0074] The sixteenth core pad CP37, seventeenth core pad CP38, and eighteenth core pad CP39 included in the sixth path 33 can be implemented using a redistribution layer (RDL) and electrically connected. The sixteenth core pad CP37, seventeenth core pad CP38, and eighteenth core pad CP39 of the sixth path 33 are respectively located at positions corresponding to the seventh core pad CP27, eighth core pad CP28, and ninth core pad CP29 of the third path 23.

[0075] Each of the third channel region 34 and the fourth channel region 35 includes multiple channels. Each of the multiple channels included in each of the third channel region 34 and the fourth channel region 35 stores data DATA by performing an independent write operation. Each of the multiple channels included in each of the third channel region 34 and the fourth channel region 35 outputs the data DATA stored in each channel by performing an independent read operation. According to one embodiment, the multiple channels included in each of the third channel region 34 and the fourth channel region 35 may include four channels or eight channels.

[0076] The fourth path 31, the fifth path 32, and the sixth path 33 are located between the third channel region 34 and the fourth channel region 35. Core pads CP31 to CP39 are located between the third channel region 34 and the fourth channel region 35.

[0077] Although Figure 1 The semiconductor device 1 shown includes a base chip 10, a first core chip 20 and a second core chip 30 arranged in a vertical stack. However, according to different embodiments, different numbers of core chips (e.g., 4, 8 and 12) are stacked on or above the base chip 10.

[0078] Figure 1 The basic through electrodes T11 to T13, core through electrodes T21 to T29, and core through electrodes T31 to T39 shown can each be implemented as cylindrical shapes made of conductive material, such that the basic through electrodes T11 to T13, core through electrodes T21 to T29, and core through electrodes T31 to T39 are vertically stacked through the base chip 10, the first core chip 20, and the second core chip 30. The bumps 111 to 119 and 211 to 219 can each be implemented as spheres made of conductive material, such that the bumps 111 to 219 can be directly connected to the circuit board.

[0079] Figure 2 This illustrates, for example, according to one embodiment, such as... Figure 1 This diagram shows the connections between the pads of the base chip 10 and the pads of the first core chip 20 and the second core chip 30. (See reference) Figure 2The connection between the pads of the base chip 10 and the pads of the first core chip 20 and the second core chip 30 according to the first embodiment of this disclosure is described. An example is described where the first base pad BP11, the second base pad BP12, and the third base pad BP13 are respectively disposed at positions corresponding to the first core pad CP21, the fourth core pad CP24, and the seventh core pad CP27. The first base pad BP11, the second base pad BP12, and the third base pad BP13 are distributed along a first direction DIR1. The first core pad CP21, the second core pad CP22, and the third core pad CP23 are distributed along a second direction DIR2. The base chip 10, the first core chip 20, and the second core chip 30 are shown spaced apart on a third direction DIR3.

[0080] The first basic pad BP11, the second basic pad BP12, and the third basic pad BP13 are disposed between the interface circuit 11 and the storage controller 12.

[0081] The first base pad BP11 is electrically connected to the first base through electrode T11 and the first bump 111. The first base pad BP11 receives the power supply voltage VDD and outputs the power supply voltage VDD to the first base through electrode T11.

[0082] The second base pad BP12 is electrically connected to the second base through electrode T12 and the fourth bump 114. The second base pad BP12 receives and outputs commands CMD and addresses ADD through the second base through electrode T12.

[0083] The third base pad BP13 is electrically connected to the third base through electrode T13 and the seventh bump 117. After a write operation begins, the third base pad BP13 receives and outputs data DATA through the third base through electrode T13. After a read operation begins, the third base pad BP13 receives and outputs data DATA through the third base through electrode T13 to the storage controller 12.

[0084] The first core pad CP21, the fourth core pad CP24, and the seventh core pad CP27 are located between the first channel region 24 and the second channel region 25.

[0085] The first core pad CP21 is electrically connected to the first core through electrode T21 and the first bump 111. The first core pad CP21 receives the power supply voltage VDD from the first core through electrode T21 and the first bump 111, and outputs the power supply voltage VDD to the first channel region 24 and the second channel region 25. When the first base pad BP11 is electrically connected to the first bump 111, the first core pad CP21 receives the power supply voltage VDD from the first base pad BP11, and outputs the power supply voltage VDD to the first channel region 24 and the second channel region 25.

[0086] The fourth core pad CP24 is electrically connected to the fourth core through electrode T24 and the fourth bump 114. The fourth core pad CP24 receives commands (CMD) and addresses (ADD) through the fourth core through electrode T24 and the fourth bump 114, and outputs the commands (CMD) and addresses (ADD) to the first channel region 24 and the second channel region 25. When the second base pad BP12 is electrically connected to the fourth bump 114, the fourth core pad CP24 receives commands (CMD) and addresses (ADD) from the second base pad BP12, and outputs the commands (CMD) and addresses (ADD) to the first channel region 24 and the second channel region 25.

[0087] The seventh core pad CP27 is electrically connected to the seventh core through electrode T27 and the seventh bump 117. After a write operation begins, the seventh core pad CP27 receives data DATA through the seventh core through electrode T27 and the seventh bump 117, and outputs data DATA to the first channel region 24 and the second channel region 25. After a write operation begins, when the third base pad BP13 is electrically connected to the seventh bump 117, the seventh core pad CP27 receives data DATA from the third base pad BP13 and outputs data DATA to the first channel region 24 and the second channel region 25. After a read operation begins, the seventh core pad CP27 receives data DATA from the first channel region 24 and the second channel region 25, and outputs data DATA through the seventh core through electrode T27 and the seventh bump 117. After a read operation begins, when the third base pad BP13 is electrically connected to the seventh bump 117, the seventh core pad CP27 outputs data DATA to the third base pad BP13 through the seventh core through electrode T27 and the seventh bump 117.

[0088] The tenth core pad CP31, the thirteenth core pad CP34, and the sixteenth core pad CP37 are located between the third channel region 34 and the fourth channel region 35.

[0089] The tenth core pad CP31 is electrically connected to the tenth core through electrode T31 and the tenth bump 211. The tenth core pad CP31 receives the power supply voltage VDD from the tenth core through electrode T31 and the tenth bump 211, and outputs the power supply voltage VDD to the third channel region 34 and the fourth channel region 35. When the first base pad BP11 is electrically connected to the first bump 111, the tenth core pad CP31 receives the power supply voltage VDD from the first base pad BP11 and outputs the power supply voltage VDD to the third channel region 34 and the fourth channel region 35.

[0090] The thirteenth core pad CP34 is electrically connected to the thirteenth core through electrode T34 and the thirteenth bump 214. The thirteenth core pad CP34 receives commands (CMD) and addresses (ADD) through the thirteenth core through electrode T34 and the thirteenth bump 214, and outputs the commands (CMD) and addresses (ADD) to the third channel region 34 and the fourth channel region 35. When the second base pad BP12 is electrically connected to the fourth bump 114, the thirteenth core pad CP34 receives commands (CMD) and addresses (ADD) from the second base pad BP12, and outputs the commands (CMD) and addresses (ADD) to the third channel region 34 and the fourth channel region 35.

[0091] The sixteenth core pad CP37 is electrically connected to the sixteenth core through electrode T37 and the sixteenth bump 217. After a write operation begins, the sixteenth core pad CP37 receives data DATA through the sixteenth core through electrode T37 and the sixteenth bump 217, and outputs data DATA to the third channel region 34 and the fourth channel region 35. After a write operation begins, when the third base pad BP13 is electrically connected to the seventh bump 117, the sixteenth core pad CP37 receives data DATA from the third base pad BP13 and outputs data DATA to the third channel region 34 and the fourth channel region 35. After a read operation begins, the sixteenth core pad CP37 receives data DATA from the third channel region 34 and the fourth channel region 35, and outputs data DATA through the sixteenth core through electrode T37 and the sixteenth bump 217. After the read operation begins, when the third base pad BP13 is electrically connected to the seventh bump 117, the sixteenth core pad CP37 outputs data DATA to the third base pad BP13 through the sixteenth core through electrode T37 and the sixteenth bump 217.

[0092] As described with respect to the semiconductor device 1 according to an embodiment of the present disclosure, the plurality of pads included in the first core chip 20 and the second core chip 30 are electrically connected, and the pads of the base chip 10 are connected to one of the plurality of pads of the core chips 20 and 30. Therefore, the base chip and the core chips including pads at different locations can be electrically connected. In the semiconductor device 1, regardless of the location of the pads of the base chip 10, the base chip 10 can be electrically connected to the core chips 20 and 30, which include pads located at multiple different locations, by connecting the pads of the base chip 10 to one of the plurality of pads of the first core chip 20 and the second core chip 30.

[0093] Figure 3 This illustrates an example according to one embodiment. Figure 1 This diagram shows the connections between the pads of the base chip and the pads of the core chip. (Reference) Figure 3 The connection between the pads of the base chip and the pads of the core chip according to the second embodiment of this disclosure is described. An example is described in which the first base pad BP11, the second base pad BP12, and the third base pad BP13 are respectively disposed at positions corresponding to the third core pad CP23, the sixth core pad CP26, and the ninth core pad CP29.

[0094] The first basic pad BP11, the second basic pad BP12, and the third basic pad BP13 are disposed between the interface circuit 11 and the storage controller 12.

[0095] The first base pad BP11 is electrically connected to the first base through electrode T11 and the third bump 113. The first base pad BP11 receives the power supply voltage VDD and outputs the power supply voltage VDD to the first base through electrode T11.

[0096] The second base pad BP12 is electrically connected to the second base through electrode T12 and the sixth bump 116. The second base pad BP12 receives the command CMD and the address ADD, and outputs the command CMD and the address ADD through the second base through electrode T12.

[0097] The third base pad BP13 is electrically connected to the third base through electrode T13 and the ninth bump 119. After a write operation begins, the third base pad BP13 receives and outputs data DATA through the third base through electrode T13. After a read operation begins, the third base pad BP13 receives and outputs data DATA through the third base through electrode T13 to the storage controller 12.

[0098] The third core pad CP23, the sixth core pad CP26, and the ninth core pad CP29 are located between the first channel area 24 and the second channel area 25.

[0099] The third core pad CP23 is electrically connected to the third core through electrode T23 and the third bump 113. The third core pad CP23 receives the power supply voltage VDD from the third core through electrode T23 and the third bump 113, and outputs the power supply voltage VDD to the first channel region 24 and the second channel region 25. When the first base pad BP11 is electrically connected to the third bump 113, the third core pad CP23 receives the power supply voltage VDD from the first base pad BP11 and outputs the power supply voltage VDD to the first channel region 24 and the second channel region 25. The third core pad CP23 is electrically connected to the first core pad CP21. The first core pad CP21 is electrically connected to the tenth bump 211.

[0100] The sixth core pad CP26 is electrically connected to the sixth core through electrode T26 and the sixth bump 116. The sixth core pad CP26 receives commands (CMD) and addresses (ADD) through the sixth core through electrode T26 and the sixth bump 116, and outputs the commands (CMD) and addresses (ADD) to the first channel region 24 and the second channel region 25. When the second base pad BP12 is electrically connected to the sixth bump 116, the sixth core pad CP26 receives commands (CMD) and addresses (ADD) from the second base pad BP12, and outputs the commands (CMD) and addresses (ADD) to the first channel region 24 and the second channel region 25. The sixth core pad CP26 is electrically connected to the fourth core pad CP24. The fourth core pad CP24 is electrically connected to the thirteenth bump 214.

[0101] The ninth core pad CP29 is electrically connected to the ninth core through electrode T29 and the ninth bump 119. After a write operation begins, the ninth core pad CP29 receives data DATA through the ninth core through electrode T29 and the ninth bump 119, and outputs data DATA to the first channel region 24 and the second channel region 25. After a write operation begins, when the third base pad BP13 is electrically connected to the ninth bump 119, the ninth core pad CP29 receives data DATA from the third base pad BP13 and outputs data DATA to the first channel region 24 and the second channel region 25. After a read operation begins, the ninth core pad CP29 receives data DATA from the first channel region 24 and the second channel region 25, and outputs data DATA through the ninth core through electrode T29 and the ninth bump 119. After a read operation begins, when the third base pad BP13 is electrically connected to the ninth bump 119, the ninth core pad CP29 outputs data DATA to the third base pad BP13 through the ninth core through electrode T29 and the ninth bump 119. The ninth core pad CP29 is electrically connected to the seventh core pad CP27. The seventh core pad CP27 is electrically connected to the sixteenth bump 217.

[0102] The tenth core pad CP31, the thirteenth core pad CP34, and the sixteenth core pad CP37 are located between the third channel region 34 and the fourth channel region 35.

[0103] The tenth core pad CP31 is electrically connected to the tenth core through electrode T31 and the tenth bump 211. The tenth core pad CP31 receives the power supply voltage VDD from the tenth core through electrode T31 and the tenth bump 211, and outputs the power supply voltage VDD to the third channel region 34 and the fourth channel region 35. When the first base pad BP11 is electrically connected to the third bump 113, the tenth core pad CP31 receives the power supply voltage VDD from the first base pad BP11 and outputs the power supply voltage VDD to the third channel region 34 and the fourth channel region 35.

[0104] The thirteenth core pad CP34 is electrically connected to the thirteenth core through electrode T34 and the thirteenth bump 214. The thirteenth core pad CP34 receives commands (CMD) and addresses (ADD) through the thirteenth core through electrode T34 and the thirteenth bump 214, and outputs the commands (CMD) and addresses (ADD) to the third channel region 34 and the fourth channel region 35. When the second base pad BP12 is electrically connected to the sixth bump 116, the thirteenth core pad CP34 receives commands (CMD) and addresses (ADD) from the second base pad BP12, and outputs the commands (CMD) and addresses (ADD) to the third channel region 34 and the fourth channel region 35.

[0105] The sixteenth core pad CP37 is electrically connected to the sixteenth core through electrode T37 and the sixteenth bump 217. After a write operation begins, the sixteenth core pad CP37 receives data DATA through the sixteenth core through electrode T37 and the sixteenth bump 217, and outputs data DATA to the third channel region 34 and the fourth channel region 35. After a write operation begins, when the third base pad BP13 is electrically connected to the ninth bump 119, the sixteenth core pad CP37 receives data DATA from the third base pad BP13 and outputs data DATA to the third channel region 34 and the fourth channel region 35. After a read operation begins, the sixteenth core pad CP37 receives data DATA from the third channel region 34 and the fourth channel region 35, and outputs data DATA through the sixteenth core through electrode T37 and the sixteenth bump 217. After the read operation begins, when the third base pad BP13 is electrically connected to the seventh bump 117, the sixteenth core pad CP37 outputs data DATA to the third base pad BP13 through the sixteenth core through electrode T37 and the sixteenth bump 217.

[0106] As described with respect to the semiconductor device 1 according to an embodiment of the present disclosure, a plurality of pads included in the first core chip 20 and the second core chip 30 are electrically connected, and the pads of the base chip 10 are connected to one of the plurality of pads of the first core chip 20 and the second core chip 30. Therefore, pads located at different positions on the base chip 10 and the core chips 20 and 30 can be electrically connected. In the semiconductor device 1, regardless of the location of the pads of the base chip 10, the core chips 20 and 30 and the base chip 10, including pads located in various different positions, can be electrically connected by connecting the pads of the base chip 10 to one of the plurality of pads of the first core chip 20 and the second core chip 30.

[0107] Figure 4 This is a block diagram illustrating a semiconductor device 2 according to an embodiment of the present disclosure. Figure 4 As shown, the semiconductor device 2 according to an embodiment of the present disclosure includes a base chip 40, a first core chip 50, and a second core chip 60. For ease of explanation, Figure 4 It is a block diagram showing the through electrodes T41 to T43, T51 to T59 and T61 to T69, as well as the bumps 411 to 419 and 511 to 619 and their interconnections and other components, rather than a top view or three-dimensional diagram of these components.

[0108] The base chip 40 includes an interface circuit PHY 41, a memory controller MC 42, and a pad area 43.

[0109] Interface circuit 41 and storage controller 42 respectively perform operations related to... Figure 1 The interface circuit 11 and the storage controller 12 shown perform similar operations.

[0110] Pad area 43 includes a first base pad BP41, a second base pad BP42, and a third base pad BP43. This example shows three possible locations for each of the first base pad BP41, the second base pad BP42, and the third base pad BP43.

[0111] The pad area 43 is arranged together with the interface circuit 41 and the storage controller 42 along the first direction DIR1, for example, arranged horizontally relative to the figure.

[0112] The first base pad BP41 is electrically connected to the first base through electrode T41. The first base pad BP41 receives the power supply voltage VDD and outputs the power supply voltage VDD to the first base through electrode T41.

[0113] Depending on the position of the first base pad BP41 relative to the corresponding core pad, the first base pad BP41 is electrically connected to one of the first bump 411, the second bump 412, and the third bump 413. When the first base pad BP41 is positioned corresponding to the first core pad CP51, the first base pad BP41 is electrically connected to the first bump 411. When the first base pad BP41 is positioned corresponding to the second core pad CP52, the first base pad BP41 is electrically connected to the second bump 412. When the first base pad BP41 is positioned corresponding to the third core pad CP53, the first base pad BP41 is electrically connected to the third bump 413.

[0114] The second base pad BP42 is electrically connected to the second base through electrode T42. The second base pad BP42 receives and outputs commands CMD and addresses ADD through the second base through electrode T42.

[0115] Depending on its position relative to the corresponding core pad, the second base pad BP42 is electrically connected to one of the fourth bump 414, the fifth bump 415, and the sixth bump 416. When the second base pad BP42 is positioned corresponding to the fourth core pad CP54, it is electrically connected to the fourth bump 414. When the second base pad BP42 is positioned corresponding to the fifth core pad CP55, it is electrically connected to the fifth bump 415. When the second base pad BP42 is positioned corresponding to the sixth core pad CP56, it is electrically connected to the sixth bump 416.

[0116] The third base pad BP43 is electrically connected to the third base through electrode T43. After a write operation begins, the third base pad BP43 receives and outputs data DATA through the third base through electrode T43. After a read operation begins, the third base pad BP43 receives and outputs data DATA to the memory controller 42 through the third base through electrode T43.

[0117] Depending on its position relative to the corresponding core pad, the third base pad BP43 is electrically connected to one of the seventh bump 417, the eighth bump 418, and the ninth bump 419. When the third base pad BP43 is positioned corresponding to the seventh core pad CP57, it is electrically connected to the seventh bump 417. When the third base pad BP43 is positioned corresponding to the eighth core pad CP58, it is electrically connected to the eighth bump 418. When the third base pad BP43 is positioned corresponding to the ninth core pad CP59, it is electrically connected to the ninth bump 419.

[0118] The first base pad BP41, the second base pad BP42, and the third base pad BP43 can be configured to be spaced apart from each other by the same distance. The first base through electrode T41, the second base through electrode T42, and the third base through electrode T43 can be configured to be spaced apart from each other by the same distance. The first base pad BP41, the second base pad BP42, and the third base pad BP43 are arranged together with the interface circuit 41 and the storage controller 42 along a first direction.

[0119] The first core chip 50 is vertically stacked on or above the base chip 40 using bumps 411 to 419.

[0120] The first core chip 50 includes a first path 51, a second path 52, a third path 53, a first channel region CH 54, and a second channel region CH 55.

[0121] The first path 51 includes a first core through electrode T51, a second core through electrode T52, a third core through electrode T53, a first core pad CP51, a second core pad CP52, and a third core pad CP53.

[0122] The first core pad CP51, the second core pad CP52, and the third core pad CP53 included in the first path 51 can be implemented using a redistribution layer RDL and electrically connected.

[0123] The structure in which the first bump 411, the second bump 412, the third bump 413, the first core through electrode T51, the second core through electrode T52, the third core through electrode T53, the first core pad CP51, the second core pad CP52, and the third core pad CP53 are electrically connected is similar to that described above. Figure 1 The structure shown is an electrically connected structure consisting of the first bump 111, the second bump 112, the third bump 113, the first core through electrode T21, the second core through electrode T22, the third core through electrode T23, the first core pad CP21, the second core pad CP22, and the third core pad CP23.

[0124] The second path 52 includes the fourth core through electrode T54, the fifth core through electrode T55, the sixth core through electrode T56, the fourth core pad CP54, the fifth core pad CP55, and the sixth core pad CP56.

[0125] The fourth core pad CP54, the fifth core pad CP55, and the sixth core pad CP56 included in the second path 52 can be implemented using the redistribution layer RDL and electrically connected.

[0126] The structure in which the fourth bump 414, the fifth bump 415, the sixth bump 416, the fourth core through electrode T54, the fifth core through electrode T55, the sixth core through electrode T56, the fourth core pad CP54, the fifth core pad CP55, and the sixth core pad CP56 are electrically connected is similar to... Figure 1 The fourth bump 114, fifth bump 115, sixth bump 116, fourth core through electrode T24, fifth core through electrode T25, sixth core through electrode T26, fourth core pad CP24, fifth core pad CP25 and sixth core pad CP26 shown are electrically connected in a similar structure.

[0127] The third path 53 includes the seventh core through electrode T57, the eighth core through electrode T58, the ninth core through electrode T59, the seventh core pad CP57, the eighth core pad CP58, and the ninth core pad CP59.

[0128] The seventh core pad CP57, the eighth core pad CP58, and the ninth core pad CP59 included in the third path 53 can be implemented using the redistribution layer RDL and electrically connected.

[0129] The structure in which the seventh bump 417, the eighth bump 418, the ninth bump 419, the seventh core through electrode T57, the eighth core through electrode T58, the ninth core through electrode T59, the seventh core pad CP57, the eighth core pad CP58, and the ninth core pad CP59 are electrically connected is similar to... Figure 1 The seventh bump 117, the eighth bump 118, the ninth bump 119, the seventh core through electrode T27, the eighth core through electrode T28, the ninth core through electrode T29, the seventh core pad CP27, the eighth core pad CP28, and the ninth core pad CP29 shown are electrically connected in a similar structure.

[0130] The first channel area 54 and the second channel area 55 respectively execute the commands as follows: Figure 1 The operations performed in the first channel region 24 and the second channel region 25 shown are similar.

[0131] The first path 51, the second path 52, and the third path 53 are configured to be spaced apart from the first channel region 54 and the second channel region 55 on the first direction DIR1.

[0132] The second core chip 60 is vertically stacked on or above the first core chip 50 using bumps 511 to 519.

[0133] The second core chip 60 includes a fourth path 61, a fifth path 62, a sixth path 63, a third channel region CH 64, and a fourth channel region CH 65.

[0134] The fourth path 61 includes the tenth core through electrode T61, the eleventh core through electrode T62, the twelfth core through electrode T63, the tenth core pad CP61, the eleventh core pad CP62, and the twelfth core pad CP63.

[0135] The tenth core pad CP61, eleventh core pad CP62 and twelfth core pad CP63 included in the fourth path 61 can be implemented using the redistribution layer RDL and electrically connected.

[0136] The structure in which the tenth bump 511, the eleventh bump 512, the twelfth bump 513, the tenth core through electrode T61, the eleventh core through electrode T62, the twelfth core through electrode T63, the tenth core pad CP61, the eleventh core pad CP62, and the twelfth core pad CP63 are electrically connected is similar to... Figure 1 The structure in which the tenth bump 211, eleventh bump 212, twelfth bump 213, tenth core through electrode T31, eleventh core through electrode T32, twelfth core through electrode T33, tenth core pad CP31, eleventh core pad CP32 and twelfth core pad CP33 are electrically connected is similar.

[0137] The fifth path 62 includes the thirteenth core through electrode T64, the fourteenth core through electrode T65, the fifteenth core through electrode T66, the thirteenth core pad CP64, the fourteenth core pad CP65, and the fifteenth core pad CP66.

[0138] The thirteenth core pad CP64, fourteenth core pad CP65, and fifteenth core pad CP66 included in the fifth path 62 can be implemented using the redistribution layer RDL and electrically connected.

[0139] The structure in which the thirteenth bump 514, the fourteenth bump 515, the fifteenth bump 516, the thirteenth core through electrode T64, the fourteenth core through electrode T65, the fifteenth core through electrode T66, the thirteenth core pad CP64, the fourteenth core pad CP65, and the fifteenth core pad CP66 are electrically connected is similar to... Figure 1 The structures of the thirteenth bump 214, fourteenth bump 215, fifteenth bump 216, thirteenth core through electrode T34, fourteenth core through electrode T35, fifteenth core through electrode T56, thirteenth core pad CP34, fourteenth core pad CP35 and fifteenth core pad CP36 shown are similar.

[0140] The sixth path 63 includes the sixteenth core through electrode T67, the seventeenth core through electrode T68, the eighteenth core through electrode T69, the sixteenth core pad CP67, the seventeenth core pad CP68, and the eighteenth core pad CP69.

[0141] The sixteenth core pad CP67, the seventeenth core pad CP68, and the eighteenth core pad CP69 included in the sixth path 63 can be implemented using a redistribution layer RDL and electrically connected.

[0142] The structure in which the sixteenth bump 517, the seventeenth bump 518, the eighteenth bump 519, the sixteenth core through electrode T67, the seventeenth core through electrode T68, the eighteenth core through electrode T69, the sixteenth core pad CP67, the seventeenth core pad CP68, and the eighteenth core pad CP69 are electrically connected is similar to... Figure 1 The structure in which the sixteenth bump 217, the seventeenth bump 218, the eighteenth bump 219, the sixteenth core through electrode T37, the seventeenth core through electrode T38, the eighteenth core through electrode T39, the sixteenth core pad CP37, the seventeenth core pad CP38, and the eighteenth core pad CP39 are electrically connected is similar.

[0143] The third channel area 64 and the fourth channel area 65 respectively execute the commands as follows: Figure 1 The third channel region 34 and the fourth channel region 35 shown in the diagram perform similar operations.

[0144] The fourth path 61, the fifth path 62 and the sixth path 63 are set to be spaced apart from the third channel region 64 and the fourth channel region 65 on the first direction DIR1.

[0145] Figure 4 The structure shown is where the base pads BP41 to BP43 and the core pads CP51 to CP69 are electrically connected. Figure 2 and Figure 3 The structure shown is similar to that of the base pads BP11 to BP13 and the core pads CP21 to CP39, which are electrically connected.

[0146] Figure 4 The basic through electrodes T41 to T43, core through electrodes T51 to T59, and core through electrodes T61 to T69 shown can all be implemented as cylindrical shapes made of conductive material, such that the basic through electrodes T41 to T43, core through electrodes T51 to T59, and core through electrodes T61 to T69 are vertically stacked through the base chip 40, the first core chip 50, and the second core chip 60. The bumps 411 to 419 and 511 to 519 can all be implemented as spheres made of conductive material, such that the bumps 411 to 419 and 511 to 519 can be directly connected to the printed circuit board.

[0147] Although Figure 4The semiconductor device 2 shown includes a base chip 40, a first core chip 50 and a second core chip 60 arranged in a vertical stacking layout, but according to different embodiments, different numbers of core chips (e.g., 4, 8 and 12) are stacked on or above the base chip 10.

[0148] As described with respect to the semiconductor device 2 according to an embodiment of the present disclosure, the multiple pads included in the core chips 50 and 60 are electrically connected, and the pads of the base chip 40 are connected to one of the multiple pads of the first core chip 50 and the second core chip 60. Therefore, pads located at different positions on the base chip 40 and the core chips 50 and 60 can be electrically connected. In the semiconductor device 2, regardless of the location of the pads of the base chip 40, the core chips 50 and 60 and the base chip 40, including pads located in various different positions, can be electrically connected by connecting the pads of the base chip 40 to one of the multiple pads of the first core chip 50 and the second core chip 60.

[0149] Figure 5 This is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 5 As shown, the semiconductor device 3 according to an embodiment of the present disclosure includes a base chip 70, a first core chip 80, and a second core chip 90. Figure 5 This is a block diagram showing the through electrodes T71 to T73, T81 to T89 and T91 to T99, as well as the bumps 711 to 719 and 811 to 819 and their interconnections and other components, rather than a top view or three-dimensional diagram of these components, for the purpose of illustration.

[0150] The base chip 70 includes an interface circuit PHY 71, a memory controller MC 72, and a pad area 73.

[0151] Interface circuit 71 and memory controller 72 respectively execute the functions of the interface circuit 71 and memory controller 72. Figure 1 The interface circuit 11 and the storage controller 12 shown perform similar operations.

[0152] Pad area 73 includes a first base pad BP71, a second base pad BP72, and a third base pad BP73. This example shows three possible locations for each of the first base pad BP71, the second base pad BP72, and the third base pad BP73.

[0153] A pad area 73 is disposed between the first surface of the base chip 70 and the interface circuit 71 and the memory controller 72, which are disposed, for example, along a first direction DIR1. The first surface of the base chip 70 may be relative to the surface of the base chip 70. Figure 5 The orientation of the top or bottom surface. The pad area 73 can be located near the edge of the first surface of the base chip 70.

[0154] The first base pad BP71 is electrically connected to the first base through electrode T71. The first base pad BP71 receives the power supply voltage VDD and outputs the power supply voltage VDD to the first base through electrode T71.

[0155] Depending on the position of the first base pad BP71 relative to the corresponding core pad, the first base pad BP71 is electrically connected to one of the first bump 711, the second bump 712, and the third bump 713. When the first base pad BP71 is positioned corresponding to the first core pad CP81, the first base pad BP71 is electrically connected to the first bump 711. When the first base pad BP71 is positioned corresponding to the second core pad CP82, the first base pad BP71 is electrically connected to the second bump 712. When the first base pad BP71 is positioned corresponding to the third core pad CP83, the first base pad BP71 is electrically connected to the third bump 713.

[0156] The second base pad BP72 is electrically connected to the second base through electrode T72. The second base pad BP72 receives and outputs commands CMD and addresses ADD through the second base through electrode T72.

[0157] Depending on its position relative to the corresponding core pad, the second base pad BP72 is electrically connected to one of the fourth bump 714, the fifth bump 715, and the sixth bump 716. When the second base pad BP72 is positioned corresponding to the fourth core pad CP84, it is electrically connected to the fourth bump 714. When the second base pad BP72 is positioned corresponding to the fifth core pad CP85, it is electrically connected to the fifth bump 715. When the second base pad BP72 is positioned corresponding to the sixth core pad CP86, it is electrically connected to the sixth bump 716.

[0158] The third base pad BP73 is electrically connected to the third base through electrode T73. After a write operation begins, the third base pad BP73 receives and outputs data DATA through the third base through electrode T73. After a read operation begins, the third base pad BP73 receives and outputs data DATA to the memory controller 72 through the third base through electrode T73.

[0159] Depending on its position relative to the corresponding core pad, the third base pad BP73 is electrically connected to one of the seventh bump 717, the eighth bump 718, and the ninth bump 719. When the third base pad BP73 is positioned corresponding to the seventh core pad CP87, it is electrically connected to the seventh bump 717. When the third base pad BP73 is positioned corresponding to the eighth core pad CP88, it is electrically connected to the eighth bump 718. When the third base pad BP73 is positioned corresponding to the ninth core pad CP89, it is electrically connected to the ninth bump 719.

[0160] The first base pad BP71, the second base pad BP72, and the third base pad BP73 can be set to be equally spaced. The first base through electrode T71, the second base through electrode T72, and the third base through electrode T73 can also be set to be equally spaced. The first base pad BP71, the second base pad BP72, and the third base pad BP73 are disposed between the surface of the base chip 70 and the interface circuit 71 and the memory controller 72; this surface can be relative to the base chip 70. Figure 5 The directional top or bottom surface.

[0161] The first core chip 80 is vertically stacked on or above the base chip 70 using bumps 711 to 719.

[0162] The first core chip 80 includes a first path 81, a second path 82, a third path 83, a first channel region CH 84, and a second channel region CH 85.

[0163] The first path 81 includes a first core through electrode T81, a second core through electrode T82, a third core through electrode T83, a first core pad CP81, a second core pad CP82, and a third core pad CP83.

[0164] The first core pad CP81, the second core pad CP82, and the third core pad CP83 included in the first path 81 can be implemented using a redistribution layer RDL and electrically connected.

[0165] The structure in which the first bump 711, the second bump 712, the third bump 713, the first core through electrode T81, the second core through electrode T82, the third core through electrode T83, the first core pad CP81, the second core pad CP82, and the third core pad CP83 are electrically connected is similar to... Figure 1The structure in which the first bump 111, the second bump 112, the third bump 113, the first core through electrode T21, the second core through electrode T22, the third core through electrode T23, the first core pad CP21, the second core pad CP22, and the third core pad CP23 are electrically connected is similar.

[0166] The second path 82 includes the fourth core through electrode T84, the fifth core through electrode T85, the sixth core through electrode T86, the fourth core pad CP84, the fifth core pad CP85, and the sixth core pad CP86.

[0167] The fourth core pad CP84, the fifth core pad CP85, and the sixth core pad CP86 included in the second path 82 can be implemented using the redistribution layer RDL and electrically connected.

[0168] The structure in which the fourth bump 714, the fifth bump 715, the sixth bump 716, the fourth core through electrode T84, the fifth core through electrode T85, the sixth core through electrode T86, the fourth core pad CP84, the fifth core pad CP85, and the sixth core pad CP86 are electrically connected is similar to... Figure 1 The fourth bump 114, the fifth bump 115, the sixth bump 116, the fourth core through electrode T24, the fifth core through electrode T25, the sixth core through electrode T26, the fourth core pad CP24, the fifth core pad CP25, and the sixth core pad CP26 shown are electrically connected in a similar structure.

[0169] The third path 83 includes the seventh core through electrode T87, the eighth core through electrode T88, the ninth core through electrode T89, the seventh core pad CP87, the eighth core pad CP88, and the ninth core pad CP89.

[0170] The seventh core pad CP87, the eighth core pad CP88, and the ninth core pad CP89 included in the third path 83 can be implemented using the redistribution layer RDL and electrically connected.

[0171] The structure in which the seventh bump 717, the eighth bump 718, the ninth bump 719, the seventh core through electrode T87, the eighth core through electrode T88, the ninth core through electrode T89, the seventh core pad CP87, the eighth core pad CP88, and the ninth core pad CP89 are electrically connected is similar to... Figure 1 The structure in which the seventh bump 117, the eighth bump 118, the ninth bump 119, the seventh core through electrode T27, the eighth core through electrode T28, the ninth core through electrode T29, the seventh core pad CP27, the eighth core pad CP28, and the ninth core pad CP29 are electrically connected is similar.

[0172] The first channel area 84 and the second channel area 85 respectively execute the commands as described above. Figure 1 The first channel region 24 and the second channel region 25 shown in the diagram perform similar operations.

[0173] The first path 81, the second path 82, and the third path 83 are disposed along the first direction DIR1 in the region between the surface of the first core chip 80 and the first channel region 84 and the second channel region 85 of the first core chip 80. The first path 81, the second path 82, and the third path 83 may be disposed near the edge of the surface of the first core chip 80. The surface of the first core chip 80 may be relative to the edge of the first core chip 80. Figure 5 The directional top or bottom surface.

[0174] The second core chip 90 is vertically stacked on or above the first core chip 80 using bumps 811 to 819.

[0175] The second core chip 90 includes a fourth path 91, a fifth path 92, a sixth path 93, a third channel region CH 94, and a fourth channel region CH 95.

[0176] The fourth path 91 includes the tenth core through electrode T91, the eleventh core through electrode T92, the twelfth core through electrode T93, the tenth core pad CP91, the eleventh core pad CP92, and the twelfth core pad CP93.

[0177] The tenth core pad CP91, eleventh core pad CP92 and twelfth core pad CP93 included in the fourth path 91 can be implemented using the redistribution layer RDL and electrically connected.

[0178] The structure in which the tenth bump 811, the eleventh bump 812, the twelfth bump 813, the tenth core through electrode T91, the eleventh core through electrode T92, the twelfth core through electrode T93, the tenth core pad CP91, the eleventh core pad CP92, and the twelfth core pad CP93 are electrically connected is similar to... Figure 1 The structure in which the tenth bump 211, eleventh bump 212, twelfth bump 213, tenth core through electrode T31, eleventh core through electrode T32, twelfth core through electrode T33, tenth core pad CP31, eleventh core pad CP32 and twelfth core pad CP33 are electrically connected is similar.

[0179] The fifth path 92 includes the thirteenth core through electrode T94, the fourteenth core through electrode T95, the fifteenth core through electrode T96, the thirteenth core pad CP94, the fourteenth core pad CP95, and the fifteenth core pad CP96.

[0180] The thirteenth core pad CP94, the fourteenth core pad CP95, and the fifteenth core pad CP96 included in the fifth path 92 can be implemented using a redistribution layer RDL and electrically connected.

[0181] The structure in which the thirteenth bump 814, the fourteenth bump 815, the fifteenth bump 816, the thirteenth core through electrode T94, the fourteenth core through electrode T95, the fifteenth core through electrode T96, the thirteenth core pad CP94, the fourteenth core pad CP95, and the fifteenth core pad CP96 are electrically connected is similar to... Figure 1 The structures of the thirteenth bump 214, fourteenth bump 215, fifteenth bump 216, thirteenth core through electrode T34, fourteenth core through electrode T35, fifteenth core through electrode T56, thirteenth core pad CP34, fourteenth core pad CP35 and fifteenth core pad CP36 shown are similar.

[0182] The sixth path 93 includes the sixteenth core through electrode T97, the seventeenth core through electrode T98, the eighteenth core through electrode T99, the sixteenth core pad CP97, the seventeenth core pad CP98, and the eighteenth core pad CP99.

[0183] The sixteenth core pad CP97, seventeenth core pad CP98, and eighteenth core pad CP99 included in the sixth path 93 can be implemented using a redistribution layer RDL and electrically connected.

[0184] The structure in which the sixteenth bump 817, the seventeenth bump 818, the eighteenth bump 819, the sixteenth core through electrode T97, the seventeenth core through electrode T98, the eighteenth core through electrode T99, the sixteenth core pad CP97, the seventeenth core pad CP98, and the eighteenth core pad CP99 are electrically connected is similar to... Figure 1 The structure in which the sixteenth bump 217, the seventeenth bump 218, the eighteenth bump 219, the sixteenth core through electrode T37, the seventeenth core through electrode T38, the eighteenth core through electrode T39, the sixteenth core pad CP37, the seventeenth core pad CP38, and the eighteenth core pad CP39 are electrically connected is similar.

[0185] The third channel area 94 and the fourth channel area 95 respectively execute the commands as described above. Figure 1 The operations performed in the third channel region 34 and the fourth channel region 35 shown are similar.

[0186] The fourth path 91, the fifth path 92, and the sixth path 93 are disposed along the first direction DIR1 in the region between the surface of the second core chip 90 and the third channel region 94 and the fourth channel region 95 of the second core chip 90. The fourth path 91, the fifth path 92, and the sixth path 93 may be disposed near the edge of the surface of the second core chip 90. The surface of the second core chip 90 may be relative to the edge of the second core chip 90. Figure 5 The directional top or bottom surface.

[0187] Figure 5 The structure shown, in which the base pads BP71 to BP73 are electrically connected to the core pads CP81 to CP89 and CP91 to CP99, is similar to... Figure 2 or Figure 3 The structure shown is in which the base pads BP11 to BP13 are electrically connected to the core pads CP21 to CP29 and CP31 to CP39.

[0188] Figure 5 The through electrodes T71 to T73, core through electrodes T81 to T89, and core through electrodes T91 to T99 shown can all be implemented as cylindrical shapes made of conductive material, such that the basic through electrodes T71 to T73, core through electrodes T81 to T89, and core through electrodes T91 to T99 are vertically stacked through the base chip 70, the first core chip 80, and the second core chip 90. The bumps 711 to 819 can all be implemented as spheres made of conductive material, such that bumps 711 to 719 and 811 to 819 can be directly connected to the printed circuit board.

[0189] although Figure 5 The semiconductor device 3 shown includes a base chip 70, a first core chip 80 and a second core chip 90 arranged in a vertical stacking layout, but depending on the embodiment, different numbers of core chips (e.g., 4, 8 and 12) are stacked on or above the base chip 70.

[0190] As described with respect to the semiconductor device 3 according to an embodiment of the present disclosure, a plurality of pads included in the first core chip 80 and the second core chip 90 are electrically connected, and the pads of the base chip 70 are connected to one of the plurality of pads of the first core chip 80 and the second core chip 90. Therefore, pads located at different positions on the base chip 70 and the core chips 80 and 90 can be electrically connected. In the semiconductor device 3, regardless of the location of the pads of the base chip 70, the core chips 80 and 90, including pads located in various different positions, and the base chip 70 can be electrically connected by connecting the pads of the base chip 70 to one of the plurality of pads of the core chips 80 and 90.

[0191] Figure 6A block diagram illustrating a stacked storage system 4 according to an embodiment of the present disclosure. (See attached diagram.) Figure 6 As shown, the stacked memory system 4 includes a first stacked memory device 3100, a second stacked memory device 3200, a processor 3300, an interposer layer 3400, and a substrate 3500.

[0192] An interposer layer 3400 is formed above or on the substrate 3500. A first stacked memory device 3100, a second stacked memory device 3200, and a processor 3300 are formed above or on the interposer layer 3400. In this example, the processor 3300 is formed between the first stacked memory device 3100 and the second stacked memory device 3200. The interposer layer 3400 electrically connects the substrate 3500, the first stacked memory device 3100, the second stacked memory device 3200, and the processor 3300. Due to the significant difference in spacing between the first stacked memory device 3100, the second stacked memory device 3200, and the processor 3300, they can be electrically connected using various types of wires.

[0193] Processor 3300 includes a first controller 3310 for controlling a first stacked memory device 3100 and a first processing interface circuit (PHY) 3320 electrically connecting the first stacked memory device 3100 and the first controller 3310. Processor 3300 also includes a second controller 3330 for controlling a second stacked memory device 3200 and a second processing interface circuit (PHY) 3340 electrically connecting the second stacked memory device 3200 and the second controller 3330. Processor 3300 transmits signals including commands and addresses controlling various internal operations of the first stacked memory device 3100 to and receives signals from the first stacked memory device 3100 through the first processing interface circuit 3320. Similarly, processor 3300 transmits signals including commands and addresses controlling various internal operations of the second stacked memory device 3200 to and receives signals from the second stacked memory device 3200 through the second processing interface circuit 3340. The first controller 3310 and the second controller 3330 can be used Figure 1 The storage controller 12 shown Figure 4 The storage controller 42 shown or Figure 5 The storage controller 72 shown is used to implement this.

[0194] The first stacked memory device 3100 includes a first base chip 3110 and first core chips 3120, 3130, 3140, and 3150. The first core chips 3120, 3130, 3140, and 3150 are sequentially stacked on or above the first base chip 3110 and receive various signals from the first base chip 3110 via through electrodes. The first stacked memory device 3100 is formed to include four first core chips 3120, 3130, 3140, and 3150, but can be formed by stacking various numbers of core chips (e.g., 4, 8, 16, or other numbers). The first stacked memory device 3100 can be used... Figure 1 Semiconductor device 1 shown Figure 4 The semiconductor device 2 shown or Figure 5 The semiconductor device 3 shown is implemented, including pads and through-electrode arrangements, such as Figures 1 to 5 As shown.

[0195] The first base chip 3110 includes a first core interface circuit PHY 3111. The first core interface circuit 3111 communicates with the first processing interface circuit 3320, receives signals from the processor 3300, and transmits signals generated by the first core chips 3120, 3130, 3140, and 3150 to the processor 3300. The first core interface circuit 3111 can be used... Figure 1 The interface circuit 11 shown Figure 4 The interface circuit 41 shown or Figure 5 The interface circuit 71 shown is used to implement this.

[0196] The second stacked memory device 3200 includes a second base chip 3210 and second core chips 3220, 3230, 3240, and 3250. The second stacked memory device 3200 can be used... Figure 1 The stacked memory device 400 shown is implemented as described. Second core chips 3220, 3230, 3240, and 3250 are sequentially stacked on or above the second base chip 3210 and receive various signals from the second base chip 3210 via through electrodes. The second stacked memory device 3200 is formed to include four second core chips 3220, 3230, 3240, and 3250, but can be formed by stacking various numbers of core chips (e.g., 4, 8, 16, or other numbers). The second stacked memory device 3200 can be used... Figure 1 Semiconductor device 1 shown Figure 4 The semiconductor device 2 shown or Figure 5 The semiconductor device 3 shown is implemented, including pads and through-electrode arrangements, such as Figures 1 to 5 As shown.

[0197] The second base chip 3210 includes a second core interface circuit PHY 3211. The second core interface circuit 3211 communicates with the second processing interface circuit 3340, receives signals from the processor 3300, and transmits signals generated by the second core chips 3220, 3230, 3240, and 3250 to the processor 3300.

[0198] Figure 7 This is a diagram illustrating a stacked storage system 5 according to an embodiment of the present disclosure. Figure 7 As shown, the stacked storage system 5 includes a first stacked memory device 4100, a second stacked memory device 4200, a system control device 4300, a substrate 4400, and a motherboard 4500.

[0199] A substrate 4400 is formed on or above a motherboard 4500. A system control unit 4300 is formed on or above the substrate 4400. A first stacked memory device 4100 and a second stacked memory device 4200 are formed on or above the system control unit 4300. The system control unit 4300 includes a processor 4310, a first controller 4320, a first processing interface circuit PHY 4330, a second controller 4340, and a second processing interface circuit PHY 4350.

[0200] Processor 4310 is electrically connected to first controller 4320 to control various internal operations of first stacked memory device 4100. Processor 4310 transmits signals including commands and addresses for controlling various internal operations of first stacked memory device 4100 to and receives signals from first stacked memory device 4100 via first processing interface circuit 4330. Processor 4310 is electrically connected to second controller 4340 to control various internal operations of second stacked memory device 4200. Processor 4310 transmits signals including commands and addresses for controlling various internal operations of second stacked memory device 4100 to and receives signals from second stacked memory device 4200 via second processing interface circuit 4350. First controller 4320 and second controller 4340 can be used... Figure 1 The storage controller 12 shown Figure 4 The storage controller 42 shown or Figure 5 The storage controller 72 shown is used for implementation. The first processing interface circuit 4330 and the second processing interface circuit 4350 can be used... Figure 1 The interface circuit 11 shown Figure 4 The interface circuit 41 shown or Figure 5 The interface circuit 71 shown is used to implement this.

[0201] The first stacked memory device 4100 includes a first base chip 4110 and first core chips 4120, 4130, 4140, and 4150. The first core chips 4120, 4130, 4140, and 4150 are sequentially stacked on or above the first base chip 4110 and receive various signals from the first base chip 4110 via through electrodes. The first stacked memory device 4100 is formed to include four first core chips 4120, 4130, 4140, and 4150, but can be formed by stacking various numbers of core chips (e.g., 4, 8, 16, or other numbers). The first stacked memory device 4100 can be used... Figure 1 Semiconductor device 1 shown Figure 4 The semiconductor device 2 shown or Figure 5 The semiconductor device 3 shown is implemented, including pads and through-electrode arrangements, such as Figures 1 to 5 As shown.

[0202] The first base chip 4110 includes a first core interface circuit PHY 4111. The first core interface circuit 4111 communicates with the first processing interface circuit 4330, receives signals from the processor 4310, and transmits signals generated by the first core chips 4120, 4130, 4140, and 4150 to the processor 4310.

[0203] The second stacked memory device 4200 includes second core chips 4210, 4220, 4230, and 4240. The second stacked memory device 4200 can be used... Figure 1 The semiconductor device 1 shown is used to implement this. Second core chips 4210, 4220, 4230, and 4240 are stacked sequentially and receive various signals via electrodes. The second stacked memory device 4200 is formed to include four second core chips 4210, 4220, 4230, and 4240, but can be formed by stacking various numbers of core chips (e.g., 4, 8, 16, or other numbers). The second stacked memory device 4200 is configured such that the core chips are stacked on or above the system control device 4300 without a base chip. The second stacked memory device 4200 includes pads and through-electrode arrangements, such as... Figures 1 to 5 As shown.

[0204] The second stacked memory device 4200 communicates with the second processing interface circuit 4350, receives signals from the processor 4310, and transmits signals generated by the second core chips 4210, 4220, 4230 and 4240 to the processor 4310.

[0205] Although detailed embodiments have been described in this disclosure, those skilled in the art will understand that various modifications, additions, and substitutions can be made to these embodiments without departing from the scope and concept of this disclosure. Therefore, the scope of this disclosure should not be limited to the foregoing embodiments. All variations within the equivalent meaning and scope of the claims are included within its scope.

Claims

1. A semiconductor device, comprising: The base chip includes a first base pad, a second base pad, and a third base pad; as well as The core chip includes a first path, a second path, and a third path, wherein the first path includes a first plurality of core pads, the second path includes a second plurality of core pads, and the third path includes a third plurality of core pads. The first base pad is electrically connected to one of the first plurality of core pads; The second base pad is electrically connected to one of the second plurality of core pads; Wherein, the third base pad is electrically connected to one of the third plurality of core pads; and The base chip and the core chip are stacked together.

2. The semiconductor device according to claim 1, wherein: The first base pad supplies power voltage to the core chip; The second base pad outputs commands and addresses that control the operation of the core chip; as well as The third basic pad inputs and outputs data stored in the core chip.

3. The semiconductor device according to claim 1, wherein: The first plurality of core pads included in the first path are electrically connected and supplied with power voltage, which is supplied to the core chip; The second plurality of core pads included in the second path are electrically connected and supplied with commands and addresses to control the operation of the core chip; and The third plurality of core pads included in the third path are electrically connected and input and output data stored in the core chip.

4. The semiconductor device according to claim 1, wherein: The first base pad is positioned at a location corresponding to the position of one of the first plurality of core pads; The second base pad is positioned at a location corresponding to the position of one of the second plurality of core pads; and The third base pad is positioned at a location corresponding to the position of one of the core pads in the third plurality of core pads.

5. The semiconductor device according to claim 1, wherein, The base chip includes: An interface circuit that: receives control signals input from an external device and outputs the control signals to a storage controller; and receives data from the storage controller and outputs the data to the external device; The storage controller, wherein: it applies the power supply voltage supplied to the core chip to the first base pad; receives the control signal from the interface circuit; applies commands and addresses controlling the operation of the core chip to the second base pad; and applies the data stored in the core chip to the third base pad; and The pad area includes the first base pad, the second base pad, and the third base pad.

6. The semiconductor device according to claim 5, wherein, The first base pad, the second base pad, and the third base pad are disposed between the interface circuit and the storage controller.

7. The semiconductor device according to claim 5, wherein, The first base pad, the second base pad, and the third base pad are arranged together with the interface circuit and the storage controller along a first direction.

8. The semiconductor device according to claim 5, wherein, The first base pad, the second base pad, and the third base pad are disposed on the surface of the base chip between the interface circuit and the memory controller.

9. A semiconductor device, comprising: A base chip, comprising base pads disposed between an interface circuit and a memory controller and receiving a power supply voltage; A first core chip includes a first path, the first path including a first plurality of core pads disposed between a first channel region and a second channel region; as well as The second core chip includes a second path, the second path including a second plurality of core pads disposed between a third channel region and a fourth channel region; Wherein, the base pad is electrically connected to one of the first plurality of core pads and is electrically connected to one of the second plurality of core pads; and The base chip, the first core chip, and the second core chip are stacked together.

10. The semiconductor device according to claim 9, wherein: The first plurality of core pads included in the first path are electrically connected; and The second plurality of core pads included in the second path are electrically connected.

11. The semiconductor device according to claim 9, wherein: The first plurality of core pads included in the first path are configured to be spaced apart by a first distance; and The second plurality of core pads included in the second path are configured to be spaced apart by a second distance.

12. The semiconductor device according to claim 9, wherein: The first plurality of core pads are electrically connected to the base pads and supply the power voltage to the first channel region and the second channel region; as well as The second plurality of core pads are electrically connected to the base pads and supply the power voltage to the third channel region and the fourth channel region.

13. The semiconductor device according to claim 9, wherein: The base pad is positioned at a location corresponding to the position of one of the first plurality of core pads; and The base pad is positioned at a location corresponding to the position of one of the second plurality of core pads.

14. The semiconductor device according to claim 12, wherein, The first plurality of core pads includes a first core pad, a second core pad, and a third core pad, and the second plurality of core pads includes a fourth core pad, a fifth core pad, and a sixth core pad: The first core pad is positioned at a location corresponding to the position of the fourth core pad; The second core pad is positioned at a location corresponding to the position of the fifth core pad; and The third core pad is located at a position corresponding to the position of the sixth core pad.

15. A semiconductor device, comprising: A base chip, comprising base pads, the base pads being disposed along a first direction together with interface circuitry and a memory controller; A first core chip includes a first path, the first path including a first plurality of core pads, the first plurality of core pads being disposed together with a first channel region and a second channel region along the first direction; as well as The second core chip includes a second path, the second path including a second plurality of core pads, the second plurality of core pads being arranged together with a third channel region and a fourth channel region along the first direction; Wherein, the base pad is electrically connected to one of the first plurality of core pads and is electrically connected to one of the second plurality of core pads; and The base chip, the first core chip, and the second core chip are stacked together.

16. The semiconductor device of claim 15, wherein: The first plurality of core pads included in the first path are electrically connected; and The second plurality of core pads included in the second path are electrically connected.

17. The semiconductor device of claim 15, wherein: The first plurality of core pads included in the first path are configured to be spaced apart by a first distance; and The second plurality of core pads included in the second path are configured to be spaced apart by a second distance.

18. The semiconductor device of claim 15, wherein: The first plurality of core pads are electrically connected to the base pads and supply power voltage, commands and data to the first channel region and the second channel region; as well as The second plurality of core pads are electrically connected to the base pads and supply the power voltage, the commands, and the data to the third channel region and the fourth channel region.

19. The semiconductor device according to claim 15, wherein, The first plurality of core pads includes a first core pad, a second core pad, and a third core pad, and the second plurality of core pads includes a fourth core pad, a fifth core pad, and a sixth core pad: The first core pad is positioned at a location corresponding to the position of the fourth core pad; The second core pad is positioned at a location corresponding to the position of the fifth core pad; and The third core pad is located at a position corresponding to the position of the sixth core pad.

20. A semiconductor device, comprising: A base chip, including base pads disposed in the area between the surface of the base chip and the interface circuitry and memory controller of the base chip; A first core chip includes a first path, the first path including a first plurality of core pads, the first plurality of core pads being disposed on the surface of the first core chip in a region between a first channel region and a second channel region of the first core chip. as well as The second core chip includes a second path, the second path including a second plurality of core pads, the second plurality of core pads being disposed on the surface of the second core chip in the region between the third channel region and the fourth channel region of the second core chip; Wherein, the base pad is electrically connected to one of the first plurality of core pads, and is electrically connected to one of the second plurality of core pads; and The base chip, the first core chip, and the second core chip are stacked together.

21. A semiconductor device, comprising: A base chip, comprising base pads located at a first location among a plurality of locations; as well as A core chip, which includes a first path, the first path including multiple core pads; The base pad is electrically connected to one of the multiple core pads located at the position corresponding to the first position. The base chip and the core chip are stacked together.

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