Processing apparatus with vector transform execution

Abstract

The invention relates to a processing apparatus with vector transform execution. An integrated circuit (102) includes an instruction pipeline (108) including instruction fetch phase circuitry (110), instruction decode phase circuitry (112), and instruction execution circuitry (114). The instruction execution circuitry includes transform circuitry to receive as input an interleaved dual vector operand and output a first naturally sequential vector including a first set of data values from the interleaved dual vector operand and a second naturally sequential vector including a second set of data values from the interleaved dual vector operand A system.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on May 26, 2020, with application number 202080036614.9 and title "Processing Apparatus for Performing Vector Transformations". Technical Field

[0003] Some example embodiments relate to a processing device, such as a microprocessor or digital signal processor, that can be formed as part of an integrated circuit and included on a system-on-a-chip (SoC). More specifically, embodiments relate to a processing device having vector data processing capabilities, such as a single-instruction, multiple-data (SIMD) processor. Background Technology

[0004] SIMD processing can involve several function units that simultaneously operate on corresponding portions of vector data as parts of an execution cycle. In response to a single SIMD instruction, each function unit receives operands as part of one or two input vectors, depending on the operation to be performed, and outputs its result as part of an output vector during execution. These function units are typically replicated hardware, such as arithmetic logic unit (ALU) hardware. For example, a SIMD processor may contain eight ALU function units, each capable of operating on 64-bit operands. All eight ALU units collectively receive a total of 512 bits (8 units * 64 bits = 512 bits) from the input vector simultaneously (or twice that in a two-operand instruction), perform ALU operations, and output the 512 bits to the output vector. In some processors, the input / output data path for each function unit is called a channel. A channel is a logical construct, sometimes imposed by hardware configuration, that defines the data path for each ALU function unit such that inputs and outputs are confined to the same channel. Therefore, for the previous example, if the 512-bit data vector VB0 is added to the 512-bit data vector VB1, then each data vector is evenly divided among the eight channels, with each channel having 64 bits. Furthermore, the input and output bits are in the same corresponding channel of each data vector, so for example, the least significant channel of VB0 (called VB0[L0]) is added to the least significant channel of VB1 (called VB1[L0]), and the result is output to the corresponding channel in the output data vector VB2, where that channel is called VB2[L0]. Thus, in this same example, for each of the eight 62-bit channels, each corresponding higher significant channel of each data vector is simultaneously added and output, where VB2[L1] = VB0[L1] + VB1[L1], VB2[L2] = VB0[L2] + VB1[L2], and so on until VB2[L7] = VB0[L7] + VB1[L7]. The output data vector VB2 thus maintains the alignment of the input vectors, thus providing what is sometimes called a natural order vector.

[0005] The aforementioned embodiments of SIMD processor operation offer significant advantages, particularly for certain types of data processing, such as computational speed, memory bandwidth, and processor scheduling, where the same operation needs to be performed across multiple independent data values ​​that can be accumulated into a vector. Examples of such data include sensor, video, voice, radar, and biomedical data. However, some mathematical operations may require operands or arithmetic outputs to be rearranged outside the corresponding channels, thereby providing vectors that are not in a natural order. For example, commonly owned U.S. Patent Application No. 16 / 551,587, published December 12, 2019, namely US 2019 / 0377690, is fully incorporated herein by reference and describes various methods and apparatuses for vector permutation in conjunction with such considerations. Those methods and apparatuses offer numerous advantages but may also require considerable complexity.

[0006] Therefore, this document provides example embodiments that improve upon some of the above concepts, as detailed below. Summary of the Invention

[0007] One embodiment includes an integrated circuit comprising an instruction pipeline including an instruction fetch stage circuitry, an instruction decode stage circuitry, and an instruction execution stage circuitry. The instruction execution stage circuitry includes a transformation circuitry for receiving interleaved dual vector operands as input and outputting a first natural order vector containing a first set of data values ​​from the interleaved dual vector operands and a second natural order vector containing a second set of data values ​​from the interleaved dual vector operands.

[0008] It also describes and advocates for other aspects. Attached Figure Description

[0009] Figure 1 A block diagram illustrating the processing device.

[0010] Figure 2A Describe the four least significant 16-bit elements of two natural order vectors VB0 and VB1.

[0011] Figure 2B illustrate Figure 1 A block diagram of the selected aspects of EX stage 114.

[0012] Figure 2C The output is interleaved to vectors VB2 and VB3, thus forming the dual vector DV0. Figure 2B product.

[0013] Figure 3A illustrate Figure 1 An instance of the extra function unit block in function unit block 206.

[0014] Figure 3Billustrate Figure 3A Two additional blocks of PTU 206_1.

[0015] Figure 4A Explanation from Figure 1 An instance of another additional function unit block in function unit block 206.

[0016] Figure 4B illustrate Figure 4B Two additional blocks of PTU 206_2. Detailed Implementation

[0017] Figure 1 This illustration depicts a block diagram of a processing device 100, which may be formed as part of an integrated circuit and included on a System-on-Chip (SoC), such as a microprocessor or a digital signal processor. For example, the processing device 100 may incorporate various processors commercially available from Texas Instruments, including its TMS3207x processor or implemented as modifications thereof. The processing device 100 is described in a simplified form to provide an understanding of exemplary embodiments. Additional details regarding processors that may be included in the processing device 100 can also be found in the above-incorporated U.S. Patent Application No. 16 / 551,587 (US 2019 / 0377690).

[0018] Processing device 100 includes a central processing unit (CPU) core 102, which may represent one or more CPU cores. CPU core 102 is coupled to a program memory (P_MEM) block 104 and a data memory (D_MEM) block 106. Each of the P_MEM block 104 and D_MEM block 106 may and most likely represent hierarchical memory, including one or more controllers accessing one or more memory tiers (e.g., via cache), wherein this memory may include both internal and external memory. Typically, P_MEM block 104 provides program instructions to CPU core 102, and D_MEM block 106 can be read from or written to by CPU core 102. Additionally, and by way of example, certain aspects of such memory can be found in jointly owned U.S. Patent Application No. 16 / 874,436, filed May 14, 2020, and U.S. Patent Application No. 16 / 874,516, filed May 14, 2020, which are incorporated herein by reference in their entirety.

[0019] CPU core 102 includes several stages that collectively provide an instruction pipeline 108 that operates in response to a clock oscillator (e.g., a crystal oscillator, internal or external and not shown separately). For illustrative purposes, and to potentially reduce the total number of stages for simplicity, Figure 1The description describes a pipeline 108 comprising three stages, each of which may contain several stages (not shown individually). The three stages are the instruction fetch (IF) stage 110, the instruction dispatch and decode (DDE) stage 112, and the execution (EX) stage 114. Furthermore, the DDE stage 112 collaborates with two potential data sources: the register file 116 and the stream engine 118. Each pipeline stage represents one or more consecutive actions taken with respect to program instructions.

[0020] Typically, IF stage 110 includes connectivity and hardware (e.g., several registers) to fetch instructions from P_MEM block 104 into a memory device, from which the instructions can then be decoded and dispatched. The address of the fetched instruction is indicated or determined in response to program counter (PC) 120. IF stage 110 may include three stages: program address generation, program memory access, and program instruction reception. It should also be noted that, as used herein, "instruction" may comprise several bits, which collectively comprise several instructions. For example, a fetch may be a 512-bit instruction package that can represent a single executable instruction or can be subdivided into individual instructions (e.g., up to 16 individual instructions, each formed by 32 bits). For example, this example may be implemented where processing device 100 is implemented as a SIMD processor including parallel execution units, each operable to simultaneously execute a corresponding instruction fetched as a portion of a larger instruction package.

[0021] Next, instructions are dispatched and decoded by DDE stage 112. DDE stage 112 may comprise three stages: a dispatch stage that includes buffered instruction packets and potentially splits the packets based on whether the packets contain multiple instructions; and first and second instruction decoding stages that decode the instruction packets (at which point they can be split from dispatch into individual instructions). Similarly, upon completion of DDE stage 112, data operations on the decoded instructions may originate from register file 116 or streaming engine 118, where streaming engine 118 is a separate mechanism that can, in some cases, stream data in a loop, for example, in conjunction with certain instructions. The source data may be in scalar or data vector form, where the data vector form is significantly relevant to the improvements described herein. As a reference example, unless otherwise stated, it is assumed that a single data vector provides a total of eight operands, each operand having 64 bits (512 bits in total per data vector). Also for reference, a byte is defined as 8 bits, a word as 32 bits, and a double word (“Dword”) as 64 bits; thus, an instance data vector provides eight Dwords. However, in the sense of providing a quantitative measure or indication of a single value, the essence of a data vector is that its bits do not necessarily, and in fact cannot, represent the entire 512-bit continuous value. Instead, it consists of equal-sized bits within the 512 bits, each representing a different and separable data value, allowing operations to be performed on each value separately from other values ​​in the same data vector. For example, the earlier background described a 64-bit (two words, or in other words, one Dword) SIMD channel, so a 512-bit data vector can be considered as having eight channels, each one Dword wide. Moreover, in some cases, within a channel, operations on smaller bit-sized quantities can occur, for example, with respect to 16-bit quantities referred to herein as elements. Therefore, according to the prior agreement, the processor least significant channel (64 bits) of data vector VB0 is the 64 least significant bits of that vector (indicated as VB0[L0]), and the second most significant channel of data vector VB0 is the 64 second most significant bits of that vector (indicated as VB0[L1]), and so on until the processor most significant channel of data vector VB0 is the 64 most significant bits of that vector (indicated as VB0[L7]). Thus, function unit operations can be performed on the channel VB0[L0] of the first vector VB0, only on (or within) that operand (e.g., constant addition) or relative to the comparable positioning channel VB1[L0] of the second vector VB1 (e.g., adding the first and second vectors along said channel). Finally, DDE stage 112 also identifies the function unit for executing the instruction and the location for storing the instruction result.

[0022] Following DDE stage 112, the decoded instructions (packets) are submitted to EX stage 114 and executed by EX stage 114. EX stage 114 occurs in conjunction with one or more operands from register file 116 or stream engine 118, where operands may be scalars, or again, such operands may be in the form of one or more data vectors. EX stage 114 may contain several (e.g., five) execution stages, which may also include memory reads and writes, so that there is not necessarily a separate write-back stage. Furthermore, one or more of the execution stages involve the operation of one or more function units operating in parallel. In practice, for the execution of data vector instructions, the function unit may contain several copy hardware structures, each operable to execute its function on a channel of the data vector. For the previously described example, another instance of the function unit is an adder with eight channels (or a larger arithmetic logic unit containing addition functionality) or eight separate adders, each with its own channel, wherein in either case each channel is operable to add a 64-bit portion from the first data vector to a comparable 64-bit portion from the second data vector. Also, as described above and further shown below, in some examples, operations on vector channels can further divide the data across the channel into smaller, equal-sized partitions; for example, across a 64-bit channel, the function unit operation can occur within the comparable 16-bit elements of the 64-bit channel. For example, the least significant sixteen bits in channel VB0[L0] of the first vector VB0 can be performed relative to the least significant sixteen bits in channel VB1[L0] of the second vector VB1, and so on across all similarly positioned 16-bit elements of both the first and second data vectors.

[0023] The core CPU 102 also includes a branch predictor (BP) block 124, which may include additional aspects such as an exit history table, a micro-branch target buffer, and a branch target buffer. Commonly, the BP block 124 performs branch prediction, which may include predicting whether a branch instruction is used (or not used) and, if so, predicting the target address of the branch instruction. In this regard, the BP block 124 receives an input 124_IN providing the current instruction address indicator value (or a portion of that value) of the program counter (PC) 120, from which the BP block 124 provides various options regarding whether a branch instruction is predicted to be used, including instructions that cause loops.

[0024] Figure 2AThe four least significant 16-bit elements of two natural order vectors VB0 and VB1 are described to illustrate an example of the relationship between certain data vectors that can be processed by processing device 100. Thus, the set of four elements for each vector is a single Dword, and the corresponding Dword of each of the two vectors VB0 and VB1 is aligned relative to the other in a channel for function unit execution with similar positioning elements. Therefore, function unit operations can be implemented where each corresponding element serves as an operand, thereby spanning the entire channel, but each operation on the aligned element is independent of elements in other positions within the channel. For example, function unit operations can be performed using the least significant elements VB0 (E0) and VB1 (E0) as operands. Simultaneously, and independently of the execution of the E0 positioning element, the same function unit can be performed using the next most significant elements VB0 (E1) and VB1 (E1) as operands, and can also be performed independently using the next most significant elements VB0 (E2) and VB1 (E2) as operands, and finally also using the next most significant elements VB0 (E3) and VB1 (E3) as operands. Based on the alternative addition instruction type, saturation (reaching the maximum value in a given binary arithmetic case) may or may not occur, but in either case, the carry will not propagate from the addition of two elements to the addition of the second most significant pair of elements. Finally, it should be noted that, for simplicity, Figure 2A This only describes a single channel consisting of 64 bits; however, if vectors VB0 and VB1 are 512-bit vectors, then... Figure 2A The alignment and conventions apply to the other bits of each vector, thereby aligning all eight Dwords of each vector across the eight corresponding channels.

[0025] Figure 2B Explanation from Figure 1A block diagram of selected aspects of EX stage 114. EX stage 114 includes a function unit controller 202 that provides operational control to the function units of EX stage 114, such as enabling (a number of) appropriate function units to input operands and execute and produce their execution outputs during (a number of) appropriate clock cycles. In this respect, function unit controller 202 includes a total of N+1 (e.g., N=7) multiplication function units, but for the sake of simplicity, only the least effective multiplication function unit 204_0 and the most effective multiplication functions up to 204_N (e.g., N=7) are shown, while all N+1 units are included in EX stage 114, and each multiplication function unit is typically operable to output 64 bits along its corresponding channel. Furthermore, each of these multiplication function units is controlled, for example, by the state in one or more control registers in function unit controller 202, to perform multiplication when the current program instruction being processed by processing unit 100 is a multiplication instruction (e.g., processed in a stage immediately preceding DDE stage 112). Function unit controller 202 is also shown to control other function unit blocks 206. Block 206 is simplified to include various details of other function units not shown but which are expected to be included, including but not limited to those previously combined. Figure 1 The details described in EX stage 114 will be discussed later; however, additional function units in such function units will be described in conjunction with certain vector transformations. EX stage 114 also includes a vector operand selection block 208, which can be selected from... Figure 1 The register file 116 and / or stream engine 118 receive data and route, for example, operand data, to other function unit blocks 206 or multiplication function units 204_0 to 204_N. Scalar data can also be used in the EX stage 114, but is not shown for simplicity. Figure 2B It will be displayed in the middle.

[0026] To maintain the precision of an M-bit multiplication, 2*M bits of output are required. Since each multiplication function unit 204_0 to 204_N outputs a 64-bit channel, for N=7, a total of 512 bits ((N+1)*64=512) can be output across all N+1 function units at once. Correspondingly, the multiplication of VB0 and VB1 is a 512-bit multiplication, thus requiring a total of 2*512=1,024 output bits. Therefore, the function unit channels need a total output of 2*512 bits, which is twice the capacity of the collective 512-bit channel and twice the capacity of a single 512-bit data vector. To accommodate the doubling of the data width for multiplication precision, the multiplication function units 204_0 to 204_N then selectively route the outputs of the multiplication function units as described in further detail below to jointly produce the outputs of two different 512-bit data vectors (e.g., vectors VB2 and VB3) as the product of two 512-bit input data vectors (e.g., VB0 and VB1).

[0027] Figure 2B Further explanation is provided regarding the inputs and outputs of multiplication function units 204_0 to 204_N (e.g., N=7) (some have been omitted for simplicity). Multiplication function units 204_0 to 204_N have identical internal structures, but each receives a different first set of corresponding vector data input operands and outputs a corresponding set of vector data based on the corresponding multiplication of the unit. As shown and now described, each multiplication function unit contains four multipliers. The first two of these multipliers each multiply by two corresponding 16-bit elements (half-words) from the less significant positions of the 64-bit portions of VB0 and VB1, producing a corresponding 32-bit product in the output data vector VB2. Simultaneously, the latter two of these multipliers each multiply by two corresponding 16-bit elements from the more significant positions of the 64-bit portions of VB0 and VB1, producing a corresponding 32-bit product in the output data vector VB3.

[0028] Figure 2B Function block 204_0 describes the four instances of multipliers introduced above, and Figure 2CThe operand selection alignment is described as follows: elements from VB0 and VB1 are selected, and the resulting product is output in vectors VB2 and VB3, thus forming a dual vector DV0 (DV0 = VB3:VB2). Specifically, function block 204_0 contains four 16-bit multipliers 210_0, 212_0, 214_0, and 216_0, each receiving operands from vector operand selection block 208. Each of the four multipliers inputs similarly positioned element pairs, such that multiplier 210_0 inputs the least significant elements VB0(E0) and VB1(E0), multiplier 212_0 inputs the second most significant elements VB0(E1) and VB1(E1), multiplier 214_0 inputs the second most significant elements VB0(E2) and VB1(E2), and multiplier 216_0 inputs the second most significant elements VB0(E3) and VB1(E3). However, since each multiplier outputs a 32-bit product, the two less significant multipliers output to vector VB2, and the two more significant multipliers output to vector VB3. Specifically, multiplier 210_0 outputs the 32-bit product of VB0(E0) and VB1(E0) as the least significant two elements (or a word) of the output data vector VB2 (displayed as VB2(E1:E0)), and multiplier 212_0 outputs the 32-bit product of VB0(E1) and VB1(E1) as the second most significant two elements (or a word) of the output data vector VB2 (displayed as VB2(E2:E1)). Therefore, the collective outputs of multipliers 210_0 and 212_0 provide the least significant 64-bit Dword of the output data vector VB2. Multipliers 214_0 and 216_0 operate similarly with respect to the second most significant elements from VB0 and VB1, but this is also true for VB3, but not for VB2. Specifically, multiplier 214_0 outputs the 32-bit product of VB0(E2) and VB1(E2) as the least significant two elements (or a word) of the output data vector VB3 (displayed as VB3(E1:E0)), and multiplier 216_0 outputs the 32-bit product of VB0(E3) and VB1(E3) as the second most significant two elements (or a word) of the output data vector VB3 (displayed as VB3(E2:E1)). Therefore, the combined outputs of multipliers 214_0 and 216_0 provide the least significant 64-bit Dword of the output data vector VB3.

[0029] The preceding description of multiplication function unit 204_0, for each increasingly valid set of four elements from VB0 and VB1, is comparable to that of the remaining multiplication function units 204_1 to 204_N. Thus, as another example, multiplication function unit 204_N comprises four multipliers 210_N, 212_N, 214_N, and 216_N. Multiplier 210_N outputs the 32-bit product of VB0 (E28) and VB1 (E28) as the least significant two elements (or a word) of the most significant Dword of the output data vector VB2 (shown as VB2(E29:E28)), and multiplier 212_N outputs the 32-bit product of VB0 (E29) and VB1 (E29) as the most significant two elements (or a word) of the most significant Dword of the output data vector VB2 (shown as VB2(E31:E30)). Similarly, but with respect to the output vector VB3, the 32-bit product of the outputs VB0 (E30) and VB1 (E31) of multiplier 214_N is used as the least significant two elements (or a word) of the most significant Dword of the output data vector VB3 (displayed as VB3(E29:E28)), and the 32-bit product of the outputs VB0 (E31) and VB1 (E31) of multiplier 216_N is used as the most significant two elements (or a word) of the most significant Dword of the output data vector VB3 (displayed as VB3(E31:E30)). Figure 2C The demonstration will be understood by those skilled in the art. Figure 2B The remaining instances of the multiplication function unit not explicitly shown in the text.

[0030] In view of the preceding text, Figure 2B and 2CEach multiplication function unit multiplies 16-bit element-wise operands from similar positions in VB0 and VB1 to produce a 32-bit product output to vectors VB2 and VB3. Furthermore, the multiplication spans four multipliers, such that the outputs of two less efficient multipliers form a Dword output to one output vector (VB2), while the outputs of two more efficient multipliers form a Dword output to another output vector (VB3). Thus, from the least efficient to the most efficient position, the outputs alternate every other output Dword between output data vectors VB2 and VB3. It should be noted that such output routing can be implemented in various ways. As an example, when multiplication function units 204_0 to 204_N operate simultaneously, another execution unit of other function unit block 206 can be temporarily locked and unable to receive corresponding instructions; in this case, its output bus can be shared with the outputs of multiplication function units 204_0 to 204_N, allowing proper data routing to occur simultaneously for all 1,024 output bits. In all cases, the result is interleaved across each of the two 512-bit data vectors. In other words, the output data vector VB2 has Dwords associated with even-numbered position words (word positions 0, 2, 4, 6, ..., 2N) in the input data vectors VB0 and VB1, while the output data vector VB3 has Dwords associated with odd-numbered position words (word positions 1, 3, 5, 7, ..., 2N+1) in the input data vectors VB0 and VB1. Therefore, when N=7, all multipliers across N+1 multiplication function units have two naturally ordered 512-bit input data vectors (e.g., VB0 and VB1) as inputs, and to maintain precision, output two 512-bit vectors (e.g., VB2 and VB3) that together provide a total of 16 Dwords (64 bits) for the product, for a total of 1,024 product bits. Therefore, the two output vectors can be characterized as a single dual vector DV0 consisting sequentially of two 512-bit (or 8-dword) output vectors (e.g., VB2 and VB3 again). Thus, according to the convention in this document, the dual vector DV0 can be represented as VB3:VB2, where the convention suggests alignment with the Dwords of VB3 (which has higher significant Dword positions) and VB2 (which has fewer significant Dword positions). Furthermore, the aforementioned interleaving is maintained across the entire dual vector DV0 = VB3:VB2, whereby the product of the least significant two consecutive input data vector elements from each 64-bit channel is output to consecutive even-numbered Dwords in the output vector VB2, and the product of the second most significant two consecutive input data vector elements from each 64-bit channel is output to consecutive Dwords in the output vector VB3.

[0031] Figure 3A and 3B Explanation from Figure 1An instance of an additional function unit block in function unit block 206, which takes a dual vector as input (e.g., DV0=VB3:VB2) and outputs two transformed single vectors by rearranging Dword from the input vector to the output vector. Figure 3A This describes the first part of the partial transformation from the dual vector to the first output vector (e.g., VB4), and Figure 3B This describes the second part of the partial transformation from the dual vector to the second output vector (e.g., VB5). Furthermore, in one example embodiment, Figure 3A and Figure 3B The operations of both can occur simultaneously, for example, in response to the execution of the same instruction. In an alternative example embodiment, Figure 3A The operation can occur in response to the execution of the first instruction, and Figure 3B The operation can occur in response to the execution of a second instruction, which indicates a partial transformation of the dual vector into one of the two output vectors. In either case, further details are provided below. Figure 3A and 3B Each of them.

[0032] Figure 3A Explanation from Figure 1 One of the function unit blocks 206 contains a partial transform unit (PTU) 206_1. PTU 206_1 contains a lower even-half PTU 302 and a lower odd-half PTU 304. Each of the lower even-half PTU 302 and the lower odd-half PTU 304 typically contains a switching or routing circuitry (e.g., a multiplexer) for selecting a Dword from a position in the source vector and outputting it to a position in the destination vector. The naming convention for these PTUs and other PTUs described below refers to the vector data position from which the PTU selects the output data, as further illustrated below. Moreover, PTUs 302 and 304, as function units, coexist with other EX stage 114 function units and can operate independently and simultaneously in response to instructions retrieved by IF stage 110 and decoded and dispatched by DDE stage. Specifically, in one embodiment, the processing device 100 includes a Dual Vector to Paired Single Vector (DVTPSV) instruction in its instruction set. The DVTPSV instruction, when fetched and decoded, specifies a 1,204-bit (e.g., interleaved) dual vector as operands and, when executed, produces a pair of single 512-bit data vectors. For example, Figure 3A This describes the DVTPSV instruction operand as the previously described dual vector DV0 = VB3:VB2. Furthermore, recall that the dual vector DV0 is described as interleaved, and therefore... Figure 3AThe description provides the eight least significant DV0 Dwords (VB2) with even-numbered Dwords, for example, from the corresponding products of previously calculated 16-bit multiplications, and relatedly... Figure 3A The specification provides odd-numbered Dwords, which are also the eight most significant DV0 Dwords (VB3) for the corresponding product. As detailed below, in response to the DVTPSV instruction being executed, PTUs 302 and 304 partially transform the elements from the input dual vector into one of two separate natural order vectors (e.g., VB4 and VB5), where Figure 3A Specify the first of the two natural order vectors (e.g., VB4).

[0033] The execution of each of PTUs 302 and 304 in response to the DVTPSV instruction is now described and shown as transforming a portion of the dual vector input into two separate natural order vectors. The lower even-numbered half PTU 302 selects (as shown by the first set of dashed lines passing through it) the four least significant even-numbered Dwords in the dual vector DV0, which are stored in the lower half of the first vector (e.g., VB2) of the two vectors forming the dual vector due to interleaving. Furthermore, the four selected Dwords are output to the four even-numbered Dword positions in the first natural order vector (e.g., VB4). Simultaneously, the lower odd-numbered half PTU 304 selects (as shown by the second set of dashed lines passing through it) the four least significant odd-numbered Dwords in the dual vector DV0, which are stored in the lower half of the second vector (e.g., VB3) of the two vectors forming the dual vector due to interleaving. Furthermore, the four selected Dwords are output to the four odd-numbered Dword positions in the first natural order vector (e.g., VB4). Given... Figure 3A As described above and the results show, half of the interleaved elements of the dual vector (DV0=VB3:VB2) are restored to their natural order in VB4, as shown by the sequence from Dword_0 at the least significant position in VB4 to Dword_7 at the most significant position in VB4.

[0034] Figure 3B This describes the two additional blocks of the first PTU 206_1, namely, the upper even-half PTU 306 and the upper odd-half PTU 308. Each of the upper even-half PTU 306 and the upper odd-half PTU 308 typically coexists with other EX stage 114 function units and responds to the DVTPSV instruction (again in...). Figure 3BThe switching or routing circuitry system is shown as operating with dual vectors DV0 = VB3:VB2. However, as detailed below, in response to the execution of the DVTPSV instruction, PTUs 306 and 308 partially transform the elements from the input dual vectors into the second of two separate natural order vectors (e.g., VB4 and VB5), where Figure 3B Explain the second of the two natural order vectors (e.g., VB5).

[0035] The execution operations of each of PTUs 306 and 308 in response to the DVTPSV instruction are now described, and can be compared with... Figure 3A The PTUs 302 and 304 are compared, but the operation is performed on the upper halves of the two vectors forming the dual vector input operands, and the elements are output to the second natural order output vector VB5. Therefore, PTUs 306 and 308 also transform the portions of the dual vector input into two separate natural order vectors. The upper even-numbered half PTU 304 selects (as shown by the first set of dashed lines passing through it) each of the four most significant even-numbered Dwords in the dual vector DV0, which are stored in the upper half of the first vector (VB2) due to interleaving. Furthermore, the four selected Dwords are output to the four even-numbered Dword positions in the second natural order vector (e.g., VB5). Simultaneously, the upper odd-numbered half PTU 308 selects (as shown by the second set of dashed lines passing through it) the four most significant odd-numbered Dwords in the dual vector DV0, which are stored in the upper half of the second vector (VB3) of the two vectors forming the dual vector due to interleaving. Furthermore, the four selected Dwords are output to four odd-numbered Dword positions in a second natural order vector (e.g., VB5). Given... Figure 3B As described above and in the results, the upper half of each vector forming the interleaved elements of the dual vectors is restored to its natural order in VB5, as shown by the sequence from Dword_8 at the least significant position in VB5 to Dword_F at the most significant position in VB5.

[0036] Figure 4A and 4B Explanation from Figure 1 An instance of an additional function unit block in function unit block 206, and together input two different (e.g., natural order) data vectors (e.g., VB4, VB5) and output a transformed interleaved dual vector (e.g., DV0=VB3:VB2) by rearranging the Dword from the input vector to the output vector. Figure 4A This describes the first part of the partial transformation from the two vectors to the dual vector (VB2), and... Figure 4BThis describes the second part of the partial transformation from two vectors to the dual vector (VB3). Figure 3A and 3B Similar to the above description, alternative embodiments may be implemented. Figure 4A and 4B The structure, in one embodiment, makes, Figure 4A and 4B The operations of both can occur simultaneously, for example, in response to the execution of the same instruction. In an alternative example embodiment, Figure 4A The operation can occur in response to the execution of the first instruction, and Figure 4B The operation can occur in response to the execution of a second instruction, which instructs that a portion of the two naturally ordered input vectors be transformed into the corresponding portion of the dual vector output. In either case, further details are provided below. Figure 4A and 4B .

[0037] Figure 4A Explanation from Figure 1 One of the function unit blocks 206 includes a PTU 206_2 containing a first vector even number Dword PTU 402 and a second vector even number Dword PTU 404. Each of the first vector even number Dword PTU 402 and the second vector even number Dword PTU 404 is also typically a switching or routing circuit system that coexists with other EX stage 114 function units as a function unit and can operate in response to instructions fetched by IF stage 110 and decoded and dispatched by DDE stage. Specifically, the processing device 100 includes in its instruction set a Paired Single Vector to Dual Vector (PSVTDV) instruction, which, when fetched and decoded, specifies two 512-bit vectors (e.g., natural order vectors) as operands and transforms those vectors into 1,204-bit (e.g., interleaved) dual vectors represented as DV0=VB3:VB2 as described above, wherein the least significant 512 bits of that dual vector are in Figure 4A The value is displayed as VB2 and the most significant 512 bits of that dual vector are in Figure 4B The example is shown as VB3. As detailed below, in response to the execution of the PSVTDV instruction, PTUs 402 and 404 partially transform the elements from the two input vectors into an interleaved order of each of the two vectors that together form the dual vector DV0. Therefore, if the input vectors (e.g., VB4 and VB5) are naturally ordered vectors, then the resulting dual vector output is interleaved, as previously described.

[0038] The execution of each of PTUs 402 and 404 in response to the PSVTDV instruction is now described and shown as transforming portions of two input vectors into a first vector in the dual vector output. The first vector even-position Dword PTU 402 selects (as shown by the first set of dashed lines passing through it) each even-position Dword of the first vector (e.g., VB4) (indicated as Dword_0, Dword_2, Dword_4, and Dword_6). Furthermore, the first vector even-position Dword PTU 402 outputs its selected even-position Dwords to the four least significant Dwords in the less efficient vector (e.g., VB2) of the output dual vector (e.g., DV0). Simultaneously, the second vector even-position Dword PTU 404 selects (as shown by the second set of dashed lines passing through it) each even-position Dword of the second vector (e.g., VB5) (indicated as Dword_8, Dword_A, Dword_C, and Dword_E). Furthermore, the second even-numbered Dword PTU 404 outputs its selected even-numbered positioned Dword to the four most efficient Dwords in the less efficient vector (e.g., VB2) of the output dual vector (e.g., DV0). Given Figure 4A As described above and in the results, selecting and outputting even-positioned Dwords of two different vectors (e.g., VB4 and VB5) to form interleaved Dwords as the least significant vector in the dual vector DV0=VB5:VB4, as shown in the sequence from Dword_0 at the least significant position in VB2, then Dword_2 at the second most significant position in VB2, and continuing to Dword_E at the most significant position in VB2.

[0039] Figure 4B This describes two additional blocks of PTU 206_2, namely, the first vector odd-Dword PTU 406 and the second vector odd-Dword PTU 408, which again typically contain functions that coexist with other EX stage 114 function units and operate in response to PSVTDV instructions (again in Figure 4BThis is a switching or routing circuit system combining two input vector operands VB4 and VB5. Similar to PTUs 402 and 404 connected to select and output even-positioned Dwords, PTUs 406 and 408 are connected to select and output odd-positioned Dwords in response to the PSVTDV instruction, but instead select and output odd-positioned Dwords, where the outputs of PTUs 406 and 408 provide the higher effective half of the Dwords of the dual vectors DV0 = VB3:VB2. Specifically, the first vector odd-positioned Dword PTU 406 selects (as shown by the first set of dashed lines passing through it) every other odd-positioned Dword of the first vector (e.g., VB4), and simultaneously, the second vector odd-positioned Dword PTU 408 selects (as shown by the second set of dashed lines passing through it) every other odd-positioned Dword of the second vector (e.g., VB5). Given Figure 4B As described above and in the results, the odd-positioned Dwords of two different vectors (e.g., VB4 and VB5) are selected to be output to form an interleaved Dword as the most significant half of the dual vector DV0=VB5:VB4, as shown in the sequence of Dword_1 at the least significant position in VB3, then Dword_3 at the second most significant position in VB3, and continuing to the most significant position in VB3.

[0040] As will be apparent to those skilled in the art from the foregoing, exemplary embodiments include processing apparatus with an instruction pipeline that includes one or more stages responsive to a specific vector transformation instruction. In exemplary embodiments, the pipeline includes, for example, a structure that decodes and executes an instruction to transform interleaved dual vector operands and responsively outputs a pair of single normal order vectors in response to a Devour Dual Vector to Paired Single Vector (DVTPSV) instruction. In one method, the structure outputs the pair of single normal order vectors simultaneously, for example, in response to a single instruction. In an alternative embodiment, the structure may, for example, respond to two different instructions at two different times, wherein a first of such instructions, when executed, transforms only a first portion (e.g., the odd-dual vector position) into the corresponding single normal order vector, while a second of such instructions, when executed, transforms only a second portion (e.g., the even-dual vector position) into the corresponding single normal order vector. This latter embodiment may be desirable, for example, where only the first or second portion is needed for further processing at a time. Furthermore, this structure can operate as a separate function unit from other function units, allowing one or more of those other function units to execute other corresponding functions simultaneously without adding additional latency, as it can be executed in parallel with other execution units (e.g., those performing arithmetic operations). In the same or different embodiments, the pipeline includes, for example, a structure that, in response to fetching a Paired Single Vector to Dual Vector (PSVTDV) instruction, decodes and executes the instruction to transform two 512-bit vectors (e.g., natural order vectors) as operands and responsively outputs a 1,204-bit (e.g., interleaved) dual vector. In one instance, the first half of the dual vector (e.g., the least significant half) is output at one time in response to a first instruction, and the second half of the dual vector (e.g., the most significant half) is output at another time in response to a second instruction. This latter approach may be desirable, for example, to reduce the total hardware footprint and when only a portion (e.g., half) of the dual vector needs to be output at a time.

[0041] Vector sizes have been provided as examples herein, but other sizes are contemplated. Furthermore, while the above properties are presented in combination, the scope of the invention includes subsets of one or more features in other embodiments. Moreover, changes to function partitioning, etc., are also contemplated, where only a few examples have been provided above, and other examples can be determined by those skilled in the art based on the teachings herein. Therefore, additional modifications to the described embodiments are possible, and other embodiments are also possible within the scope of the appended claims.

Claims

1. An apparatus comprising: The multiplication unit is configured as follows: Receive vector data; Perform a multiplication operation on the vector data; as well as An output vector is generated in response to the multiplication operation; as well as Transformation unit, configured as follows: Receive the vector data; In parallel with the multiplication unit performing the multiplication operation, the words are rearranged from the vector data into a transformed vector; and Output the transformed vector.

2. The apparatus of claim 1, wherein the transformation unit comprises a plurality of multiplexers configured to receive the word from the vector data.

3. The apparatus of claim 2, wherein the plurality of multiplexers are configured to output the transformed vector.

4. The apparatus according to claim 1, The transformation unit includes a lower even-numbered half transformation unit and a lower odd-numbered half transformation unit. The lower even-half transform unit is configured to receive a set of least significant even-numbered positioning Dwords from the first vector received at the transform unit, and The lower odd half transformation unit is configured to receive a set of least significant odd-position Dwords from the second vector received at the transformation unit.

5. The apparatus according to claim 1, The transformation unit includes an upper even-numbered half transformation unit and an upper odd-numbered half transformation unit. The upper even-half transformation unit is configured to receive a set of most significant even-numbered location Dwords from the first vector received at the transformation unit, and The upper odd half transformation unit is configured to receive a set of the most significant odd-numbered localization Dwords from the second vector received at the transformation unit.

6. The apparatus of claim 1, wherein the transformation unit comprises a multiplexer configured to select a Dword from the vector data and output the Dword to a position in the transformed vector.

7. The apparatus according to claim 1, in, In order to receive the vector data, the transformation unit is configured to receive the dual vector; and In order to output the transformed vector, the transformation unit is configured to output two single vectors.

8. The apparatus of claim 1, further comprising a controller, the controller including one or more control registers, The multiplication unit is controlled by the state in one or more control registers in the controller.

9. The apparatus of claim 1, further comprising an instruction pipeline, the instruction pipeline including: Instruction fetching phase; Instruction dispatch and decoding stages; and The instruction execution phase includes the multiplication unit and the transformation unit.

10. The apparatus according to claim 1, The multiplication unit mentioned above is the first multiplication unit. The device further includes a controller and a second multiplication unit. in, In order to receive the vector data, the transformation unit is configured to receive a first set of vector operands and a second set of vector operands. The first multiplication unit is configured to receive the first set of vector operands on the first set of multiplication inputs. The second multiplication unit is configured to receive the second set of vector operands on the second set of multiplication inputs. The controller is configured to control the first multiplication unit and the second multiplication unit to produce the output vector, and The output vector contains interleaved vector operands based on the first set of vector operands and the second set of vector operands.

11. The apparatus according to claim 1, in, In order to receive the vector data, the transformation unit is configured to receive a first vector and a second vector. Specifically, in order to output the transformed vector, the transformation unit is configured to output the dual vector. The transformation unit includes a first set of multiplexers configured to select an even-positioned Dword from the first vector and output the even-positioned Dword from the first vector to the least significant Dword in the less effective vector of the dual vector. The transformation unit includes a second set of multiplexers configured to select an even-numbered Dword from the second vector and output the even-numbered Dword from the second vector to the most effective Dword in the less effective vector of the dual vector.

12. The apparatus according to claim 11, The transformation unit includes a third set of multiplexers configured to select an odd-positioned Dword from the first vector and output the odd-positioned Dword from the first vector to the least significant Dword in the higher significant vector of the dual vectors. The transformation unit includes a fourth set of multiplexers configured to select an odd-positioned Dword from the second vector and output the odd-positioned Dword from the second vector to the highest effective Dword in the higher effective vector of the dual vector.

13. A method comprising: Receive vector data at the multiplication unit; The multiplication operation is performed on the vector data through the multiplication unit; as well as An output vector is generated by the multiplication unit in response to the multiplication operation; The vector data is received at the transformation unit; In parallel with the multiplication unit performing the multiplication operation, the transformation unit rearranges the words from the vector data into a transformed vector; and The transformed vector is output through the transformation unit.

14. The method of claim 13, wherein receiving the vector data at the transformation unit comprises receiving the word from the vector data at a plurality of multiplexers in the transformation unit.

15. The method of claim 14, wherein outputting the transformed vector comprises outputting the transformed vector through the plurality of multiplexers.

16. The method of claim 13, wherein the transformation unit comprises a lower even-numbered half transformation unit and a lower odd-numbered half transformation unit, and wherein the method comprises: At the lower even-numbered half-transformation unit, a set of least significant even-numbered positioning Dwords from the first vector are received; as well as At the lower odd half transform unit, a set of least significant odd-numbered positioning Dwords from the second vector is received.

17. The method of claim 13, wherein the transformation unit comprises an upper even-numbered half transformation unit and an upper odd-numbered half transformation unit, and wherein the method comprises: At the upper even-numbered half-transformation unit, a set of the most significant even-numbered positioning Dwords from the first vector is received; as well as At the upper odd half transformation unit, a set of the highest effective odd positioning Dwords from the second vector is received.

18. The method of claim 13, further comprising: The Dword is selected from the vector data by the multiplexer of the transformation unit; as well as The multiplexer outputs the Dword to the position in the transformed vector.

19. The method according to claim 13, Receiving the vector data at the transformation unit includes receiving the dual vector, and The output of the transformed vector includes two single vectors output through the transformation unit.

20. The method of claim 13, further comprising controlling the multiplication unit based on the state in one or more registers.

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