Method and on-chip bus interconnect system for accessing I / O memory

Abstract

This application provides a method for accessing I / O memory and an on-chip bus interconnect system. The method includes: for an I / O memory address access request initiated by a first requesting node in the system, firstly routing the request to a first routing proxy node associated with the requesting node in the die where the requesting node resides; if the destination slave device node is within the die, the first routing proxy node directly forwards the access request to the destination slave device node; otherwise, it forwards the access request to a second routing proxy node in the die where the destination slave device node resides, and the second routing proxy node forwards the access request to the destination slave device node in the die where the second routing proxy node resides, wherein the destination slave device node is a slave device node that mounts I / O memory containing the I / O memory address. In this way, the expansion of the number of chips and dies in the on-chip bus interconnect system is no longer limited by the hardware resources of the slave device nodes.

Description

Technical Field

[0001] This document relates to the field of computer technology, and in particular to a method for accessing I / O memory and an on-chip bus interconnect system. Background Technology

[0002] An on-chip bus interconnect system may contain one or more chips, and each chip may include one or more dies. In this system, input / output (I / O) memory accesses typically do not require consistency maintenance, so the master node can directly route access requests to slave nodes. For example, in peer-to-peer (P2P) access between Peripheral Component Interconnect Express (PCIe) devices, the master node can access the I / O memory region of the entire system address space, which requires the slave node to have the ability to receive I / O memory accesses initiated by any master node in the system.

[0003] However, as the number of chips and / or the number of dies within a single chip increases in an on-chip bus interconnect system, the number of master nodes also increases accordingly. Since the hardware resources of a single slave node are limited in recording the source node, it is difficult to support direct access from a large number of master nodes, thus limiting the expansion of the number of chips and dies. This problem restricts further scaling of the system and urgently requires corresponding optimization and improvement. Summary of the Invention

[0004] This application provides a method for accessing I / O memory and an on-chip bus interconnect system, which can solve the problem that the limited internal hardware resources of slave device nodes make it difficult to support direct access from a large number of master device nodes, thus limiting the expansion of the number of chips and dies.

[0005] To solve the above-mentioned technical problems, the embodiments of this application are implemented as follows:

[0006] A first aspect provides a method for accessing I / O memory in an on-chip bus interconnect system, the on-chip bus interconnect system including at least one chip, each chip including at least one die, each die including multiple nodes, the multiple nodes including at least one requesting node, at least one routing proxy node and at least one slave node, the slave node having I / O memory accessed by the requesting node, the method comprising:

[0007] The first requesting node determines the location information of the destination slave device node as the first location information based on the I / O memory address to be accessed, generates an access request including the first location information, and sends the access request to the first routing proxy node. The first requesting node is any requesting node in any die on any chip in the at least one chip. The first routing proxy node is a routing proxy node configured to be associated with the first requesting node in the die where the first requesting node is located. The destination slave device node is a slave device node that mounts I / O memory containing the I / O memory address. The first location information includes information indicating the chip where the destination slave device node is located, information indicating the die where the destination slave device node is located, and information indicating the destination slave device node itself.

[0008] The first routing proxy node forwards the access request based on the first location information, wherein:

[0009] If the first routing proxy node is located in the same chip as the one indicated by the first location information, it will directly send the access request to the destination slave device node.

[0010] If the first routing proxy node forwards the access request to the second routing proxy node when the dies indicated by the first location information and the dies where the first routing proxy node is located are not the same dies, the second routing proxy node is a routing proxy node in the dies where the destination slave device node is located that is configured to be associated with the first routing proxy node; and the method further includes: the second routing proxy node sending the access request to the destination slave device node.

[0011] Secondly, an on-chip bus interconnect system is provided, the on-chip bus interconnect system comprising at least one chip, each chip comprising at least one die, each die comprising multiple nodes, the multiple nodes comprising at least one requesting node, at least one routing proxy node, and at least one slave device node, the slave device node being equipped with I / O memory accessible by the requesting node, wherein:

[0012] A first requesting node is configured to determine the location information of the destination slave device node as first location information based on the I / O memory address to be accessed, generate an access request including the first location information, and send the access request to a first routing proxy node. The first requesting node is any requesting node in any die on any chip in the at least one chip. The first routing proxy node is a routing proxy node configured to be associated with the first requesting node in the die where the first requesting node is located. The destination slave device node is a slave device node that mounts I / O memory containing the I / O memory address. The first location information includes information indicating the chip where the destination slave device node is located, information indicating the die where the destination slave device node is located, and information indicating the destination slave device node itself.

[0013] The first routing proxy node is configured to forward the access request based on the first location information, wherein:

[0014] The first routing proxy node is configured to send the access request directly to the destination slave device node when the die indicated by the first location information and the die where the first routing proxy node is located are the same die.

[0015] The first routing proxy node is configured to forward the access request to the second routing proxy node when the dies indicated by the first location information and the dies where the first routing proxy node is located are not the same dies. The second routing proxy node is a routing proxy node in the dies where the destination slave device node is located that is configured to be associated with the first routing proxy node.

[0016] The second routing proxy node is configured to send the access request to the destination slave device node.

[0017] Thirdly, a processor is provided, comprising: an on-chip bus interconnect system as described in the second aspect.

[0018] In this embodiment, for any requesting node in the on-chip bus interconnect system to access an I / O memory address, the requesting node can first route it to a routing proxy node associated with it in the die where it resides, namely the first routing proxy node. If the destination slave device node is within the die, the first routing proxy node directly forwards the access request to it. If the destination slave device node is not within the die, the first routing proxy node forwards the access request to a second routing proxy node in the die where the destination slave device node resides. The second routing proxy node then forwards the access request to the destination slave device node in its own die, where the destination slave device node is a slave device node that mounts the I / O memory containing the I / O memory address. It is easy to see that this solution allows slave device nodes to only record the routing proxy node information within their own die, without needing to pay attention to requesting nodes on other chips or other dies within the same chip. Therefore, the slave device node is not affected by the number of chips in the on-chip bus interconnect system, the number of dies on each chip, or the number of requesting nodes. In this way, the expansion of the number of chips and dies in the on-chip bus interconnect system is no longer limited by the size of the hardware resources of the slave device node. Even if the hardware resources of the slave device node remain unchanged, it can support a larger number of chips and an expansion of the number of dies in the chips. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the routing path for accessing I / O memory in an on-chip bus interconnect system in related technologies.

[0021] Figure 2 This is a schematic diagram of the structure of an on-chip bus interconnect system provided by some embodiments of this application.

[0022] Figure 3 This is a flowchart illustrating a method for accessing I / O memory in an on-chip bus interconnect system, provided by some embodiments of this application.

[0023] Figure 4 This is a schematic diagram of the structure of a first routing component provided in some embodiments of this application.

[0024] Figure 5 This is a schematic diagram of the structure of a second routing component provided in some embodiments of this application.

[0025] Figure 6 This is a flowchart illustrating a method for accessing I / O memory in an on-chip bus interconnect system, provided by some embodiments of this application.

[0026] Figure 7 This is a schematic diagram of the access request routing path for a method of accessing I / O memory in an on-chip bus interconnect system provided by some embodiments of this application.

[0027] Figure 8 This is a schematic diagram illustrating the source node information that the slave device node needs to record in a method for accessing I / O memory in an on-chip bus interconnect system, provided by some embodiments of this application. Detailed Implementation

[0028] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in one or more embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the protection scope of this document.

[0029] The terms "first," "second," etc., used in this application and claims are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in this application and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0030] When accessing I / O memory in an on-chip bus interconnect system, the CPU or other master devices can initiate access to the entire system I / O address space. These I / O address spaces can be partitioned and mounted to slave device nodes (ZHP as mentioned below). The slave device node can be a PCIe or other peripheral devices such as accelerators.

[0031] In related technologies, such as Figure 1 As shown, when a Request Node (RN) on die 0 in chip 0 initiates an I / O memory access, the routing path for the destination I / O memory address to be accessed is as follows: (The path is provided in the original text, but the context is unclear.)

[0032] Path 1-1-1: The RN on die 0 in chip 0 initiates an I / O memory access to ZHP on chip 1. The RN node first routes the access to the cross-chip node (C2C) that interconnects the chip and the target chip (chip 1).

[0033] Path 1-1-2: The C2C on die 0 of chip 1 forwards the I / O memory access to the ZHP on this chip, and the C2C on die 0 of chip 1 routes the I / O memory access to the destination ZHP.

[0034] Path 1-2: The RN on chip 0 initiates an I / O memory access to the ZHP on chip 0. The RN node can directly route the access to the destination ZHP on the chip.

[0035] It is not difficult to see that in the I / O memory access routing schemes of related technologies, the RN directly routes the access to the destination ZHP. Each ZHP node may receive direct access from any chip or RN node within any die. The ZHP needs to record the ID information of all source nodes to return access responses. When there are multiple chips in the system and the number of master devices within the chips increases, the number of access response entries in the ZHP also increases. Due to the limitation of limited hardware resources, this access scheme cannot support the interconnection of more chips, which limits the expansion of the number of chips and dies in the system.

[0036] To address the problem that limited hardware resources within slave device nodes make it difficult to support direct access from a large number of master device nodes, thus restricting the expansion of the number of chips and dies, this application proposes a method for accessing I / O memory in an on-chip bus interconnect system, an on-chip bus interconnect system, and a processor.

[0037] In some embodiments, an on-chip bus interconnect system proposed in this application may include at least one chip, each chip may include at least one die, and each die may include multiple nodes, which may include at least one request node (RN), at least one routing agent node, and at least one slave node, wherein the slave node is equipped with I / O memory accessible by the request node.

[0038] In some embodiments, the routing agent node may be a coherent home node (CHN). The slave node may be a ZCN I / O coherent home node with PCIe optimization (ZHP).

[0039] In some embodiments, each chip includes one or more dies, which also include at least one cross-chip node (Chip to Chip Protocol Gateway, C2C) for cross-chip communication.

[0040] In some embodiments, the on-chip bus interconnect system is a mesh network. The on-chip bus interconnect system may employ a coherent bus, such as a Coherent Hub Interface (CHI) bus, to connect the nodes in the mesh network. A mesh network is a physical connection topology in which on-chip computing nodes (such as CPU cores and memory controllers) are arranged in a two-dimensional grid, with each node directly connected to its adjacent nodes. This network can solve the bandwidth bottleneck of traditional buses and support large-scale parallel communication.

[0041] In some embodiments, the on-chip bus interconnect system may adopt a symmetric multiprocessing (SMP) architecture, that is, the on-chip bus interconnect system includes multiple symmetrical chips (i.e. multiple chips with the same structure), and each pair of chips communicates with each other through cross-chip nodes. Each chip includes at least one die, and each die contains a request node (RN), a routing proxy node (CHN), and a cross-chip node (C2C).

[0042] For example, such as Figure 2 As shown, the on-chip bus interconnect system may include chip 0 and chip 1. Both chip 0 and chip 1 may include die 0 and die 1, wherein die 0 may include multiple nodes, which may include at least one RN, at least one CHN, and at least one C2C. Dies 0 and die 1 have the same structure. The dies in chip 0 and chip 1 can achieve cross-chip communication through their respective C2Cs.

[0043] In some embodiments, the grain may also be referred to as a CCD (cpu die), and the CCD may be a physical grain integrating at least one RN, at least one CHN and at least one C2C.

[0044] The functions of the request node (RN), routing proxy node (CHN), slave device node (ZHP), and cross-shard node (C2C) will be briefly introduced below.

[0045] In some embodiments, a request node (RN) can be used to connect to a CPU or other master device and can initiate I / O memory access to any memory address in the full address space.

[0046] In some embodiments, the slave device node (ZHP) has I / O memory that is accessible to the requesting node (RN); the slave device node (ZHP) can also maintain I / O memory consistency and support PCIe transaction streaming.

[0047] In some embodiments, the routing proxy node (CHN) can be used to forward I / O memory access requests initiated by the request node (RN).

[0048] In some embodiments, cross-chip nodes (C2C) can be used for cross-chip communication between chips. Cross-chip communication generally uses a different transmission protocol than on-chip communication, such as Cache Coherent Interconnect for Accelerators (CCIX) or Peripheral Component Interconnect Express (PCIE).

[0049] In some embodiments, the request node (RN) and the cross-shard node (C2C) are each provided with a first routing component, and the routing proxy node (CHN) is provided with a second routing component.

[0050] In some embodiments, the first routing component is configured with a Request Node Address Route Table (RART). The RART in the first routing component of the request node (RN) contains first configuration information. This first configuration information indicates which routing proxy nodes among the routing proxy nodes included in the die where the request node resides are configured to be associated with the request node, for processing access requests to I / O memory within the request node (RN) and finding the next-level routing destination node. The RART in the first routing component of the cross-chip node (C2C) contains fourth configuration information. For each routing proxy node on a chip other than the chip where the cross-chip node (C2C) resides, the fourth configuration information indicates which routing proxy node on each die of the chip where the cross-chip node (C2C) resides is associated with the routing proxy node, for processing access requests to I / O memory within that (C2C) and finding the next-level routing proxy node.

[0051] In some embodiments, the second routing component is configured with a Local Node Address Route Table (HART), which contains at least one of second and third configuration information. Specifically, for each other die on the chip where a routing agent node resides (excluding the die itself), the second configuration information configured in the HART of the routing agent node indicates the routing agent node associated with the first routing agent node on that other die, in order to find the next-level routing agent node. For each other chip besides the chip where a routing agent node resides, the third configuration information configured in the HART of the routing agent node indicates the cross-chip node on the chip where the routing agent node resides, configured to be associated with cross-chip communication between the chip where the routing agent node resides and the other chips, in order to find the cross-chip node on this chip as the next-level routing destination node.

[0052] In some embodiments, the location information of each node in the on-chip bus interconnect system may include information indicating the chip in which the node is located, information indicating the die in which the node is located, and information indicating the node itself. As an example, the location information of a node may include: the identifier of the chip in which the node is located (e.g., chip ID: chipid), the identifier indicating the die in which the node is located (e.g., die ID: dieid), and the identifier indicating the node itself (e.g., node ID: nodeid).

[0053] In some embodiments, each chip in the on-chip bus interconnect system has a unique chipid within the system, each die has a unique dieid within its chip, and each node has a unique nodeid within its die. The location information of each node may include the chipid of the chip it resides in, the dieid of the die it resides in, and the nodeid of the node itself. Each node's ID information is unique across the entire system. For each slave device node (ZHP), any routing agent node (CHN) within the die knows the dieid and nodeid of that slave device node (ZHP).

[0054] As an example, a node's location information may include: Chipid, dieid, and nodeid, where:

[0055] 1) chipid: A zero value indicates that the node is located on a local chip, while a non-zero value indicates that the node is located on a remote chip. The local chip refers to the chip where the node resides, and the remote chip refers to any chip other than the one where the node resides. Optionally, cross-chip nodes on each chip can be encoded sequentially starting from 1 as the internal logical ID of each cross-chip node. This internal logical ID of the cross-chip node is then considered the valid ID for routing to the destination chip.

[0056] 2) dieid: Each die is sequentially encoded according to the number of dies on a chip, and all nodes on a die have the same dieid;

[0057] 3) nodeid: The node ID of each node in the interconnect network within a die. During routing, this nodeid can be used to route to the corresponding destination node. The encoding method of nodeid is different in different types of interconnect networks. For example, in a mesh network, the coordinates (x, y) of the x and y axes in the first quadrant of the cross coordinate system can be used as the nodeid.

[0058] In some embodiments, during each forwarded access request, whether it is an intra-die, inter-die, or inter-chip access, the destination node ID (TgtID) and source node ID (SrcID) transmitted in the bus can be marked and transmitted using the above-described {chipid, dieid, nodeid} format, where:

[0059] TgtID={Tgtchipid, Tgtdieid, Tgtnodeid};

[0060] SrcID={Srcchipid,Srcdieid,Srcnodeid}.

[0061] In some embodiments, the chip where the target node (Tgtnode) is located is called the target chip (Tgtchip), and the die where the target node is located is called the target die (Tgtdie).

[0062] In some embodiments, a chip's chipid represents the on-chip logical ID of a cross-chip node within that chip that interconnects with cross-chip nodes within other chips. This needs to be distinguished from the actual physical IDs of the chips in the on-chip bus interconnect system.

[0063] In some embodiments, access requests for I / O memory addresses issued by each node in the on-chip bus interconnect system are transmitted in the request channel on the bus. Cross-chip nodes are mainly responsible for transparently transmitting and forwarding access requests. The processing of cross-chip nodes and non-cross-chip nodes (such as requesting nodes and routing agent nodes) in the request channel is as follows:

[0064] 1) Non-cross-shard nodes (such as request nodes and routing proxy nodes)

[0065] For on-chip I / O memory access:

[0066] Tgtchipid=0, Tgtdieid=the dieid of the next-level destination node, Tgtnodeid=the nodeid of the next-level destination node;

[0067] Srcchipid=0, Srcdieid=the dieid of this node, Srcnodeid=the nodeid of this node.

[0068] For cross-chip I / O memory access:

[0069] Tgtchipid=C2C logic ID, Tgtdieid=0, Tgtnodeid=0;

[0070] Srcchipid=0, Srcdieid=the dieid of this node, Srcnodeid=the nodeid of this node.

[0071] 2) Cross-shard nodes (C2C)

[0072] Used to forward I / O access requests sent from other chips to this chip, therefore all are on-chip accesses:

[0073] Tgtchipid=0, Tgtdieid=the dieid of the next-level destination node, Tgtnodeid=the nodeid of the next-level destination node;

[0074] Srcchipid = C2C logic ID, Srcdieid = pass-through parent node dieid, Srcnodeid = pass-through parent node nodeid.

[0075] It should be noted that within a single die, the dieid and nodeid information of a cross-die node are recorded in all other nodes. When Tgtchipid points to the on-chip logic ID (C2C logic ID) of a cross-die node, each node can route to that destination cross-die node based on the recorded dieid and nodeid information of that cross-die node.

[0076] The following description, in conjunction with the accompanying drawings, illustrates a method for accessing I / O memory in an on-chip bus interconnect system provided by an embodiment of this application.

[0077] Some embodiments of this application provide a method for accessing I / O memory in an on-chip bus interconnect system. The on-chip bus interconnect system may include at least one chip, each chip including at least one die, each die including multiple nodes, the multiple nodes including at least one requesting node, at least one routing proxy node, and at least one slave node, the slave node having I / O memory accessed by the requesting node. Figure 3 As shown, the method may include:

[0078] Step 301: The first requesting node determines the location information of the destination slave device node as the first location information based on the I / O memory address to be accessed, generates an access request including the first location information, and sends the access request to the first routing proxy node.

[0079] Wherein, the first requesting node can be any requesting node in any die on any chip in at least one chip included in the on-chip bus interconnect system; the first routing proxy node can be a routing proxy node configured to be associated with the first requesting node in the die where the first requesting node is located; the destination slave device node can be a slave device node that has I / O memory mounted with the I / O memory address to be accessed; the first location information can include information indicating the chip where the destination slave device node is located, information indicating the die where the destination slave device node is located, and information indicating the destination slave device node itself.

[0080] In some embodiments, a single die may contain multiple routing proxy nodes. Within the die, there are no particular constraints on the relationship between request nodes and routing proxy nodes. The relationship between request nodes and routing proxy nodes may be one-to-one, multiple request nodes may be associated with the same routing proxy node, or one request node may be associated with multiple routing proxy nodes.

[0081] In some embodiments, each request node has first configuration information, which indicates the routing proxy nodes configured to be associated with the request node among the routing proxy nodes included in the die where the request node resides. For example, the first configuration information may include identification information of one or more routing proxy nodes associated with the request node within the die where the request node resides, and the identification information may include: dieID and nodeID. In this case, in step 301, the first request node sending the access request to the first routing proxy node may include:

[0082] Based on its own first configuration information, the first requesting node determines that the first requesting node is configured as the first routing proxy node associated with the first requesting node in the crystal where the first requesting node is located;

[0083] The first requesting node sends the access request to the first routing proxy node, and the access request may carry the first location information.

[0084] In some embodiments, in the request node, the dieid and nodeid of the routing agent nodes throughout the chip can be configured in the order of die and routing agent node numbering, ignoring bad nodes (such as damaged or disabled routing agent nodes) within the chip.

[0085] In some embodiments, each request node is provided with a first routing component, which is configured with a Request Node Address Route Table (RART). The RART in the first routing component contains first configuration information, which indicates that the routing proxy node configured to be associated with the request node is one of the routing proxy nodes included in the die where the request node resides. This routing proxy node is used to process access requests for I / O memory within the request node and to find the next-level routing node.

[0086] For example, such as Figure 4 As shown, a first routing component 400 can be configured in the first request node. The RART of the first routing component 400 contains first configuration information, which may include identification information of one or more routing proxy nodes within the die where the request node is located. This identification information may include dieID and nodeID. Based on this, as an example, the first request node determines the location information of the destination slave device node as first location information based on the I / O memory address to be accessed, generates an access request including the first location information, and sends the access request to the first routing proxy node. This may include:

[0087] Step A. The DMR matching unit in the first routing component 400 determines the DMR region that the I / O memory address to be accessed falls into through Direct Map Region (DMR). The DMR region can be defined by a base address (start address) and an end address, or by a base address (its start address) and a region size. When the I / O memory address to be accessed falls within a DMR range, it is considered to have hit that DMR region.

[0088] Step B. The first routing component 400 outputs the hit DMR area: The first routing component 400 can determine the location information of the destination slave device node as the first location information based on the configuration information of the hit DMR area and output it. The location information of the destination slave device node (i.e., the first location information) may include:

[0089] The purpose is to determine the physical chipid of the I / O memory address range contained in the hit DMR region from the chip ID of the device node, such as ZHP_Tgtchipid.

[0090] The destination slave node's die ID, such as ZHP_Tgtdieid, represents the dieid of the destination slave node configured in the hit DMR region. Optionally, ZHP_Tgtdieid has a valid value only when ZHP_Tgtchipid represents the DMR region of the local chip, and no valid value when ZHP_Tgtchipid represents the DMR region of the remote chip.

[0091] The destination node ID is the node ID of the device node itself, such as ZHP_Tgtnodeid, which represents the node ID of the destination device node configured in the hit DMR region. Optionally, ZHP_Tgtnodeid has a valid value only when ZHP_Tgtchipid represents the DMR region of the local chip, and has no valid value when ZHP_Tgtchipid represents the DMR region of the remote chip.

[0092] Step C. The first routing component 400 determines, based on the first configuration information in the register, the first routing agent node configured to be associated with the first request node in the die where the first request node is located, and sends the routing level and location information of the first routing agent node to the output arbitration unit.

[0093] Step D. The output arbitration unit in the first routing component 400 performs output arbitration for the routing agent node: if the first routing agent node is determined to be a first-level agent based on the received routing level, then the location information of the first routing agent node is output.

[0094] Typically, the routing level of the first routing component in a request node (RN) is configured as a first-level proxy, i.e., route_leve=1. In this case, the local route proxy node configured in the first configuration information is directly used as the next-level route destination node, i.e., the first route proxy node.

[0095] The location information of the first routing agent node may include:

[0096] TgtchipID represents the chip ID of the chip where the first routing agent node is located. It can be understood that since the first request node and the first routing agent node are located on the same chip, the value of TgtchipID can be 0.

[0097] TgtdieID represents the die ID of the die where the first routing agent node is located;

[0098] TgtnodeID represents the node ID of the first routing agent node itself.

[0099] In some embodiments, the access request forwarded by the first requesting node to the first routing proxy node may carry the following information:

[0100] The I / O memory address to be accessed;

[0101] The location information of the source node, which is the first requesting node at this time;

[0102] The location information of the destination node, where the destination node is the first routing proxy node;

[0103] The objective is to obtain the location information of the device node, i.e., the first location information.

[0104] Step 302: The first routing proxy node forwards the access request based on the first location information.

[0105] It is understandable that the first routing proxy node can determine the location relationship between the destination slave device node and the first routing proxy node through the first location information. This location relationship can reflect the access attributes of the access request, which may include, but are not limited to, the following three types:

[0106] This access request is an intra-crystal I / O memory access, meaning the destination slave device node and the first routing agent node are located in the same crystal.

[0107] This access request is a cross-die I / O memory access, meaning the destination slave device node and the first routing agent node are located on different dies within the same chip;

[0108] This access request is a cross-chip I / O memory access, meaning the destination slave device node and the first routing agent node are located on different chips.

[0109] In the embodiments of this application, the routing paths are different for access requests with different access attributes. For example, for intra-die I / O memory access, the first routing proxy node can send the access request directly to the destination slave device node, while for cross-die or cross-chip I / O memory access, it cannot be sent directly to the destination slave device node, but must be forwarded through other nodes. These will be explained separately below.

[0110] In some embodiments, the first routing proxy node forwarding the access request based on the first location information may include:

[0111] 1) If the first routing agent node is located in the same die as the die indicated by the first location information (i.e., the access request belongs to I / O memory access within the die), the first routing agent node will send the access request directly to the destination slave device node.

[0112] 2) If the first routing proxy node is located in a different die than the die indicated by the first location information (i.e., the access request is a cross-die I / O memory access, or the access request is a cross-chip I / O memory access), it forwards the access request to the second routing proxy node. The second routing proxy node is a routing proxy node configured to be associated with the first routing proxy node within the die where the destination slave device node resides. Figure 3 The method shown may also include: the second routing proxy node sending the access request to the destination slave device node.

[0113] In the first scenario described above, the first routing proxy node directly sends the access request to the destination slave device node, which may include: the first routing proxy node directly sending the access request to the destination slave device node based on the first location information. As mentioned earlier, since any routing proxy node (CHN) within this die knows the dieid and nodeid of each slave device node (ZHP), the first routing proxy node can directly send the access request to the destination slave device node based on the first location information.

[0114] In some embodiments, each routing proxy node (CHN) is provided with a second routing component, which sends the access request directly to the destination slave device node based on the first location information.

[0115] For case 2) above, it can be further divided into the following two sub-cases:

[0116] Sub-case 1: The access request is a cross-crystal I / O memory access.

[0117] At this time, if the first routing proxy node forwards the access request to the second routing proxy node when the die indicated by the first location information and the die where the first routing proxy node is located are not the same die, the forwarding of the access request to the second routing proxy node may include:

[0118] If the chip indicated by the first location information and the chip where the first routing agent node is located are the same chip, and the die indicated by the first location information and the die where the first routing agent node is located are not the same die (i.e., the access request belongs to cross-die I / O memory access), the first routing agent node will directly send the access request to the second routing agent node on the die indicated by the first location information.

[0119] In some embodiments, each routing proxy node (CHN) has second configuration information. For each other die on the chip where the routing proxy node resides, excluding the die where the routing proxy node resides, the second configuration information of the routing proxy node indicates the routing proxy node associated with the first routing proxy node on that other die. In this case, the first routing proxy node directly sends the access request to the second routing proxy node on the die indicated by the first location information, which may include:

[0120] The first routing proxy node determines, based on its own second configuration information, the routing proxy node associated with the first routing proxy node on the chip indicated by the first location information as the second routing proxy node;

[0121] The first routing proxy node sends the access request directly to the second routing proxy node.

[0122] Specifically, the first routing agent node determines, based on its own second configuration information, the routing agent node associated with the first routing agent node on the dies indicated by the first location information as the second routing agent node, which may include:

[0123] The first routing agent node determines the routing agent node associated with the first routing agent node on the chip indicated by the first location information as the second routing agent node based on its own second configuration information and the identifier ID of the chip where the destination slave device node is located.

[0124] It is understandable that, since the access request in sub-case 1 of the above-mentioned case 2) belongs to I / O memory access across different dies within the same chip, the first proxy routing node within this chip can find the second proxy routing node associated with the first proxy routing node in the die where the destination slave device node is located, based on the ID of the die where the destination slave device node is located.

[0125] In some embodiments, each routing agent node (CHN) is provided with a second routing component, which is configured with a local node address routing table (HART). The HART in the second routing component contains second configuration information. For each other die on the chip where the routing agent node resides (excluding the die itself), the second configuration information of the routing agent node indicates the routing agent nodes associated with the routing agent node on that other die.

[0126] Sub-case 2: The access request is a cross-chip I / O memory access.

[0127] At this time, each chip includes one or more dies, which also include at least one cross-die node for cross-chip communication. If the first routing proxy node forwards the access request to the second routing proxy node when the die indicated by the first location information and the die where the first routing proxy node is located are not the same die, the forwarding of the access request to the second routing proxy node may include:

[0128] If the chip indicated by the first location information and the chip where the first routing proxy node is located are not the same chip, the first routing proxy node forwards the access request to the second routing proxy node on the die where the destination slave device node is located through the first cross-chip node and the second cross-chip node. The first cross-chip node is a cross-chip node on the first chip configured for cross-chip communication between the first chip and the second chip. The first chip is the chip where the first routing proxy node is located, the second chip is the chip where the destination slave device node is located, and the second cross-chip node is a cross-chip node on the second chip that is bound to the first cross-chip node.

[0129] In some embodiments, in sub-case 2 of the above-described second case, the first routing proxy node forwards the access request to the second routing proxy node on the die where the destination slave device node is located via the first cross-shard node and the second cross-shard node, which may include:

[0130] The first routing proxy node determines the first cross-chip node on the first chip and forwards the access request to the first cross-chip node;

[0131] The first cross-chip node forwards the access request to the second cross-chip node on the second chip that is bound to the first cross-chip node;

[0132] The second cross-chip node determines the chip where the destination device node is located, the die where the destination device node is located, and the location of the destination device node itself.

[0133] The second cross-chip node determines the routing proxy node associated with the first routing proxy node on the die where the destination device node is located as the second routing proxy node;

[0134] The second cross-shard node sends the access request to the second routing proxy node.

[0135] In some embodiments, each routing proxy node has third configuration information. For each other chip besides the chip where the routing proxy node resides, the third configuration information of the routing proxy node indicates a cross-chip node on the chip where the routing proxy node resides that is configured to be associated with cross-chip communication between the chip where the routing proxy node resides and the other chips. In this case, the first routing proxy node determining the first cross-chip node on the first chip may include:

[0136] The first routing agent node determines, based on its own third configuration information, the first cross-chip node in the first chip that is configured for cross-chip communication between the first chip and the second chip.

[0137] In some embodiments, after determining the first cross-chip node on the chip based on third configuration information, the first routing proxy node may forward the access request to the first cross-chip node.

[0138] In some embodiments, there is no specific association between routing agent nodes and cross-chip nodes in each chip of an on-chip interconnect system, and each routing agent in a chip can communicate with all cross-chip nodes within that chip.

[0139] As an example, suppose the third configuration information in the first routing agent node may include: the physical chipid of other chips (such as the second chip) and the chip logic ID (C2Clogic ID) of the cross-chip node corresponding to the first chip (i.e. the first chip). Then the first routing agent node can query the third configuration information based on the chipid of the second chip to find the chip logic ID of the cross-chip node corresponding to the second chip in the first chip, thereby determining the first cross-chip node.

[0140] In some embodiments, when there are multiple first cross-chip nodes that are connected to the second chip on the first chip, access requests can be evenly distributed across these multiple first cross-chip nodes by hash calculation in order to balance the load of the first cross-chip nodes.

[0141] In some embodiments, each routing agent node (CHN) is provided with a second routing component, which is configured with a local node address routing table (CHN Address Route Table, HART). The HART in the second routing component contains the third configuration information.

[0142] As an example, such as Figure 5As shown, a second routing component 500 can be configured in the first routing proxy node. The HART of the second routing component 500 contains second configuration information 502 and third configuration information 504. Wherein:

[0143] For each other die on the chip where the first routing agent node is located, excluding the die where the first routing agent node is located, the second configuration information 502 indicates the routing agent node associated with the first routing agent node on that other die;

[0144] For each other die on the chip where the first routing agent node is located, excluding the die where the first routing agent node is located, the third configuration information 504 indicates a cross-chip node on the chip where the first routing agent node is located that is configured to be associated with cross-chip communication between the chip where the first routing agent node is located and the other chip.

[0145] In some embodiments, such as Figure 5 As shown, in the second routing component 500 of the first routing agent node, the nodeids (such as CHN 0, ..., CHN) of the associated routing agent nodes in other dies can be configured in dies according to the die order. <n>As the second configuration information 502, when the destination slave device node to be accessed by the access request is located in another die within this chip, the second configuration information 502 can be queried according to the ID (ZHP_TgtdieID) of the die where the destination slave device node is located, and the routing proxy node associated with the first routing proxy node in another die within this chip can be found as the second routing proxy node.

[0146] In some embodiments, such as Figure 5 As shown, in the second routing component 500 of the first routing proxy node, the physical chipid of other chips (such as the second chip) and the chip-to-chip logical ID (C2C logic id) of the cross-chip node corresponding to the first chip can be used as the third configuration information 504. In this way, the first routing proxy node can directly query the third configuration information based on the chipid of the second chip or query the third configuration information based on the hash calculation result of the chipid of the second chip to find the chip-to-chip logical ID of the cross-chip node corresponding to the second chip in the first chip, thereby determining the first cross-chip node.

[0147] The first routing agent node is configured with the following settings: Figure 5 Based on the second routing component shown, as an example, the first routing proxy node forwards access requests according to the first location information, and may include:

[0148] Step A: The access attribute identification unit 501 in the second routing component 500 performs access attribute identification.

[0149] The access attribute identification unit 501 can identify whether the access request is a cross-chip I / O memory access based on the identifier (ZHP_Phychipid) of the chip where the destination slave node is located carried in the received access request.

[0150] If the access request is a cross-chip I / O memory access, the number of cross-chip nodes connected to the target chip (second chip) on this chip (first chip) needs to be determined first according to the third configuration information 504. When there are multiple cross-chip nodes on this chip (first chip) connected to the cross-chip nodes on the target chip (second chip), step B needs to be executed to determine the on-chip logic ID of the first cross-chip node. When there is only one cross-chip node on this chip (first chip) connected to the cross-chip node on the target chip (second chip), the on-chip logic ID of the cross-chip node on this chip (first chip) can be sent directly to the output arbitration unit 505 according to the third configuration information.

[0151] If the access request is not a cross-chip I / O memory access, but a cross-die I / O memory access, then proceed to step C.

[0152] If the access request is an in-die I / O memory access, the second routing component 500 can directly send the destination slave node location information (ZHP_Tgtchipid, ZHP_Tgtdieid, ZHP_Tgtnodeid) carried in the access request to the output arbitration unit 505.

[0153] Step B: The C2C hash calculation unit 503 in the second routing component 500 calculates the index of the first cross-chip node and determines the on-chip logical ID of the first cross-chip node based on the calculated index.

[0154] The C2C hash calculation unit 503 can perform hash calculations based on the number of cross-chip nodes connected on this chip (first chip) to the cross-chip node on the destination chip (second chip), and look up the corresponding in-chip logical ID of the first cross-chip node based on the calculated index. The hash calculation method can include at least one of the following: power-law hash (P2), non-power-law hash (NP2), and hierarchical hash. Alternatively, it can directly map a first cross-chip node.

[0155] Step C: The second routing component 500 directly queries the second configuration information based on the die ID (ZHP_Tgtdieid) of the destination die, finds the identification information (such as dieid and nodeid) of the second routing agent node with the same logical ID on each die in this chip, and sends it to the output arbitration unit 505.

[0156] Step D, the output arbitration unit 505 performs the following arbitration:

[0157] When the destination chip (ZHP_Phychipid) is a remote chip, the logic ID of the first cross-chip node obtained in step B is used as the Tgtchipid output, and Tgtdieid and Tgtnodeid are 0 by default;

[0158] When the destination slave device node's chip (ZHP_Phychipid) is a local chip, but the destination slave device node's die (ZHP_Tgtdieid) is not a local die, Tgtchipid is 0, and the dieid and nodeid of the second routing agent node obtained in step C are used as Tgtdieid and Tgtnodeid respectively;

[0159] When the destination slave node is located on a local chip (ZHP_Phychipid) and the destination slave node is located on a local die (ZHP_Tgtdieid), Tgtchipid is 0, and the ZHP_Tgtdieid and ZHP_nodeid directly passed in are used as Tgtdieid and Tgtnodeid respectively.

[0160] In short, for a routing proxy node, the next destination node can be determined based on the ID information of the destination slave device node corresponding to the I / O memory address to be accessed by the received access request: If the destination slave device node is within the die where the routing proxy node is located, the access request is directly sent to the destination slave device node based on the nodeid in the destination slave device node's ID information; if the destination slave device node is not within the die where the routing proxy node is located, but within the chip where the routing proxy node is located, the routing proxy node associated with the routing proxy node on the die where the destination slave device node is located is searched in the second configuration information of the routing proxy node, and the access request is sent to the associated routing proxy node; if the destination slave device node is not within the chip where the routing proxy node is located, the cross-chip node on the chip where the routing proxy node is located is searched in the third configuration information of the routing proxy node, and the access request is sent to the found cross-chip node on the chip where the routing proxy node is located.

[0161] In some embodiments, upon receiving an access request from a first routing proxy node, the first cross-slice node can pass the access request transparently to a second cross-slice node on a second chip that is bound to the first cross-slice node. Transparent passing means that the first cross-slice node does not modify the source node ID and destination node ID information in the received access request, but directly passes the received access request to the second cross-slice node. That is, the access request sent by the first routing proxy node to the first cross-slice node and the access request sent by the first cross-slice node to the second cross-slice node carry the same information. For example, both the access request sent by the first routing proxy node to the first cross-slice node and the access request sent by the first cross-slice node to the second cross-slice node can carry the following information:

[0162] The I / O memory address to be accessed;

[0163] The location information of the source node, where the source node is the first routing proxy node;

[0164] The location information of the destination node, which is the second cross-chip node at this time.

[0165] In some embodiments, the access request sent by the first routing proxy node to the first cross-shard node and the access request sent by the first cross-shard node to the second cross-shard node may also carry the location information of the destination slave device node.

[0166] In some embodiments, the second cross-chip node determines the location of the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself, including at least one of the following:

[0167] ① The second cross-chip node determines the location information of the destination slave device node as the second location information based on the I / O memory address in the access request, and includes the second location information in the access request sent to the second routing agent node, wherein the second location information indicates the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself;

[0168] ② The second cross-chip node determines the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself based on the first location information carried in the access request.

[0169] In some embodiments, each cross-chip node has fourth configuration information, which indicates the routing proxy nodes associated with the routing proxy node on each die of the chip where the cross-chip node resides, for each routing proxy node on other chips besides the chip where the cross-chip node resides. In this case, the second cross-chip node may determine the routing proxy node associated with the first routing proxy node on the die where the destination slave device node resides as the second routing proxy node, which may include:

[0170] The second cross-chip node determines the routing agent node associated with the first routing agent node on the die where the destination slave device node is located as the second routing agent node based on its own fourth configuration information.

[0171] In some embodiments, the associated routing proxy nodes have the same intra-crystal logical ID, and the intra-crystal logical ID of the first routing proxy node is carried in the access request sent by the first cross-slice node to the second cross-slice node. In this case, the second cross-slice node, based on its own fourth configuration information, determines that the routing proxy node associated with the first routing proxy node on the slice where the destination device node resides is the second routing proxy node, which may include:

[0172] The second cross-chip node determines, based on its own fourth configuration information, the ID of the die where the destination slave device node is located, and the logical ID within the die of the first routing agent node, that the routing agent node on the die where the destination slave device node is located has the same logical ID within the die as the first routing agent node as the second routing agent node.

[0173] In some embodiments, each cross-chip node is provided with a first routing component, which is configured with a Request Node Address Route Table (RART). The RART in the first routing component contains fourth configuration information. For each routing proxy node on a chip other than the chip where the cross-chip node resides, the fourth configuration information indicates the routing proxy node associated with that routing proxy node on each die of the chip where the cross-chip node resides, used to process access requests to I / O memory in the requesting node and find the next-level routing proxy node.

[0174] As an example, such as Figure 4 As shown, the second cross-chip node is equipped with a first routing component 400. The RART of the first routing component 400 contains fourth configuration information, which may include: the intra-die logical IDs of routing proxy nodes on each die of other chips associated with the intra-die logical ID of the first routing proxy node, such as CHN. <1> dieID, nodeID, ..., CHN <n>dieID, nodeID. At this point, the first routing component 400 in the second cross-shard node can determine the second routing proxy node by performing the following steps:

[0175] Step A. The DMR matching unit in the first routing component 400 determines and outputs the DMR region that the I / O memory address to be accessed falls into through Direct Map Region (DMR). The DMR region can be defined by a base address (start address) and an end address, or by a base address (its start address) and a region size. When the I / O memory address to be accessed falls within a DMR range, it is considered that the DMR region has been hit.

[0176] Step B. The first routing component 400 outputs the hit DMR area.

[0177] The first routing component 400 can determine the location information of the destination slave device node as the first location information based on the configuration information of the hit DMR region and output it.

[0178] The destination device node's location information (i.e., the first location information) may include:

[0179] ZHP_Tgtchipid represents the physical chipid to which the I / O memory address range contained in the hit DMR region belongs;

[0180] ZHP_Tgtdieid represents the dieid of the die where the target slave device node is located in the hit DMR region. Optionally, ZHP_Tgtdieid has a valid value only when ZHP_Tgtchipid represents the DMR region of the local chip, and has no valid value when ZHP_Tgtchipid represents the DMR region of the remote chip.

[0181] ZHP_Tgtnodeid represents the nodeid of the target slave device node configured in the hit DMR region. Optionally, ZHP_Tgtnodeid has a valid value only when ZHP_Tgtchipid represents the DMR region of the local chip, and has no valid value when ZHP_Tgtchipid represents the DMR region of the remote chip.

[0182] Step C. The first routing component 400 can first calculate the index of the second routing proxy node based on the intra-die logical ID (such as CHN logic ID) of the first routing proxy node carried in the input access request, and the ID (ZHP_Tgtdieid) of the die where the destination slave device node is located corresponding to the DMR region hit by the I / O memory address to be accessed:

[0183] agent_chn_index = ZHP_Tgtdieid*chn_num_per_die + CHN logic ID;

[0184] Then, the first routing component 400 can find the dieid and nodeid of the secondary routing agent node that has the same intra-crystal logical ID (such as CHN logic ID) within the same crystal as the destination slave device node, based on the fourth configuration information.

[0185] Step D. The output arbitration unit in the first routing component 400 performs output arbitration for the routing proxy node:

[0186] The output arbitration unit determines that the second routing agent node belongs to the second-level agent based on the routing level configured in the register, and then outputs the location information of the second routing agent node.

[0187] Typically, the routing level of the first routing component in a cross-shard node is configured as a second-level proxy, i.e., route_level=2. In this case, the second routing proxy node found in step C needs to be used as the next-level routing destination node.

[0188] The location information of the second routing agent node may include:

[0189] TgtchipID represents the chip ID of the chip where the second routing agent node is located. It can be understood that since the second cross-chip node and the second routing agent node are located on the same chip, the value of TgtchipID can be 0.

[0190] TgtdieID represents the die ID of the die where the second routing agent node is located;

[0191] TgtnodeID represents the node ID of the second routing agent node itself.

[0192] In some embodiments, the access request forwarded by the second cross-shard node to the second routing proxy node may carry the following information:

[0193] The I / O memory address to be accessed;

[0194] The location information of the source node, where the source node is the second cross-shard node;

[0195] The location information of the destination node, where the destination node is the second routing proxy node;

[0196] The objective is to obtain the location information of the device node, i.e., the second location information.

[0197] As can be seen from the above explanation, for cross-chip nodes, when the received access request comes from the routing proxy node in this chip (such as the access request sent by the first routing proxy node to the first cross-chip node), the access request can be passed through (i.e., without modifying the ID information of the source node and the ID information of the destination node) to the cross-chip node on the destination chip connected to it; when the received access request comes from other chips (such as the access request passed through by the first cross-chip node to the second cross-chip node), after determining the routing proxy node as the next destination node, the ID information of the cross-chip node is used as the ID information of the source node in the access request sent to the routing proxy node, and the ID information of the routing proxy node is used as the ID information of the next destination node.

[0198] In some embodiments of the second scenario described above, after the first routing proxy node forwards the access request to the second routing proxy node... Figure 3 The method shown may also include:

[0199] The second routing proxy node sends the access request to the destination slave device node.

[0200] In some embodiments, the second routing proxy node sends the access request to the destination slave device node, which may include: the second routing proxy node sending the access request to the destination slave device node based on the location information of the destination slave device node.

[0201] In some embodiments, the second-reason proxy node may determine the location information of the destination slave device node according to at least one of the following methods:

[0202] ① The second reason is that the proxy node determines the location information of the destination slave device node again based on the I / O memory address in the access request. The location information of the destination slave device node includes the location of the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself.

[0203] ② The second reason is that the proxy node determines the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself based on the second location information carried in the access request.

[0204] As an example, such as Figure 5 As shown, a second routing component 500 can be configured in the second routing proxy node. The second routing proxy node sends the access request to the destination slave device node based on the location information of the destination slave device node. This can include: the second routing component 500 in the second routing proxy node sending the access request to the destination slave device node based on the location information of the destination slave device node. This process is similar to the forwarding process of the second routing component in the first routing proxy node described above when the received access request is an in-die I / O memory access; therefore, it will not be described again here.

[0205] This application proposes a method for accessing I / O memory in an on-chip bus interconnect system. For any requesting node in the on-chip bus interconnect system initiating an I / O memory address access request, the requesting node can first route the request to a routing proxy node associated with the requesting node in the die where the requesting node resides, i.e., a first routing proxy node. If the destination slave device node is within the die, the first routing proxy node directly forwards the access request to the destination slave device node. If the destination slave device node is not within the die, the first routing proxy node forwards the access request to a second routing proxy node in the die where the destination slave device node resides. The second routing proxy node then forwards the access request to the destination slave device node in its own die, where the destination slave device node is a slave device node that mounts the I / O memory containing the I / O memory address. It is easy to see that this solution allows slave device nodes to only need to record the routing proxy node information within their own die, without needing to pay attention to requesting nodes on other chips or other dies within the same chip. Therefore, the slave device node is not affected by the number of chips in the on-chip bus interconnect system, the number of dies on each chip, or the number of requesting nodes. In this way, the expansion of the number of chips and dies in the on-chip bus interconnect system is no longer limited by the size of the hardware resources of the slave device node. Even if the hardware resources of the slave device node remain unchanged, it can support a larger number of chips and an expansion of the number of dies in the chips.

[0206] Let's combine them again below. Figure 6 and Figure 7 This application describes a method for accessing I / O memory in an on-chip bus interconnect system.

[0207] Some embodiments of this application provide a method for accessing I / O memory in an on-chip bus interconnect system. The on-chip bus interconnect system may include at least one chip, each chip including at least one die, each die including multiple nodes, the multiple nodes including at least one requesting node, at least one routing proxy node, and at least one slave node, the slave node having I / O memory accessed by the requesting node. Figure 6 As shown, the method may include:

[0208] Step 601, Begin.

[0209] Step 602: The first requesting node initiates an access to I / O memory. The first routing component in the first requesting node determines the location information of the destination slave device node as the first location information based on the I / O memory address to be accessed by the access, generates an access request including the first location information, and determines the first routing proxy node.

[0210] Wherein, the first requesting node can be any requesting node in any die on any chip in at least one chip included in the on-chip bus interconnect system; the first routing proxy node can be a routing proxy node configured to be associated with the first requesting node in the die where the first requesting node is located; the destination slave device node can be a slave device node that has I / O memory mounted with the I / O memory address to be accessed; the first location information can include information indicating the chip where the destination slave device node is located, information indicating the die where the destination slave device node is located, and information indicating the destination slave device node itself.

[0211] For details regarding the specific content of the destination device node's location information, and how the first requesting node determines the first routing proxy node, please refer to the above text. Figure 3 The description of the illustrated embodiments will not be repeated here.

[0212] Step 603: The first requesting node forwards the access request to the first routing proxy node, and then proceeds to step 604.

[0213] Step 604: The routing proxy node determines whether the destination slave device node is located on the local chip based on the location information of the destination slave device node, that is, whether ZHP_Tgtchipid is a local chip; if yes, proceed to step 607, otherwise proceed to step 605.

[0214] It should be noted that in step 604 above, step 607 below and step 609 below, the term "routing agent node" refers to any routing agent node, which can be either the first routing agent node or the second routing agent node.

[0215] Step 605: The first routing proxy node determines, based on its third configuration information, that it is configured as a first cross-chip node in the first chip for cross-chip communication between the first chip and the second chip, sends the access request to the first cross-chip node, and the first cross-chip node passes the access request to the second cross-chip node associated with it.

[0216] For details regarding the specific content of the third configuration information and how the first routing proxy node determines the first cross-slice node, please refer to the above text. Figure 3 The description of the illustrated embodiments will not be repeated here.

[0217] Step 606: The second cross-chip node determines the routing agent node with the same internal logical ID as the first routing agent node on the same crystalline chip as the destination slave device node based on its own fourth configuration information, the ID of the destination slave device node and the internal logical ID of the first routing agent node, and then proceeds to step 604.

[0218] For details regarding the specific content of the fourth configuration information and how the second cross-shard node determines the second routing proxy node, please refer to the above text. Figure 3 The description of the illustrated embodiments will not be repeated here.

[0219] Step 607: The routing agent node determines whether the destination slave device node is located in this die based on the location information of the destination slave device node, that is, whether ZHP_Tgtdieid is a local die; if yes, proceed to step 609, otherwise proceed to step 608.

[0220] Step 608: The first routing proxy node determines, based on its own second configuration information, the routing proxy node associated with the first routing proxy node on the chip indicated by the first location information as the second routing proxy node, and then proceeds to step 604.

[0221] For details regarding the specific content of the second configuration information and how the first routing proxy node determines the second routing proxy node, please refer to the above text. Figure 3 The description of the illustrated embodiments will not be repeated here.

[0222] Step 609: The routing proxy node sends the access request directly to the destination slave device node.

[0223] Step 610, End.

[0224] pass Figure 6 As shown in the process diagram, after the first requesting node initiates an I / O memory access request, it is first processed by the first routing component within the first requesting node and routed to the first routing proxy node within this die. After the access request reaches the first routing proxy node, the second routing component in the first routing proxy node may forward the access request in the following three ways:

[0225] 1) In-die I / O memory access: The first routing proxy node directly routes the access request to the destination slave device node to complete the access.

[0226] 2) Cross-die I / O memory access: The first routing proxy node routes the access request to the second routing proxy node in the destination die, and then the second routing component in the second routing proxy node processes the access request and routes it to the destination slave device node to complete the access.

[0227] 3) Cross-chip I / O memory access: The first routing proxy node routes the access request to the first cross-chip node on the same chip, and then the first cross-chip node passes it through to the second cross-chip node on the destination chip. The second cross-chip node processes the access request through its internal first routing component and then routes it to the second routing proxy node in the destination die. The second routing proxy node then processes the access request through its second routing component and routes it to the destination slave device node, thus completing the access.

[0228] Figure 7 The diagram illustrates the routing paths for access requests in the three scenarios described above. Figure 7 As shown:

[0229] 1) The routing paths for I / O memory access within the die include:

[0230] Path 1: The RN on die0 of chip0 initiates an I / O memory access, which is processed by the RART in the RN node and then routed to the first routing proxy node (first CHN) in this die.

[0231] Path 2-3: The HART in the first routing agent node (first CHN) on die0 of chip0 processes the I / O memory access, determines that the I / O memory address of the I / O memory access is the slave device node (ZHP) within this die, and directly routes the I / O memory access to the destination slave device node (ZHP) within this die.

[0232] 2) The routing paths for cross-die I / O memory access include:

[0233] Path 1: The RN on die0 of chip0 initiates an I / O memory access, which is processed by the RART in the RN node and then routed to the first routing proxy node (first CHN) in this die.

[0234] Path 2-1: The HART in the routing proxy node (first CHN) on die0 of chip0 processes the I / O memory access, determines that the I / O memory address of the I / O memory access is a slave device node (ZHP) on another die within this chip, and routes the I / O memory access to the second routing proxy node (second CHN) on the destination die (die1 of chip0).

[0235] Path 2-3: The HART in the second routing agent node (second CHN) on die1 of chip0 processes the I / O memory access, determines that the I / O memory address of the I / O memory access is the slave device node (ZHP) within this die, and directly routes the I / O memory access to the destination slave device node (ZHP) within this die.

[0236] 3) The routing paths for cross-chip I / O memory access include:

[0237] Path 1: The RN on die0 of chip0 initiates an I / O memory access, which is processed by the RART in the RN node and then routed to the first routing proxy node (first CHN) in this die.

[0238] Path 2-2-1: The HART in the first routing proxy node (first CHN) on die0 of chip0 processes the I / O memory access, determines that the I / O memory address of the I / O memory access is the slave device node (ZHP) on the remote chip, and routes the I / O memory access to the second cross-chip node (second C2C) interconnected with the destination chip to forward the I / O memory access.

[0239] Path 2-2-2: The HART in the second cross-chip node (second C2C) on die0 of chip1 processes the I / O memory access, determines that the I / O memory address of the I / O memory access is the slave device node (ZHP) of this chip, and routes the I / O memory access to the second routing proxy node (second CHN) on the destination die (die0 / 1 of chip1).

[0240] Path 2-3: The HART in the second routing agent node (second CHN) on die0 / 1 of chip0 processes the I / O memory access, determines that the I / O memory address of the I / O memory access is the slave device node (ZHP) within this die, and directly routes the I / O memory access to the destination slave device node (ZHP) within this die.

[0241] Will Figure 7 and Figure 1 A comparison reveals that, compared to I / O memory access schemes in related technologies, the scheme provided in this application allows slave device nodes to record only the routing proxy node information within their own die, without needing to pay attention to requesting nodes on other chips or other dies within the same chip. Therefore, slave device nodes are not affected by the number of chips in the on-chip bus interconnect system, the number of dies on each chip, or the number of requesting nodes. Thus, the expansion of the number of chips and dies in the on-chip bus interconnect system is no longer limited by the hardware resource size of the slave device node. Even with unchanged hardware resources for the slave device node, it can support a larger number of chips and an expansion of the number of dies within each chip.

[0242] In addition, such as Figure 8 As shown, in an on-chip bus interconnect system containing at least two chips, for I / O memory access, after being proxied by the routing proxy node (CHN), the slave device node (ZHP) in each die of each chip will only receive I / O memory access forwarded by the routing proxy node (CHN) in its own die. That is, for a slave device node (ZHP), I / O memory access initiated by requesting nodes in other dies and other chips must first be proxied by the routing proxy node (CHN) in its destination die. Therefore, the slave device node (ZHP) only needs to record the SrcID information of n routing proxy nodes (CHN) on its own die so that when the request cache entry is full, it can initiate a retransmission response to the upper level. In this way, the hardware resources of the slave device node (ZHP) are not affected by the expansion of multi-chip connections. The number of chips in the system can change from 1 to n. As long as the number of routing proxy nodes (CHN) in a die remains unchanged and the source node entry resources in the slave device node (ZHP) remain unchanged, it can support the expansion of multi-chips.

[0243] Furthermore, in some embodiments, the resources used for retry in the slave device node (ZHP) can be optimized: during cross-die access, the primary proxy routing agent nodes (CHNs) and secondary proxy routing agent nodes (CHNs) between each die are bound through register configuration; during cross-chip access, the primary proxy routing agent nodes (CHNs) of this chip and the secondary proxy routing agent nodes (CHNs) of the destination chip are bound using the same intra-die logical ID, and the routing agent nodes (CHNs) in the entire system will only receive I / O memory access requests from the routing agent nodes (CHNs) they are bound to, thus ensuring that this proxy routing design does not increase the retry resources of intermediate routing nodes.

[0244] In some embodiments, this application also provides an on-chip bus interconnect system, the on-chip bus interconnect system including at least one chip, each chip including at least one die, each die including multiple nodes, the multiple nodes including at least one request node, at least one routing proxy node and at least one slave device node, the slave device node being equipped with I / O memory accessible by the request node.

[0245] The first requesting node is configured to determine the location information of the destination slave device node as the first location information based on the I / O memory address to be accessed, generate an access request including the first location information, and send the access request to the first routing proxy node.

[0246] Wherein, the first requesting node can be any requesting node in any die on any chip in at least one chip included in the on-chip bus interconnect system; the first routing proxy node can be a routing proxy node configured to be associated with the first requesting node in the die where the first requesting node is located; the destination slave device node can be a slave device node that has I / O memory mounted with the I / O memory address to be accessed; the first location information can include information indicating the chip where the destination slave device node is located, information indicating the die where the destination slave device node is located, and information indicating the destination slave device node itself.

[0247] In some embodiments, a single die may contain multiple routing proxy nodes. Within the die, there are no particular constraints on the relationship between request nodes and routing proxy nodes. The relationship between request nodes and routing proxy nodes may be one-to-one, multiple request nodes may be associated with the same routing proxy node, or one request node may be associated with multiple routing proxy nodes.

[0248] In some embodiments, each request node has first configuration information, which indicates that the routing proxy node in the die containing the request node is configured to be associated with the request node; accordingly, the first request node is configured to determine, based on its own first configuration information, a first routing proxy node in the die containing the first request node is configured to be associated with the first request node, and send the access request to the first routing proxy node.

[0249] In some embodiments, in the request node, the dieid and nodeid of the routing agent nodes throughout the chip can be configured in the order of die and routing agent node numbering, ignoring bad nodes (such as damaged or disabled routing agent nodes) within the chip.

[0250] In some embodiments, each request node is provided with a first routing component, which is configured with a Request Node Address Route Table (RART). The RART in the first routing component contains first configuration information, which indicates that the routing proxy node configured to be associated with the request node is one of the routing proxy nodes included in the die where the request node resides. This routing proxy node is used to process access requests for I / O memory within the request node and to find the next-level routing node.

[0251] The location information of the first routing agent node may include:

[0252] TgtchipID represents the chip ID of the chip where the first routing agent node is located. It can be understood that since the first request node and the first routing agent node are located on the same chip, the value of TgtchipID can be 0.

[0253] TgtdieID represents the die ID of the die where the first routing agent node is located;

[0254] TgtnodeID represents the node ID of the first routing agent node itself.

[0255] In some embodiments, the access request forwarded by the first requesting node to the first routing proxy node may carry the following information:

[0256] The I / O memory address to be accessed;

[0257] The location information of the source node, which is the first requesting node at this time;

[0258] The location information of the destination node, where the destination node is the first routing proxy node;

[0259] The objective is to obtain the location information of the device node, i.e., the first location information.

[0260] The first routing proxy node is configured to forward the access request based on the first location information.

[0261] It is understandable that the first routing proxy node can determine the location relationship between the destination slave device node and the first routing proxy node through the first location information. This location relationship can reflect the access attributes of the access request, which may include, but are not limited to, the following three types:

[0262] This access request is an intra-crystal I / O memory access, meaning the destination slave device node and the first routing agent node are located in the same crystal.

[0263] This access request is a cross-die I / O memory access, meaning the destination slave device node and the first routing agent node are located on different dies within the same chip;

[0264] This access request is a cross-chip I / O memory access, meaning the destination slave device node and the first routing agent node are located on different chips.

[0265] In the embodiments of this application, the routing paths are different for access requests with different access attributes. For example, for intra-die I / O memory access, the first routing proxy node can send the access request directly to the destination slave device node, while for cross-die or cross-chip I / O memory access, it cannot be sent directly to the destination slave device node, but must be forwarded through other nodes. These will be explained separately below.

[0266] 1) The first routing proxy node is configured to send the access request directly to the destination slave device node when the die indicated by the first location information and the die where the first routing proxy node is located are the same die (i.e. the access request belongs to I / O memory access within the die).

[0267] In some embodiments, the first routing proxy node is configured to send the access request directly to the destination slave device node based on the first location information when the die indicated by the first location information and the die where the first routing proxy node is located are the same die (i.e., the access request belongs to I / O memory access within the die).

[0268] In some embodiments, each routing proxy node (CHN) is provided with a second routing component, which sends the access request directly to the destination slave device node based on the first location information.

[0269] 2) The first routing proxy node is configured to forward the access request to the second routing proxy node when the die indicated by the first location information and the die where the first routing proxy node is located are not the same die (i.e., the access request belongs to cross-die I / O memory access, or the access request belongs to cross-chip I / O memory access), wherein the second routing proxy node is a routing proxy node in the die where the destination slave device node is located that is configured to be associated with the first routing proxy node.

[0270] In some embodiments, the second routing proxy node is configured to send the access request to the destination slave device node.

[0271] For case 2) above, it can be further divided into the following two sub-cases:

[0272] Sub-case 1: The access request is a cross-chip I / O memory access. In this case, the first routing proxy node can be configured to send the access request directly to the second routing proxy node on the chip indicated by the first location information when the chip indicated by the first location information and the chip where the first routing proxy node is located are the same chip, and the chip indicated by the first location information and the chip where the first routing proxy node is located are not the same chip (i.e., the access request is a cross-chip I / O memory access).

[0273] In some embodiments, each routing proxy node has second configuration information. For each other die on the chip where the routing proxy node is located, excluding the die where the routing proxy node is located, the second configuration information of the routing proxy node indicates the routing proxy node associated with the first routing proxy node on that other die. Accordingly, the first routing proxy node is configured to determine the routing proxy node associated with the first routing proxy node on the die indicated by the first location information as the second routing proxy node based on its own second configuration information, when the chip indicated by the first location information and the chip where the first routing proxy node is located are the same chip, and the die indicated by the first location information and the die where the first routing proxy node is located are not the same die, and directly send the access request to the second routing proxy node.

[0274] In some embodiments, a first routing proxy node may be configured to determine, based on its own second configuration information and the identifier ID of the die where the destination slave device node is located, a second routing proxy node associated with the first routing proxy node on the die indicated by the first location information.

[0275] In some embodiments, each routing agent node (CHN) is provided with a second routing component, which is configured with a local node address routing table (HART). The HART in the second routing component contains second configuration information. For each other die on the chip where the routing agent node resides (excluding the die itself), the second configuration information of the routing agent node indicates the routing agent nodes associated with the routing agent node on that other die.

[0276] Sub-case 2: The access request is a cross-chip I / O memory access. In this case, each chip includes one or more dies, which also include at least one cross-chip node for cross-chip communication; the first routing proxy node can be configured to forward the access request to a second routing proxy node on the die where the destination slave device node is located, through the first cross-chip node and the second cross-chip node, when the chip indicated by the first location information and the chip where the first routing proxy node is located are not the same chip. The first cross-chip node is a cross-chip node on the first chip configured for cross-chip communication between the first chip and the second chip, the first chip is the chip where the first routing proxy node is located, the second chip is the chip where the destination slave device node is located, and the second cross-chip node is a cross-chip node on the second chip that is bound to the first cross-chip node.

[0277] In some embodiments, the first routing proxy node is configured to determine the first cross-chip node on the first chip and forward the access request to the first cross-chip node if the chip indicated by the first location information and the chip where the first routing proxy node is located are not the same chip.

[0278] In some embodiments, the first cross-chip node is configured to forward the access request to a second cross-chip node on the second chip that is bound to the first cross-chip node.

[0279] In some embodiments, the second cross-chip node is configured to determine the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself, determine the routing proxy node on the die where the destination slave device node is located that is associated with the first routing proxy node as the second routing proxy node, and send the access request to the second routing proxy node.

[0280] In some embodiments, each routing proxy node has third configuration information. For each other chip other than the chip where the routing proxy node is located, the third configuration information of the routing proxy node indicates a cross-chip node on the chip where the routing proxy node is located that is configured to be associated with cross-chip communication between the chip where the routing proxy node is located and the other chip. Accordingly, the first routing proxy node is configured to determine, based on its own third configuration information, a first cross-chip node in the first chip that is configured for cross-chip communication between the first chip and the second chip when the chip indicated by the first location information and the chip where the first routing proxy node is located are not the same chip.

[0281] In some embodiments, each routing agent node (CHN) is provided with a second routing component, which is configured with a local node address routing table (CHN Address Route Table, HART). The HART in the second routing component contains the third configuration information.

[0282] In some embodiments, each cross-chip node has fourth configuration information, which indicates the routing proxy node associated with the routing proxy node on each die of the chip where the cross-chip node is located, for each routing proxy node on other chips besides the chip where the cross-chip node is located; accordingly, the second cross-chip node is configured to determine, according to the fourth configuration information, the routing proxy node associated with the first routing proxy node on the die where the destination slave device node is located as the second routing proxy node.

[0283] In some embodiments, interconnected routing proxy nodes have the same intra-chip logical identifier ID, and the first routing proxy node carries the intra-chip logical ID of the first routing proxy node in the access request sent by the first cross-chip node to the second cross-chip node; correspondingly, the second cross-chip node is configured to determine, based on its own fourth configuration information, the ID of the chip where the destination slave device node is located, and the intra-chip logical ID of the first routing proxy node, the routing proxy node on the chip where the destination slave device node is located that has the same intra-chip logical ID as the first routing proxy node as the second routing proxy node.

[0284] In some embodiments, each cross-chip node is provided with a first routing component, which is configured with a Request Node Address Route Table (RART). The RART in the first routing component contains fourth configuration information. For each routing proxy node on a chip other than the chip where the cross-chip node resides, the fourth configuration information indicates the routing proxy node associated with that routing proxy node on each die of the chip where the cross-chip node resides, used to process access requests to I / O memory in the requesting node and find the next-level routing proxy node.

[0285] The location information of the second routing agent node may include:

[0286] TgtchipID represents the chip ID of the chip where the second routing agent node is located. It can be understood that since the second cross-chip node and the second routing agent node are located on the same chip, the value of TgtchipID can be 0.

[0287] TgtdieID represents the die ID of the die where the second routing agent node is located;

[0288] TgtnodeID represents the node ID of the second routing agent node itself.

[0289] In some embodiments, the access request forwarded by the second cross-shard node to the second routing proxy node may carry the following information:

[0290] The I / O memory address to be accessed;

[0291] The location information of the source node, where the source node is the second cross-shard node;

[0292] The location information of the destination node, where the destination node is the second routing proxy node;

[0293] The objective is to obtain the location information of the device node, i.e., the second location information.

[0294] In some embodiments, the second routing proxy node is configured to send the access request to the destination slave node based on the location information of the destination slave node.

[0295] In some embodiments, the second-reason proxy node may determine the location information of the destination slave device node according to at least one of the following methods:

[0296] ① The second reason is that the proxy node determines the location information of the destination slave device node again based on the I / O memory address in the access request. The location information of the destination slave device node includes the location of the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself.

[0297] ② The second reason is that the proxy node determines the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself based on the second location information carried in the access request.

[0298] The on-chip bus interconnect system provided in this application also implements a method for accessing I / O memory in an on-chip bus interconnect system proposed in this application, and achieves the same technical effect. The details of this application will not be elaborated here.

[0299] This application also provides a processor, including the on-chip bus interconnect system provided in this application, which can achieve the same technical effects, and will not be described in detail here.

[0300] The foregoing has described specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0301] In summary, the above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

[0302] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0303] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0304] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0305] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.< / n> < / n>

Claims

1. A method for accessing I / O memory in an on-chip bus interconnect system, characterized in that, The on-chip bus interconnect system includes at least one chip, each chip includes at least one die, each die includes multiple nodes, the multiple nodes include at least one requesting node, at least one routing proxy node, and at least one slave device node, the slave device node is equipped with I / O memory accessible by the requesting node, and the method includes: The first requesting node determines the location information of the destination slave device node as the first location information based on the I / O memory address to be accessed, generates an access request including the first location information, and sends the access request to the first routing proxy node. The first requesting node is any requesting node in any die on any chip in the at least one chip. The first routing proxy node is a routing proxy node configured to be associated with the first requesting node in the die where the first requesting node is located. The destination slave device node is a slave device node that mounts I / O memory containing the I / O memory address. The first location information includes information indicating the chip where the destination slave device node is located, information indicating the die where the destination slave device node is located, and information indicating the destination slave device node itself. The first routing proxy node forwards the access request based on the first location information, wherein: If the first routing proxy node is located in the same chip as the one indicated by the first location information, it will directly send the access request to the destination slave device node. If the first routing proxy node forwards the access request to the second routing proxy node when the dies indicated by the first location information and the dies where the first routing proxy node is located are not the same dies, the second routing proxy node is a routing proxy node in the dies where the destination slave device node is located that is configured to be associated with the first routing proxy node; and the method further includes: the second routing proxy node sending the access request to the destination slave device node.

2. The method according to claim 1, characterized in that, Each request node has first configuration information, which indicates that the routing proxy node configured to be associated with the request node is one of the routing proxy nodes included in the die where the request node resides. The first request node sends the access request to the first routing proxy node, including: The first requesting node determines, based on its own first configuration information, that the first requesting node is configured as the first routing proxy node associated with the first requesting node in the dies where the first requesting node is located; The first requesting node sends the access request to the first routing proxy node.

3. The method according to claim 1, characterized in that, The first routing proxy node sends the access request directly to the destination slave device node, including: The first routing proxy node sends the access request directly to the destination slave device node based on the first location information.

4. The method according to claim 1, characterized in that, Each chip includes one or more dies, which also include at least one cross-die node for cross-chip communication. The first routing proxy node forwards the access request to a second routing proxy node when the die indicated by the first location information and the die where the first routing proxy node is located are not the same die. This includes: If the chip indicated by the first location information and the chip where the first routing proxy node is located are the same chip, but the die indicated by the first location information and the die where the first routing proxy node is located are not the same die, the first routing proxy node will directly send the access request to the second routing proxy node on the die indicated by the first location information. If the chip indicated by the first location information and the chip where the first routing proxy node is located are not the same chip, the first routing proxy node forwards the access request to the second routing proxy node on the die where the destination slave device node is located through the first cross-chip node and the second cross-chip node. The first cross-chip node is a cross-chip node on the first chip configured for cross-chip communication between the first chip and the second chip. The first chip is the chip where the first routing proxy node is located, the second chip is the chip where the destination slave device node is located, and the second cross-chip node is a cross-chip node on the second chip that is bound to the first cross-chip node.

5. The method according to claim 4, characterized in that, Each routing agent node has second configuration information. For each other die on the chip where the routing agent node is located, excluding the die where the routing agent node is located, the second configuration information of the routing agent node indicates the routing agent node associated with the first routing agent node on the other die. Wherein, the first routing proxy node directly sends the access request to the second routing proxy node on the die indicated by the first location information, including: The first routing proxy node determines, based on its own second configuration information, the routing proxy node associated with the first routing proxy node on the chip indicated by the first location information as the second routing proxy node; The first routing proxy node sends the access request directly to the second routing proxy node.

6. The method according to claim 4, characterized in that, The first routing proxy node forwards the access request to the second routing proxy node on the dies where the destination slave device node is located via the first cross-shard node and the second cross-shard node, including: The first routing proxy node determines the first cross-chip node on the first chip and forwards the access request to the first cross-chip node; The first cross-chip node forwards the access request to the second cross-chip node on the second chip that is bound to the first cross-chip node; The second cross-chip node determines the location of the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself; The second cross-chip node determines the routing proxy node on the die where the destination slave device node is located, which is associated with the first routing proxy node, as the second routing proxy node; The second cross-shard node sends the access request to the second routing proxy node.

7. The method according to claim 6, characterized in that, Each routing agent node has third configuration information. For each other chip besides the chip where the routing agent node is located, the third configuration information of the routing agent node indicates that the chip where the routing agent node is located is configured as a cross-chip node associated with cross-chip communication between the chip where the routing agent node is located and the other chip. Wherein, the first routing proxy node determines the first cross-chip node on the first chip, including: The first routing proxy node determines, based on its own third configuration information, the first cross-chip node in the first chip that is configured for cross-chip communication between the first chip and the second chip.

8. The method according to claim 6, characterized in that, The second cross-chip node determines the location of the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself, including at least one of the following: The second cross-chip node determines the location information of the destination slave device node as the second location information based on the I / O memory address in the access request, and includes the second location information in the access request sent to the second routing agent node. The second location information indicates the location of the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself. The second cross-chip node determines the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself based on the first location information in the access request.

9. The method according to claim 6, characterized in that, Each cross-chip node has fourth configuration information, which indicates the routing proxy node associated with the routing proxy node on each die of the chip where the cross-chip node is located, for each routing proxy node on other chips besides the chip where the cross-chip node is located. Wherein, the second cross-chip node determines the routing proxy node associated with the first routing proxy node on the die where the destination slave device node is located as the second routing proxy node, including: The second cross-chip node determines, based on its own fourth configuration information, the routing proxy node associated with the first routing proxy node on the die where the destination slave device node is located as the second routing proxy node.

10. The method according to any one of claims 4-9, characterized in that, The second routing proxy node sends the access request to the destination slave device node, including: The second routing proxy node sends the access request to the destination slave device node based on the location information of the destination slave device node.

11. The method according to claim 5, characterized in that, The first routing proxy node, based on its own second configuration information, determines the routing proxy node associated with the first routing proxy node on the dies indicated by the first location information as the second routing proxy node, including: The first routing proxy node determines the routing proxy node associated with the first routing proxy node on the chip indicated by the first location information as the second routing proxy node based on its own second configuration information and the identifier ID of the chip where the destination slave device node is located.

12. The method according to claim 9, characterized in that, The interconnected routing proxy nodes have the same intra-crystal logical identifier ID, and the first routing proxy node carries its intra-crystal logical ID in the access request sent by the first cross-crystal node to the second cross-crystal node. The second cross-crystal node, based on its own fourth configuration information, determines the routing proxy node associated with the first routing proxy node on the same cletex as the destination slave device node as the second routing proxy node, including: The second cross-chip node determines, based on its own fourth configuration information, the ID of the die where the destination slave device node is located, and the intra-die logical ID of the first routing proxy node, that the routing proxy node on the die where the destination slave device node is located has the same intra-die logical ID as the first routing proxy node as the second routing proxy node.

13. The method according to any one of claims 1-9 and 11-12, characterized in that, The location information of the target device node includes: The objective is to identify the chip where the device node resides using its identifier ID; The objective is derived from the ID of the die where the device node resides; The purpose is to obtain the ID of the device node itself.

14. An on-chip bus interconnect system, characterized in that, The on-chip bus interconnect system includes at least one chip, each chip includes at least one die, each die includes multiple nodes, the multiple nodes include at least one request node, at least one routing proxy node, and at least one slave node, the slave node is equipped with I / O memory for access by the request node, wherein: A first requesting node is configured to determine the location information of the destination slave device node as first location information based on the I / O memory address to be accessed, generate an access request including the first location information, and send the access request to a first routing proxy node. The first requesting node is any requesting node in any die on any chip in the at least one chip. The first routing proxy node is a routing proxy node configured to be associated with the first requesting node in the die where the first requesting node is located. The destination slave device node is a slave device node that mounts I / O memory containing the I / O memory address. The first location information includes information indicating the chip where the destination slave device node is located, information indicating the die where the destination slave device node is located, and information indicating the destination slave device node itself. The first routing proxy node is configured to forward the access request based on the first location information, wherein: The first routing proxy node is configured to send the access request directly to the destination slave device node when the die indicated by the first location information and the die where the first routing proxy node is located are the same die. The first routing proxy node is configured to forward the access request to the second routing proxy node when the dies indicated by the first location information and the dies where the first routing proxy node is located are not the same dies. The second routing proxy node is a routing proxy node in the dies where the destination slave device node is located that is configured to be associated with the first routing proxy node. The second routing proxy node is configured to send the access request to the destination slave device node.

15. The on-chip bus interconnect system according to claim 14, characterized in that, Each request node has first configuration information, which indicates that the routing proxy node in the die containing the request node is configured to be associated with the request node. The first request node is configured to determine, based on its own first configuration information, a first routing proxy node configured to be associated with the first request node in the die where the first request node is located, and to send the access request to the first routing proxy node.

16. The on-chip bus interconnect system according to claim 14, characterized in that, Each chip includes one or more dies, and also includes at least one cross-chip node for cross-chip communication; wherein, The first routing proxy node is configured to send the access request directly to the second routing proxy node on the first routing proxy node when the chip indicated by the first location information and the chip where the first routing proxy node is located are the same chip, and the die indicated by the first location information and the die where the first routing proxy node is located are not the same die. The first routing proxy node is configured to forward the access request to the second routing proxy node on the die where the destination slave device node is located via a first cross-chip node and a second cross-chip node when the chip indicated by the first location information and the chip where the first routing proxy node is located are not the same chip. The first cross-chip node is a cross-chip node on the first chip configured for cross-chip communication between the first chip and the second chip. The first chip is the chip where the first routing proxy node is located, the second chip is the chip where the destination slave device node is located, and the second cross-chip node is a cross-chip node on the second chip that is bound to the first cross-chip node.

17. The on-chip bus interconnect system according to claim 16, characterized in that, Each routing agent node has second configuration information. For each other die on the chip where the routing agent node is located, excluding the die where the routing agent node is located, the second configuration information of the routing agent node indicates the routing agent node associated with the first routing agent node on the other die. The first routing proxy node is configured to, based on its own second configuration information, determine the routing proxy node associated with the first routing proxy node on the chip indicated by the first location information as the second routing proxy node when the chip indicated by the first location information and the chip where the first routing proxy node is located are the same chip, and the die indicated by the first location information and the die where the first routing proxy node is located are not the same die, and directly send the access request to the second routing proxy node.

18. The on-chip bus interconnect system according to claim 16, characterized in that, The first routing proxy node is configured to determine the first cross-chip node on the first chip and forward the access request to the first cross-chip node when the chip indicated by the first location information and the chip where the first routing proxy node is located are not the same chip. The first cross-chip node is configured to forward the access request to the second cross-chip node on the second chip that is bound to the first cross-chip node; The second cross-chip node is configured to determine the chip where the destination slave device node is located, the die where the destination slave device node is located, and the location of the destination slave device node itself, determine the routing proxy node on the die where the destination slave device node is located that is associated with the first routing proxy node as the second routing proxy node, and send the access request to the second routing proxy node.

19. The on-chip bus interconnect system according to claim 18, characterized in that, Each routing agent node has third configuration information. For each other chip besides the chip where the routing agent node is located, the third configuration information of the routing agent node indicates that the chip where the routing agent node is located is configured as a cross-chip node associated with cross-chip communication between the chip where the routing agent node is located and the other chip. The first routing proxy node is configured to determine, based on its own third configuration information, a first cross-chip node in the first chip that is configured for cross-chip communication between the first chip and the second chip, when the chip indicated by the first location information and the chip where the first routing proxy node is located are not the same chip.

20. The on-chip bus interconnect system according to claim 18, characterized in that, Each cross-chip node has fourth configuration information, which indicates the routing proxy node associated with the routing proxy node on each die of the chip where the cross-chip node is located, for each routing proxy node on other chips besides the chip where the cross-chip node is located. The second cross-chip node is configured to determine, based on the fourth configuration information, the routing proxy node associated with the first routing proxy node on the die where the destination slave device node is located as the second routing proxy node.

21. The on-chip bus interconnect system according to claim 17, characterized in that, The first routing proxy node is configured to determine, based on its own second configuration information and the identifier ID of the die where the destination slave device node is located, the routing proxy node associated with the first routing proxy node on the die indicated by the first location information as the second routing proxy node.

22. The on-chip bus interconnect system according to claim 20, characterized in that, The interconnected routing proxy nodes have the same intra-chip logical identifier ID, and the intra-chip logical ID of the first routing proxy node is carried in the access request sent by the first cross-chip node to the second cross-chip node. The second cross-chip node is configured to determine, based on its own fourth configuration information, the ID of the die where the destination slave device node is located, and the intra-die logical ID of the first routing proxy node, the routing proxy node that has the same intra-die logical ID as the first routing proxy node on the die where the destination slave device node is located.

23. A processor, characterized in that, include: The on-chip bus interconnect system as described in any one of claims 14-22.

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