Flexible direct current converter valve multi-level transient thermal network modeling method and system and storage medium

Abstract

The invention relates to the technical field of flexible direct-current power transmission, in particular to a flexible direct-current converter valve multi-level transient thermal network modeling method and system and a storage medium, and the method comprises the steps: constructing a valve tower level thermal network model; calculating the valve layer power loss of a plurality of serially connected valve layers in the converter valve, updating the valve layer power loss by adopting a first sampling rate, inputting the valve layer power loss into the valve tower level thermal network model, and solving the cooling water temperature corresponding to each serially connected valve layer according to the thermal capacity and thermal resistance parameters; constructing a valve level thermal network model; calculating sub-module power loss of a plurality of serially connected sub-modules in each valve layer, inputting the sub-module power loss into the valve level thermal network model, and solving cooling water temperature corresponding to each sub-module according to the heat exchange parameters; and establishing a device-level thermal network model, and calculating the junction temperature of the power semiconductor device and the internal temperature of the capacitor. According to the invention, the problem of temperature jump distortion of the valve-level thermal network caused by high-frequency cooling water temperature boundary and low-frequency sub-module power updating is effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of flexible direct current transmission, in particular to a multi-level transient thermal network modeling method, system and storage medium for a flexible direct current converter valve. BACKGROUND

[0002] In the operation of a high-voltage direct current transmission system, the power semiconductor devices and capacitors of a flexible direct current converter valve continue to generate heat due to current on-off and energy conversion processes. If the temperature of such key components is out of control, it will directly cause performance degradation or failure of the equipment.

[0003] The current mainstream thermal management scheme often uses the following methods: one is a whole temperature estimation method, which only estimates the average temperature rise state according to the cooling system inlet water temperature and the total loss power of the valve tower, which is easy to cause detection failure of local overheating points; two is a single device static boundary simulation, which defaults the cooling medium temperature of the power module to be constant when analyzing the heat dissipation of the power module alone, which ignores the actual temperature fluctuation along the water cooling system, so that the chip junction temperature calculation result is out of touch with the real heat transfer environment; in order to capture the transient thermal shock of the cooling liquid, the key nodes of the cooling liquid need to be monitored at a high frequency, and due to the complexity of loss calculation, the power consumption of the sub-module can only be updated at a low frequency, and the difference in data rate between the two causes integration difficulties, that is, when the high-frequency cooling data and the low-frequency power data are directly coupled, the temperature value jumps at the input interface of the model, causing stepwise interference.

[0004] The fundamental contradiction of the prior art is that the real-time fluctuation of the cooling system cannot be responded by the power consumption data updated at a low frequency, forming a non-physical temperature mutation, which, when transmitted to the device temperature rise calculation link, causes directional deviation or excessive warning false alarm risk in the evaluation of the semiconductor junction temperature and the internal temperature of the capacitor, misses the real thermal stress accumulation, and finally affects the reliability decision of the converter valve.

[0005] The information disclosed in this BACKGROUND section is only intended to enhance the understanding of the general background of the present disclosure and is not intended to confirm or imply that the information constitutes prior art to the present disclosure. SUMMARY

[0006] The present application provides a multi-level transient thermal network modeling method and system for a flexible direct current converter valve, which can effectively solve the problems in the background art.

[0007] In order to achieve the above purpose, the technical solution adopted by the present application is: The multi-level transient thermal network modeling method for a flexible direct current converter valve comprises the following steps: constructing a valve tower level thermal network model, wherein the valve tower level thermal network model comprises thermal capacity and thermal resistance parameters of the cooling channels and water cooling pipelines of the series valve layers; Setting a measured instantaneous temperature at an inlet of a water cooling circuit of the converter valve as a first boundary condition of the valve tower level thermal network model, wherein a sampling rate of the measured instantaneous temperature is set as a first sampling rate, and the measured instantaneous temperature is collected by using the first sampling rate; Calculating valve layer power losses of a plurality of the series valve layers in the converter valve and updating the valve layer power losses by using the first sampling rate, inputting the valve layer power losses into the valve tower level thermal network model, and solving cooling water temperatures corresponding to each of the series valve layers according to the thermal capacity and thermal resistance parameters; Building a valve layer level thermal network model, the valve layer level thermal network model including a sub-module waterway topology structure and heat exchange parameters of a corresponding valve layer, and the cooling water temperatures of each valve layer being set as second boundary conditions of the corresponding valve layer level thermal network model respectively; Calculating sub-module power losses of a plurality of series sub-modules in each valve layer, inputting the sub-module power losses into the valve layer level thermal network model, and solving the cooling water temperatures corresponding to each sub-module according to the heat exchange parameters, wherein the sub-module power losses are updated by using a second sampling rate lower than the first sampling rate; Building a device level thermal network model, the device level thermal network model including a packaging heat dissipation path of a power semiconductor device, setting the cooling water temperatures of each sub-module as third boundary conditions of the device level thermal network model, and calculating a junction temperature of the power semiconductor device and an internal temperature of a capacitor.

[0008] Further, building a valve tower level thermal network model includes: Obtaining cooling channel geometric structure parameters of the series valve layers and material physical property parameters of the water cooling pipe; Coupling the cooling channel geometric structure parameters and the material physical property parameters to generate the thermal capacity and thermal resistance parameters; Determining a heat flow conduction path between the series valve layers based on a topological connection relationship of the water cooling pipe; Integrating the thermal capacity and thermal resistance parameters and the heat flow conduction path into a transient heat transfer structure of the valve tower level thermal network model.

[0009] Further, solving the cooling water temperatures corresponding to each of the series valve layers according to the thermal capacity and thermal resistance parameters includes: Inputting the measured instantaneous temperature at the inlet of the water cooling circuit as an initial heat flow conduction starting point into the valve tower level thermal network model; Determining a cumulative heat flow propagation process of the valve layer power losses between the series valve layers based on the heat flow conduction path; Calculating a heat flow conduction delay amount according to heat transfer characteristics of the thermal capacity and thermal resistance parameters in the transient heat transfer structure; A dynamic temperature compensation relationship between the power loss of the valve layer and the temperature of the cooling water is established based on the heat flow conduction delay along the heat flow conduction path. The dynamic temperature compensation relationship and the cumulative heat flow propagation process are integrated to generate the real-time cooling water temperature output corresponding to the series valve layer.

[0010] Furthermore, a valve-level thermal network model is constructed, including: Analyze the water circuit topology of each valve layer and identify the parallel branches and series water circuit nodes in the water circuit topology of the sub-modules. Configure the local conduction weights of the heat exchange parameters according to the geometric cross-sectional characteristics and water flow distribution relationship of the parallel branches; The cooling water temperature of each valve layer is set as the second boundary condition of the valve layer-level thermal network model and mapped to the initial temperature field of the series water channel node. The distributed heat conduction architecture of the valve-level heat network model is defined based on the local conduction weights of the heat exchange parameters and the initial temperature field.

[0011] Further, the cooling water temperature corresponding to each of the sub-modules is calculated based on the heat exchange parameters, including: The power loss of the sub-module updated using the second sampling rate is imported into the corresponding sub-module location in the distributed heat conduction architecture; The heat exchange efficiency correlated with the Reynolds number of the parallel branch is used as the first influencing factor, and the equivalent hydraulic diameter and local turbulence intensity of the parallel branch are combined to generate a second influencing factor. The first influence factor and the second influence factor are subjected to a heat conduction weighted aggregation operation based on the local conduction weight; Based on the results of the weighted aggregation operation, a heat flux gradient field is generated in the initial temperature field, driving the forced convection heat exchange process of the fluid micro-elements in the distributed heat conduction architecture. The temperature time-varying sequence of the series water circuit nodes during the forced convection heat exchange process is calculated iteratively. When the differential change of the temperature time-varying sequence is lower than the critical thermal stability threshold, the steady-state cooling water temperature value of each sub-module is obtained.

[0012] Furthermore, a device-level thermal network model is established, including: A three-layer heat dissipation topology for the power semiconductor device is constructed, and the chip bonding layer node, the metallization substrate node, and the thermal interface layer node are connected sequentially in the direction of heat conduction to generate an internal heat flow path for the package. The cooling water temperature of each of the sub-modules is set to the boundary temperature value of the thermal interface layer node. Configure the anisotropic thermal conductivity properties of the metallized substrate nodes to distinguish the physical parameter differences between the longitudinal thermal conductivity of the copper layer and the transverse thermal conductivity of the ceramic layer. The transient thermal power input of the chip bonding layer node is generated based on the switching cycle characteristics of the power loss of the submodule. Establish a radial thermal resistance chain structure for the metal foil layer of the capacitor winding core, including the topological connection of the core center node, the dielectric filling layer node, and the outer shell contact layer node; The cooling water temperature of each of the sub-modules is applied to the contact layer nodes of the outer shell to generate the outer boundary heat transfer conditions of the radial thermal resistance chain structure.

[0013] Further, calculating the junction temperature of the power semiconductor device and the internal temperature of the capacitor includes: Drive the heat transfer on the three-layer heat dissipation topology, and trigger the thermal response of the chip welding area based on the transient thermal power input of the chip bonding layer node and the boundary temperature value of the thermal interface layer node; Record the temperature gradient transfer pattern from the chip bonding layer node to the metallization substrate node, and deduce the junction temperature fluctuation range of the power semiconductor device based on the temperature gradient transfer pattern. The thermal accumulation process of the radial thermal resistance chain structure is activated, and the heat transfer from the dielectric filling layer node to the core center node is driven according to the outer boundary heat transfer conditions. The temperature rise characteristics of the core center node are monitored, and the thermal state inside the wound core is determined as the internal temperature reference point of the capacitor.

[0014] Furthermore, the boundary-driven mechanism of the valve-level thermal network model is optimized, including: The temperature abruptness characteristics of the cooling water temperature corresponding to each valve layer under the second boundary condition caused by the difference in sampling rate are detected. Based on the temperature change characteristics, the inlet heat flux density of the submodule waterway topology is zero-crossing detected to generate a periodic fluctuation threshold. The thermal response hysteresis compensation intensity is adjusted in reverse based on the periodic fluctuation threshold. In the valve-level thermal network model, a negative feedback calibration loop is established based on the initial temperature field of the second boundary condition. According to the negative feedback calibration loop, the periodic fluctuation threshold is constrained to the steady-state heat transfer range, and the boundary temperature calibration amount of the valve-level thermal network model is output. The boundary temperature calibration value is injected into the low-speed heat dissipation region of the parallel branch of the submodule water circuit topology to generate a lower boundary constraint that matches the second sampling rate and is then passed to the cooling water temperature calculation process of each submodule.

[0015] A multi-stage transient thermal network modeling system for flexible DC converter valves, the system comprising: The valve tower model module constructs a valve tower-level thermal network model, setting the measured instantaneous temperature at the inlet of the water-cooled circuit of the converter valve as the first boundary condition of the valve tower-level thermal network model. The valve layer temperature module calculates the valve layer power loss of multiple series valve layers in the converter valve and updates it using the first sampling rate. It inputs the valve layer power loss into the valve tower thermal network model and solves the cooling water temperature corresponding to each series valve layer based on the thermal capacity and thermal resistance parameters. The valve layer model module constructs a valve layer-level thermal network model, and the cooling water temperature of each valve layer is set as the second boundary condition of the corresponding valve layer-level thermal network model. The submodule temperature module calculates the submodule power loss of multiple submodules connected in series within each valve layer, inputs the submodule power loss into the valve layer thermal network model, and solves for the cooling water temperature corresponding to each submodule based on the heat exchange parameters. The device model module establishes a device-level thermal network model, sets the cooling water temperature of each sub-module as the third boundary condition of the device-level thermal network model, and calculates the junction temperature of the power semiconductor device and the internal temperature of the capacitor.

[0016] A computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, can implement any of the methods for modeling multi-level transient thermal networks of flexible DC converter valves.

[0017] The technical solution of this invention can achieve the following technical effects: By constructing a three-level transient thermal network model at the valve tower level, valve layer level, and device level, and introducing a sampling rate mismatch compensation mechanism in the cross-level boundary transfer, the problem of temperature jump distortion in the valve layer thermal network caused by high-frequency cooling water temperature boundary and low-frequency submodule power update is solved, ensuring the thermal state reliability of power semiconductors and capacitors.

[0018] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating the modeling method for multi-level transient thermal networks of flexible DC converter valves; Figure 2 A schematic diagram of the process for constructing a valve tower-level heat network model; Figure 3 A schematic diagram of the process for constructing a valve-level thermal network model; Figure 4 A schematic diagram of the process for establishing a device-level thermal network model. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0023] Example 1; like Figure 1 As shown, this application provides a multi-level transient thermal network modeling method for flexible DC converter valves, the method including: A valve tower-level thermal network model is constructed, which includes the thermal capacity and thermal resistance parameters of the cooling channels and water-cooled pipes of the series valve layer. The instantaneous temperature measured at the inlet of the water-cooled circuit of the converter valve is set as the first boundary condition of the valve tower-level thermal network model, and the sampling rate of the instantaneous temperature is set as the first sampling rate. The instantaneous temperature is collected using the first sampling rate. Calculate the power loss of multiple series valve layers in the converter valve and update it using the first sampling rate. Input the power loss of the valve layer into the valve tower thermal network model and solve the cooling water temperature corresponding to each series valve layer according to the thermal capacity and thermal resistance parameters. A valve-level thermal network model is constructed, which includes the sub-module water circuit topology and heat exchange parameters of the corresponding valve layer. The cooling water temperature of each valve layer is set as the second boundary condition of the corresponding valve-level thermal network model. Calculate the submodule power loss of multiple series-connected submodules in each valve layer, input the submodule power loss into the valve layer thermal network model, and solve the cooling water temperature corresponding to each submodule based on the heat exchange parameters. The submodule power loss is updated using a second sampling rate lower than the first sampling rate. A device-level thermal network model is established, which includes the heat dissipation path of the power semiconductor device package. The cooling water temperature of each sub-module is set as the third boundary condition of the device-level thermal network model, and the junction temperature of the power semiconductor device and the internal temperature of the capacitor are calculated.

[0024] Specifically, firstly, in this embodiment, the valve tower-level thermal network model consists of multiple valve layers connected in series. The cooling channels of each valve layer are connected by water-cooled pipes, and the model is built based on its heat capacity and thermal resistance parameters. Within the model, the heat capacity and thermal resistance relationship of each segment of the water-cooled pipe are defined, while considering the heat exchange effect between the cooling water and the environment to make the calculation results more accurate. In addition, to improve dynamic performance, the cooling pipe structure in the valve tower level can be designed with efficient flow characteristics, for example, by optimizing the cooling water flow rate and temperature difference to ensure rapid response to transient temperature changes. For the instantaneous temperature at the inlet of the water-cooled circuit, this embodiment sets a first boundary condition. The first boundary condition is achieved by arranging a temperature acquisition device at the water-cooled inlet to monitor the inlet in real time. The water cooling temperature is sampled at a high first sampling rate to meet the computational requirements of transient changes. For example, the instantaneous fluid temperature at the inlet of the converter valve can be sampled at a frequency of ten times per second. The collected data is directly input into the valve tower-level thermal network model. This method can dynamically reflect the changing trend of the thermal network and support accurate thermal analysis of the valve layer. Next, the power loss inside the valve layer needs to be calculated. This embodiment performs a detailed analysis of the power loss of multiple series valve layers in the converter valve. For example, under a specific operating state, the power loss of each valve layer may change due to different load conditions. The valve layer power loss is updated by a high sampling rate, i.e., the first sampling rate. The dynamically changing data is input into the valve tower-level thermal network model. The model uses input power loss and thermal resistance parameters to update the cooling water temperature of each valve layer in real time, ensuring that the modeling results are consistent with the actual dynamic temperature field. The valve layer-level thermal network model is further refined to the internal structure of the corresponding valve layer. In this embodiment, a sub-module water circuit topology is established for each valve layer, and the cooling water temperature is stratified as a second boundary condition in combination with heat exchange parameters. A preferred scheme can introduce a multi-layer simulator to comprehensively analyze the load and heat dissipation effect of each sub-module. For example, for a single valve layer, its internal water circuit can adopt a parallel multi-channel structure to improve cooling efficiency. At the same time, the heat exchange coefficient of each channel is calibrated based on experimental data to meet the accuracy requirements. At this stage, the power loss of the sub-module is lower than that of the valve layer. The first sampling rate is updated to the second sampling rate to achieve more stable analysis results. For the device-level thermal network model, this embodiment further refines it to the heat dissipation path of the power semiconductor device package. Specifically, the cooling water temperature of the sub-module is used as the third boundary condition to support the analysis of the junction temperature of the power semiconductor device and the internal temperature of the capacitor. For example, in specific applications, the loss and heat dissipation path characteristics of a single power semiconductor device can be monitored. Combined with the thermal resistance of the packaging material and the internal heat conduction path, the temperature change of the critical junction temperature can be estimated. In addition, for the temperature change of the capacitor, this embodiment calculates the thermal imbalance state between the internal heating of the capacitor and the cooling of the environment by dynamically responding to the change of the cooling water temperature, so as to ensure the thermal stability of the system operation.

[0025] The technical solution of this invention constructs a three-level transient thermal network model of valve tower level, valve layer level and device level. A sampling rate mismatch compensation mechanism is introduced in the cross-level boundary transfer, which solves the problem of temperature jump distortion in valve layer thermal network caused by high frequency cooling water temperature boundary and low frequency sub-module power update, and ensures the thermal state reliability of power semiconductors and capacitors.

[0026] Furthermore, such as Figure 2 As shown, a valve tower-level thermal network model is constructed, including: Obtain the geometric parameters of the cooling channels of the series valve layer and the material properties of the water-cooled pipes; The thermal capacity and thermal resistance parameters are generated by coupling the geometric parameters of the cooling channel with the material properties. The heat flow conduction path between series valve layers is determined based on the topological connection relationship of the water-cooled pipeline; The transient heat transfer structure of the valve tower-level thermal network model is integrated with the thermal capacity and thermal resistance parameters and the heat flow conduction path.

[0027] As a preferred embodiment of the above, firstly, in order to construct the valve tower-level thermal network model, it is necessary to obtain the geometric parameters of the cooling channels of the series valve layer and the material properties of the water-cooled pipes. The geometric parameters of the cooling channels include the length, cross-sectional shape, and planar dimensions of the cooling channels, which are preferably extracted through external measuring equipment or based on a design model of the converter valve. Simultaneously, the material properties of the water-cooled pipes include the thermal conductivity, heat capacity, and density of the material. These parameters can be obtained through experimental measurements or by referring to material databases. For example, in a certain application scenario, copper is used as the material for the water-cooled pipes because of its excellent thermal conductivity; experimental measurements show a high thermal conductivity value. By reducing thermal resistance... The function is to improve heat transfer efficiency. Next, the geometric parameters of the cooling channel are coupled with material properties to generate thermal capacity and thermal resistance parameters. Specifically, the dimensional parameters of the channel geometry are combined with the thermal conductivity of the material to calculate the thermal resistance value of the cooling channel. Simultaneously, the thermal capacity parameter is calculated from the heat capacity distribution within the channel. A preferred approach is to dynamically adjust the model in a specific experimental environment using real valve layer structure parameters and cooling material parameters. For example, when the cross-sectional area of ​​the cooling channel is small, the thermal resistance will increase accordingly. This requires considering the overall heat dissipation capacity in the design of the hot and cold flow rates to optimize the cooling effect. Based on the topological connection relationship of the water-cooled pipeline, the heat flow conduction between the series valve layers is determined. In this embodiment, considering the actual layout of the cooling water pipe connections, the connection method between each cooling pipe segment and the valve layer is clearly defined. The cooling circuit is divided into inlet and outlet pipes. Topological analysis is used to refine the conduction path of each layer in the water cooling flow process. For example, in a certain converter valve structure, the water cooling pipes of the series valve layers are connected sequentially in a uniform distribution. The cooling water flows through each layer sequentially to form a circulation. At this point, the overall heat transfer efficiency can be analyzed by adjusting the inlet and outlet flow velocities. Based on this different level connection relationship, the topological description is used as the basis for heat flow calculation, ensuring the accuracy and reliability of the modeling results. Finally, the heat capacity and thermal resistance parameters are compared with the heat transfer path. The transient heat transfer structure of the valve tower-level thermal network model is integrated into the path. The thermal capacity and thermal resistance parameters are the core components of the transient heat transfer structure. Their definition depends on the local characteristics of the cooling channel and can reflect the specific relationship between the heat conduction rate and the heat capacity. The heat flow conduction path determines the overall heat transfer direction of the cooling water flow process. In this process, the preferred implementation of the valve tower-level model can select an appropriate parameter integration method according to the actual structure. For example, for the complex path structure in a large-scale converter valve system, a segmented integration method is adopted to calculate the parameters of each water-cooling path layer by layer and design a heat dissipation coordination method in conjunction with it to ensure that the transient heat transfer effect meets the system optimization requirements.

[0028] Furthermore, the cooling water temperature corresponding to each series valve layer is calculated based on the thermal capacity and thermal resistance parameters, including: The instantaneous temperature measured at the inlet of the water-cooling circuit is used as the initial heat flow conduction starting point and input into the valve tower-level heat network model; The cumulative heat flow propagation process of valve layer power loss between series valve layers is determined based on the heat flow conduction path. Calculate the heat flow conduction delay based on the heat transfer characteristics corresponding to the thermal capacity and thermal resistance parameters in the transient heat transfer structure. A dynamic temperature compensation relationship between valve layer power loss and cooling water temperature is established based on the heat flow conduction delay along the heat flow conduction path. The dynamic temperature compensation relationship and the cumulative heat flow propagation process are integrated to generate the real-time cooling water temperature output corresponding to the series valve layer.

[0029] As a preferred embodiment of the above, firstly, in order to obtain the cooling water temperature corresponding to the series valve layer, the instantaneous temperature measured at the inlet of the water-cooled circuit is used as the starting point for initial heat flow conduction and input into the valve tower-level thermal network model. In this preferred scheme, this instantaneous temperature is collected in real time by a high-precision temperature sensor at the inlet. The sampling rate can be adjusted according to the thermal analysis requirements. It is recommended to use a higher sampling rate, such as ten samples per second, to fully capture dynamic temperature changes and provide accurate initial boundary conditions. For example, when the converter valve operates at a certain power, its inlet water-cooled temperature usually fluctuates within a stable range. This scheme can directly input dynamic temperature changes. Temperature data is used to ensure the accuracy of subsequent model calculations. Next, based on the heat flow conduction path, the cumulative heat flow propagation process of valve layer power loss between series valve layers is determined. In a preferred embodiment, by analyzing the heat exchange relationship between the heat generated by each valve layer and the flowing water cooling, the heat in the converter valve is accumulated and dissipated layer by layer. Specifically, the power loss of each valve layer will directly lead to an increase in its local heat. With the water cooling channel as the main heat dissipation path, the heat is transferred to the next layer of cooling system through the hierarchical pipes. For example, if the heat dissipation of the top valve layer is weak in a certain operating condition, the initial heat flow will spread rapidly downwards. At this time, the cooling system inside the valve must be adjusted. The flow rate is balanced to optimize the heat flow propagation process. During the calculation phase, the heat flow conduction delay is calculated based on the heat transfer characteristics corresponding to the thermal capacity and thermal resistance parameters in the transient heat transfer structure. For example, when the thermal resistance of the water-cooled pipeline is large, the heat flow will be delayed between the exchange valve stages. This means that heat cannot reach the next cooling path in a short time. Therefore, the preferred approach is to reduce the delay effect in the thermal network model by increasing the cooling water flow rate or optimizing the thermal conductivity characteristics of the pipeline material. Assuming that a certain cooling channel uses copper pipes as the material, which has higher thermal conductivity than steel pipes, the corresponding delay in the heat flow conduction process can be effectively reduced. Along the heat flow conduction path, a dynamic temperature compensation relationship between valve layer power loss and cooling water temperature is established based on the heat flow conduction delay. A preferred implementation method includes calibrating the coupling model of power loss value and cooling water temperature in real time to clarify the dynamic relationship between the two. Under specific operating conditions, the dynamic compensation curve can be generated by periodically monitoring the valve layer operating status, such as monitoring the heat dissipation efficiency changes of each valve layer under different power conditions. This ensures that the cooling water temperature can respond in real time to the heat load changes caused by power loss. This compensation relationship can effectively reduce the response delay of cooling water temperature to thermal changes during system operation and ensure the stable operation of the converter valve.Finally, the dynamic temperature compensation relationship is integrated with the cumulative heat flow propagation process to generate the real-time cooling water temperature output corresponding to the series valve layer. In this stage, the preferred implementation can monitor the real-time status of the entire cooling system using both pressure and temperature sensors. By combining heat flow data with the input power loss curve, a real-time cooling water temperature is generated for each series valve layer. For example, when the converter valve system experiences temporary overload operation, this preferred solution can quickly adjust the cooling water temperature output, ensuring the system's internal thermal stability and avoiding the risk of thermal imbalance. Furthermore, by combining real-time data storage and analysis, a stable temperature management solution can be provided for the long-term operation of the converter valve.

[0030] Furthermore, such as Figure 3 As shown, a valve-level thermal network model is constructed, including: Analyze the sub-module water circuit topology of each valve layer and identify the parallel branches and series water circuit nodes in the sub-module water circuit topology; The local conduction weights of the heat exchange parameters are configured based on the geometric cross-sectional characteristics and water flow distribution relationship of the parallel branches; The cooling water temperature of each valve layer is set as the second boundary condition of the valve layer-level thermal network model and mapped to the initial temperature field of the series water channel node. A distributed heat conduction architecture for a valve-level heat network model is defined based on local conduction weights of heat exchange parameters and the initial temperature field.

[0031] As a preferred embodiment of the above, firstly, to construct the valve-level thermal network model, it is necessary to analyze the sub-module water circuit topology corresponding to the valve layer and identify the parallel branches and series water circuit nodes in the water circuit. In the preferred scheme, the sub-module water circuit topology includes multiple parallel and series channels. Parallel branches are used to evenly distribute the cooling water flow, while series water circuit nodes are responsible for transferring the cooling water to the next level step by step. For example, in the water circuit design of a converter valve sub-module, a multi-parallel structure is adopted to optimize cooling efficiency, while the series connection allows the water flow path to run through the entire valve layer. During the analysis process, the topological relationship can be extracted by simulation software, and the details of the cooling structure can be verified by combining the physical model, thereby ensuring the accuracy of the water circuit layout. Firstly, practical operability is considered. Secondly, the local conduction weights of heat exchange parameters are configured based on the geometric cross-sectional characteristics and water flow distribution relationship of the parallel branches. In the preferred embodiment, the geometric cross-sectional characteristics include the length, width, and shape of each channel within the submodule, while the water flow distribution relationship determines the velocity variation and flow rate distribution ratio on different branches. In specific implementation, it is preferable to arrange a flow controller on each parallel branch to measure the water flow distribution data, and adjust the heat transfer weights of multiple channels based on the measurement results. For example, if the cross-section of a certain parallel branch is narrow and its flow rate ratio is relatively low, the local conduction weight of that branch should be increased to compensate for insufficient local heat dissipation. In addition, the configuration of heat exchange parameters needs to be corrected in conjunction with experimental data. To ensure that the transferred weights match the actual heat transfer quality, the initial field setting of the valve layer cooling water temperature is then used as the second boundary condition of the model, mapping it to the series water path nodes to achieve the initial definition of the temperature field. In the preferred scheme, the valve layer cooling water temperature can be directly provided by the temperature distribution results output by the valve tower-level model and synchronized with the start-up conditions of the submodule. In practical applications, this temperature mapping process can distribute the valve layer cooling temperature to each series water path node based on the input and output heat flux of the submodule. For example, under a certain operating condition, when the cooling water outlet temperature of the converter valve is a stable value, this scheme can map the temperature field node by node to the series water path, forming an initial distribution that gradually decays or is transferred. The distribution state enables the temperature field to have dynamic response capability. Finally, based on the local conduction weights of the heat exchange parameters and the initial temperature field, the distributed heat conduction architecture of the valve-level heat network model is defined. In this embodiment, it is preferable to calculate and correlate how the local heat of the cooling water flow is conducted and absorbed by the local branches and the temperature change characteristics of each node during the conduction process when constructing the distributed heat conduction architecture. For example, when the cooling water of the submodule repeatedly flows through certain high-load areas, the local conduction weight will increase, thereby optimizing the overall heat conduction path. In addition, by combining the heat exchange parameters and the experimentally measured efficiency ratio, a local distributed heat transfer mechanism is defined for each series and parallel node, thereby completing the overall construction of the heat network model.

[0032] Furthermore, the cooling water temperature for each submodule is calculated based on the heat exchange parameters, including: The submodule power loss updated using the second sampling rate is imported into the corresponding submodule location in the distributed heat conduction architecture; The heat exchange efficiency, which is related to the Reynolds number of the parallel branch, is used as the first influencing factor, and the equivalent hydraulic diameter of the parallel branch and the local turbulence intensity are combined to generate the second influencing factor. The first and second influence factors are weighted by thermal conduction based on the local conduction weights. Based on the results of weighted aggregation calculations, a heat flux gradient field is generated in the initial temperature field, driving the forced convection heat exchange process of fluid micro-elements in the distributed heat conduction architecture. The time-varying temperature sequence of the series water circuit nodes during forced convection heat exchange is calculated iteratively. When the differential change of the time-varying temperature sequence is lower than the critical thermal stability threshold, the steady-state cooling water temperature value of each sub-module is obtained.

[0033] As a preferred embodiment of the above, firstly, in order to begin calculating the cooling water temperature, the submodule power loss updated at the second sampling rate is imported into the corresponding submodule location in the distributed heat conduction architecture. The second sampling rate is set to conserve computing resources while ensuring that dynamic thermal parameters can be updated in a timely manner. A preferred sampling rate is, for example, once per second or once per minute, depending on the stability of the converter valve's operating environment and the data update requirements. For example, when the equipment is operating at high power, the update frequency of the submodule power loss needs to be increased to adapt to rapid power changes, thereby accurately transmitting the loss data to the submodule location in the distributed heat conduction architecture. Furthermore, the input power loss data needs to be combined with the structural properties of the submodule for further processing. Preprocessing is performed to ensure that the specific energy consumption characteristics of each submodule are covered in the next heat conduction calculation. Then, the heat exchange efficiency, correlated with the Reynolds number of the parallel branch water flow, is used as the first influencing factor. A second influencing factor is generated by combining the equivalent hydraulic diameter of the parallel branch and the local turbulence intensity. In the preferred method, the Reynolds number, determined by the water flow rate and channel geometry, represents the cooling water flow state and affects the heat exchange capacity. For example, when the Reynolds number is high, the water flow changes from laminar to turbulent, and the heat exchange efficiency increases accordingly. The equivalent hydraulic diameter, calculated through the cross-sectional area and perimeter of the water channel, determines the characteristics of the heat transfer path and, together with the local turbulence intensity, constitutes the second influencing factor, reflecting the internal characteristics of the cooling system. The heat transfer efficiency is improved. For example, in a practical application, by using a booster pump to increase turbulence intensity and optimizing the water path design to increase the equivalent hydraulic diameter, the convective heat transfer effect is improved. Subsequently, a heat transfer weighted aggregation calculation is performed on the first and second influencing factors based on the local conduction weight. The local conduction weight is a parameter set by combining the geometric characteristics of the cooling water flowing through the submodule and the power loss distribution. Multiple influencing factors are aggregated into a comprehensive index that can reflect the heat transfer characteristics of the region. In the preferred scheme, the weight value needs to be dynamically adjusted to adapt to different operating conditions. For example, when a specific submodule experiences local heat accumulation due to high power load, the conduction weight of that region is increased to prioritize heat exchange. To improve heat dissipation, the weight values ​​can be determined through empirical formulas or experimental calibration to support accurate calculations. Based on the results of weighted aggregation calculations, a heat flux gradient field is generated in the initial temperature field to drive the forced convection heat exchange process of fluid micro-elements in the distributed heat conduction architecture. In the preferred implementation, the gradient field is generated by driving the cumulative heat flux distribution characteristics of the initial temperature field. Fluid micro-elements undergo temperature adjustment through local heat flux exchange. For example, after cooling water flows into a high-heat area in a specific sub-module, its micro-element temperature changes rapidly, generating forced convection. The advantage of this process is that it improves the thermal response capability of the cooling water flow and allows for dynamic observation of heat exchange efficiency on the fluid micro-element time scale.Finally, by iteratively calculating the time-varying temperature sequence of the series water circuit nodes during forced convection heat exchange, the steady-state cooling water temperature value at each submodule location is obtained when the differential change of the time-varying temperature sequence is lower than the critical thermal stability threshold. In the preferred scheme, the critical thermal stability threshold can be calibrated through system experiments to ensure the accuracy of the steady-state judgment. In practical applications, such as in a converter valve operation scenario, when the temperature change stabilizes within a certain range, such as a change of less than 0.1 degrees Celsius per second, it can be determined that a thermally stable state has been reached, thereby obtaining the steady-state water temperature value under this state. In addition, the temperature of each submodule needs to be closely monitored during the iterative calculation process to avoid excessively high temperatures causing abnormal heat load on the submodule, and adjustments should be made in real time as needed.

[0034] Furthermore, such as Figure 4 As shown, a device-level thermal network model is established, including: A three-layer heat dissipation topology for power semiconductor devices is constructed by sequentially connecting the chip bonding layer node, the metallization substrate node, and the thermal interface layer node in the direction of heat conduction to generate the internal heat flow path of the package. Set the cooling water temperature of each submodule to the boundary temperature value of the thermal interface layer node. Configure the anisotropic thermal conductivity properties of the metallized substrate nodes to distinguish the physical parameter differences between the longitudinal thermal conductivity of the copper layer and the transverse thermal conductivity of the ceramic layer. The transient thermal power input of the chip bonding layer node is generated based on the switching cycle characteristics of submodule power loss. Establish a radial thermal resistance chain structure for the metal foil layer of the capacitor winding core, including the topological connection of the core center node, the dielectric filling layer node, and the outer shell contact layer node; The cooling water temperature of each submodule is applied to the contact layer nodes of the outer shell to generate the outer boundary heat transfer conditions of the radial thermal resistance chain structure.

[0035] As a preferred embodiment of the above, firstly, a three-layer heat dissipation topology for the power semiconductor device is constructed. This topology includes a chip bonding layer node, a metallized substrate node, and a thermally conductive interface layer node, which are sequentially connected according to the heat conduction direction to form an internal heat flow path within the package. In a preferred embodiment, the chip bonding layer node is the starting point for heat flow transfer, and its thermal resistance is mainly determined by the thermal properties of the chip and the bonding material. For example, a copper bonding layer, due to its high thermal conductivity, can quickly transfer heat to the substrate node. The metallized substrate node is the second layer for heat flow transfer, and its structure typically includes a copper layer and a ceramic layer. The copper layer provides excellent longitudinal thermal conductivity, while the ceramic layer has lower lateral thermal conductivity. A significant directional characteristic is formed along the heat flow path. The thermal interface layer node is the part that finally comes into contact with the cooling water. Its thermal conductivity is usually determined by the thickness of the interface material and the thermal conductivity efficiency. For example, the thermal interface layer uses a layer of high thermal conductivity silicone grease, and its uniformity is ensured through fine processing to optimize the heat conduction path. Next, the cooling water temperature of the submodule is set as the boundary temperature value of the thermal interface layer node. In a preferred embodiment, the cooling water temperature is output in real time through the valve-level thermal network model and directly used as the temperature boundary condition input of the thermal interface layer. This setting allows the power semiconductor device to dynamically respond to changes in cooling water temperature and maintain a thermally stable state inside the package. When the cooling water temperature drops, the thermally conductive interface layer can rapidly reduce internal heat accumulation, thereby preventing the chip bonding layer temperature from exceeding the critical temperature value. Subsequently, the anisotropic thermal conductivity properties of the metallized substrate nodes are configured to differentiate the physical parameter differences between the longitudinal thermal conductivity of the copper layer and the transverse thermal conductivity of the ceramic layer. Preferably, the thermal conductivity of the copper layer is set to a higher value to enhance the longitudinal heat transfer capability, while considering the relatively lower transverse heat transfer capability of the ceramic layer. This design allows the substrate to preferentially conduct longitudinal heat and reduce the interference of transverse thermal convection effects inside the device. For example, in a specific substrate design, increasing the copper layer thickness will further improve the longitudinal thermal conductivity, while the selection of the ceramic layer can... High thermal conductivity reinforced ceramic materials are given priority to enhance overall heat dissipation performance. Furthermore, transient thermal power input of chip bonding layer nodes is generated based on the switching cycle characteristics of submodule power loss. In the preferred implementation process, considering the dynamic characteristics of power semiconductor devices during rapid switching, the transient power input has periodic fluctuation characteristics and drives significant thermal changes. For example, in dynamic operation, the switching mode of the device may change frequently within a second interval. The power loss value input must reflect this change characteristic cycle by cycle. At the same time, by updating the power loss parameters in real time, high-precision thermal power input data can be obtained to ensure the effectiveness of the chip layer thermal analysis results.In addition, to comprehensively describe the thermal network characteristics of the capacitor, a radial thermal resistance chain structure is established for the capacitor's wound core metal foil layer. This structure includes the topological connections of the core center node, dielectric filling layer nodes, and outer shell contact layer nodes. It describes how the heat path gradually transfers from the inside of the capacitor to the outer shell contact nodes. In a preferred embodiment, the core center node serves as the heat dissipation starting point, and its material selection should prioritize metal foil layers with high thermal conductivity. For example, aluminum foil is preferred due to its light weight and good thermal conductivity. The dielectric filling layer nodes are responsible for transferring heat to the outer shell layer, and the dielectric should be a capacitor-specific material with good thermal conductivity to reduce overall thermal resistance. Finally, the cooling water temperature of the submodule is applied to the outer shell contact layer nodes to generate the outer boundary heat transfer conditions of the radial thermal resistance chain structure. For example, by applying the cooling water temperature to the outer shell layer, the heat flow can further diffuse to the cooling water system, ultimately forming a closed loop of heat transport. In a specific implementation environment, the heat transfer boundary conditions of the outer shell contact layer nodes can simulate the temperature change range of the cooling water within its stable operating range, and combined with an effective boundary heat transfer algorithm, further improve the temperature response capability of the structure.

[0036] Furthermore, calculating the junction temperature of power semiconductor devices and the internal temperature of capacitors includes: The heat transfer on the three-layer heat dissipation topology is driven by the transient thermal power input of the chip bonding layer node and the boundary temperature value of the thermal interface layer node, which triggers the thermal response of the chip bonding area. Record the temperature gradient transfer pattern from the chip bonding layer node to the metallization substrate node, and deduce the junction temperature fluctuation range of the power semiconductor device based on the temperature gradient transfer pattern. The thermal accumulation process of the radial thermal resistance chain structure is stimulated, and the heat migration from the nodes of the dielectric filling layer to the central node of the core is driven according to the heat transfer conditions of the outer boundary. Monitor the temperature rise characteristics of the core center node and determine the internal thermal state of the wound core as the internal temperature reference point of the capacitor.

[0037] As a preferred embodiment of the above, firstly, in order to calculate the junction temperature of the power semiconductor device, heat transfer on the three-layer heat dissipation topology is driven, and the thermal response of the chip bonding area is triggered based on the transient thermal power input of the chip bonding layer node and the boundary temperature value of the thermal interface layer node. In a preferred embodiment, the transient thermal power input is dynamically updated by the calculation results of the submodule. The heat input pattern of power loss is derived based on the switching periodic changes of the actual power load and the chip operating state. For example, the power loss during chip operation causes heat accumulation, which is conducted to the substrate through the chip bonding layer and finally diffuses to the thermal interface layer. During this process, the heat input pattern of the chip bonding area is determined. To enhance the rapid thermal response capability of the chip region, in the preferred implementation, welding materials with good thermal conductivity, such as low-melting-point silver-tin alloys, are selected to further improve heat transfer efficiency while reducing the thermal resistance of the welding layer. This avoids the impact of high heat accumulation on chip performance. The cooling water temperature, as the boundary temperature value of the thermal interface layer, becomes the final controlled condition for heat dissipation in the chip region. This value is output in real time by the underlying cooling system and fed back to the heat dissipation path. Next, the temperature gradient transfer pattern from the chip welding layer node to the metallization substrate node is recorded, and the junction temperature fluctuation range of the power semiconductor device is derived based on this pattern. In practice, the thermal flow path response from the chip to the metallization substrate is measured. This allows us to observe temperature differences at different material interfaces, such as the temperature gradient that typically exists at the junction of the solder layer and the copper layer. Ideally, a high-precision temperature sensor should be used to record this heat transfer characteristic, and the changes should be monitored dynamically over time to build a predictive model for junction temperature fluctuations. For example, under normal operating conditions, the junction temperature of a power semiconductor device may remain within a certain range, such as 50 to 75 degrees Celsius. However, under short-term overload conditions, the real-time recorded temperature gradient can predict whether the instantaneous junction temperature fluctuation exceeds a set operating threshold, thus promptly identifying excessive heat loads that may cause equipment problems. Then, to calculate the internal temperature of the capacitor... First, the thermal accumulation process of the radial thermal resistance chain structure is activated. Based on the heat transfer conditions at the outer boundary, the heat transfer from the dielectric filling layer node to the core center node is driven. In the preferred embodiment, the heat transfer conditions at the outer boundary of the capacitor are provided by the cooling water temperature of the submodule, while the heat transfer is achieved by the radial thermal resistance chain structure. The external heat input, the thermal conductivity of the filling layer, and the dynamic thermal response of the core jointly affect the thermal accumulation process of the center node. For example, in the case of a low cooling water temperature, the heat transfer process of the core will slow down, while a sudden increase in external temperature will directly accelerate the heat transfer from the filling layer. This dynamic relationship needs to be verified by experiments to set the optimal boundary conditions to optimize the transfer efficiency.Finally, the temperature rise characteristics of the core center node are monitored, and the thermal state inside the wound core is determined as the internal temperature reference point of the capacitor. This reference point is the basis for calculating the thermal stability state of the capacitor. In a preferred embodiment, multiple temperature sensors are arranged to monitor the temperature rise trend of the core center node in real time and collect dynamic curves of temperature changes. For example, when the external cooling water temperature fluctuates, the temperature rise rate of the focal core node can directly reflect the response efficiency of the internal thermal resistance chain of the capacitor. At the same time, the setting of the reference point needs to be verified in conjunction with the normal operating environment of the capacitor to determine its temperature range. For example, the internal temperature of the core is usually set in the range of 30 to 60 degrees Celsius, and the stable operating state is used as the basis for temperature adjustment.

[0038] Furthermore, optimizing the boundary-driven mechanism of the valve-level thermal network model includes: The temperature abrupt change characteristics of each valve layer's corresponding cooling water temperature generated by the sampling rate difference under the second boundary condition were detected. Based on the temperature change characteristics, the inlet heat flux density of the submodule water channel topology is zero-crossing detected to generate a periodic fluctuation threshold. The intensity of thermal response hysteresis compensation is based on the reverse adjustment of heat exchange parameters according to the periodic fluctuation threshold. In the valve-level thermal network model, a negative feedback calibration loop is established based on the initial temperature field of the second boundary condition. According to the negative feedback calibration loop, the periodic fluctuation threshold is constrained to the steady-state heat transfer range, and the boundary temperature calibration amount of the valve-level thermal network model is output. The boundary temperature calibration value is injected into the low-speed heat dissipation area of ​​the parallel branch of the submodule water circuit topology to generate a lower boundary constraint that matches the second sampling rate and is then passed to the cooling water temperature calculation process of each submodule.

[0039] As a preferred embodiment of the above, firstly, during the optimization process, it is necessary to detect the temperature abrupt change characteristics of the cooling water temperature corresponding to each valve layer under the second boundary condition due to the difference in sampling rate. In the preferred embodiment, temperature acquisition needs to be combined with high and low sampling rates to make full use of temperature fluctuation information in a short period of time. By arranging temperature sensors, sudden temperature changes that occur during the cooling water flow process, as well as temperature measurement abrupt changes caused by changes in sampling rate, are captured. For example, under a certain operating condition, if a temperature abrupt change is captured by a low sampling rate, it may indicate an excessive behavior of environmental disturbance or thermal change within the system in a short period of time. In this case, subsequent heat flow adjustments should be made in conjunction with measured data. Then, based on the temperature abrupt change characteristics, the submodule water... Zero-crossing detection is performed on the inlet heat flux density of the road topology to generate a periodic fluctuation threshold. At this stage, the detection focuses on the fluctuation amplitude, frequency of occurrence, and regularity within the sampling period. Preferably, a computer algorithm is used to input the data into the heat flux model, identify the fluctuation period under stable operating conditions, and use this target to generate a recordable threshold point. For example, at the submodule inlet, zero-crossing detection can help identify local high-frequency fluctuations caused by coil switching operations or load variations, thereby further analyzing the periodic changes in water flow characteristics. Next, based on the periodic fluctuation threshold, the thermal response hysteresis compensation intensity of the heat exchange parameters is adjusted in reverse. Specifically, if hysteresis is detected in the heat transfer path... The phenomenon leads to a decrease in local thermal response efficiency, requiring adjustment of the thermal conductivity or flow friction coefficient to improve system synergy. In preferred implementation, adjustment seeks real-time coupling guided by fluctuation thresholds, such as optimizing the reaction time in real time through an automated controller, successfully weakening or eliminating the challenge of hysteresis effects on stable system operation. A negative feedback calibration loop is established in the valve-level thermal network model based on the initial temperature field of the second boundary condition. This loop originates from the cyclic monitoring and feedback correction of each fluctuation through temperature signal, introducing a calibration mechanism to limit the fluctuation threshold within a stable range. Preferred technical solutions can simplify the negative feedback structure, improve the linearity of the decision condition, and thus achieve more efficient alternative compensation adjustment, for example, pre- The pre-calibrated temperature range and acceptable fluctuation range can be dynamically adjusted, and the corresponding boundary temperature correction amount is output to improve the heat transfer in the next stage. Finally, the obtained boundary temperature correction amount is injected into the low-speed heat dissipation area of ​​the parallel branch of the submodule water circuit topology to generate a lower boundary constraint that matches the second sampling rate and is transferred to the cooling water temperature calculation process. The core is to accurately apply the constraint conditions during the flow of cooling water section by section, and limit the region boundary to the real-time measured thermal state to prevent excessively high or low temperature fluctuations from affecting the final temperature field prediction. Preferred implementation schemes may include empirically verifying and theoretically adjusting the dynamically calculated heat distribution according to the predetermined cooling rate strategy to improve the cooling efficiency under redesign work.

[0040] Example 2; Based on the same inventive concept as the multi-level transient thermal network modeling method for flexible DC converter valves in the foregoing embodiments, this invention also provides a multi-level transient thermal network modeling system for flexible DC converter valves, the system comprising: The valve tower model module constructs a valve tower-level thermal network model, setting the measured instantaneous temperature at the inlet of the water-cooled circuit of the converter valve as the first boundary condition of the valve tower-level thermal network model. The valve layer temperature module calculates the valve layer power loss of multiple series valve layers in the converter valve and updates it using the first sampling rate. It inputs the valve layer power loss into the valve tower thermal network model and solves the cooling water temperature corresponding to each series valve layer based on the thermal capacity and thermal resistance parameters. The valve layer model module constructs a valve layer-level thermal network model, and the cooling water temperature of each valve layer is set as the second boundary condition of the corresponding valve layer-level thermal network model. The submodule temperature module calculates the submodule power loss of multiple submodules connected in series within each valve layer, inputs the submodule power loss into the valve layer thermal network model, and solves for the cooling water temperature corresponding to each submodule based on the heat exchange parameters. The device model module establishes a device-level thermal network model, sets the cooling water temperature of each sub-module as the third boundary condition of the device-level thermal network model, and calculates the junction temperature of the power semiconductor device and the internal temperature of the capacitor.

[0041] The adjustment system described above in this invention can effectively realize the multi-level transient thermal network modeling method for flexible DC converter valves, and the technical effects it can achieve are as described in the above embodiments, which will not be repeated here.

[0042] Example 3; A computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, can implement any of the following: a method for modeling a multi-level transient thermal network of a flexible DC converter valve.

[0043] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of the application as defined herein, and are to be considered as covering any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Thus, if such modifications and modifications fall within the scope of this application and its equivalents, this application intends to include such modifications and modifications.

Claims

1. A method for modeling multi-stage transient thermal networks of flexible DC converter valves, characterized in that, The method includes: A valve tower-level thermal network model is constructed, which includes the thermal capacity and thermal resistance parameters of the cooling channels and water-cooled pipes of the series valve layer. The instantaneous temperature measured at the inlet of the water-cooled circuit of the converter valve is set as the first boundary condition of the valve tower-level thermal network model, wherein the sampling rate of the instantaneous temperature is set as the first sampling rate, and the instantaneous temperature is collected using the first sampling rate. Calculate the power loss of multiple series valve layers in the converter valve and update it using the first sampling rate. Input the power loss of the valve layer into the valve tower thermal network model and solve the cooling water temperature corresponding to each series valve layer according to the thermal capacity and thermal resistance parameters. A valve-level thermal network model is constructed, which includes the sub-module water circuit topology and heat exchange parameters of the corresponding valve layer. The cooling water temperature of each valve layer is set as the second boundary condition of the corresponding valve-level thermal network model. Calculate the submodule power loss of multiple series-connected submodules within each valve layer, input the submodule power loss into the valve layer thermal network model, and solve the cooling water temperature corresponding to each submodule based on the heat exchange parameters, wherein the submodule power loss is updated using a second sampling rate lower than the first sampling rate; A device-level thermal network model is established, which includes the heat dissipation path of the power semiconductor device package. The cooling water temperature of each sub-module is set as the third boundary condition of the device-level thermal network model, and the junction temperature of the power semiconductor device and the internal temperature of the capacitor are calculated.

2. The method for modeling multi-stage transient thermal networks of flexible DC converter valves according to claim 1, characterized in that, Constructing a valve tower-level thermal network model includes: Obtain the geometric parameters of the cooling channel of the series valve layer and the material properties of the water-cooled pipeline; The thermal capacity and thermal resistance parameters are generated by coupling the geometric parameters of the cooling channel with the material properties. The heat flow conduction path between the series valve layers is determined based on the topological connection relationship of the water-cooled pipeline. The thermal capacity and thermal resistance parameters are integrated with the heat flow conduction path to form the transient heat transfer structure of the valve tower-level heat network model.

3. The multi-stage transient thermal network modeling method for flexible DC converter valves according to claim 2, characterized in that, The cooling water temperature corresponding to each of the series valve layers is calculated based on the heat capacity and thermal resistance parameters, including: The instantaneous temperature measured at the inlet of the water-cooling circuit is used as the initial heat flow conduction starting point and input into the valve tower-level heat network model; The cumulative heat flow propagation process of the valve layer power loss between the series valve layers is determined based on the heat flow conduction path. Calculate the heat flow conduction delay based on the heat transfer characteristics corresponding to the thermal capacity and thermal resistance parameters in the transient heat transfer structure. A dynamic temperature compensation relationship between the power loss of the valve layer and the temperature of the cooling water is established based on the heat flow conduction delay along the heat flow conduction path. The dynamic temperature compensation relationship and the cumulative heat flow propagation process are integrated to generate the real-time cooling water temperature output corresponding to the series valve layer.

4. The method for modeling multi-stage transient thermal networks of flexible DC converter valves according to claim 1, characterized in that, Constructing a valve-level thermal network model includes: Analyze the water circuit topology of each valve layer and identify the parallel branches and series water circuit nodes in the water circuit topology of the sub-modules. Configure the local conduction weights of the heat exchange parameters according to the geometric cross-sectional characteristics and water flow distribution relationship of the parallel branches; The cooling water temperature of each valve layer is set as the second boundary condition of the valve layer-level thermal network model and mapped to the initial temperature field of the series water channel node. The distributed heat conduction architecture of the valve-level heat network model is defined based on the local conduction weights of the heat exchange parameters and the initial temperature field.

5. The multi-stage transient thermal network modeling method for flexible DC converter valves according to claim 4, characterized in that, Calculating the cooling water temperature corresponding to each submodule based on the heat exchange parameters includes: The power loss of the sub-module updated using the second sampling rate is imported into the corresponding sub-module location in the distributed heat conduction architecture; The heat exchange efficiency correlated with the Reynolds number of the parallel branch is used as the first influencing factor, and the equivalent hydraulic diameter and local turbulence intensity of the parallel branch are combined to generate a second influencing factor. The first influence factor and the second influence factor are subjected to a heat conduction weighted aggregation operation based on the local conduction weight; Based on the results of the weighted aggregation operation, a heat flux gradient field is generated in the initial temperature field, driving the forced convection heat exchange process of the fluid micro-elements in the distributed heat conduction architecture. The temperature time-varying sequence of the series water circuit nodes during the forced convection heat exchange process is calculated iteratively. When the differential change of the temperature time-varying sequence is lower than the critical thermal stability threshold, the steady-state cooling water temperature value of each sub-module is obtained.

6. The method for modeling multi-stage transient thermal networks of flexible DC converter valves according to claim 1, characterized in that, Establish a device-level thermal network model, including: A three-layer heat dissipation topology for the power semiconductor device is constructed, and the chip bonding layer node, the metallization substrate node, and the thermal interface layer node are connected sequentially in the direction of heat conduction to generate an internal heat flow path for the package. The cooling water temperature of each of the sub-modules is set to the boundary temperature value of the thermal interface layer node. Configure the anisotropic thermal conductivity properties of the metallized substrate nodes to distinguish the physical parameter differences between the longitudinal thermal conductivity of the copper layer and the transverse thermal conductivity of the ceramic layer. The transient thermal power input of the chip bonding layer node is generated based on the switching cycle characteristics of the power loss of the submodule. Establish a radial thermal resistance chain structure for the metal foil layer of the capacitor winding core, including the topological connection of the core center node, the dielectric filling layer node, and the outer shell contact layer node; The cooling water temperature of each of the sub-modules is applied to the contact layer nodes of the outer shell to generate the outer boundary heat transfer conditions of the radial thermal resistance chain structure.

7. The method for modeling multi-stage transient thermal networks of flexible DC converter valves according to claim 6, characterized in that, Calculating the junction temperature of the power semiconductor device and the internal temperature of the capacitor includes: Drive the heat transfer on the three-layer heat dissipation topology, and trigger the thermal response of the chip welding area based on the transient thermal power input of the chip bonding layer node and the boundary temperature value of the thermal interface layer node; Record the temperature gradient transfer pattern from the chip bonding layer node to the metallization substrate node, and deduce the junction temperature fluctuation range of the power semiconductor device based on the temperature gradient transfer pattern. The thermal accumulation process of the radial thermal resistance chain structure is activated, and the heat migration of the dielectric filling layer nodes to the core center node is driven according to the outer boundary heat transfer conditions. The temperature rise characteristics of the core center node are monitored, and the thermal state inside the wound core is determined as the internal temperature reference point of the capacitor.

8. The method for modeling multi-stage transient thermal networks of flexible DC converter valves according to claim 1, characterized in that, Optimizing the boundary-driven mechanism of the valve-level thermal network model includes: The temperature abruptness characteristics of the cooling water temperature corresponding to each valve layer under the second boundary condition caused by the difference in sampling rate are detected. Based on the temperature change characteristics, the inlet heat flux density of the submodule waterway topology is zero-crossing detected to generate a periodic fluctuation threshold. The thermal response hysteresis compensation intensity is adjusted in reverse based on the periodic fluctuation threshold. In the valve-level thermal network model, a negative feedback calibration loop is established based on the initial temperature field of the second boundary condition. According to the negative feedback calibration loop, the periodic fluctuation threshold is constrained to the steady-state heat transfer range, and the boundary temperature calibration amount of the valve-level thermal network model is output. The boundary temperature calibration value is injected into the low-speed heat dissipation region of the parallel branch of the submodule water circuit topology to generate a lower boundary constraint that matches the second sampling rate and is then passed to the cooling water temperature calculation process of each submodule.

9. A multi-stage transient thermal network modeling system for flexible DC converter valves, characterized in that, The system includes: The valve tower model module constructs a valve tower-level thermal network model, setting the measured instantaneous temperature at the inlet of the water-cooled circuit of the converter valve as the first boundary condition of the valve tower-level thermal network model. The valve layer temperature module calculates the valve layer power loss of multiple series valve layers in the converter valve and updates it using the first sampling rate. It inputs the valve layer power loss into the valve tower thermal network model and solves the cooling water temperature corresponding to each series valve layer based on the thermal capacity and thermal resistance parameters. The valve layer model module constructs a valve layer-level thermal network model, and the cooling water temperature of each valve layer is set as the second boundary condition of the corresponding valve layer-level thermal network model. The submodule temperature module calculates the submodule power loss of multiple submodules connected in series within each valve layer, inputs the submodule power loss into the valve layer thermal network model, and solves for the cooling water temperature corresponding to each submodule based on the heat exchange parameters. The device model module establishes a device-level thermal network model, sets the cooling water temperature of each sub-module as the third boundary condition of the device-level thermal network model, and calculates the junction temperature of the power semiconductor device and the internal temperature of the capacitor.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which includes program instructions that, when executed by a processor, implement the multi-level transient thermal network modeling method for flexible DC converter valves as described in any one of claims 1-8.

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