Sequential circuit representation learning method based on graph neural network and state space model

Abstract

The invention provides a sequential circuit characterization learning method based on a graph neural network and a state space model, and belongs to the field of electronic design automation, and the method comprises the steps: obtaining a sequential circuit diagram, and constructing a graph neural network reasoning module through designing a quadrupole embedding space; performing dynamic function modeling on the time sequence circuit diagram by using a diagram neural network reasoning module to obtain a node embedding vector; the method comprises the following steps: constructing a Mama memory module on the basis of a token method and a Mama framework; and performing dual structure modeling on node embedding by using a Mamba memory module to obtain an embedded vector, and completing sequential circuit characterization learning. The method solves the problems that an existing sequential circuit characterization learning method destroys the original structure of the circuit, cannot capture the core of the sequential circuit, is low in processing efficiency, is low in training speed, is limited in performance improvement, and is not obvious in precision advantage.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation, and particularly relates to a method for learning the representation of sequential circuits based on graph neural networks and state-space models. Background Technology

[0002] Understanding the structure and functional characteristics of sequential circuits is crucial for verification and testing in electronic design automation (EDA), such as power consumption estimation and reliability analysis. With the development of deep learning, graph neural networks (GNNs) have begun to be applied to the representation learning of sequential circuits, providing flexible support for various downstream tasks. However, existing sequential circuit representation learning methods often directly adopt learning schemes for combinational circuits, ignoring a key issue: combinational circuit methods are not suitable for sequential circuits. This paper finds that due to the binary structure and dynamic functional characteristics of sequential circuits, there are significant differences between them and combinational circuits, and these differences are the bottleneck limiting the performance of current methods.

[0003] In EDA, sequential circuits are a fundamental and important type of circuit data, crucial for critical applications such as chip power consumption assessment and reliability analysis. Traditional sequential circuit analysis methods mainly rely on analog or heuristic algorithms, which are insufficient in terms of efficiency and accuracy to meet the demands of complex chip manufacturing and optimization.

[0004] With the development of artificial intelligence technology, the use of neural networks for sequential circuit representation learning has become a research hotspot, aiming to efficiently model its structure and function and then apply it to downstream tasks such as power consumption estimation to accelerate the chip iteration process. Prior to this, representation learning for combinational circuits had already attracted attention, and the methods usually adopted directed acyclic graph neural networks. Since both combinational circuits and sequential circuits belong to circuit data, existing sequential circuit representation learning is usually derived from combinational circuits.

[0005] Existing technologies are mainly based on sequential circuit representation learning models adapted from combinational circuit learning methods. These models aim to learn the representation of sequential circuits through neural networks to support downstream tasks such as power consumption assessment and reliability analysis. While existing technologies have achieved some application results, they suffer from the following significant drawbacks, which are precisely the technical problems that this invention aims to solve: Disrupting the original circuit structure makes it impossible to capture the core characteristics of sequential circuits: Existing technologies, in order to use directed acyclic graph neural networks, forcibly remove loop structures from sequential circuits. This operation destroys the inherent topological information of the circuit. Loop structures are the physical basis for the "memory" function of sequential circuits, as shown in the attached figure. Figure 2 As shown, removing loops severely impacts the model's ability to learn about circuit timing behavior and state dependencies; Low processing efficiency and slow training speed: Due to the use of a relatively complex design (such as dual attention mechanism and decoupled representation learning) and the fact that its architecture is not optimized for the characteristics of sequential circuits, the training efficiency of the existing technology is very low. Limited performance improvement and no significant accuracy advantage: Compared with the large training time cost, the prediction accuracy improvement of existing technologies is not significant, and their complex model design has not been effectively translated into performance advantage. Summary of the Invention

[0006] To address the aforementioned shortcomings in existing technologies, this invention provides a sequential circuit representation learning method based on graph neural networks and state-space models. This method solves the problems of existing sequential circuit representation learning methods, such as destroying the original structure of the circuit, failing to capture the core of the sequential circuit, low processing efficiency, slow training speed, limited performance improvement, and insignificant accuracy advantages.

[0007] To achieve the above objectives, the technical solution adopted by this invention is: a time-series circuit representation learning method based on graph neural networks and state-space models, comprising the following steps: S1. Obtain the timing circuit diagram and construct the graph neural network inference module by designing a quadrupole embedding space; S2. Using the graph neural network inference module, dynamic functional modeling of the timing circuit diagram is performed to obtain the node embedding vector; S3. Based on the token-based system and Mamba architecture, construct a Mamba memory module; S4. Using the Mamba memory module, perform dual structure modeling on node embedding to obtain embedding vectors and complete the learning of time-series circuit representation.

[0008] The beneficial effects of the present invention are as follows: The present invention provides a method that can directly process directed graph neural networks containing loops, retain the complete topological information of sequential circuits, and thus more realistically model the behavior of circuits. Furthermore, it models the core characteristics of the flip-flops of logic gates in sequential circuits, avoiding damage to the original structure of the circuit and effectively capturing the core of sequential circuits. By employing a computationally efficient, parallelizable, and significantly shorter training time sequential circuit learning scheme, processing efficiency and training speed are improved. By leveraging the Mamba memory module, the performance of sequential circuit representation learning is improved, enabling more accurate learning of sequential circuit representations and achieving higher accuracy in downstream prediction tasks.

[0009] Further, S1 includes the following steps: S101. Obtain the timing circuit diagram, and obtain the preset type of state transition based on the changes between the low and high levels of each node in the timing circuit diagram; S102. Based on the state transition of the preset types, the initial features of each node are mapped using a preset number of independent linear layers to design a four-pole embedding space. S103. Signal transmission based on Boolean logic: the first differentiable logic operator is defined as the bitwise minimum of any two embedded vectors, and the second differentiable logic operator is defined as the bitwise complement of the embedded vectors. S104. Define the third differentiable logic operator as the identity transformation, and process the embedding vector through the first differentiable logic operator, the second differentiable logic operator, and the third differentiable logic operator to obtain the embedding message and update the node embedding, and design the logic propagation direction. S105. Construct a graph neural network inference module based on the quadrupole embedding space and the logical propagation direction.

[0010] Furthermore, S2 includes the following steps: S201. Using the quad-pole embedding space, the initial characteristics of each node in the timing circuit diagram are processed to obtain the state transition vector of the node. S202. Based on the node's state transition vector, using the logical propagation direction, by performing bitwise inversion, bitwise minimum value, and judgments of not performing logical operations, obtain the node embedding vector, obtain the embedding message, and obtain the node embedding by updating.

[0011] Furthermore, the expression for the state transition vector of the node is as follows: , ; , ; in, Represents a node i The transition vector from state 0 to state 0. Represents a node i The transition vector from state 0 to state 1. Represents a node i The transition vector from state 1 to state 0. Represents a node i The transition vector from state 1 to state 2. Represents a node i initial characteristics, This represents the activation function. , , as well as Both represent linear transformation matrices.

[0012] Furthermore, the expressions for the embedded messages and node embeddings are as follows: ;

[0013] in, Indicates embedded message, Indicates the first l Layer state x to state y , This represents the first differentiable logic operator. Represents a node i The predecessor node, Indicates the first l -1 level nodes j From state x to state y The transition vector, Indicates the first l -1 level nodes i From state x to state y The transition vector, This represents the set of AND gates in a circuit diagram. This represents the second differentiable logic operator. Indicates the first l -1 level nodes j From state y to state x The transition vector, Indicates the first l -1 level nodes i From state y to state x The transition vector, This represents the set of NOT gates in a circuit diagram. This represents the first differentiable logic operator. This represents the set of flip-flops in a circuit diagram. This represents the initial set of input nodes in the circuit diagram. Indicates node embedding, This represents a linear transformation matrix.

[0014] The beneficial effects of the above-mentioned further solutions are as follows: By constructing a four-level embedding space, the present invention maps the initial features of each node to four embedding spaces, thereby improving the prediction capability; Furthermore, a logic propagation judgment was designed, and a differentiable logic operator was defined based on Boolean logic to aggregate the information of the predecessor node, thereby improving the efficiency and logic of modeling sequential circuits.

[0015] Furthermore, step S3 includes the following steps: S301. Based on the token method and graph segmentation, a predecessor-aware segmentation method is designed by using special padding tokens to complete sequences with fewer than two predecessor nodes. S302. Sort the token sequence according to the clock-driven order, and use the same index mapping to sort the token sequences other than the current token sequence, thus designing a clock-driven token sorting strategy. S303. Based on the Mamba architecture, a causal one-dimensional convolution is constructed, and the calculation expressions for the interval and mapping matrix are defined. The temporal dependency is modeled by using the evolution matrix, and the evolution matrix and mapping matrix are discretized by using the zero-order preservation rule to obtain the discrete state space model layer. S304. Using the discrete state-space model layer, the latent state is updated, and the updated latent state is combined with the original input to obtain the output embedding. The output embedding is then concatenated and linearly transformed to obtain a one-way Mamba. S305. Based on the predecessor-aware word segmentation method, the clock-driven token sorting strategy, and unidirectional Mamba, construct the Mamba memory module.

[0016] Furthermore, step S4 includes the following steps: S401. Use the predecessor-aware word segmentation method to segment the node embedding to obtain the token sequence; S402. Based on the clock-driven token sorting strategy, using the token sequence as a reference, sort the token sequence corresponding to the node itself according to the clock-driven order, and use the same index mapping to sort the token sequences other than the token sequence corresponding to the node itself, to obtain the dimensional sequence. S403. Based on the node sequence, use the dimension sequence to obtain the input sequence; S404. Based on unidirectional Mamba, the input sequence is processed using causal one-dimensional convolution to obtain the token relationship. Combining the token relationship, the calculation expression of the interval, and the calculation expression of the mapping matrix, the interval and mapping matrix are obtained. Combined with the evolution matrix, the latent state is updated using the discrete state space model layer. S405. Combine the updated latent state with the input sequence to obtain the output embedding, and then concatenate and linearly transform the output embedding to obtain the embedding vector.

[0017] Furthermore, the expression for the token sequence is as follows: ; in, Represents a token sequence. Indicates the node itself, This indicates the first predecessor node of the current node. Indicates the second predecessor node of the current node; The expression for the dimensional sequence is as follows: ; in, Represents a dimensional sequence.

[0018] The beneficial effects of the above-mentioned further solutions are as follows: By utilizing the discrete state space model layer, the present invention obtains a one-way Mamba with high linear complexity and dynamic memory capability, thereby improving the accuracy and effectiveness of dual structure modeling. By designing a precursor-aware word segmentation method, the key features of sequential circuits can be accurately represented for the special directed graphs of sequential circuits. The clock-driven token sorting strategy accurately reflects the dependencies in sequential circuits. Furthermore, by leveraging the directionality of unidirectional Mamba modeling circuits, the accuracy and efficiency of sequential circuit representation learning are improved. Attached Figure Description

[0019] Figure 1 This is a flowchart of the method of the present invention.

[0020] Figure 2 This is a flowchart of an algorithm for learning the representation of time-series circuits based on graph neural networks and state-space models. Detailed Implementation

[0021] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0022] Before describing this embodiment, the following terms will be explained: StateSeq: A temporal circuit representation learning method based on a hybrid architecture of graph neural networks and state-space models; Mamba: Graph Neural Networks and State-Space Models; DeepSeq: A framework for learning sequence circuit representations; GNN: Graph Neural Network; EDA: Electronic Design Automation; SSM: State-space model; PT: Precursor-aware word segmentation; CTO: Clock-driven lexical sorting strategy; MAE: Mean Absolute Error; TPP: Turnover Rate Prediction; FFSP: Trigger Similarity Prediction; MLP: Multilayer Perceptron.

[0023] Example 1 This embodiment proposes a sequential circuit representation learning method (StateSeq) and framework based on a hybrid architecture of graph neural networks and state-space models. This is the first neural network model specifically designed for modeling the binary structure and dynamic functions of sequential circuits, and also the first sequential circuit learning framework based on a hybrid architecture of graph neural networks and state-space models (Mamba). In this framework, the GNN module is used for logical reasoning, and a quadrupole embedding and logic propagation mechanism is proposed to model the dynamic functional characteristics of the circuit. In addition, Mamba is introduced to model the memory structure of sequential circuits, and a predecessor-aware tokenization and clock-driven token sorting strategy are specifically designed to match the unique topological and timing characteristics of sequential circuits.

[0024] like Figure 1 As shown, this invention provides a time-series circuit representation learning method based on graph neural networks and state-space models, the implementation of which is as follows: S1. Obtain the timing circuit diagram, and construct the graph neural network inference module by designing a quadrupole embedding space. The specific steps are as follows: S101. Obtain the timing circuit diagram, and obtain the preset type of state transition based on the changes between the low and high levels of each node in the timing circuit diagram; S102. Based on the state transition of the preset type, the initial features of each node are mapped using a preset number of independent linear layers to design a four-pole embedding space.

[0025] In this embodiment, to construct a GNN inference module for modeling dynamic functions, based on the key feature of functionality compared to ordinary graph data, each node performs specific logical operations. Unlike combinational circuits whose states are only affected by the current clock cycle, the states of sequential circuits are affected by both the current and previous clock cycles. We call this characteristic of sequential circuits dynamic functionality, which requires the model to be able to distinguish different state transition modes, not just states 0 and 1.

[0026] In this embodiment, a timing circuit diagram is obtained. In a timing circuit, state transition refers to the change of node state between low level (denoted as 0) and high level (denoted as 1) within each clock cycle. Therefore, there are four possible state transitions: 0→0, 0→1, 1→0 and 1→1, resulting in four state transitions. Based on the functional representation bottleneck principle, to avoid confusion between different transitions during message passing, an independent embedding representation is constructed for each state transition, resulting in a four-pole embedding space. Each node has a corresponding representation in four subspaces. The mapped four-pole embedding is obtained by using four independent linear layers, i.e., for each node...i Quad-pole embedding specifically refers to: Represents a node i The transition from state 0 to state 0, Represents a node i The transition from state 0 to state 1, Represents a node i The transition from state 1 to state 0, Represents a node i Transition from state 1 to state 1.

[0027] S103. Signal transmission based on Boolean logic: the first differentiable logic operator is defined as the bitwise minimum of any two embedded vectors, and the second differentiable logic operator is defined as the bitwise complement of the embedded vectors. S104. Define the third differentiable logic operator as the identity transformation, and process the embedding vector through the first differentiable logic operator, the second differentiable logic operator, and the third differentiable logic operator to obtain the embedding message and update the node embedding, and design the logic propagation direction. S105. Construct a graph neural network inference module based on the quadrupole embedding space and the logical propagation direction.

[0028] In this embodiment, the functional characteristics of a node in a sequential circuit are reflected through Boolean logic-based signal transmission. For example, Boolean logic-based signal transmission involves performing a Boolean intersection operation on an AND gate. and To preserve the functional information of bitwise summation during time-series learning, the first differentiable logic operator is employed. Second differentiable logic operator and the third differentiable logic operator Used to process embedded vectors, specifically: Defined as the bitwise minimum of two embedding vectors. Defined as the bitwise complement of the embedded vector. Defined as an identity transformation, bitwise inversion and bitwise minimum satisfy the necessary conditions of Boolean logic: For bitwise inversion, the second application will cancel the effect of the first application, restoring the original embedded vector, as expressed mathematically: ,in, Represents the node embedding vector; For bitwise minimum value operations, when all inputs are the same, the result is always equal to the input itself, that is... ; For triggers that do not perform logical operations, through operate; By using the first differentiable logic operator, the second differentiable logic operator, and the third differentiable logic operator, the embedded message is obtained and the node embedding is updated, and the logical propagation direction is designed. Based on the four-pole embedding space and the logical propagation direction, construct as follows: Figure 2 (a) shows the graph neural network inference module.

[0029] S2. Using the graph neural network inference module, dynamic functional modeling of the timing circuit diagram is performed to obtain the node embedding vector. The specific steps are as follows: S201. Using the quad-pole embedding space, the initial characteristics of each node in the timing circuit diagram are processed to obtain the state transition vector of the node. S202. Based on the node's state transition vector, using the logical propagation direction, by performing bitwise inversion, bitwise minimum value, and judgments of not performing logical operations, obtain the node embedding vector, obtain the embedding message, and obtain the node embedding by updating.

[0030] In this embodiment, the initial features of each node in the timing circuit diagram By inputting the four-level embedding space, we obtain the four-level embedding, which is the state transition vector of the node; The expression for the state transition vector of the node is as follows: , ; , ; in, Represents a node i The transition from state 0 to state 0, Represents a node i The transition from state 0 to state 1, Represents a node i The transition from state 1 to state 0, Represents a node i The transition from state 1 to state 1, Represents a node i initial characteristics, This represents the activation function. , , as well as Both represent linear transformation matrices.

[0031] In this embodiment, based on the node's state transition vector , , as well as By utilizing the logical propagation direction and performing bitwise negation, bitwise minimum value determination, and checks for exceptions to logical operations, the node embedding vector is obtained, thus yielding the embedded message. And obtain the node embedding through updates. ; The expressions for the embedded message and node embedding are as follows: ;

[0032] in, Indicates embedded message, Indicates the first l Layer state x to state y , It can be , , as well as , This represents the first differentiable logic operator. Represents a node i The predecessor node, Indicates the first l -1 level nodes j From state x to state y The transition vector, Indicates the first l -1 level nodes i From state x to state y The transition vector, This represents the set of AND gates in a circuit diagram. This represents the second differentiable logic operator. Indicates the first l -1 level nodes j From state y to state x The transition vector, Indicates the first l -1 level nodes i From state y to state x The transition vector, This represents the set of NOT gates in a circuit diagram. This represents the first differentiable logic operator. This represents the set of flip-flops in the circuit diagram. This represents the initial set of input nodes in the circuit diagram. Indicates node embedding, Represents a linear transformation matrix; NOT gate usage Propagating information from predecessor nodes, such as state transition vectors. Used for updating This ensures that the message reflects the inverted operation of the NOT gate.

[0033] S3. Based on the token-based system and the Mamba architecture, construct the Mamba memory module. The specific steps are as follows: S301. Based on the token method and graph segmentation, a predecessor-aware segmentation method is designed by using special padding tokens to complete sequences with fewer than two predecessor nodes. In this embodiment, based on the dual structure, another important characteristic of sequential circuits, the linear complexity and dynamic memory capability of the Mamba architecture are utilized to address the limitation of GNN modules, which can only perform logical reasoning. To construct the Mamba memory module, a precursor-aware word segmentation method is designed, specifically: Graph segmentation is a crucial step in mapping graph structures to sequences, enabling sequence encoders to adapt to graph data. However, for directed graphs like sequential circuits, there is currently no effective solution. This paper analyzes two key characteristics of sequential circuits: first, the signal of each node is directly influenced by its predecessor node; second, all nodes have at most two predecessor nodes. A design is developed that utilizes special padding tokens... , Given an all-zero embedding, the sequence with fewer than two predecessor nodes is padded to obtain the predecessor-aware word segmentation method.

[0034] S302. Sort the token sequence according to the clock-driven order, and use the same index mapping to sort the token sequences other than the current token sequence, thus designing a clock-driven token sorting strategy. In this embodiment, after word segmentation, in order to adapt the Mamba model to graph data, the word segmentation is defined sequentially, and the interval Δ, the first mapping matrix B, and the second mapping matrix C are designed as input functions. Since each token should be placed after all the tokens it depends on, each token will be updated based on the tokens preceding it in the sequence. In order to correctly represent the dependencies in the timing circuit, based on the inherent clock dependency in the timing circuit, specifically: compared to nodes that respond to clock signals later, nodes that respond earlier have less context information. According to the signal propagation rules in sequential circuits, the main input terminal and the flip-flop will respond to the signal first, and then propagate these signals to subsequent nodes along the topological order. In actual operation, the main input terminal and the flip-flop are placed at the beginning of the sequence, followed by the successor nodes of the predecessor node.

[0035] Since StateSeq uses a predecessor-aware token segmentation method, in order to ensure that nodes at the same position in the token sequence can correspond to each other, it sorts the nodes according to the clock-driven order based on its own node, and then applies the same index mapping to the sorting process of the other two sequences, thus designing a clock-driven token sorting strategy.

[0036] S303. Based on the Mamba architecture, a causal one-dimensional convolution is constructed, and the expressions for calculating the interval and mapping matrix are defined. The temporal dependency is modeled by using the evolution matrix, and the evolution matrix and mapping matrix are discretized by using the zero-order preservation rule to obtain the discrete state space model layer.

[0037] In this embodiment, based on the Mamba architecture, unlike existing works that use bidirectional Mamba to model undirected graphs, StateSeq uses three unidirectional Mamba modules to model the directionality of the circuit, constructs a causal one-dimensional convolution, and models the relationship between input tokens. The expression representing the relationship between the tokens is as follows: ; in, Indicates a token relationship. This represents the activation function. Indicates a convolutional layer. Represents a linear transformation matrix. Representation layer regularization, Represents the input sequence; Define the interval Δ and the first mapping matrix. and the second mapping matrix The calculation expression is used to filter the input information. The specific expression is as follows: , , ; in, Denotes the first mapping matrix, This represents the second mapping matrix, where △ represents the interval. This represents the activation function. , as well as Both represent linear transformation matrices; The evolutionary matrix is ​​used to model the temporal dependency, and the zero-order preservation rule is used to model the evolutionary matrix and the first mapping matrix. The discretization process is performed, and the specific expressions for the discretized evolution matrix and the first mapping matrix are as follows: , ; in, This represents the discretized evolution matrix. This represents the first mapping matrix after discretization. Representing the identity matrix, we obtain the discrete state-space model layer.

[0038] S304. Using the discrete state-space model layer, the latent state is updated, and the updated latent state is combined with the original input to obtain the output embedding. The output embedding is then concatenated and linearly transformed to obtain a one-way Mamba. S305. Based on the predecessor-aware word segmentation method, the clock-driven token sorting strategy, and unidirectional Mamba, construct the Mamba memory module.

[0039] In this embodiment, the discrete state-space model layer is used to update the potential state, and the specific expression is as follows: ; in, Indicates the updated potential state. Indicates a potential state; The updated latent state is combined with the original input to generate the output embedding, as shown in the following expression: ; in, Indicates output embedding. and Both represent linear transformation matrices. Indicates element-wise multiplication; The output embeddings are concatenated and then a linear transformation is applied to obtain a one-way Mamba; Integrating predecessor-aware word segmentation, clock-driven token sorting strategy, and one-way Mamba, a system is constructed as follows: Figure 2 (b) shows the Mamba memory module.

[0040] S4. Using the Mamba memory module, perform dual structure modeling on the node embeddings to obtain the embedding vectors, and complete the temporal circuit representation learning. The specific steps are as follows: S401. Use the predecessor-aware word segmentation method to segment the node embedding to obtain the token sequence; S402. Based on the clock-driven token sorting strategy, using the token sequence as a reference, sort the token sequence corresponding to the node itself according to the clock-driven order, and use the same index mapping to sort the token sequences other than the token sequence corresponding to the node itself, to obtain the dimensional sequence. S403. Based on the node sequence, use the dimension sequence to obtain the input sequence.

[0041] In this embodiment, the predecessor-aware word segmentation method is used to segment the node embedding, resulting in three token sequences, as shown in the following expression: ; in, Represents a token sequence. Indicates the node itself, This indicates the first predecessor node of the current node. Indicates the second predecessor node of the current node; Based on the clock-driven token sorting strategy, using the node itself as the base and following the clock-driven order, the token sequences corresponding to the node itself are sorted. Then, using the same index mapping, the token sequences other than those corresponding to the node itself are sorted to obtain the dimensional sequence, expressed as follows: ; in, Represents a dimensional sequence; Based on the node sequence, the input sequence is obtained using the dimension sequence, as shown in the following expression: ; in, Both indicate node embedding. Represents a node i In the l The resulting embedding vectors, sorted according to their own node order, are integrated. , to obtain the input sequence For padding tokens, all zeros are used for embedding.

[0042] S404. Based on unidirectional Mamba, the input sequence is processed using causal one-dimensional convolution to obtain the token relationship. Combining the token relationship, the calculation expression of the interval, and the calculation expression of the mapping matrix, the interval and mapping matrix are obtained. Combined with the evolution matrix, the latent state is updated using the discrete state space model layer. S405. Combine the updated latent state with the input sequence to obtain the output embedding, and then concatenate and linearly transform the output embedding to obtain the embedding vector.

[0043] In this embodiment, based on unidirectional Mamba, three unidirectional Mamba modules are used to model the directionality of the circuit, and three token sequence embeddings are employed. , , By processing the input sequence using causal one-dimensional convolution, token relationships are obtained. ; Combining token relationships The calculation expressions for the interval Δ, the first mapping matrix B, and the second mapping matrix C are obtained. These, combined with the evolution matrix A, are used to update the latent state using the discrete state-space model layer, resulting in the updated latent state. ; The updated latent state and the input sequence are combined to obtain the output embedding; because They are respectively from , , Therefore, the output embeddings are concatenated and linearly transformed to obtain the embedding vector. ; The specific expression for concatenating and linearly transforming the output embedding is as follows: ; in, Represents an embedding vector. Represents a linear transformation matrix. Indicates the first l The node embedding vector of a layer after sorting its own node order. Indicates the first l The node embedding vector of a layer, sorted according to the order of its first predecessor node. Indicates the first l The node embedding vector of a layer after sorting its nodes according to the order of their second predecessor nodes.

[0044] In this embodiment, the overall framework of the StateSeq algorithm based on GNN and Mamba modules is as follows: Figure 2 As shown; specifically, considering that there are four state transition strategies for nodes in a sequential circuit, StateSeq first maps the initial features of each node to four embedding spaces; in the graph neural network module, differentiable logic operators are defined based on Boolean logic to aggregate the information of predecessor nodes; then in the Mamba module, each node is converted into three tokens according to the predecessor nodes, and the tokens are sorted according to the clock-driven token ordering strategy (CTO), and finally input into a unidirectional Mamba structure to realize dynamic memory; using the unidirectional Mamba structure to realize dynamic memory, the final layer embedding vector is output to complete the sequential circuit representation learning.

[0045] In this embodiment, the core idea of ​​the present invention lies in the hybrid architecture of GNN and memory model and the customized design of circuit characteristics, and there are alternative solutions for some of its technical points. Alternatives to the Mamba memory module: This invention preferentially selects Mamba as the memory module, but it is not the only option. Other efficient state-space models capable of modeling long-range dependencies can also replace the Mamba module. In addition, some advanced sequence models, such as recurrent neural network variants with special memory mechanisms or Transformer variants optimized for handling long sequences, can also serve as alternatives to this memory module after appropriate modifications, although there may be differences in efficiency. Alternatives to the GNN inference module: The GNN module of this invention uses customized logic operators. Its underlying graph neural network architecture can be replaced with other types of directed graph neural networks, such as directed graph attention networks. The key point is that, regardless of the underlying architecture, it needs to be integrated or modified to support the core ideas of the four-pole embedding and differentiable logic operators proposed in this invention. Alternatives to tokenization and ordering strategies: The "predecessor-aware tokenization" proposed in this invention can be extended. For example, in addition to considering direct predecessors, second-order or higher-order neighbors of nodes can be included in the tokenization process. "Clock-driven token ordering" can also incorporate other heuristics, such as weighted ordering based on the importance of node type or the fan-out number of nodes, to explore better sequence processing orders; Application Expansion: This invention demonstrates effectiveness in tasks such as toggle rate prediction and flip-flop similarity prediction. However, the high-quality circuit characterization learned by this technical solution is general and can therefore be widely applied to other downstream tasks in the EDA field, such as power consumption analysis, reliability analysis, fault diagnosis, formal verification, and logic synthesis.

[0046] Example 2 In this embodiment, two tasks are selected to evaluate the performance of different models: state transition probability prediction (TPP) and flip-flop similarity prediction (FFSP). TPP is a key task that reflects the spatiotemporal correlation in sequential circuits and is widely used in the field of power consumption estimation. FFSP is an effective task for assisting power consumption estimation and reliability analysis. It evaluates the situation where flip-flops under the same input conditions have the same state transition, enabling the model to distinguish circuits with similar transition probabilities but different timing behaviors. To predict state transition probabilities, for the TPP task, the prediction results are generated using 01 and 10 embeddings, as shown in the following expression: ; in, Represents the simulation logic probability. This represents a multilayer perceptron. Represents a node i In the L The state vector of the layer from 0 to 1. Represents a node i In the L The layer's state vectors range from 1 to 0, and this applies to all nodes in the circuit. The difference between the simulated logic probability and the predicted value is measured using the mean absolute error. The specific steps are as follows: ; in, Indicates the mean absolute error. This represents all nodes in the circuit. This represents the predicted value.

[0047] In this embodiment, trigger similarity prediction is performed. For the FFSP task, for each clock cycle t, for each pair of triggers... Two indicator states were defined. and When the trigger and When the states are the same, It is 1 if it is active, otherwise it is 0; when the trigger... and Not only are the states the same, but when transitioning to the same state, 1 if true, 0 otherwise; trigger The similarity can be evaluated by calculating the ratio of matching state transitions to identical states across all evaluation periods, as shown in the following expression: ; in, Indicates trigger The similarity between two triggers (FF) can be determined by embedding. and The expression is as follows: ; in, Indicates similarity. By splicing four embedded , These represent the representation vectors of trigger a and trigger b, respectively. and The difference is obtained through calculation, and the specific steps are as follows: ; in, This represents the difference between trigger similarity and similarity score. Represents a set of triggers; To facilitate comparison of different models, two metrics are selected: mean absolute error (MAE) and average running time (Avg.RT). For TPP and FFSP tasks, MAE is defined by the above formulas respectively; Avg.RT is defined as the average time spent in each training round, which can evaluate the performance and speed of each model in different tasks.

[0048] In this embodiment, the model benchmarks used are: 1. General directed graph neural networks: MagNet, DIMPA, DirGCN, DirSAGE, DUPLEX, and LightDiC; MagNet uses complex matrices for graph diffusion, with its real and imaginary parts representing undirected adjacency relationships and edge directions, respectively; DIMPA proposes a directed flow imbalance loss function for self-supervised node embedding; DirGCN and DirSAGE aggregate incoming and outgoing edges to enhance structural modeling capabilities; DUPLEX utilizes Hermitian adjacency matrix decomposition and dual GAT encoders to model directional neighbor interactions; LightDiC simplifies the complex-based learning process into a single linear transformation, thereby reducing algorithm complexity; 2. Sequential circuit diagram neural networks: DeepSeq and DeepSeq2. DeepSeq uses DAGNN combined with a dual attention mechanism to encode state correlations, while DeepSeq2 designs three independent embedding spaces to learn decoupled sequential circuit representations.

[0049] In this embodiment, toggle ratio prediction (TPP) is performed. Table 1 shows the performance of all models on the TPP task. Based on these results, the following conclusions can be drawn: First, StateSeq exhibits the best performance with the lowest MAE value of 0.0165, achieving a 70.85% error reduction compared to the state-of-the-art benchmark model (DeepSeq2). Second, thanks to the highly parallel graph neural network and efficient Mamba architecture, StateSeq's runtime is significantly lower than DeepSeq and DeepSeq2, achieving a 91.61% speedup compared to DeepSeq2. Finally, DirGCN also achieved performance comparable to DeepSeq. The results indicate that, due to the lack of a suitable benchmark model for comparison, the design choices for timing circuit representation in DeepSeq may not have produced significant effects. In contrast, the StateSeq of this invention effectively models the dynamic functionality and binary structure characteristics of sequential circuits, avoiding the complex and inefficient design schemes of DeepSeq and DeepSeq2. Therefore, StateSeq is significantly better than existing sequential circuit graph neural networks in terms of both operating efficiency and test set error.

[0050] Table 1

[0051] In this embodiment, trigger similarity prediction (FFSP) was performed. Table 2 shows the performance results of all models on the FFSP task, from which the following conclusions can be drawn: First, StateSeq achieved the lowest mean absolute error (MAE), reducing it by 63.99% compared to the best sequence circuit learning model, DeepSeq2, and also outperforming various directed graph neural networks. In addition, in terms of training time, StateSeq significantly outperformed DeepSeq2 with a reduction of 91.66%, further highlighting the efficiency of StateSeq. It is worth noting that although the test error of DeepSeq2 is significantly reduced compared to DeepSeq, it still does not reach the level of some directed graph neural networks (such as DirSAGE). This result once again confirms that DeepSeq and DeepSeq2 are not good at sequence circuit learning, while directed graph neural networks, as an important baseline model category, cannot be ignored.

[0052] Table 2

[0053] In this embodiment, experimental results on two representative sequential circuit learning tasks show that StateSeq is significantly better than the best existing model, improving learning ability by 70.85% (63.99%) and efficiency by 91.61% (91.66%).

[0054] Table 3

[0055] In this embodiment, as shown in Table 3, in the experiments of the flip rate prediction task and the trigger similarity prediction task, in StateSeq (without logic propagation judgment part), QE is to remove the fourth-level embedding space and replace it with a single space; LO is to remove the differentiable logic operator and replace it with the mean operation; ALL is to remove QE and LO at the same time and only retain the Mamba memory module. In StateSeq (without discrete state space), PT removes the predecessor-aware word segmentation method and replaces it with a single token; CTO removes the clock-driven token sorting strategy and replaces it with a node-degree sorting strategy; ALL removes both PT and CTO, retaining only the graph neural network inference module; based on the flip-flop rate prediction (TPP) and trigger similarity prediction (FFSP), the mean absolute error (MAE) value is obtained. It can be seen that this application integrates a four-level embedding space, differentiable logic operators, predecessor-aware word segmentation method, and clock-driven token sorting strategy to obtain a high-performance, high-precision, and non-destructive sequential circuit representation learning method.

Claims

1. A method for learning representations of time-series circuits based on graph neural networks and state-space models, characterized in that, Includes the following steps: S1. Obtain the timing circuit diagram and construct the graph neural network inference module by designing a quadrupole embedding space; S2. Using the graph neural network inference module, dynamic functional modeling of the timing circuit diagram is performed to obtain the node embedding vector; S3. Based on the token-based system and Mamba architecture, construct a Mamba memory module; S4. Using the Mamba memory module, perform dual structure modeling on node embedding to obtain embedding vectors and complete the learning of time-series circuit representation.

2. The time-series circuit representation learning method based on graph neural networks and state-space models according to claim 1, characterized in that, S1 includes the following steps: S101. Obtain the timing circuit diagram, and obtain the preset type of state transition based on the changes between the low and high levels of each node in the timing circuit diagram; S102. Based on the state transition of the preset types, the initial features of each node are mapped using a preset number of independent linear layers to design a four-pole embedding space. S103. Signal transmission based on Boolean logic: the first differentiable logic operator is defined as the bitwise minimum of any two embedded vectors, and the second differentiable logic operator is defined as the bitwise complement of the embedded vectors. S104. Define the third differentiable logic operator as the identity transformation, and process the embedding vector through the first differentiable logic operator, the second differentiable logic operator, and the third differentiable logic operator to obtain the embedding message and update the node embedding, and design the logic propagation direction. S105. Construct a graph neural network inference module based on the quadrupole embedding space and the logical propagation direction.

3. The time-series circuit representation learning method based on graph neural networks and state-space models according to claim 2, characterized in that, S2 includes the following steps: S201. Using the quad-pole embedding space, the initial characteristics of each node in the timing circuit diagram are processed to obtain the state transition vector of the node. S202. Based on the node's state transition vector, using the logical propagation direction, by performing bitwise inversion, bitwise minimum value, and judgments of not performing logical operations, obtain the node embedding vector, obtain the embedding message, and obtain the node embedding by updating.

4. The time-series circuit representation learning method based on graph neural networks and state-space models according to claim 3, characterized in that, The expression for the state transition vector of the node is as follows: ， ； ， ； in, Represents a node i The transition vector from state 0 to state 0. Represents a node i The transition vector from state 0 to state 1. Represents a node i The transition vector from state 1 to state 0. Represents a node i The transition vector from state 1 to state 2. Represents a node i initial characteristics, This represents the activation function. , , as well as Both represent linear transformation matrices.

5. The time-series circuit representation learning method based on graph neural networks and state-space models according to claim 3, characterized in that, The expressions for the embedded message and node embedding are as follows: in, Indicates embedded message, Indicates the first l Layer state x to state y , This represents the first differentiable logic operator. Represents a node i The predecessor node, Indicates the first l -1 level nodes j From state x to state y The transition vector, Indicates the first l -1 level nodes i From state x to state y The transition vector, This represents the set of AND gates in a circuit diagram. This represents the second differentiable logic operator. Indicates the first l -1 level nodes j From state y to state x The transition vector, Indicates the first l -1 level nodes i From state y to state x The transition vector, This represents the set of NOT gates in a circuit diagram. This represents the first differentiable logic operator. This represents the set of flip-flops in a circuit diagram. This represents the initial set of input nodes in the circuit diagram. Indicates node embedding. This represents a linear transformation matrix.

6. The time-series circuit representation learning method based on graph neural networks and state-space models according to claim 1, characterized in that, S3 includes the following steps: S301. Based on the token method and graph segmentation, a predecessor-aware segmentation method is designed by using special padding tokens to complete sequences with fewer than two predecessor nodes. S302. Sort the token sequence according to the clock-driven order, and use the same index mapping to sort the token sequences other than the current token sequence, thus designing a clock-driven token sorting strategy. S303. Based on the Mamba architecture, a causal one-dimensional convolution is constructed, and the calculation expressions for the interval and mapping matrix are defined. The temporal dependency is modeled by using the evolution matrix, and the evolution matrix and mapping matrix are discretized by using the zero-order preservation rule to obtain the discrete state space model layer. S304. Using the discrete state-space model layer, the latent state is updated, and the updated latent state is combined with the original input to obtain the output embedding. The output embedding is then concatenated and linearly transformed to obtain a one-way Mamba. S305. Based on the predecessor-aware word segmentation method, the clock-driven token sorting strategy, and unidirectional Mamba, construct the Mamba memory module.

7. The time-series circuit representation learning method based on graph neural networks and state-space models according to claim 6, characterized in that, S4 includes the following steps: S401. Use the predecessor-aware word segmentation method to segment the node embedding to obtain the token sequence; S402. Based on the clock-driven token sorting strategy, using the token sequence as a reference, sort the token sequence corresponding to the node itself according to the clock-driven order, and use the same index mapping to sort the token sequences other than the token sequence corresponding to the node itself, to obtain the dimensional sequence. S403. Based on the node sequence, use the dimension sequence to obtain the input sequence; S404. Based on unidirectional Mamba, the input sequence is processed using causal one-dimensional convolution to obtain the token relationship. Combining the token relationship, the calculation expression of the interval, and the calculation expression of the mapping matrix, the interval and mapping matrix are obtained. Combined with the evolution matrix, the latent state is updated using the discrete state space model layer. S405. Combine the updated latent state with the input sequence to obtain the output embedding, and then concatenate and linearly transform the output embedding to obtain the embedding vector.

8. The time-series circuit representation learning method based on graph neural networks and state-space models according to claim 7, characterized in that, The expression for the token sequence is as follows: in, Represents a token sequence. Indicates the node itself, This indicates the first predecessor node of the current node. Indicates the second predecessor node of the current node; The expression for the dimensional sequence is as follows: in, Represents a dimensional sequence.

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