Cross-design software netlist data co-processing method

Abstract

The invention is applicable to the technical field of electronic design automation, and provides a cross-design software netlist data co-processing method, which comprises the following steps: acquiring first netlist data; wherein the first netlist data is used for representing a logic connection relationship among a plurality of electrical components in the first schematic diagram, packaging library information corresponding to the electrical components and the like; wherein the first schematic diagram is a schematic diagram constructed based on first design software; performing data format conversion on the first netlist data to obtain second netlist data; importing the second netlist data into second design software; wherein the second design software is different from the first design software; and generating a circuit diagram corresponding to the printed circuit board based on the second netlist data and the second design software. According to the method, when cross-software circuit diagram design is carried out, an engineer does not need to consume extra time in format adaptation and data verification, so that the method focuses on core design links such as circuit diagram layout and wiring, the design period is shortened on the whole, and the working efficiency is improved.

Description

Technical Field

[0001] This application belongs to the field of electronic design automation technology, and in particular relates to a method for collaborative processing of netlist data across design software. Background Technology

[0002] In the field of electronic system equipment design, there are many types of Electronic Design Automation (EDA) (such as Altium Designer, Pads, Allegro, Mentor, etc.). Different companies and different hardware engineers have different usage habits, resulting in the coexistence of multiple software programs.

[0003] In the existing technology, there is a lack of efficient and compatible schematic data connection methods between various EDA software. When hardware engineers use software such as Altium Designer to draw schematics, if printed circuit board (PCB) engineers need to use Allegro software for PCB design, they often have to redesign from scratch to achieve normalization, which results in a large amount of repetitive work and low design efficiency. Summary of the Invention

[0004] This application provides a cross-design software netlist data collaborative processing method, which allows engineers to focus on core design aspects such as circuit layout and routing without spending extra time on format adaptation and data verification, thereby shortening the overall design cycle and improving work efficiency.

[0005] In a first aspect, embodiments of this application provide a method for collaborative processing of netlist data across design software, including: Obtain the first netlist data; wherein, the first netlist data is used to characterize the logical connection relationship between multiple electrical components in the first schematic diagram and the package library information corresponding to the multiple electrical components, etc.; wherein, the first schematic diagram is a schematic diagram constructed based on the first design software; The data format of the first netlist is converted to obtain the data of the second netlist; Import the second netlist data into the second design software; the second design software is different from the first design software. The circuit diagram corresponding to the printed circuit board is generated based on the second netlist data and the second design software.

[0006] In this embodiment, by extracting the netlist data from the first design software and converting it to a format compatible with the second design software, repetitive work such as manually redrawing schematics or inputting electrical connection relationships due to software differences is avoided, reducing manual input errors. Simultaneously, the netlist data directly relates to the logical relationships of electrical components, ensuring the consistency of design logic during cross-software conversion. This eliminates the need for engineers to spend extra time on format adaptation and data verification, allowing them to focus on core design aspects such as circuit board layout and routing, thus shortening the overall design cycle and improving work efficiency.

[0007] In one possible implementation of the first aspect, before obtaining the first netlist data, the method includes: Create a schematic package library corresponding to the first design software; wherein, the schematic package library contains multiple first electrical components and a first package identifier corresponding to each first electrical component and a first pin information corresponding to each first electrical component; Create a printed circuit board package library corresponding to the second design software; wherein the printed circuit board package library includes multiple second electrical components and a second package identifier corresponding to each second electrical component and a second pin information corresponding to each second electrical component; wherein the multiple first electrical components in the schematic package library correspond one-to-one with the multiple second electrical components in the printed circuit board package library, the first package identifier of each first electrical component is the same as the second package identifier of the corresponding second electrical component, and the first pin information of each first electrical component is the same as the second pin information of the corresponding second electrical component.

[0008] In this embodiment of the application, by unifying the package identifiers of corresponding electrical components in different design software package libraries, the consistency of component physical information is ensured when netlist data is converted across software, thus avoiding import errors caused by package mismatch from the source, reducing the time cost of repeated corrections, and improving the smoothness of cross-software design processes.

[0009] In one possible implementation of the first aspect, the first netlist data is converted to a different data format to obtain the second netlist data, including: Obtain the design version corresponding to the first netlist data; Match the format conversion tool to the design version; The data format of the first netlist data is converted using a format conversion tool to obtain the second netlist data.

[0010] In this embodiment, by matching the corresponding format conversion tool according to the design version, the accuracy and compatibility of the netlist data format conversion are ensured, conversion errors caused by version differences are avoided, rework is reduced, and cross-software data conversion efficiency is improved.

[0011] In one possible implementation of the first aspect, the method further includes: After importing the second netlist data into the second design software, determine whether there are any error messages; If an error message is found, the second netlist data is corrected to obtain the corrected third netlist data; Import the data from the third netlist into the second design software.

[0012] In this embodiment, by performing error detection and correction iteration on the netlist data imported into the second design software, data errors can be eliminated in a timely manner, ensuring that the netlist information accurately matches the software requirements, avoiding the accumulation of errors that affect subsequent circuit board design, and improving the reliability and efficiency of cross-software design.

[0013] In one possible implementation of the first aspect, the second netlist data is modified to obtain modified third netlist data, including: If the error message indicates that there is incorrect format data in the second netlist, then determine the data type corresponding to the incorrect format data; If the data type representing the netlist data of the second netlist has a format error in the netlist name, then the netlist name of the second netlist data is modified to obtain the third netlist data; If the data type indicates that there is unrecognized symbolic data in the second netlist data, then the unrecognized symbolic data will be deleted to obtain the third netlist data.

[0014] In this embodiment, by accurately locating and correcting errors in netlist name format and deleting unrecognized symbol data, netlist data format problems can be efficiently solved, ensuring that the corrected netlist data meets the requirements of the second design software, and improving the success rate of netlist import and correction efficiency.

[0015] In one possible implementation of the first aspect, the second netlist data is modified to obtain the modified third netlist data, and the method further includes: If the error message indicates that there is a package identifier error in the second netlist data, then the schematic package library of the first design software is compared with the printed circuit board package library corresponding to the second design software to obtain the comparison result; If the comparison result indicates that there is no corresponding information between the schematic package library and the printed circuit board package library, then the schematic package library and the printed circuit board package library are modified respectively, so that the multiple electrical components in the modified schematic package library correspond one-to-one with the multiple electrical components in the printed circuit board package library, the package identifier of each electrical component in the schematic package library is the same as the package identifier of the corresponding electrical component in the printed circuit board package library, and the pin information of each electrical component in the schematic package library is the same as the pin information of the corresponding electrical component in the printed circuit board package library. The first netlist data is reformatted to obtain the converted fourth netlist data.

[0016] In this embodiment of the application, by comparing and correcting the correspondence between electrical components, package identifiers and pin information between the schematic package library and the printed circuit board package library, the package identifier error of the second netlist data is resolved, ensuring that the first netlist data is converted into an accurate and usable third netlist data.

[0017] In one possible implementation of the first aspect, the method further includes: Re-import the third or fourth netlist data into the second design software and re-check whether there are any error messages; If error messages are found, continue to correct them until the corrected fifth netlist data is correctly imported into the second design software.

[0018] In this embodiment, the process of re-importing the corrected third netlist data into the second design software to verify errors, and continuing to correct errors until the generated netlist data can be correctly imported, can completely solve the compatibility problem between the netlist data and the second design software, avoid failures in subsequent PCB design stages due to residual errors, ensure the accuracy and availability of the netlist data, and provide a reliable guarantee for the smooth generation of PCB circuit diagrams and subsequent layout and routing work.

[0019] Secondly, embodiments of this application provide a cross-design software netlist data collaborative processing apparatus, comprising: The data acquisition module is used to acquire first netlist data; wherein, the first netlist data is used to characterize the logical connection relationship between multiple electrical components in the first schematic diagram; wherein, the first schematic diagram is a schematic diagram constructed based on the first design software; The format conversion module is used to convert the data format of the first netlist data to obtain the second netlist data. The netlist import module is used to import the second netlist data into the second design software; the second design software is different from the first design software.

[0020] The circuit diagram generation module is used to generate the circuit diagram corresponding to the printed circuit board based on the second netlist data and the second design software.

[0021] Thirdly, embodiments of this application provide a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements a cross-design software netlist data collaborative processing method as described in any of the first aspects above.

[0022] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements a cross-design software netlist data collaborative processing apparatus as described in any of the first aspects above.

[0023] Fifthly, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute the cross-design software netlist data collaborative processing apparatus described in any of the first aspects above.

[0024] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart illustrating the cross-design software netlist data collaborative processing method provided in an embodiment of this application; Figure 2 This is a flowchart illustrating the format conversion method provided in an embodiment of this application; Figure 3 This is a schematic diagram of the process for importing netlist data into target software, provided in an embodiment of this application. Figure 1 ; Figure 4 This is a schematic diagram of the error message correction process provided in the embodiments of this application. Figure 1 ; Figure 5 This is a schematic diagram of the error message correction process provided in the embodiments of this application. Figure 2 ; Figure 6 This is a schematic diagram of the process for importing netlist data into target software, provided in an embodiment of this application. Figure 2 ; Figure 7 This is a structural block diagram of the cross-design software netlist data collaborative processing device provided in the embodiments of this application; Figure 8 This is a schematic diagram of the structure of the terminal device provided in the embodiments of this application. Detailed Implementation

[0027] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0028] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0029] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0030] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0031] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0032] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0033] In the field of electronic system equipment design, there are many types of Electronic Design Automation (EDA) (such as Altium Designer, Pads, Allegro, Mentor, etc.). Different companies and different hardware engineers have different usage habits, resulting in the coexistence of multiple software programs.

[0034] In the existing technology, there is a lack of efficient and compatible schematic data connection methods between various EDA software. When hardware engineers use software such as Altium Designer to draw schematics, if printed circuit board (PCB) engineers need to use Allegro software for PCB design, they often have to redesign from scratch to achieve normalization, which results in a large amount of repetitive work and low design efficiency.

[0035] To address the aforementioned technical issues, this application provides a cross-design software netlist data collaborative processing method. The method involves exporting a Telesis (.NET) netlist from Altium Designer, converting it to an Allegro-compatible WG2005-p_a_tel.tel netlist using a relevant conversion tool, importing it into Allegro, correcting package issues (such as mismatched identifiers) or netname issues (such as # symbols or Chinese characters) based on a txt error file, and repeating the import process until no errors occur. Then, the packaged devices are imported via Place-quickplace, finally completing the import for PCB layout and routing. This method solves the compatibility problem between the two software programs and avoids repetitive design.

[0036] See Figure 1 This is a flowchart illustrating a cross-design software netlist data collaborative processing method provided in an embodiment of this application. It is intended as an example and not a limitation. The method may include the following steps: S101, Obtain the first netlist data; wherein, the first netlist data is used to characterize the logical connection relationship between multiple electrical components in the first schematic diagram, etc.; wherein, the first schematic diagram is a schematic diagram constructed based on the first design software.

[0037] In this embodiment of the application, "extracting netlist data that reflects the electrical connection logic between components from the schematic diagram (i.e., the first schematic diagram) created by a specific design software" is essentially to transform the visual logic of "which components are connected together and how they are connected" in the schematic diagram into structured data (i.e., the first netlist data) that can be recognized and transmitted by the software, so as to provide a data foundation for subsequent cross-software design.

[0038] For example, first ensure that the first schematic has been drawn in the first design software (such as Altium Designer) and that the schematic has no basic errors (such as missing components or incomplete wire connections). At the same time, configure the software's package library in advance (to avoid missing key component information in the subsequent netlist).

[0039] Next, open the first schematic file you have drawn, find the netlist export path in the software menu (e.g., in Altium Designer, through the "Design" → "netlist for project" menu), and select the netlist format that matches the schematic (e.g., Telesis format).

[0040] Finally, after confirming the export parameters (such as whether to include component package identifiers, net name notes, etc.), execute the export. The software will automatically scan the schematic and organize the logical information such as "component model, component reference number, and connection relationship between each component pin" into a structured netlist file (such as the .TXT or .NET format file exported by Altium Designer). This file is the "first netlist data". Opening it will directly show connection logic descriptions such as "Pin 1 of component R1 is connected to pin 3 of component U1" and "Net name VCC_5V is associated with pin 2 of component C1 and pin 1 of R2".

[0041] In one embodiment, before obtaining the first netlist data in step S101, the method further includes: Create a schematic footprint library corresponding to the first design software; wherein the schematic footprint library contains multiple first electrical components and a first footprint identifier corresponding to each first electrical component, as well as first pin information corresponding to each first electrical component; create a printed circuit board footprint library corresponding to the second design software; wherein the printed circuit board footprint library contains multiple second electrical components and a second footprint identifier corresponding to each second electrical component, as well as second pin information corresponding to each second electrical component; wherein the multiple first electrical components in the schematic footprint library correspond one-to-one with the multiple second electrical components in the printed circuit board footprint library, the first footprint identifier of each first electrical component is the same as the second footprint identifier of the corresponding second electrical component, and the first pin information of each first electrical component is the same as the second pin information of the corresponding second electrical component.

[0042] In this embodiment, a package library is created for two different design software programs (the schematic package library corresponding to the first design software and the PCB package library corresponding to the second design software). The corresponding electrical components, package identifiers, and pin information in the two package libraries are ensured to be completely consistent. Essentially, this unifies the "component physical parameter language" for cross-software design in advance, avoiding the inability to identify components due to mismatched package identifiers (e.g., "RES_0402" in software A and "RES0402" in software B) when importing netlists later. This removes the basic obstacles for the cross-software flow of netlist data.

[0043] The process involves creating a schematic footprint library for the primary design software (such as Altium Designer). First, open Altium Designer and create a new footprint library file (.PcbLib format) through the "Library" panel. Then, for the electrical components (such as resistors, capacitors, and chips) required in the project, draw or call standard footprints one by one. This results in a schematic footprint library containing multiple "first electrical components (such as 0402 resistors and SSOP16 chips) + corresponding first footprint identifiers." Save and configure this library in the Altium Designer's library path to ensure that the footprint can be matched when the schematic calls a component.

[0044] To create a printed circuit board footprint library for a second design software (such as Allegro), first open Allegro and create a new footprint library file (.dra format). For each first electrical component in the schematic footprint library, create a corresponding second electrical component in Allegro. After creating footprints for all corresponding components, a printed circuit board footprint library is formed. Configure its path in Allegro to ensure that the footprint identifier can be recognized when importing the netlist later.

[0045] Finally, compile the correspondence table between the "Schematic Package Library - Printed Circuit Board Package Library" and check one by one: whether the first electrical component (such as the 0402 resistor) and the second electrical component (the 0402 resistor in Allegro) correspond one-to-one, and whether their package identifiers (both are "RES_0402") and physical parameters (pads, dimensions, etc.) are completely consistent, to avoid subsequent PCB components being unable to be soldered due to parameter deviations.

[0046] In addition, after creating the wrapper libraries for the two software programs, it is necessary to set the wrapper library paths for both. This is to ensure that the software can find and call the pre-created wrapper library (ensuring that the wrapper information used by the two software programs is consistent), and to avoid errors caused by "software cannot find wrapper" or "calling the wrong wrapper" when exporting / importing netlists later. This is a basic configuration step for cross-software design.

[0047] The above method ensures the consistency of component physical information when converting netlist data across software by unifying the package identifiers of corresponding electrical components in different design software package libraries. This avoids import errors caused by package mismatch from the source, reduces the time cost of repeated corrections, and improves the smoothness of cross-software design processes.

[0048] S102, convert the data format of the first netlist data to obtain the second netlist data.

[0049] In this embodiment, the first netlist data (e.g., .TEL format) exported from the first design software (e.g., Altium Designer) is adjusted in a specific way in terms of its data structure, syntax rules, or file format to conform to the standards that the second design software (e.g., Allegro) can recognize and read. Finally, a second netlist data (e.g., WG2005-p_a_tel.tel format) that can be directly used by the second design software is generated. Essentially, this solves the problem of "language incompatibility" between netlist data from different software and enables cross-software data transfer.

[0050] See Figure 2 This is a flowchart illustrating the format conversion method provided in the embodiments of this application, such as... Figure 2 As shown, step S102 includes: S201, obtain the design version corresponding to the first netlist data.

[0051] In this embodiment of the application, the specific version of the design file (such as schematic diagram or project) corresponding to the first netlist data exported from the first design software (such as Altium Designer) is determined. The purpose is to ensure that the tools and rules of the corresponding version can be matched when converting the netlist format and importing it into the second design software, so as to avoid conversion or import failure due to version incompatibility.

[0052] For example, you can open the source project from which the first netlist data was exported (such as the schematic project in Altium Designer), find the "Project" or "File" related options in the software menu bar (such as right-clicking the project name in Altium Designer → "Properties"), and view the "Design Version" information in the project properties window (some software will record the project creation version, update version, or you need to manually mark the version number, such as "V1.0" "V2.1").

[0053] Another example is to find the first exported netlist file (such as .TEL or .NET format), right-click the file → "Properties", and view the software version associated with the file when it was created in "Details" or "Summary" (some software will mark the version information at the beginning of the netlist file, such as "Altium Designer22.10 - Netlist V1.0" displayed in the first line after opening the netlist file, directly obtain the corresponding design version).

[0054] S202, a format conversion tool that matches the design version.

[0055] In this embodiment of the application, a compatible netlist format conversion tool is selected or determined based on the design version corresponding to the first netlist data (such as the Altium Designer software version from which the netlist was exported, or the project design stage version). Essentially, this ensures that the conversion tool can accurately identify the structure and syntax of the netlist data through version matching, avoiding conversion errors caused by incompatibility between the tool and the netlist version, and guaranteeing the conversion effect from the first netlist to the second netlist.

[0056] For example, if the first netlist is a Telesis format netlist exported from Altium Designer 22 (design version is "Altium Designer 22-V1.0"), then a tool that supports the conversion of netlists for this version needs to be matched. If the commonly used Allegro-specific skill script "pta" in the project has two versions, V2.0 and V3.0, and V3.0 is explicitly marked as "supporting Altium Designer 20 and above netlist conversion", then the V3.0 version of the "pta" script should be selected as the format conversion tool. If the first netlist was exported from an older version of Altium Designer 18, and "pta" V2.0 is only compatible with the older version netlist, then the V2.0 version of the "pta" script should be matched, or a third-party conversion tool compatible with the corresponding older version should be selected.

[0057] S203, The data format of the first netlist data is converted using a format conversion tool to obtain the second netlist data.

[0058] In this embodiment of the application, the first netlist data (such as the .TEL format netlist of Altium Designer) exported from the first design software is processed using a previously matched format conversion tool (such as the Allegro dedicated skill script "pta" in the document, or a third-party conversion tool).

[0059] Specifically, the data structure and syntax rules of the netlist will be adjusted (such as correcting symbols and field arrangements that do not conform to the specifications of the second design software), or the file format will be converted to generate second netlist data (such as WG2005-p_a_tel.tel format netlist) that can be recognized and used by the second design software (such as Allegro). In essence, it is to enable different software to "understand" the same batch of electrical appliance connection logic data.

[0060] The above method ensures the accuracy and compatibility of netlist data format conversion by matching the corresponding format conversion tool according to the design version, avoids conversion errors caused by version differences, reduces rework, and improves the efficiency of cross-software data conversion.

[0061] S103, import the second netlist data into the second design software; wherein the second design software is different from the first design software.

[0062] In this embodiment of the application, the second netlist data (such as WG2005-p_a_tel.tel) that has been converted into a format recognizable by the second design software (such as Allegro) is loaded into the software to provide component connection logic data for subsequent PCB design (such as component placement and layout routing).

[0063] Specifically, open the second design software (Allegro), find the "File" related operation path in the top menu bar (such as "File—import—logic—other" in the document), in the pop-up file selection window, locate the storage path of the second netlist data (WG2005-p_a_tel.tel) and select the file, click "OK", the software will automatically read the component connection logic in the netlist and complete the import; if the netlist conforms to the software specifications, it will prompt that the import is successful; if there is incompatible content (such as incorrect package identifier), it will generate an error file (such as a txt file) to indicate the problem.

[0064] In one embodiment, see Figure 3 This is a schematic diagram of the process for importing netlist data into target software, provided in an embodiment of this application. Figure 1 ,like Figure 3As shown, step S103 includes: S301: After importing the second netlist data into the second design software, determine whether there are any error messages.

[0065] In the embodiments of this application, S302, if there is an error message, the second netlist data is corrected to obtain the corrected third netlist data.

[0066] In this embodiment of the application, after importing the second netlist data (such as WG2005-p_a_tel.tel adapted for Allegro) into the second design software (such as Allegro), it is checked whether the software provides an error message in order to determine whether the netlist data conforms to the import specifications of the software. The purpose is to promptly detect problems in the netlist data (such as incorrect package identifiers or abnormal net name formats) and prevent erroneous data from entering the subsequent PCB design stage.

[0067] For example, after the netlist import operation is completed, the second design software (Allegro) will directly pop up a prompt window. If it displays information such as "import successful" or "no errors", then there are no errors; if it prompts "there are XX errors" or "some data cannot be recognized", then there are error messages.

[0068] Another example is that some software (such as Allegro) will automatically generate an error log file (mostly in txt format, such as the error txt file mentioned in the document) when the netlist import fails or there are errors. You can find the file in the software's default storage path (or the path specified during import) and open it to view the specific error information (such as "Encapsulation RES_0402 not found" "Network name VCC#5V format error").

[0069] In one embodiment, see Figure 4 This is a schematic diagram of the error message correction process provided in the embodiments of this application. Figure 1 ,like Figure 4 As shown, step S302 includes: S401, if the error message indicates that there is incorrect format data in the second netlist data, then determine the data type corresponding to the incorrect format data.

[0070] In this embodiment of the application, when the netlist is imported into the second design software, if the error message is clearly "the second netlist data has a format error", then it is further distinguished and determined which type of data in the netlist (such as net name, package identifier, component parameters, etc.) does not conform to the software specification. The purpose is to accurately locate the specific type of format problem, provide a basis for subsequent targeted correction, and avoid blindly modifying the netlist.

[0071] S402, if the data type representing the netlist name of the second netlist data has a format error, then modify the netlist name of the second netlist data to obtain the third netlist data.

[0072] In this embodiment of the application, when it is determined that the error originates from "the netlist name of the second netlist data does not conform to the format specification" (such as the netlist name containing special characters, exceeding the length limit, etc.), the netlist name is modified to conform to the requirements of the second design software (such as Allegro). The new netlist data obtained after modification is the third netlist data. The purpose is to solve the netlist import problem caused by incorrect name format.

[0073] Specifically, first, locate the incorrect netlist name through the software error file (such as a .txt file) or the netlist file itself. For example, if the error message is "Netlist name 'Altium#Designer Netlist' contains invalid character '#'", then the incorrect netlist name is "Altium#Designer Netlist". The error is caused by the inclusion of the special symbol "#" which is not supported by the second design software. Then, check the netlist name requirements of the second design software (such as Allegro) to confirm the specifications (usually "only contains English letters, numbers, and underscores, excluding spaces, #, @, and other special symbols, and the length does not exceed XX characters").

[0074] Finally, open the second netlist data file (e.g., WG2005-p_a_tel.tel) with a text editor (such as Notepad). Locate the netlist name field (usually in the file header, such as "NETLIST_NAME: Altium#Designer Netlist") and modify the name according to the specifications. Change "Altium#Designer Netlist" to "Altium_Designer_Netlist" (remove the "#", replace the Chinese characters with English characters, and connect them with underscores). After modification, save the netlist file with the new name (or overwrite the original file; it is recommended to back it up before proceeding). This netlist file is now the "third netlist data," and you can try importing it into the second design software again.

[0075] S403, if the data type indicates that there is unrecognized symbolic data in the second netlist data, then delete the unrecognized symbolic data to obtain the third netlist data.

[0076] In this embodiment, when it is determined that the error originates from "symbol data that the second design software cannot recognize in the second netlist data" (such as redundant special symbols, software incompatible format marks, etc.), these unrecognized symbols are deleted to make the netlist data conform to the software's recognition specifications. The newly generated netlist data after modification is the third netlist data. The purpose is to solve the problem of netlist import failure caused by unrecognized symbols. The netlist data obtained after deleting unrecognized characters is the third netlist data, which can be re-imported into the second design software to verify whether the error has been resolved.

[0077] The above method can efficiently solve netlist data format problems by accurately locating and correcting netlist name format errors and deleting unrecognized symbol data, ensuring that the corrected netlist data meets the requirements of the second design software, and improving the success rate of netlist import and correction efficiency.

[0078] In one embodiment, see Figure 5 This is a schematic diagram of the error message correction process provided in the embodiments of this application. Figure 2 ,like Figure 5 As shown, it includes: S501, if the error message indicates that there is a package identifier error in the second netlist data, then the schematic package library of the first design software is compared with the printed circuit board package library corresponding to the second design software to obtain the comparison result.

[0079] In this embodiment of the application, when the second netlist data is imported into the second design software and an error is reported, and the error reason is clearly "package identifier error", the schematic package library (a library that stores component package identifiers and physical parameters) of the first design software (such as Altium Designer) is compared with the PCB package library of the second design software (such as Allegro) to find the differences between the two in package identifiers and parameters, locate the root cause of the error (such as inconsistent identifier naming, parameter mismatch, etc.), and provide a basis for subsequent correction of package identifier errors.

[0080] Specifically, you can open Altium Designer, find the schematic footprint library (.SchLib) or PCB footprint library (.PcbLib) corresponding to the project, and export the footprint information list, which includes key information such as "footprint identifier (e.g., RES_0402), pad size / spacing, and component physical dimensions" for each component. Organize this information into a table (columns: component reference number, footprint identifier, pad parameters). Then, open Allegro, retrieve the corresponding PCB footprint library (.dra / .psm file), and export the footprint information through the software "Library Manager". Organize this information into a table as well, keeping the column names consistent with the first design software list (component reference number, footprint identifier, pad parameters).

[0081] Verify that the identifier of the same component (e.g., 0402 resistor) in the first design software library (e.g., RES_0402) is completely consistent with the identifier in the second design software library (e.g., Res0402 / RES0402). Locate identification errors caused by differences in capitalization, symbols, or naming rules. Compare the pad size, spacing, and component outline dimensions under the same identifier to confirm whether there are "identical identifier names but inconsistent parameters" (e.g., the pad width of 0402 resistor in the first library is 0.2mm, while in the second library it is 0.3mm). Such situations will also trigger a "package identifier error" report.

[0082] S502, if the comparison result indicates that the schematic package library and the printed circuit board package library do not correspond, then the schematic package library and the printed circuit board package library are modified respectively, so that the multiple electrical components in the modified schematic package library correspond one-to-one with the multiple electrical components in the printed circuit board package library, the package identifier of each electrical component in the schematic package library is the same as the package identifier of the corresponding electrical component in the printed circuit board package library, and the pin information of each electrical component in the schematic package library is the same as the pin information of the corresponding electrical component in the printed circuit board package library.

[0083] In this embodiment, when comparing the schematic footprint library of the first design software and the PCB footprint library of the second design software, if mismatches are found in footprint identifiers, component correspondences, and pin information, the contents of the two footprint libraries need to be adjusted respectively to ultimately achieve three types of core matching: First, one-to-one correspondence at the component level (all components in the first library are also in the second library, with no omissions or misalignments); second, the footprint identifiers of corresponding components are completely consistent (no differences in naming, capitalization, or symbols); and third, the pin information (pin quantity, number, position, and electrical attributes) of corresponding components are completely matched, thus solving the problem of incorrect footprint identifiers in the netlist from the root and avoiding repeated errors during subsequent netlist imports.

[0084] Specifically, when modifying a schematic footprint library (such as Altium Designer's .SchLib), you can open the library file to edit the corresponding component properties, unify the footprint identifier (to be consistent with the PCB library), and adjust the pin count / number / electrical properties to ensure compliance with design specifications. When modifying a PCB footprint library (such as Allegro's .dra / .psm), you can create / edit footprints through the library manager, match the identifier naming of the schematic library, calibrate the pad size, pin position and spacing, and finally use a comparison verification tool to confirm that the components in the two libraries correspond one-to-one and that the identifiers and pin information are completely consistent.

[0085] S503, re-convert the format of the first netlist data to obtain the converted fourth netlist data.

[0086] In this embodiment, the format conversion process is re-executed for the initial first netlist data (such as a native Telesis format netlist exported from Altium Designer) (rather than based on the corrected second / third netlist) to generate a completely new fourth netlist data. This is usually done because the root cause of the problem was found in the format conversion stage when the netlist data was corrected earlier (such as incomplete initial conversion rules or version mismatch). It is necessary to re-convert to ensure that the netlist format is compatible with the second design software (such as Allegro) from the source, and to avoid the inefficient operation of repeatedly correcting the netlist.

[0087] In the above method, by comparing and correcting the correspondence of electrical components, package identifiers and pin information between the schematic package library and the printed circuit board package library, the package identifier error of the second netlist data is resolved, ensuring that the first netlist data is converted into an accurate and usable fourth netlist data.

[0088] S303, import the third or fourth netlist data into the second design software.

[0089] In this embodiment, the third netlist data after error correction (such as modifying the netlist name, deleting unrecognized symbols, and replacing incorrect package identifiers) or the fourth netlist data after modifying the package library and re-converting the format is reloaded into the second design software (such as Allegro). The purpose is to verify whether the previous errors have been resolved and to ensure that the netlist data can be correctly recognized by the second design software, laying the foundation for subsequent PCB component placement, layout and routing, etc. Essentially, it is a secondary confirmation of the usability of the corrected netlist.

[0090] In the above method, by performing error detection and correction iteration on the netlist data imported into the second design software, data errors can be eliminated in a timely manner, ensuring that the netlist information accurately matches the software requirements, avoiding the accumulation of errors that affect subsequent circuit board design, and improving the reliability and efficiency of cross-software design.

[0091] In one embodiment, see Figure 6 This is a schematic diagram of the process for importing netlist data into target software, provided in an embodiment of this application. Figure 2 ,like Figure 6 As shown, the method also includes: S601, re-import the third or fourth netlist data into the second design software, and re-determine whether there are any error messages.

[0092] In this embodiment, based on the results of previous netlist correction or re-conversion, the third netlist data with corrected errors (such as the netlist after package identification and symbol format correction) or the fourth netlist data generated by re-format conversion (such as the netlist obtained from the original first netlist after correcting the conversion rules) is selected and imported into the second design software (such as Allegro) again. The purpose is to verify the final compatibility of the netlist data and ensure that the subsequent PCB design can proceed smoothly.

[0093] S603, if there are error messages, continue to correct the error messages until the corrected fifth netlist data is correctly imported into the second design software.

[0094] In this embodiment, if errors still occur after the third or fourth netlist data is re-imported into the second design software (such as Allegro), it is necessary to continuously correct the new error information (such as residual format errors, package identification mismatch, pin mapping deviation, etc.), and iterate the "import-error-correction" process repeatedly until the final generated fifth netlist data can be successfully imported into the second design software without errors, ensuring that the netlist data fully complies with the software specifications and clearing data obstacles for subsequent PCB design.

[0095] The above method involves a cyclical process of re-importing the corrected third netlist data into the second design software to verify errors, and continuing to correct errors until the generated netlist data can be correctly imported. This process can completely solve the compatibility problem between the netlist data and the second design software, avoid failures in subsequent PCB design stages due to residual errors, ensure the accuracy and usability of the netlist data, and provide a reliable guarantee for the smooth generation of PCB circuit diagrams and subsequent layout and routing work.

[0096] S104 generates the circuit diagram corresponding to the printed circuit board based on the second netlist data and the second design software.

[0097] In this embodiment, based on the second netlist data adapted to the second design software (such as Allegro), the circuit diagram (i.e. the initial PCB design diagram, which includes component layout and electrical connection relationship framework) required for printed circuit board (PCB) design is generated using the component connection logic contained in the netlist in the software. Essentially, the "abstract connection logic" in the netlist is transformed into a "visual PCB design diagram" that can be edited by the software, providing a foundation for subsequent layout optimization, routing and other work.

[0098] Specifically, in the second design software (Allegro), it was confirmed that the second netlist data had been imported without any errors, and that the printed circuit board package library path was configured correctly (the component package identifier in the netlist could match the actual package file in the library).

[0099] Then, in the Allegro menu bar, select "Place" → "Quickplace". The software will automatically read the "component information (such as reference designator and package identifier)" and "connection logic (such as which component pins are connected)" from the second netlist data, call the corresponding package from the printed circuit board package library and place it into the PCB design interface. At the same time, the electrical connection relationship between components will be displayed in the form of "flying wires" (temporary connections) to form the initial PCB circuit diagram.

[0100] Finally, based on the PCB design requirements, set basic parameters (such as PCB board size, number of layers, board edge shape, etc.) in the generated initial drawing. The software will then adjust the component placement area based on these parameters to ensure that the initial circuit diagram meets actual production requirements.

[0101] The above method extracts netlist data from the first design software and converts it to a format compatible with the second design software. This avoids the repetitive work of manually redrawing schematics or inputting electrical connection relationships due to software differences, reducing manual input errors. Simultaneously, the netlist data directly relates to the logical relationships of electrical components, ensuring the consistency of design logic during cross-software conversion. This allows engineers to focus on core design aspects such as circuit board layout and routing without spending extra time on format adaptation and data verification, thus shortening the overall design cycle and improving work efficiency.

[0102] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0103] Corresponding to the cross-design software netlist data collaborative processing method, apparatus, and storage medium method in the above embodiments, Figure 7 This is a structural block diagram of the cross-design software netlist data collaborative processing device provided in the embodiments of this application. For ease of explanation, only the parts related to the embodiments of this application are shown.

[0104] Reference Figure 7 The cross-design software netlist data collaborative processing device includes: The data acquisition module 71 is used to acquire first netlist data; wherein, the first netlist data is used to characterize the logical connection relationship between multiple electrical components in the first schematic diagram; wherein, the first schematic diagram is a schematic diagram constructed based on the first design software; The format conversion module 72 is used to convert the data format of the first netlist data to obtain the second netlist data. The netlist import module 73 is used to import the second netlist data into the second design software; wherein the second design software is different from the first design software.

[0105] The circuit diagram generation module 74 is used to generate a circuit diagram corresponding to the printed circuit board based on the second netlist data and the second design software.

[0106] Optionally, the format conversion module 72 is also used for: Obtain the design version corresponding to the data in the first netlist; Match the format conversion tool according to the design version; The first netlist data is converted using the format conversion tool to obtain the second netlist data.

[0107] The optional netlist import module 73 is also used for: After importing the second netlist data into the second design software, determine whether there are any error messages; If an error message is found, the second netlist data is corrected to obtain the corrected third netlist data; Import the third netlist data into the second design software.

[0108] The optional netlist import module 73 is also used for: If the error message indicates that there is incorrect format data in the second netlist data, then determine the data type corresponding to the incorrect format data; If the data type indicates that the netlist name of the second netlist data has a format error, then the netlist name of the second netlist data is modified to obtain the third netlist data; If the data type indicates that the second netlist data contains unrecognized symbolic data, then the unrecognized symbolic data is deleted to obtain the third netlist data.

[0109] The optional netlist import module 73 is also used for: If the error message indicates that there is an incorrect package identifier in the second netlist data, then the incorrect package identifier is replaced with the first package identifier corresponding to the third electrical component to obtain the third netlist data; wherein, the third electrical component is the electrical component corresponding to the incorrect package identifier in the schematic package library.

[0110] The optional netlist import module 73 is also used for: The third netlist data is re-imported into the second design software, and the existence of the error message is re-determined. If the error message exists, continue to correct the error message until the corrected fourth netlist data is correctly imported into the second design software.

[0111] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0112] in addition, Figure 7 The cross-design software netlist data collaborative processing device shown can be a software unit, hardware unit, or a combination of software and hardware built into existing terminal devices. It can also be integrated into terminal devices as an independent component or exist as an independent terminal device.

[0113] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0114] Figure 8 This is a schematic diagram of the structure of the terminal device provided in the embodiments of this application. For example... Figure 8 As shown, the terminal device 8 of this embodiment includes: at least one processor 80 ( Figure 8 (Only one is shown in the diagram) a processor, a memory 81, and a computer program 82 stored in the memory 81 and executable on at least one processor 80. When the processor 80 executes the computer program 82, it implements the steps in the embodiments of the above-described cross-design software netlist data collaborative processing methods.

[0115] The terminal device can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. This terminal device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that... Figure 8 This is merely an example of terminal device 8 and does not constitute a limitation on terminal device 8. It may include more or fewer components than shown in the figure, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0116] The processor 80 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0117] In some embodiments, memory 81 may be an internal storage unit of the terminal device 8, such as a hard disk or memory of the terminal device 8. In other embodiments, memory 81 may be an external storage device of the terminal device 8, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the terminal device 8. Furthermore, memory 81 may include both internal storage units and external storage devices of the terminal device 8. Memory 81 is used to store operating systems, applications, boot loaders, data, and other programs, such as program code of computer programs. Memory 81 can also be used to temporarily store data that has been output or will be output.

[0118] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps in the above-described method embodiments.

[0119] This application provides a computer program product that, when run on a terminal device, enables the terminal device to implement the steps described in the various method embodiments above.

[0120] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. A computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0121] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0122] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0123] In the embodiments provided in this application, it should be understood that the disclosed apparatus / terminal devices and methods can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0124] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0125] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for collaborative processing of netlist data across design software, characterized in that, The method includes: Obtain first netlist data; wherein, the first netlist data is used to characterize the logical connection relationship between multiple electrical components in the first schematic diagram and the package library information corresponding to the multiple electrical components; wherein, the first schematic diagram is a schematic diagram constructed based on the first design software; The data format of the first netlist data is converted to obtain the second netlist data; Import the second netlist data into the second design software; wherein the second design software is different from the first design software; The circuit diagram corresponding to the printed circuit board is generated based on the second netlist data and the second design software.

2. The cross-design software netlist data collaborative processing method as described in claim 1, characterized in that, Before acquiring the first netlist data, the method includes: Create a schematic package library corresponding to the first design software; wherein, the schematic package library contains multiple first electrical components and a first package identifier corresponding to each first electrical component and a first pin information corresponding to each first electrical component; Create a printed circuit board package library corresponding to the second design software; wherein the printed circuit board package library includes multiple second electrical components and a second package identifier corresponding to each second electrical component and a second pin information corresponding to each second electrical component; wherein the multiple first electrical components in the schematic package library correspond one-to-one with the multiple second electrical components in the printed circuit board package library, the first package identifier of each first electrical component is the same as the second package identifier of the corresponding second electrical component, and the first pin information of each first electrical component is the same as the second pin information of the corresponding second electrical component.

3. The cross-design software netlist data collaborative processing method as described in claim 2, characterized in that, The step of converting the data format of the first netlist data to obtain the second netlist data includes: Obtain the design version corresponding to the data in the first netlist; Match the format conversion tool according to the design version; The first netlist data is converted using the format conversion tool to obtain the second netlist data.

4. The cross-design software netlist data collaborative processing method as described in claim 3, characterized in that, The method further includes: After importing the second netlist data into the second design software, determine whether there are any error messages; If an error message is found, the second netlist data is corrected to obtain the corrected third netlist data; Import the third netlist data into the second design software.

5. The cross-design software netlist data collaborative processing method as described in claim 4, characterized in that, The step of correcting the second netlist data to obtain the corrected third netlist data includes: If the error message indicates that there is incorrect format data in the second netlist data, then determine the data type corresponding to the incorrect format data; If the data type indicates that the netlist name of the second netlist data has a format error, then the netlist name of the second netlist data is modified to obtain the third netlist data; If the data type indicates that the second netlist data contains unrecognized symbolic data, then the unrecognized symbolic data is deleted to obtain the third netlist data.

6. The cross-design software netlist data collaborative processing method as described in claim 5, characterized in that, The method further includes: If the error message indicates that there is a package identifier error in the second netlist data, then the schematic package library of the first design software is compared with the printed circuit board package library corresponding to the second design software to obtain the comparison result; If the comparison result indicates that there is no corresponding information between the schematic package library and the printed circuit board package library, then the schematic package library and the printed circuit board package library are modified respectively, so that the multiple electrical components in the modified schematic package library correspond one-to-one with the multiple electrical components in the printed circuit board package library, the package identifier of each electrical component in the schematic package library is the same as the package identifier of the corresponding electrical component in the printed circuit board package library, and the pin information of each electrical component in the schematic package library is the same as the pin information of the corresponding electrical component in the printed circuit board package library. The first netlist data is reformatted to obtain the converted fourth netlist data.

7. The cross-design software netlist data collaborative processing method as described in claim 6, characterized in that, The method further includes: Re-import the third netlist data or the fourth netlist data into the second design software, and re-determine whether the error message exists; If the error message exists, continue to correct the error message until the corrected fifth netlist data is correctly imported into the second design software.

8. A cross-design software netlist data collaborative processing device, characterized in that, include: The data acquisition module is used to acquire first netlist data; wherein, the first netlist data is used to characterize the logical connection relationship between multiple electrical components in the first schematic diagram and the package library information corresponding to the multiple electrical components; wherein, the first schematic diagram is a schematic diagram constructed based on the first design software; The format conversion module is used to convert the data format of the first netlist data to obtain the second netlist data. The netlist import module is used to import the second netlist data into the second design software; wherein the second design software is different from the first design software. The circuit diagram generation module is used to generate the circuit diagram corresponding to the printed circuit board based on the second netlist data and the second design software.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7.

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