PCB component layout method, device and equipment based on multi-modal large model

Abstract

The application discloses a PCB component layout method, device and equipment based on a multi-modal large model, relates to the technical field of electronic design automation, and comprises the following steps: performing quality screening on a plurality of laid-out PCB design files to obtain a qualified design file set; based on the qualified design file set, a serialized training sample set is constructed; each training sample sequence comprises a plurality of training samples arranged in a layout logic sequence; each training sample comprises multi-modal data representing a current layout state and real position coordinates of a next component to be laid out; based on the serialized training sample set, an open-source multi-modal large model is trained to obtain a PCB component layout model; and based on a netlist file of a target PCB and the PCB component layout model, a layout file of the target PCB is iteratively generated. The PCB component layout model trained based on laid-out data has strong generalization ability and low cost, and can realize rapid component layout of a new PCB.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, specifically to a PCB component placement method, apparatus, and equipment based on a multimodal large model. Background Technology

[0002] As electronic devices evolve towards higher density and higher performance, the complexity of printed circuit board (PCB) layout design has increased dramatically. Traditional, purely manual layout methods relying on engineers' experience are inefficient and inconsistent, making them unsuitable for the rapidly iterating market demands. Therefore, the industry has proposed various PCB component placement methods aimed at reducing manual intervention and improving design consistency. These methods can be mainly categorized as follows:

[0003] 1. Functional template matching method: This method involves pre-building a functional module template library, matching the functional modules of the circuit to be laid out with the templates, and reusing the layout rules of known modules. However, this method heavily relies on the completeness of the prior knowledge base. For novel, undefined circuit modules, the system will fail or require a lot of manual intervention, resulting in poor generalization ability.

[0004] 2. Optimized layout and routing methods combining multiple algorithms and thermal analysis: The layout problem is typically modeled as a multi-objective optimization problem, and algorithms such as particle swarm optimization are combined with physical tools such as thermal analysis and electromagnetic compatibility simulation for iterative solution and verification. However, the optimization algorithms themselves converge slowly, and coupled with computationally intensive fluid dynamics or electromagnetic field simulations, each layout evaluation is time-consuming, resulting in extremely high computational costs and insufficient practicality.

[0005] 3. Knowledge Graph-Based and Multi-Objective Optimization Approach: This approach constructs a knowledge graph encompassing component attributes and design rules, and integrates multiple optimization engines to handle the dual-objective optimization of layout and routing. However, the construction and maintenance of the knowledge graph are extremely costly, requiring large-scale, high-quality structured data as support, making data preparation a massive undertaking.

[0006] Therefore, existing PCB component placement methods generally suffer from inherent defects such as poor generalization ability, low computational efficiency, and insufficient practicality due to system complexity and high cost. They cannot achieve efficient, intelligent, and widely adaptable automatic placement while ensuring high-quality design. Summary of the Invention

[0007] The technical problem to be solved by the present invention is that existing PCB component placement methods have problems such as poor generalization ability, low computational efficiency, complex algorithms and high cost. The purpose is to provide a PCB component placement method, device and equipment based on a multimodal large model, which solves the above problems.

[0008] This invention is achieved through the following technical solution:

[0009] In a first aspect, the present invention provides a PCB component layout method based on a multimodal large model, comprising:

[0010] The quality of multiple laid-out PCB design files is screened to obtain a set of qualified design files; each design file includes a netlist file and a layout file;

[0011] Based on the qualified design file set, a serialized training sample set is constructed; wherein, the serialized training sample set contains multiple training sample sequences; each training sample sequence corresponds to a design file and contains multiple training samples arranged in layout logical order; each training sample includes multimodal data representing the current layout state and the actual position coordinates of the next component to be placed; the multimodal data includes a layout state image generated based on the placed components and descriptive text of the placed components;

[0012] Based on the serialized training sample set, the open-source multimodal large model is trained to obtain a PCB component layout model.

[0013] Based on the netlist file and design constraint information of the target PCB, the layout is initialized and multimodal data of the current layout state is generated.

[0014] The multimodal data of the current layout state is input into the PCB component layout model, the predicted position coordinates of the next component to be placed are output, and the current layout state and the corresponding multimodal data are updated according to the predicted position coordinates until all components in the netlist file of the target PCB are placed, and the layout file of the target PCB is generated.

[0015] Optionally, the step of quality screening of multiple laid-out PCB design files to obtain a set of qualified design files includes:

[0016] Convert the layout files of the multiple PCB design files into corresponding layout images;

[0017] Image processing technology is used to analyze the layout image, and design files in which there is no component overlap and all components do not exceed the circuit board boundary are selected to form the qualified design file set.

[0018] Optionally, constructing a serialized training sample set based on the qualified design document set includes:

[0019] For each design file in the qualified design file set, perform the following steps:

[0020] Based on the netlist file and layout file of each design file, a layout order list is determined for each design file; the layout order list is used to indicate the layout order of all components in the corresponding design file.

[0021] According to the layout order list, the placement process of all components is simulated iteratively; in each iteration, the multimodal data is generated based on the currently placed components, and the real position coordinates of the next component to be placed in the layout order list are used as supervision labels to form a training sample.

[0022] The process continues until all components in each design file have been simulated and placed, thus obtaining the training sample sequence corresponding to each design file.

[0023] Optionally, determining the layout order list for each design file based on the netlist file and layout file of each design file includes:

[0024] From the netlist file of each design file, the electrical connection relationship between each component, the total number of pins of each component, and the number of pins involved in the connection are parsed and obtained.

[0025] From the layout file of each design file, parse and obtain the actual position coordinates and physical area of ​​each component;

[0026] The priority score of each component is obtained based on its physical area, total number of pins, and number of pins involved in connection.

[0027] Based on the priority scores of all components in each design file and the electrical connection relationships, a layout order list for each design file is determined.

[0028] Optionally, the step of parsing and obtaining the electrical connection relationships between the components includes:

[0029] Extract all component pins as nodes from each electrical network in the netlist file;

[0030] Based on the location information of the nodes, a complete graph of the corresponding electrical network is constructed;

[0031] The minimum spanning tree algorithm is used to process the complete graph of each electrical network to obtain the minimum set of pin pairs corresponding to each electrical network;

[0032] Based on the minimum set of pin pairs corresponding to all electrical networks, the electrical connection relationships between each component are determined.

[0033] Optionally, the priority score for each component, based on its physical area, total number of pins, and number of pins involved in the connection, includes:

[0034] The physical area, total number of pins, and number of pins involved in connection of each component are normalized to obtain the corresponding normalized physical area, normalized total number of pins, and normalized number of pins involved in connection.

[0035] The normalized physical area, the normalized total number of pins, and the normalized number of pins involved in connection are weighted and summed to obtain the priority score of each component; wherein, the weight of the normalized physical area is greater than the weight of the normalized number of pins involved in connection; and the weight of the normalized number of pins involved in connection is greater than the weight of the normalized total number of pins.

[0036] Optionally, the step of determining the layout order list for each design file based on the priority scores of all components in each design file and the electrical connection relationships includes:

[0037] Sort all components in each design file from highest to lowest according to their priority scores to form an initial placement queue;

[0038] All components in each design file are placed into the current set of components to be laid out. The component with the highest priority score is selected from the current set of components to be laid out and added to the layout order list as the current core component.

[0039] Based on the electrical connection relationship, identify all components that are connected to the current core component and are not added to the layout order list to form an association group;

[0040] The components in the associated group are sorted from high to low according to their priority scores and added to the layout order list in sequence. The components that have been added to the layout order list are removed from the current set of components to be laid out until the current set of components to be laid out is empty, thus obtaining the final layout order list.

[0041] Optionally, the step of training an open-source multimodal large model based on the serialized training sample set to obtain a PCB component layout model includes:

[0042] Based on the aforementioned serialized training sample set, low-rank adaptation technology is used to fine-tune the parameters of the open-source multimodal large model to obtain the basic layout model.

[0043] Data augmentation is performed on the serialized training sample set to construct preference data pairs;

[0044] Based on the aforementioned preference data pairs, the basic layout model is trained using a direct preference optimization method to obtain a PCB component layout model.

[0045] Secondly, the present invention provides a PCB component placement device based on a multimodal large model, comprising:

[0046] The filtering module is used to perform quality screening on multiple laid-out PCB design files to obtain a set of qualified design files; each design file includes a netlist file and a layout file;

[0047] A construction module is used to construct a serialized training sample set based on the qualified design file set; wherein the serialized training sample set contains multiple training sample sequences; each training sample sequence corresponds to a design file and contains multiple training samples arranged in a layout logical order; each training sample includes multimodal data representing the current layout state and the actual position coordinates of the next component to be placed; the multimodal data includes a layout state image generated based on the placed components and descriptive text of the placed components;

[0048] The training module is used to train the open-source multimodal large model based on the serialized training sample set to obtain the PCB component layout model.

[0049] The initialization module is used to initialize the layout based on the netlist file and design constraint information of the target PCB, and generate multimodal data of the current layout state.

[0050] The generation module is used to input the multimodal data of the current layout state into the PCB component layout model, output the predicted position coordinates of the next component to be placed, and update the current layout state and the corresponding multimodal data according to the predicted position coordinates, until all components in the netlist file of the target PCB are placed, and generate the layout file of the target PCB.

[0051] Thirdly, the present invention provides a computer device, the computer device including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement a PCB component layout method based on a multimodal large model as described in any one of the first aspects.

[0052] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, wherein a processor executes the computer program to implement a PCB component layout method based on a multimodal large model as described in any one of the first aspects.

[0053] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0054] This application provides a PCB component placement method based on a multimodal large model. By constructing sequential samples of "current state - next action," the model's learning process simulates the actual component placement process of human engineers. Employing a multimodal large model as its core architecture, the model implicitly learns general layout rules and spatial relationship reasoning capabilities from massive and diverse historical layout data, rather than relying on preset, fixed functional templates or manually constructed knowledge graphs. This allows the model to generate reasonable and feasible layout schemes even when encountering new components, non-standard functional modules, or circuit topologies not explicitly present in the training set, thanks to its powerful representation learning and transfer learning capabilities. This effectively solves the problem of insufficient generalization ability of traditional methods for new designs. In practical applications, the PCB component placement model's decision for each component's placement is a forward propagation process, avoiding the thousands of iterative calculations and time-consuming simulations (such as thermal analysis and EM simulation) required by traditional optimization algorithms. This achieves near real-time layout generation, significantly shortening the design cycle, and offering high computational efficiency and strong practicality. Attached Figure Description

[0055] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0056] Figure 1 A flowchart illustrating the PCB component placement method based on a multimodal large model provided in this application embodiment;

[0057] Figure 2 A schematic diagram of a layout image provided for an embodiment of this application;

[0058] Figure 3 This is a schematic diagram of the layout state after placing the components in step t, as provided in an embodiment of this application.

[0059] Figure 4 A schematic diagram of the layout state after placing the components in step t+1, as provided in an embodiment of this application;

[0060] Figure 5 A schematic diagram of the minimum spanning tree provided in an embodiment of this application;

[0061] Figure 6 A schematic diagram of the data enhancement process provided for embodiments of this application;

[0062] Figure 7This is a schematic diagram of the PCB component placement device based on a multimodal large model provided in an embodiment of this application. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0064] To address the problems of poor generalization ability, low computational efficiency, complex algorithms, and high cost in existing PCB component placement methods, this application provides a PCB component placement method based on a multimodal large model. Please refer to... Figure 1 This is a flowchart illustrating a PCB component placement method based on a multimodal large model provided in this application embodiment. The following is a further explanation. Figure 1 The PCB component layout method based on a multimodal large model is introduced.

[0065] S1. Perform quality screening on multiple PCB design files that have been laid out to obtain a set of qualified design files.

[0066] In the specific implementation process, multiple PCB design files with detailed layouts are obtained from the company's internal historical project library or publicly available PCB design datasets. Each design file includes the following:

[0067] (1) Netlist file: Used to describe the logical connection relationship of the circuit. It defines a list of all components (such as resistors, capacitors, integrated circuits) in the circuit, and how the pins of these components are connected to each other to form various electrical networks.

[0068] (2) Layout file: A file used to describe the physical implementation information of the circuit. It records the precise position coordinates, placement angle, and board layer of each component on the PCB board, as well as the outline dimensions and package information such as the keep-out area of ​​the PCB board itself.

[0069] Since original design files may contain incorrect layouts, non-compliant designs, or inconsistent formatting, direct use can lead to the model learning undesirable patterns. Therefore, automated quality screening of original design files is necessary to build a set of qualified design files.

[0070] In one possible embodiment, the layout files of multiple PCB design files are converted into corresponding layout images; image processing technology is used to analyze the layout images, and design files in which there is no component overlap and all components do not exceed the circuit board boundary are selected to form a qualified design file set.

[0071] In the actual implementation process, for each design file, the geometric information recorded in its layout file is extracted. A dedicated drawing module is then used to convert the abstract coordinate data into a visual layout image.

[0072] Please refer to Figure 2 This is a schematic diagram of a layout image provided in an embodiment of this application. In order to clearly distinguish different design elements, the outer contour of the PCB board is drawn with closed polygons, and the shape of each component is represented by a solid quadrilateral. Different colors can be used to fill the quadrilaterals to distinguish the board layers where the components are located. For example, blue is used to represent the top layer components, and yellow is used to represent the bottom layer components.

[0073] After obtaining the layout images, image processing techniques (such as OpenCV) are used to analyze each layout image to detect whether two components overlap or whether any components extend beyond the circuit board boundary. If two components overlap or a component extends beyond the circuit board boundary in a given layout image, the corresponding design file does not meet quality requirements and is deleted. If no two components overlap or all components do not extend beyond the circuit board boundary in a given layout image, the corresponding design file meets quality requirements and is retained. All retained design files constitute the set of qualified design files.

[0074] In this embodiment, by converting design files into images and using mature image processing algorithms for geometric analysis, massive amounts of design files can be batch-wise and objectively inspected at millisecond levels, accurately identifying and removing "dirty data" containing fundamental physical errors. This ensures that every data sample input into subsequent model training conforms to basic physical manufacturability rules, eliminating the possibility of the model learning incorrect layout patterns from the source.

[0075] S2. Construct a serialized training sample set based on the qualified design file set.

[0076] The serialized training sample set contains multiple training sample sequences; each training sample sequence corresponds to a design file and contains multiple training samples arranged in a logical layout order. Each training sample includes multimodal data representing the current layout state and the actual position coordinates of the next component to be placed. The multimodal data integrates visual and textual information to comprehensively describe the layout state, specifically including:

[0077] (1) Layout status image: This is an image generated immediately after each simulation of placing a component. It shows the physical distribution, shape, and board layer of all currently placed components on the PCB, and clearly indicates their electrical connection relationship through visual coding (such as specific colors, highlights, or connecting lines).

[0078] (2) Description text of placed components: This is a structured description text that lists all currently placed components and records the unique identifier (such as R1, U5, etc.), component type (such as 0805 resistor, SOIC-8 op-amp, etc.) and actual location coordinates of each component.

[0079] For example:

[0080]

[0081] in, This represents the i-th training sample. This represents the image data (i.e., the layout state image) of the i-th training sample. This represents the text data (i.e., the description text of the placed components) in the i-th training sample. This represents the label data in the i-th training sample (i.e., the actual position coordinates of the next component to be laid out).

[0082] In one possible embodiment, for each design file in the qualified design file set, the following steps are performed to generate a training sample sequence corresponding to each design file:

[0083] Based on the netlist and layout files of each design file, a layout order list for all components in each design file is determined. The layout order list indicates the layout order of all components in the corresponding design file. The placement process of all components is iteratively simulated according to the layout order list. In each iteration, multimodal data is generated based on the currently placed components, and the real position coordinates of the next component to be placed in the layout order list are used as supervision labels to form a training sample. This process continues until all components in each design file have been simulated and placed, obtaining the training sample sequence corresponding to each design file.

[0084] In the specific implementation process, for the layout file in each qualified design file, the original placement coordinates of all components are extracted. The original placement coordinates are then globally scaled based on a preset target image scale, so that all layout data are uniformly transformed into the same standard image coordinate space. For example, the maximum value of the original coordinate range is mapped to the maximum value of the target image size (such as scaling the original maximum of 10,000 units to the maximum of 2,000 pixels in the target image).

[0085] For each qualified design document, perform the following iterative process:

[0086] S11. Based on the scaled coordinates and layout order list of the layout file, start the simulation on an empty circuit board image.

[0087] S12. According to the layout order list, each time a component to be laid out is taken from the list, it is recorded as a simulation step.

[0088] S13. In each step, place the component to be laid out onto the simulated circuit board image with its scaled real position coordinates.

[0089] S14. After placement, generate multimodal data of the current layout state.

[0090] S15. Combine the multimodal data of the current layout state with the scaled real position coordinates of the next component to be laid out in the layout order list to form a training sample.

[0091] S16. Repeat steps S12 to S15 until all components in the design file have been simulated and placed. Thus, for a design file containing N components, a training sample sequence containing N samples arranged in time step order will be generated.

[0092] For example, the layout state image after placing the components in step t is as follows: Figure 3 As shown, the layout state image after placing the components in step t+1 is as follows: Figure 4 As shown.

[0093] In this embodiment, by simulating the actual workflow of a human designer "building from scratch and placing items step by step," the generated sequential training sample set is of high quality and self-interpretability. The label (position coordinates) of each sample is directly derived from the already laid-out PCB, ensuring the correctness of the learning objective. The state of each decision point contains all the layout information (image + text) up to the current point, providing the model with all the context needed to make a reasonable judgment. The "step-by-step decision-making" data structure is consistent with the actual human layout process, enhancing the interpretability of the model's behavior.

[0094] In one possible embodiment, based on the netlist file and layout file of each design file, a layout order list for each design file is determined, including:

[0095] From the netlist file of each design file, the electrical connection relationships between each component, the total number of pins of each component, and the number of pins involved in the connection are parsed and obtained; from the layout file of each design file, the actual position coordinates and physical area of ​​each component are parsed and obtained; based on the physical area, total number of pins, and number of pins involved in the connection of each component, the priority score of all components is obtained; based on the priority score and electrical connection relationships of all components in each design file, the layout order list of each design file is determined.

[0096] In the implementation process, each design file includes a netlist file and a layout file. The electrical connection relationships are obtained by parsing the netlist file. These electrical connections refer to the set of logical conductive paths established between the pins of different components on the PCB to achieve a specific circuit function. Simultaneously, the total number of pins for each component is obtained by querying its symbol library or parsing its package definition. By traversing all nets, the number of pins of the component that actually appear in the net declaration (i.e., are connected and used) is counted to determine the number of pins involved in the connection. The actual position coordinates of each component are directly extracted from the layout file. Based on the component package type recorded in the layout file, the corresponding package graphic library is queried to obtain its external dimensions, and the physical area of ​​each component is calculated accordingly.

[0097] In this embodiment, three types of heterogeneous information—physical (area), topological (connectivity), and functional (pin count)—are integrated for comprehensive decision-making. This multi-feature fusion mechanism enables the system to cope with various complex circuit types, whether it is a digital main control board, an analog RF module, or a mixed-signal circuit, and can generate layout logic that is compatible with it, demonstrating extremely strong generalization ability and robustness.

[0098] In one possible embodiment, parsing and obtaining the electrical connection relationships between the components includes:

[0099] From each electrical network in the netlist file, extract the pins of all components as nodes; construct a complete graph of the corresponding electrical network based on the node location information; process the complete graph of each electrical network using the minimum spanning tree algorithm to obtain the minimum set of pin pairs corresponding to each electrical network; determine the electrical connection relationships between each component based on the minimum set of pin pairs corresponding to all electrical networks.

[0100] In the specific implementation process, for each electrical network in the netlist file, the pins of all components in that network are extracted, and each pin is treated as a graph node. A complete graph is constructed based on these nodes. Each edge in the complete graph is assigned a weight, which is typically defined as the logical distance or expected routing length between two pin nodes. If no geometric information is available, the weight can be uniformly set to 1. For the constructed weighted complete graph, the minimum spanning tree algorithm is run. The goal of this algorithm is to find a tree that connects all nodes and minimizes the sum of all edge weights. For example... Figure 5 As shown, the edges contained in this minimum spanning tree constitute the set of minimum pin pairs representing the simplest and most economical connection scheme for this electrical network. After traversing all electrical networks in the netlist file, the sets of minimum pin pairs obtained from all electrical networks are merged to obtain the electrical connection relationships of the PCB corresponding to the netlist file.

[0101] In this embodiment, key electrical connection relationships are extracted based on the minimum spanning tree algorithm, which realizes automated denoising and feature enhancement of the original connection data, discards redundant and secondary connections, and retains those critical paths that play a decisive role in the network topology. The minimum pin pair set extracted thereby is a higher density and higher quality representation of connection relationships.

[0102] In one possible embodiment, a priority score for each component is obtained based on its physical area, total number of pins, and number of pins involved in connection, including:

[0103] The physical area, total number of pins, and number of pins involved in connection of each component are normalized to obtain the corresponding normalized physical area, normalized total number of pins, and normalized number of pins involved in connection. The normalized physical area, normalized total number of pins, and normalized number of pins involved in connection are then weighted and summed to obtain the priority score of each component. Among them, the weight of normalized physical area is greater than the weight of normalized number of pins involved in connection, and the weight of normalized number of pins involved in connection is greater than the weight of normalized total number of pins.

[0104] In practice, the normalization method can be the maximum-minimum normalization method. The formula for calculating the priority score is as follows:

[0105]

[0106] in, Let i be the priority score of the i-th component; Let be the normalized physical area of ​​the i-th component; This represents the normalized number of connection pins for the i-th component. This represents the normalized total number of pins for the i-th component. They are respectively , , The weight, ,and .

[0107] Engineers can flexibly adjust according to different product types (such as high-density digital boards, high-power analog boards) or design preferences. This guides the model to generate different layout schemes (such as more compact or more heat dissipation-focused).

[0108] As a preferred embodiment, .

[0109] In this embodiment of the application, normalization eliminates the dimensional interference of the data itself, and a carefully designed weighting model is used ( The core layout principles are encoded into executable mathematical rules. This transforms the abstract importance of the layout into an objective, computable priority score, providing a reliable and consistent basis for decision-making in the subsequent automated generation of layout sequences.

[0110] In one possible embodiment, a layout order list for each design file is determined based on the priority scores and electrical connections of all components, including:

[0111] Sort all components in each design file according to their priority scores from highest to lowest to form an initial placement queue. Place all components in each design file into the current set of components to be laid out. Select the component with the highest priority score from the current set of components to be laid out as the current core component and add it to the layout order list. Based on electrical connections, find all components connected to the current core component that are not added to the layout order list to form an association group. Sort the components in the association group according to their priority scores from highest to lowest and add them to the layout order list in sequence. Remove the components that have been added to the layout order list from the current set of components to be laid out until the current set of components to be laid out is empty, and obtain the final layout order list.

[0112] In the specific implementation process, firstly, all components in each design file are sorted from high to low according to their priority scores to form a global initial placement queue, which reflects the global importance ranking of the components.

[0113] Next, create a collection of components to be laid out and put all the components into it.

[0114] Then, repeat the following steps until all components have been arranged:

[0115] S2.1 Select the component with the highest priority score from the current set of components to be laid out, mark it as the current core component, and move it from the current set of components to be laid out to the end of the layout order list.

[0116] S2.2 Based on electrical connection relationships, identify all components that have direct electrical connections with the current core components and have not yet been added to the layout order list, and form an association group for these components.

[0117] S2.3 Sort the components in the associated component group according to their priority scores from highest to lowest. Then, add this sorted subsequence to the end of the final layout order list.

[0118] S2.4 Remove all newly added components (i.e., the current core components and their associated groups) from the current set of components to be laid out in this iteration.

[0119] Repeat steps S2.1-S2.4 until the current set of components to be laid out becomes empty. At this point, the system has obtained a reasonable layout order for all components in a PCB design file, which is the final layout order list.

[0120] In this embodiment, an initial placement queue ensures that highly important components are prioritized. Components closely related to the core components are "attracted" together through electrical connections, forming sequential layout modules. This effectively simulates the practice of engineers centrally arranging components for a functional module, resulting in a more logically coherent sequence of training samples that better facilitates model learning of modular layout strategies.

[0121] S3. Based on the serialized training sample set, train the open-source multimodal large model to obtain the PCB component layout model.

[0122] In one possible embodiment, based on a serialized training sample set, a low-rank adaptation technique is used to fine-tune the parameters of an open-source multimodal large model to obtain a basic layout model; data augmentation is performed on the serialized training sample set to construct preference data pairs; based on the preference data pairs, a direct preference optimization method is used to perform reinforcement learning training on the basic layout model to obtain a PCB component layout model.

[0123] In the specific implementation process, firstly, the Qwen2.5-VL-7B open-source model was selected as the multimodal large model. Fine-tuning all parameters of the Qwen2.5-VL-7B model is extremely costly; therefore, Low-Rank Adaptation (LoRA) technology was used to fine-tune the parameters of the Qwen2.5-VL-7B model, keeping all original parameters unchanged. Trainable, low-rank adapter matrices were injected into key modules such as the model's attention mechanism. The parameter size of these adapter matrices is much smaller than that of the original model, allowing the fine-tuning process to optimize only a very small number of parameters (usually less than 1% of the original model) to obtain the basic layout model.

[0124] Secondly, the sequential training sample set is augmented to construct preference data pairs for reinforcement learning. Each preference data pair consists of a preferred sample (representing a better layout choice) and a rejection sample (representing a suboptimal layout choice).

[0125] Then, using the basic layout model as a reference model and freezing all parameters of the reference model, the basic layout model is copied to construct the PCB component layout model to be optimized. All parameters of the PCB component layout model to be optimized are trainable. The reference model and the PCB component layout model to be optimized have the same network architecture and initial parameters.

[0126] Finally, based on the prediction errors of the reference model and the PCB component layout model to be optimized, an optimization loss function is defined. This loss function is minimized using gradient descent based on the preference data pairs. The parameters of the PCB component layout model to be optimized are then updated while keeping the parameters of the reference model unchanged. Training stops when any convergence condition is met, yielding the optimized PCB component layout model.

[0127] Convergence conditions include, for example, the evaluation metric on the validation set reaching a preset threshold, the direct preference optimization loss function changing less than a preset tolerance over multiple consecutive training epochs, and reaching a preset maximum number of training epochs. The evaluation metric is the predicted position coordinates of the target components output by the PCB component layout model. with actual location coordinates The deviation between them. A pixel tolerance threshold is set, such as Δ=30. When the deviation of the coordinates in both dimensions is simultaneously less than the preset error, the model prediction is considered correct.

[0128]

[0129]

[0130] Experiments show that after adopting a two-stage training method (parameter fine-tuning and reinforcement learning), the layout accuracy of the PCB component layout model on the test set is significantly improved from 39.83% in the fine-tuning stage to 80.58%, verifying the effectiveness of the direct preference optimization method for layout quality optimization.

[0131] In this embodiment, LoRA technology requires optimization of only a few adapter parameters, significantly reducing computational resource consumption, training time, and storage overhead, thus solving the problems of high training costs and difficulty in deployment for large models. The DPO inverse method directly utilizes static preference data for offline optimization, resulting in a more stable and faster convergence process, without requiring an additional reward model, significantly reducing the complexity and computational cost of the reinforcement learning phase. Furthermore, by learning from preference data pairs, the model can distinguish subtle quality differences, enabling it to make reasonable inferences even when faced with component types or circuit structures not present in the training set, thereby improving its generalization ability to meet new design challenges.

[0132] Please refer to Figure 6 This is a schematic diagram of the data enhancement process provided in an embodiment of this application. The following is in conjunction with... Figure 6 Introduce the data augmentation process.

[0133] S3.1 Obtain the serialized training sample set as the original dataset, where each training sample contains multimodal data of the layout state and the coordinates of the labeled position of the target component.

[0134] S3.2. For each training sample in the original dataset, perform the following operations:

[0135] Perform N independent boosting attempts on the current training sample, where N is an integer greater than 1;

[0136] In each enhancement attempt, the following two perturbation strategies are executed in parallel:

[0137] First strategy: Apply destructive disturbance to the target component. The destructive disturbance includes randomly translating it from the marked position coordinates beyond a first preset distance threshold, or moving it to a position that overlaps with the components already placed in the current layout.

[0138] The second strategy is to apply an optimization perturbation to the target component. The optimization perturbation includes randomly assigning a new position coordinate to it within a range not exceeding the second preset distance threshold, and the new position coordinate does not overlap with any component already placed in the current layout state.

[0139] S3.3. Generate new samples based on the perturbation results:

[0140] If the first strategy is successfully applied, a sample is generated and marked as a rejection sample based on the layout state after the destructive disturbance is applied and the new component position coordinates.

[0141] If the second strategy is successfully applied, a sample is generated and marked as a preferred sample based on the layout state after applying the optimization perturbation and the new component position coordinates.

[0142] If the second strategy fails to be applied, the original training samples will be used directly as the preference samples.

[0143] S3.4 Based on the augmentation attempt results of all training samples, construct a set of preference data pairs, where each preference data pair includes a preference sample and a rejection sample.

[0144] For example:

[0145]

[0146] in, This represents the i-th pair of preference data. This represents the label data of the rejection sample in the i-th preference data pair (i.e., the rejection position coordinates of the next component to be laid out). This represents the image data (i.e., the layout state image) of the rejected sample in the i-th preference data pair. This represents the text data (i.e., the description text of the placed components) of the rejected sample in the i-th preference data pair. This represents the label data of the preference sample in the i-th preference data pair; This represents the image data of the preferred sample in the i-th preference data pair. This represents the text data of the preference sample in the i-th preference data pair.

[0147] S4. Based on the netlist file and design constraint information of the target PCB, perform initial layout and generate multimodal data of the current layout state.

[0148] In the specific implementation process, the target PCB refers to the PCB to be laid out. The netlist file of the target PCB is read, and the component list, electrical connections, and package size information contained within are parsed. Design constraint information, such as board boundary dimensions and coordinates of pre-placed components, is read. All pre-placed components are directly placed on the layout canvas according to their specified coordinates and dimensions. The board outline boundaries are drawn on the background layer of the layout canvas with a specific color or line style, thus constructing the initial layout state. The initial layout state is then encoded into multimodal data, including a layout state image generated based on the placed components and descriptive text for the placed components.

[0149] S5. Input the multimodal data of the current layout state into the PCB component layout model, output the predicted position coordinates of the next component to be placed, and update the current layout state and corresponding multimodal data according to the predicted position coordinates until all components in the netlist file of the target PCB are placed, and generate the layout file of the target PCB.

[0150] In the specific implementation process, the following steps shall be performed:

[0151] S5.1 Input the multimodal data of the current layout state into the PCB component layout model and output a predicted position coordinate, which represents the model's recommended placement position for the next component to be laid out.

[0152] S5.2 Place the next component to be placed according to the corresponding predicted position coordinates, thereby updating the current layout state, saving the layout state image of the current layout state (including the next component to be placed), and appending the information of the next component to be placed to the end of the description text, thereby updating the multimodal data.

[0153] S5.3 checks if all components have been placed in the netlist file. If not, it returns to S5.1 to continue execution. If yes, it exits the loop and outputs the layout file of the target PCB.

[0154] In summary, this application also provides a PCB component placement method based on a multimodal large model. This method, centered on a multimodal large model, is entirely data-driven, integrating LoRA for efficient fine-tuning and DPO reinforcement learning to allow the model to gradually learn "component placement rules" and "engineer habits" from the data. It eliminates reliance on other complex steps, pre-set templates, or complex multi-algorithm integration, reducing manual intervention and system complexity. Furthermore, offline perturbation enhancement is introduced to balance data validity and diversity, avoiding overfitting and the over-reliance on high-quality data common in existing methods. Based on this PCB component placement model, rapid component placement on new PCBs can be achieved.

[0155] Based on the same inventive concept, please refer to Figure 7 This application also provides a PCB component placement device based on a multimodal large model, the device comprising:

[0156] The filtering module is used to perform quality screening on multiple laid-out PCB design files to obtain a set of qualified design files; each design file includes a netlist file and a layout file;

[0157] The construction module is used to construct a serialized training sample set based on a qualified design file set. The serialized training sample set contains multiple training sample sequences. Each training sample sequence corresponds to a design file and contains multiple training samples arranged in a layout logical order. Each training sample includes multimodal data representing the current layout state and the actual position coordinates of the next component to be placed. The multimodal data includes a layout state image generated based on the placed components and descriptive text of the placed components.

[0158] The training module is used to train an open-source multimodal large model based on a serialized training sample set to obtain a PCB component layout model.

[0159] The initialization module is used to initialize the layout based on the netlist file and design constraint information of the target PCB, and generate multimodal data of the current layout state.

[0160] The generation module is used to input the multimodal data of the current layout state into the PCB component layout model, output the predicted position coordinates of the next component to be placed, and update the current layout state and the corresponding multimodal data according to the predicted position coordinates, until all components in the netlist file of the target PCB are placed, and generate the layout file of the target PCB.

[0161] Optionally, the filtering module is specifically used for:

[0162] Convert the layout files of multiple PCB design files into corresponding layout images;

[0163] Image processing techniques are used to analyze the layout images, and design files that do not have overlapping components and whose components do not exceed the circuit board boundaries are selected to form a qualified design file set.

[0164] Optionally, the constructor module is specifically used for:

[0165] For each design document in the qualified design document set, perform the following steps:

[0166] Based on the netlist file and layout file of each design file, determine the layout order list for each design file; the layout order list is used to indicate the layout order of all components in the corresponding design file;

[0167] Based on the layout order list, the placement process of all components is simulated iteratively. In each iteration, multimodal data is generated based on the currently placed components, and the real position coordinates of the next component to be placed in the layout order list are used as supervision labels to form a training sample.

[0168] The process continues until all components in each design file have been simulated and placed, thus obtaining the training sample sequence corresponding to each design file.

[0169] Optionally, the constructor module is specifically used for:

[0170] From the netlist file of each design file, the electrical connection relationship between each component, the total number of pins of each component, and the number of pins involved in the connection are parsed and obtained.

[0171] From the layout file of each design file, parse and obtain the actual position coordinates and physical area of ​​each component;

[0172] The priority score of each component is obtained based on its physical area, total number of pins, and number of pins involved in connection.

[0173] Based on the priority scores and electrical connections of all components in each design file, determine the layout order list for each design file.

[0174] Optionally, the constructor module is specifically used for:

[0175] Extract all component pins as nodes from each electrical network in the netlist file;

[0176] Based on the location information of the nodes, construct a complete graph of the corresponding electrical network;

[0177] The minimum spanning tree algorithm is used to process the complete graph of each electrical network to obtain the minimum set of pin pairs corresponding to each electrical network;

[0178] Based on the minimum set of pin pairs corresponding to all electrical networks, the electrical connection relationships between each component are determined.

[0179] Optionally, the constructor module is specifically used for:

[0180] The physical area, total number of pins, and number of pins involved in connection of each component are normalized to obtain the corresponding normalized physical area, normalized total number of pins, and normalized number of pins involved in connection.

[0181] The priority score of each component is obtained by weighted summing of the normalized physical area, the normalized total number of pins, and the normalized number of pins involved in connection; among them, the weight of the normalized physical area is greater than the weight of the normalized number of pins involved in connection; the weight of the normalized number of pins involved in connection is greater than the weight of the normalized total number of pins.

[0182] Optionally, the constructor module is specifically used for:

[0183] Sort all components in each design file according to their priority scores from high to low to form an initial placement queue;

[0184] Place all components in each design file into the current set of components to be laid out, and select the component with the highest priority score from the current set of components to be laid out as the current core component and add it to the layout order list.

[0185] Based on electrical connections, identify all components that are connected to the current core component but are not included in the layout order list to form an association group;

[0186] After sorting the components in the associated group from highest to lowest priority score, add them to the layout order list in sequence. Remove the components that have been added to the layout order list from the current set of components to be laid out, until the current set of components to be laid out is empty, and obtain the final layout order list.

[0187] Optionally, the training module is specifically used for:

[0188] Based on a sequential training sample set, a low-rank adaptation technique is used to fine-tune the parameters of an open-source multimodal large model to obtain a basic layout model.

[0189] Data augmentation is performed on the serialized training sample set to construct preference data pairs;

[0190] Based on preference data pairs, the direct preference optimization method is used to train the basic layout model through reinforcement learning to obtain the PCB component layout model.

[0191] It should be noted that each module in the PCB component layout device based on the multimodal large model in this embodiment corresponds one-to-one with each step in the PCB component layout method based on the multimodal large model in the aforementioned embodiment. Therefore, the specific implementation of this embodiment can refer to the implementation of the PCB component layout method based on the aforementioned multimodal large model, and will not be repeated here.

[0192] Based on the same inventive concept, this application also provides a computer device, which includes a processor, a memory, and a computer program stored in the memory. The computer program is executed by the processor to implement the aforementioned PCB component layout method based on a multimodal large model.

[0193] Based on the same inventive concept, this application also provides a computer storage medium storing a computer program, which is executed by a processor to implement the aforementioned PCB component layout method based on a multimodal large model.

[0194] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a device including one or any combination of the above-mentioned memories. The computer may be a variety of computing devices, including smart terminals and servers.

[0195] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0196] As an example, executable instructions may, but do not necessarily, correspond to files in the file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0197] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0198] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0199] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0200] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A PCB component placement method based on a multimodal large model, characterized in that, include: The quality of multiple laid-out PCB design files is screened to obtain a set of qualified design files; each design file includes a netlist file and a layout file; Based on the qualified design file set, a serialized training sample set is constructed; wherein, the serialized training sample set contains multiple training sample sequences; each training sample sequence corresponds to a design file and contains multiple training samples arranged in layout logical order; each training sample includes multimodal data representing the current layout state and the actual position coordinates of the next component to be placed; the multimodal data includes a layout state image generated based on the placed components and descriptive text of the placed components; Based on the serialized training sample set, the open-source multimodal large model is trained to obtain a PCB component layout model. Based on the netlist file and design constraint information of the target PCB, the layout is initialized and multimodal data of the current layout state is generated. The multimodal data of the current layout state is input into the PCB component layout model, the predicted position coordinates of the next component to be placed are output, and the current layout state and the corresponding multimodal data are updated according to the predicted position coordinates until all components in the netlist file of the target PCB are placed, and the layout file of the target PCB is generated. The construction of a serialized training sample set based on the qualified design document set includes: For each design file in the qualified design file set, perform the following steps: Based on the netlist file and layout file of each design file, a layout order list is determined for each design file; the layout order list is used to indicate the layout order of all components in the corresponding design file. According to the layout order list, the placement process of all components is simulated iteratively; in each iteration, the multimodal data is generated based on the currently placed components, and the real position coordinates of the next component to be placed in the layout order list are used as supervision labels to form a training sample. The process continues until all components in each design file have been simulated and placed, thus obtaining the training sample sequence corresponding to each design file.

2. The PCB component layout method based on a multimodal large model according to claim 1, characterized in that, The process of quality screening of multiple laid-out PCB design files to obtain a set of qualified design files includes: Convert the layout files of the multiple PCB design files into corresponding layout images; Image processing technology is used to analyze the layout image, and design files in which there is no component overlap and all components do not exceed the circuit board boundary are selected to form the qualified design file set.

3. The PCB component layout method based on a multimodal large model according to claim 1, characterized in that, The list of layout order for each design file, determined based on the netlist file and layout file of each design file, includes: From the netlist file of each design file, the electrical connection relationship between each component, the total number of pins of each component, and the number of pins involved in the connection are parsed and obtained. From the layout file of each design file, parse and obtain the actual position coordinates and physical area of ​​each component; The priority score of each component is obtained based on its physical area, total number of pins, and number of pins involved in connection. Based on the priority scores of all components in each design file and the electrical connection relationships, a layout order list for each design file is determined.

4. The PCB component layout method based on a multimodal large model according to claim 3, characterized in that, The process of analyzing and obtaining the electrical connection relationships between various components includes: Extract all component pins as nodes from each electrical network in the netlist file; Based on the location information of the nodes, a complete graph of the corresponding electrical network is constructed; The minimum spanning tree algorithm is used to process the complete graph of each electrical network to obtain the minimum set of pin pairs corresponding to each electrical network; Based on the minimum set of pin pairs corresponding to all electrical networks, the electrical connection relationships between each component are determined.

5. The PCB component layout method based on a multimodal large model according to claim 3, characterized in that, The priority score for each component is obtained based on its physical area, total number of pins, and number of pins involved in the connection, including: The physical area, total number of pins, and number of pins involved in connection of each component are normalized to obtain the corresponding normalized physical area, normalized total number of pins, and normalized number of pins involved in connection. The normalized physical area, the normalized total number of pins, and the normalized number of pins involved in connection are weighted and summed to obtain the priority score of each component; wherein, the weight of the normalized physical area is greater than the weight of the normalized number of pins involved in connection; and the weight of the normalized number of pins involved in connection is greater than the weight of the normalized total number of pins.

6. The PCB component placement method based on a multimodal large model according to claim 3, characterized in that, The layout order list for each design file is determined based on the priority scores of all components in each design file and the electrical connection relationships, including: Sort all components in each design file from highest to lowest according to their priority scores to form an initial placement queue; All components in each design file are placed into the current set of components to be laid out. The component with the highest priority score is selected from the current set of components to be laid out and added to the layout order list as the current core component. Based on the electrical connection relationship, identify all components that are connected to the current core component and are not added to the layout order list to form an association group; The components in the associated group are sorted from high to low according to their priority scores and added to the layout order list in sequence. The components that have been added to the layout order list are removed from the current set of components to be laid out until the current set of components to be laid out is empty, thus obtaining the final layout order list.

7. The PCB component layout method based on a multimodal large model according to claim 1, characterized in that, The step of training an open-source multimodal large model based on the serialized training sample set to obtain a PCB component layout model includes: Based on the aforementioned serialized training sample set, low-rank adaptation technology is used to fine-tune the parameters of the open-source multimodal large model to obtain the basic layout model. Data augmentation is performed on the serialized training sample set to construct preference data pairs; Based on the aforementioned preference data pairs, the basic layout model is trained using a direct preference optimization method to obtain a PCB component layout model.

8. A PCB component placement device based on a multimodal large model, characterized in that, include: The filtering module is used to perform quality screening on multiple laid-out PCB design files to obtain a set of qualified design files; each design file includes a netlist file and a layout file; A construction module is used to construct a serialized training sample set based on the qualified design file set; wherein the serialized training sample set contains multiple training sample sequences; each training sample sequence corresponds to a design file and contains multiple training samples arranged in a layout logical order; each training sample includes multimodal data representing the current layout state and the actual position coordinates of the next component to be placed; the multimodal data includes a layout state image generated based on the placed components and descriptive text of the placed components; The training module is used to train the open-source multimodal large model based on the serialized training sample set to obtain the PCB component layout model. The initialization module is used to initialize the layout based on the netlist file and design constraint information of the target PCB, and generate multimodal data of the current layout state. The generation module is used to input the multimodal data of the current layout state into the PCB component layout model, output the predicted position coordinates of the next component to be placed, and update the current layout state and the corresponding multimodal data according to the predicted position coordinates, until all components in the netlist file of the target PCB are placed, and generate the layout file of the target PCB. The construction of a serialized training sample set based on the qualified design document set includes: For each design file in the qualified design file set, perform the following steps: Based on the netlist file and layout file of each design file, a layout order list is determined for each design file; the layout order list is used to indicate the layout order of all components in the corresponding design file. According to the layout order list, the placement process of all components is simulated iteratively; in each iteration, the multimodal data is generated based on the currently placed components, and the real position coordinates of the next component to be placed in the layout order list are used as supervision labels to form a training sample. The process continues until all components in each design file have been simulated and placed, thus obtaining the training sample sequence corresponding to each design file.

9. A computer device, characterized in that, The computer device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement a PCB component layout method based on a multimodal large model as described in any one of claims 1-7.

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