Cooperative etching compensation method and device based on multi-layer layout and cmp topography prediction, medium, program product and terminal

Abstract

The application provides a collaborative etching compensation method and device based on multi-layer layout and CMP topography prediction, a medium, a program product and a terminal. The application obtains and associates layout data of a current layer layout and its adjacent upper and lower layer layouts, extracts interlayer features based on the layout data, and predicts three-dimensional profile height data after CMP through topography simulation, then integrates the three-dimensional profile height data and the graphical effects of the upper and lower layer layouts into an imaging model and an etching process simulation model, optimizes the simulation environment, and performs iterative compensation in the environment to generate the final mask pattern and process parameters of the current layer layout. Through deep fusion of multi-layer layout information and CMP topography prediction, comprehensive consideration of process coupling effects between multi-layer layouts and changes in chemical mechanical polishing topography, an accurate simulation model is established, collaborative optimization across process links is realized, and etching compensation accuracy is significantly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a collaborative etching compensation method and device based on multi-layer layout and CMP topography prediction, a medium, a program product and a terminal. BACKGROUND

[0002] At present, with the continuous shrinking of the process node of integrated circuits, the process coupling effect in the semiconductor manufacturing process is increasingly significant. The traditional single-layer etching compensation method faces the following technical bottlenecks:

[0003] Firstly, the chemical mechanical polishing process causes nanoscale undulations on the wafer surface due to the pattern density effect, which is related to the layout of the lower layer. This unevenness can cause problems such as uneven photoresist thickness, photoetching focal plane deviation, and inconsistent etching depth. Secondly, the multi-layer process interaction effects include the influence of the lower layer pattern density distribution on the surface flatness after CMP, the complex interaction between multiple pattern technology masks, and the potential impact of the upper layer pattern on the current layer process. In addition, the traditional OPC method based on the assumption of "ideal flat surface" cannot accurately predict the CMP topography effect, and the single-layer compensation strategy ignores the interlayer process coupling, and the existing technical solutions have failed to effectively solve the physical coupling problem.

[0004] These factors together cause significant critical dimension variation and edge placement error, which can reach several nanometers in advanced processes, severely restricting the yield and performance of chip manufacturing. As the process node continues to shrink, this problem will become more prominent. Therefore, the traditional compensation method based only on the current layer information cannot meet the precision requirements of advanced processes, resulting in an unavoidable edge placement error (EPE) between the final silicon wafer pattern and the design target, causing electrical short circuits, open circuits or performance failures. SUMMARY

[0005] In view of the above shortcomings of the prior art, the present application provides a collaborative etching compensation method and device based on multi-layer layout and CMP topography prediction, a medium, a program product and a terminal, which are used to solve the pattern distortion problem caused by interlayer process coupling and chemical mechanical polishing topography effect in advanced processes.

[0006] To achieve the above object and other related objects, the first aspect of the present application provides a collaborative etching compensation method based on multi-layer layout and CMP topography prediction, comprising: obtaining layout data of a current layer layout, a previous layer layout and a next layer layout in a multi-layer layout; performing feature extraction on the layout data of the multi-layer layout to obtain feature data of the multi-layer layout; performing computational fluid dynamics and mechanical wear simulation based on the feature data of the multi-layer layout by using a CMP process topography simulation model to obtain three-dimensional profile height data of a wafer surface after CMP; inputting the three-dimensional profile height data of the wafer surface after CMP and the feature data of the multi-layer layout into a lithography imaging model and an etching process simulation model, and iteratively optimizing and compensating mask patterns of the current layer layout to generate mask patterns of the current layer layout after optimization and compensation.

[0007] In some embodiments of the first aspect of the present application, the process of performing feature extraction on the layout data of the multi-layer layout to obtain the feature data of the multi-layer layout comprises: performing key feature recognition on the layout data of the multi-layer layout to obtain key feature recognition results of each layer layout; establishing an inter-layer alignment mapping relationship according to the key feature recognition results of each layer layout, and extracting inter-layer feature data between the multi-layer layouts according to the inter-layer alignment mapping relationship; and taking the key feature recognition results of each layer layout and the inter-layer feature data between the multi-layer layouts as the feature data of the multi-layer layout.

[0008] In some embodiments of the first aspect of the present application, the key feature recognition results of each layer layout comprise: initial line width and pitch of patterns of the current layer layout, pattern density distribution of the next layer layout, and pattern density distribution of a projection overlapping area of the previous layer layout on the current layer layout.

[0009] In some embodiments of the first aspect of the present application, the process of inputting the three-dimensional profile height data of the wafer surface after CMP and the feature data of the multi-layer layout into the lithography imaging model and the etching process simulation model, iteratively optimizing and compensating mask patterns of the current layer layout, and generating mask patterns of the current layer layout after optimization and compensation comprises: establishing a focal plane compensation function based on the three-dimensional profile height data of the wafer surface after CMP and photoresist thickness, and performing dynamic focal plane compensation according to the focal plane compensation function in the lithography simulation process of the current layer layout in the lithography imaging simulation model to obtain compensated lithography imaging simulation images; inputting the compensated lithography imaging simulation images and the feature data of the next layer layout into the etching process simulation model to obtain etching simulation layout of the current layer layout; calculating errors between the etching simulation layout of the current layer layout and the mask patterns of the current layer layout based on a preset optimization function, and performing iterative optimization and compensation operations according to the errors to generate mask patterns of the current layer layout after optimization and compensation.

[0010] In some embodiments of the first aspect of the present application, the formula of the focal plane compensation function is: ; wherein, is a coordinate of an arbitrary position on the wafer surface, is a post-compensation focal plane, is a reference focal plane, is a CMP topography height of an arbitrary position on the wafer surface, is a photoresist thickness.

[0011] In some embodiments of the first aspect of the present application, the preset optimization function includes an edge placement error.

[0012] To achieve the above object and other related objects, the second aspect of the present application provides a collaborative etching compensation device based on multi-layer layout and CMP topography prediction, comprising: a layout data acquisition module, configured to acquire layout data of a current layer layout, a previous layer layout and a next layer layout in a multi-layer layout; a feature extraction module, configured to perform feature extraction on the layout data of the multi-layer layout to obtain feature data of the multi-layer layout; a CMP topography simulation module, configured to perform computational fluid dynamics and mechanical wear simulation based on the feature data of the multi-layer layout using a CMP process topography simulation model to obtain three-dimensional profile height data of a wafer surface after CMP; and an optimization compensation module, configured to input the three-dimensional profile height data of the wafer surface after CMP and the feature data of the multi-layer layout into a lithography imaging model and an etching process simulation model, and iteratively optimize and compensate a mask pattern of the current layer layout to generate a mask pattern of the current layer layout after optimization and compensation.

[0013] To achieve the above object and other related objects, the third aspect of the present application provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the collaborative etching compensation method based on multi-layer layout and CMP topography prediction.

[0014] To achieve the above object and other related objects, the fourth aspect of the present application provides a computer program product, wherein the computer program product includes computer program code, and when the computer program code runs on a computer, the computer program code causes the computer to implement the collaborative etching compensation method based on multi-layer layout and CMP topography prediction.

[0015] To achieve the above object and other related objects, the fifth aspect of the present application provides an electronic terminal, comprising a memory, a processor and a computer program stored on the memory; the processor executes the computer program to implement the collaborative etching compensation method based on multi-layer layout and CMP topography prediction.

[0016] As described above, the collaborative etching compensation method, device, medium, program product and terminal based on multi-layer layout and CMP topography prediction provided by the present application have the following beneficial effects:

[0017] (1) Higher precision: By introducing upper and lower layer layout information, the process model is closer to reality, greatly improving the accuracy of prediction and compensation for etching load effect and optical proximity effect, effectively reducing EPE.

[0018] (2) Global optimization: Solves the problem of inter-layer process coupling, avoids the limitation of traditional methods considering only the current layer layout, and realizes cross-layer collaborative optimization.

[0019] (3) Improve yield: More accurate compensation means lower risk of short and open circuits, especially at advanced process nodes, which can significantly improve chip manufacturing yield and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The flowchart shows a collaborative etching compensation method based on multi-layer layout and CMP topography prediction in an embodiment of the present application.

[0021] Figure 2 The structural diagram shows a collaborative etching compensation device based on multi-layer layout and CMP topography prediction in an embodiment of the present application.

[0022] Figure 3 The structural diagram shows an electronic terminal in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The embodiments of the present application will be described in detail below with specific, concrete examples. Those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied in other different specific embodiments, and the details in the present specification can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0024] Before the present application is further described, the terms and phrases involved in the embodiments of the present application are explained, which are applicable to the following explanations:

[0025] <1> EPE (Edge Placement Error) refers to the deviation between the actual position of the pattern edge and the designed position in the lithography process. EPE is an important indicator to measure the accuracy of lithography, which directly affects the performance and yield of the device.

[0026] <2> Chemical Mechanical Planarization (CMP): also known as chemical mechanical polishing, is an important step in the fine surface processing of semiconductor manufacturing technology. It has become the most widely used planarization technology in the era of very large-scale integrated circuits. By combining chemical etching of polishing fluid and mechanical removal of polishing particles, excess material on the wafer surface is removed, so that the polished surface achieves a nanometer-level smoothness, ensuring the accuracy of subsequent photolithography, deposition and other processes.

[0027] <3> OPC (Optical Proximity Correction): Optical proximity correction is a technique used to improve the quality of lithography patterns on semiconductor chips. It makes tiny corrections to the original design pattern to compensate for optical near-field effects and chemical effects during the lithography process, thereby improving the precision and reliability of chip manufacturing.

[0028] <4> Etching Loading Effect: The loading effect refers to the influence of pattern density on the etching process. In chip etching, different pattern densities affect parameters such as etching rate and depth, thereby affecting the structure and performance of the final product.

[0029] <5> Line width and spacing: Line width is the width of lines or graphics in the chip design and manufacturing layout, while spacing is the width of different graphics.

[0030] This application provides a collaborative etching compensation method based on multi-layer layout and CMP topography prediction. By deeply fusing multi-layer layout information and CMP topography prediction, and comprehensively considering the process coupling effect between multi-layer layouts and the changes in chemical mechanical polishing topography, an accurate simulation model is established to achieve collaborative optimization across process stages, significantly improving etching compensation accuracy. This application is applicable to advanced process technologies and can effectively solve the pattern distortion problem caused by inter-layer interactions and chemical mechanical polishing topography effects, significantly improving chip manufacturing accuracy and yield.

[0031] To facilitate understanding of the embodiments of this application, firstly, in conjunction with Figure 1 Detailed explanation. Figure 1 This document illustrates a flowchart of a collaborative etching compensation method based on multi-layer layout and CMP topography prediction, as described in an embodiment of the present invention. The method in this embodiment includes:

[0032] Step S11: Obtain the layout data of the current layer, the previous layer, and the next layer in the multi-layer layout.

[0033] It should be noted that the layout file is a core file type in the field of electronic design automation, used to describe the physical structure information of an integrated circuit or microelectronic device, including the size, shape, position and interconnection of elements in the circuit. The layout file is a key bridge from abstract logic to actual manufacturing of chip design, directly determines the function, performance and reliability of the chip. The layout file includes multiple layers of layout, in the present embodiment, when performing etching compensation of the current layer of layout, the information of multiple layers of layout is considered, therefore, the layout data of the current layer of layout, and the upper layer of layout and the lower layer of layout adjacent to the current layer of layout need to be obtained respectively. For example, the current layer of layout, the upper layer of layout and the lower layer of layout are obtained in the order from top to bottom as the upper layer of layout, the current layer of layout and the lower layer of layout. Figure Three

[0034] Step S12: performing feature extraction on the layout data of the multiple layers of layout to obtain feature data of the multiple layers of layout.

[0035] In an embodiment of the present application, the process of performing feature extraction on the layout data of the multiple layers of layout to obtain feature data of the multiple layers of layout includes: performing key feature recognition on the layout data of the multiple layers of layout to obtain key feature recognition results of each layer of layout; establishing an inter-layer alignment mapping relationship according to the key feature recognition results of each layer of layout, and extracting inter-layer feature data between the multiple layers of layout according to the inter-layer alignment mapping relationship; taking the key feature recognition results of each layer of layout and the inter-layer feature data between the multiple layers of layout as the feature data of the multiple layers of layout.

[0036] In an embodiment of the present application, the key feature recognition results of each layer of layout include: the initial line width and pitch of the current layer of layout, the pattern density distribution of the next layer of layout, and the pattern density distribution of the projection overlapping area of the upper layer of layout on the current layer of layout.

[0037] It should be noted that the feature extraction algorithm is used to perform feature extraction on the layout data of the multiple layers of layout, i.e. the feature extraction is performed on the layout data of the current layer of layout, the layout data of the upper layer of layout and the layout data of the lower layer of layout respectively, and the pattern density distribution, key dimension statistical features and other key feature recognition results of each layer of layout are extracted.

[0038] ​​​​​​​The feature extraction algorithms include, but are not limited to, edge detection algorithms, shape feature extraction algorithms, and deep learning extraction algorithms. Edge detection algorithms include, but are not limited to, the Canny algorithm, Laplacian algorithm, Roberts algorithm, Prewitt algorithm, and Sobel algorithm. Shape feature extraction algorithms include, but are not limited to, Fourier algorithms, Zernike moment algorithms, grid algorithms, and shape description matrix algorithms. Deep learning extraction algorithms include, but are not limited to, convolutional neural networks and graph neural networks.

[0039] The graphic density distribution includes the proportion of line width or spacing per unit area in the layout. The key dimensional statistical features include statistical distribution data for line width and spacing. For example, obtaining the current layer ( ) map, upper layer ( ) map and the next layer ( After obtaining the layout data of the layout, feature extraction is performed on the three layers of layout data to obtain the current layer ( The initial line width and spacing of the map, the next layer ( The graphic density distribution of the map, the upper layer ( The graphic density distribution of the overlapping area of ​​the projection of the map onto the current layer map.

[0040] Furthermore, after obtaining the key feature recognition results of each layer of the layout, an inter-layer alignment mapping relationship is established to ensure coordinate accuracy, thereby obtaining the layout topology information between each layer of the layout as inter-layer feature data. The layout topology information includes the adjacency relationships and network structure between graphics in each layer of the layout. For example, matching the spatial positions of graphics in a three-layer layout ensures that the current layer ( The layer directly below a certain graphic on the map is the next layer. Which structure of the layout? After extracting the density distribution, key dimension statistical features, and layout topology information of each layer, the format is uniformly converted into a standardized data format for subsequent simulation to obtain the final multi-layer layout feature data.

[0041] Step S13: Based on the feature data of the multi-layer layout, the CMP process topography simulation model is used to perform computational fluid dynamics and mechanical wear simulation to obtain the three-dimensional contour height data of the wafer surface after CMP.

[0042] In the embodiment, the key feature data affecting the flatness after CMP and the etching load effect are extracted from the feature data of the multi-layer layout. The key feature data affecting the flatness after CMP includes the pattern density distribution of the current layer layout, the pattern geometry parameter of the current layer layout, the pattern density distribution of the next layer layout, the pattern density distribution of the projection overlapping area of the last layer layout on the current layer layout, and the like. The key feature data affecting the etching load effect includes the local pattern density of the current layer layout, the pattern spacing, the pattern edge density, and the like.

[0043] It should be noted that the CMP process topography simulation in the embodiment is to predict the wafer surface topography before the process of the current layer layout. First, the layout data of the current layer layout and its adjacent upper and lower layer layouts (the last layer layout and the next layer layout) are associated, and then the feature data of the multi-layer layout is obtained according to the layout data of the multi-layer layout. According to the key feature data affecting the flatness after CMP and the etching load effect in the feature data of the multi-layer layout, a CMP process topography simulation model is constructed by using a CMP simulation tool, and the geometric features (such as pattern density distribution, line width, etc.) and the CMP process parameters (such as pressure, slurry characteristics, etc.) of the current layer layout are input into the CMP process topography simulation model. The computational fluid dynamics and mechanical wear simulation are performed, and finally the three-dimensional profile height data of the wafer surface after CMP is output. The three-dimensional profile height data records the height of each position on the wafer surface before the process of the current layer layout relative to the reference plane The CMP process topography simulation before the process of the current layer layout in the embodiment considers the correlation features of the current layer layout and the adjacent upper and lower layer layouts, realizes more accurate prediction of the surface topography after CMP, and improves the accuracy of the prediction of the wafer surface topography after CMP.

[0044] Step S14: inputting the three-dimensional profile height data of the wafer surface after CMP and the feature data of the multi-layer layout into the lithography imaging model and the etching process simulation model, iteratively optimizing and compensating the mask pattern of the current layer layout, and generating the optimized and compensated mask pattern of the current layer layout.

[0045] In an embodiment of the present application, the three-dimensional profile height data of the wafer surface after CMP and the feature data of the multi-layer layout are input into a lithography imaging model and an etching process simulation model, the mask pattern of the current layer layout is iteratively optimized and compensated, and the process of generating the mask pattern of the current layer layout after optimization and compensation includes: establishing a focal plane compensation function based on the three-dimensional profile height data of the wafer surface after CMP and the photoresist thickness, in the lithography simulation process of the current layer layout in the lithography imaging simulation model, the dynamic focal plane compensation is performed according to the focal plane compensation function to obtain the compensated lithography imaging simulation graph; the compensated lithography imaging simulation graph and the feature data of the next layer layout are input into the etching process simulation model to obtain the etching simulation layout of the current layer layout; based on a preset optimization function, the error between the etching simulation layout of the current layer layout and the mask pattern of the current layer layout is calculated, and the error is judged to perform the iterative optimization and compensation operation to generate the mask pattern of the current layer layout after optimization and compensation.

[0046] It should be noted that in the embodiment, the three-dimensional profile height data of the wafer surface after CMP before the process of the current layer layout is obtained through CMP process simulation, that is, the CMP profile height is predicted. According to the dynamic focal plane compensation based on the CMP profile height, the subsequent lithography simulation process can truly reflect the in-plane defocus variation caused by the CMP profile. Based on the CMP profile height of any position on the wafer surface and the photoresist thickness , the focal plane compensation function (such as formula 1) is constructed as a compensation value to compensate in the lithography simulation process of the current layer layout.

[0047] In the embodiment, the formula of the focal plane compensation function is:

[0048] ; (Formula 1)

[0049] Wherein, is the coordinate of any position on the wafer surface, is the compensated focal plane, is the reference focal plane, is the CMP profile height of any position on the wafer surface, is the photoresist thickness.

[0050] Specifically, for any position in the lithography simulation region (i.e. the wafer surface) , the compensated focal plane for lithography imaging calculation is not the reference focal plane , the focal plane of the position is affected by the CMP profile height and the photoresist thickness influence. Therefore, on the basis of the reference focal plane , the CMP topography height at the current position and the photoresist thickness are used to make corresponding focal length compensation to obtain the compensated focal plane . The photoresist thickness is the photoresist thickness change amount calculated according to the layout data of the next layer layout. The lithography simulation based on the compensated focal plane can truly reflect the in-plane defocus variation caused by the CMP topography, and improve the simulation accuracy.

[0051] In an embodiment of the present application, the preset optimization function includes an edge placement error.

[0052] Further, when the preset optimization function adopted is the edge placement error, the compensated lithography imaging simulation image is obtained, the compensated lithography imaging simulation image and the feature data of the next layer layout are input into an etching process simulation model to obtain the etching simulation layout of the current layer layout. Then, the error between the etching simulation layout of the current layer layout and the mask pattern of the current layer layout is calculated according to the edge placement error, and then the size of the error and the preset error threshold is judged. If the error is greater than or equal to the preset error threshold, the etching simulation layout of the current layer layout is subjected to iterative optimization and compensation operation until the error between the lithography simulation result after the iterative optimization and compensation operation and the mask pattern of the current layer layout is less than the preset error threshold, and the mask pattern of the current layer layout after optimization and compensation is output.

[0053] The error is usually represented by the edge placement error (EPE) between the simulation pattern and the mask pattern of the current layer layout. The specific iterative optimization and compensation operation process is as follows: according to the EPE value, the edge position (Edge Movement) of the mask pattern of the current layer layout is adjusted or sub-resolution assist features (SRAF) are added to generate the mask pattern after optimization and compensation, and then the simulation-compensation loop process is iteratively executed until the EPE value is less than the preset error threshold, and the final mask pattern after optimization and compensation is output.

[0054] In the process of iterative optimization and compensation operation, multi-level convergence criteria are set, a fast feedback mechanism is established, reference is provided for process parameter configuration and design optimization, efficient iterative optimization can be realized, and the CMP process parameters and etching process are adjusted. A complete verification system can be established subsequently, strict manufacturability design checks are performed, process window verification is performed, detailed manufacturing guidance documents are generated, and manufacturability evaluation reports are provided.

[0055] For the purpose of facilitating the understanding of the method for collaborative etching compensation based on multi-layer layout and CMP topography prediction of the present application, the following specific embodiments are provided for illustration.

[0056] Embodiment one: taking a metal layer of a nanometer process node as an example.

[0057] The layout pattern density of the current layer layout varies sharply, and the adjacent directly lower layer is a complex fin field effect transistor (FinFET) active area (AA), and the surface topography is extremely complex. When using the traditional method, EPE>6nm.

[0058] The layout of the AA layer, the layout of the V0 layer, and the layout of the via layer (V0) are taken as inputs, the input layout is processed, interlayer alignment calibration is performed to ensure coordinate accuracy. The CMP process topography simulation model accurately predicts the protrusion on the transistor array and the depression (difference of 15nm) on the isolation area. The lithography imaging model shows that in the depression area, the line width is 3nm thinner even at the best dose; the etching process simulation model shows that in the dense line area, the etching rate is 8% slower than that of isolated lines. After 5 rounds of iteration, the isolated lines in the depression area are asymmetrically curved and thickened, and the design line width in the dense area is slightly tightened. At the same time, it is suggested to fine-tune the CMP process parameters (pressure distribution optimization). Finally, the layer curve mask data is generated, and adjustment suggestions for CMP and etching processes are provided. The simulation data shows that the root mean square value of the global EPE is reduced from 7.2nm to 2.1nm, and the yield of related structures is significantly improved.

[0059] The layout data of the current layer layout and the layout data of its adjacent upper and lower layer layouts are obtained and associated, the interlayer features are extracted based on the layout data, the three-dimensional profile height data after CMP is predicted through topography simulation, and then the three-dimensional profile height data and the pattern effects of the upper and lower layer layouts are integrated into the imaging model and the etching process simulation model, the simulation environment is optimized, and the iteration compensation is performed in this environment to generate the final mask pattern and process parameters of the current layer layout. The present application realizes the paradigm shift from "single-layer local compensation" to "multi-layer collaborative optimization", significantly improving the etching profile accuracy and chip manufacturing yield.

[0060] It should be emphasized that the method for collaborative etching compensation based on multi-layer layout and CMP topography prediction provided by the present application has the following beneficial effects:

[0061] (1) Higher accuracy: By introducing the upper and lower layer layout information, the process model is closer to reality, greatly improving the accuracy of prediction and compensation of etching load effect and optical proximity effect, and effectively reducing EPE. ​

[0062] (2) Global optimization: solves the problem of inter-layer process coupling, avoids the limitation of traditional methods which only consider the current layer layout, and realizes cross-layer collaborative optimization.

[0063] (3) Improve yield: more accurate compensation means lower risk of short circuit and open circuit, especially at advanced process nodes, which can significantly improve the manufacturing yield and reliability of chips.

[0064] In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish the same or similar items with basically the same function and effect, and do not limit the order. Those skilled in the art can understand that the terms "first", "second", etc. do not limit the number and execution order, and the terms "first", "second", etc. also do not necessarily mean different.

[0065] It should be noted that in the embodiments of the present application, the words "exemplary" or "for example" indicate an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of the words "exemplary" or "for example" is intended to present the relevant concept in a specific manner.

[0066] In the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. The association relationship between the associated objects is described, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects. "At least one of the following" or similar expressions means any combination of these items, including single item or any combination of multiple items. For example, at least one of a, b or c, which can represent: a, b, c, a-b, a-c, b-c or a-b-c, where a, b and c can be single or multiple.

[0067] Figure 2 The schematic block diagram of the collaborative etching compensation device based on multi-layer layout and CMP topography prediction provided by the embodiments of the present application is shown in Figure 2 As shown in the figure, the device 200 includes:

[0068] The layout data acquisition module 201 is configured to acquire layout data of a current layer layout, a previous layer layout and a next layer layout in a multi-layer layout.

[0069] The feature extraction module 202 is configured to perform feature extraction on the layout data of the multi-layer layout to obtain feature data of the multi-layer layout.

[0070] The CMP topography simulation module 203 is configured to perform computational fluid dynamics and mechanical wear simulation based on the feature data of the multi-layer layout by using a CMP process topography simulation model, to obtain three-dimensional profile height data of the wafer surface after CMP;

[0071] The optimization compensation module 204 is configured to input the three-dimensional profile height data of the wafer surface after CMP and the feature data of the multi-layer layout into a lithography imaging model and an etching process simulation model, to iteratively optimize and compensate the mask pattern of the current layer layout, to generate the mask pattern of the current layer layout after optimization and compensation.

[0072] It should be understood that the specific process of each module performing the corresponding steps described above has been described in detail in the method embodiments described above, and for the sake of brevity, will not be repeated here.

[0073] It should also be understood that the division of the modules in the embodiments of the present application is illustrative, and is only a logical functional division. In actual implementation, there can be another division manner. In addition, each functional module in each embodiment of the present application can be integrated in one processor, or can be physically separated, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module.

[0074] Figure 3 is a schematic block diagram of an electronic terminal provided by the embodiments of the present application. As shown in Figure 3 , the electronic terminal includes at least one processor 301, a memory 302, at least one network interface 303 and a user interface 305. Each component in the apparatus is coupled together through a bus system 304. It can be understood that the bus system 304 is used to realize the connection and communication between these components. In addition to including a data bus, the bus system 304 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, all kinds of buses are marked as a bus system in Figure 3 .

[0075] The user interface 305 can include a display, a keyboard, a mouse, a trackball, a click gun, a key, a button, a touchpad or a touch screen, etc.

[0076] It is to be understood that the memory 302 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM, Read Only Memory), a programmable read-only memory (PROM, Programmable Read-Only Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM can be used, such as static random access memory (SRAM, Static Random Access Memory), synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory). The memory described in the embodiments of the present application is intended to include but not limited to these and any other suitable category of memory.

[0077] The memory 302 in the embodiments of the present application is used to store various categories of data to support the operation of the electronic terminal 300. Examples of these data include: any executable program for operating on the electronic terminal 300, such as an operating system 3021 and an application program 3022; the operating system 3021 contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application program 3022 can contain various application programs, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The implementation of the collaborative etching compensation method based on multi-layer layout and CMP topography prediction provided by the embodiments of the present application can be included in the application program 3022.

[0078] The method disclosed by the embodiments of the present application can be applied to the processor 301 or implemented by the processor 301. The processor 301 can be an integrated circuit chip having a processing capability of signals. In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware in the processor 301 or the instruction in the form of software. The processor 301 described above can be a general processor, a digital signal processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The processor 301 can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application. The general processor 301 can be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in conjunction with the embodiments of the present application can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory to complete the steps of the foregoing method in combination with the hardware thereof.

[0079] In the exemplary embodiments, the electronic terminal 300 can be one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), or the like for executing the foregoing method.

[0080] According to the method provided by the embodiments of the present application, the present application further provides a computer program product, which comprises computer program code, and when the computer program code runs on a computer, the computer executes the collaborative etching compensation method based on the multi-layer layout and CMP topography prediction in any of the embodiments.

[0081] According to the method provided by the embodiments of the present application, the present application further provides a computer readable storage medium, which stores program code, and when the program code runs on a computer, the computer executes the collaborative etching compensation method based on the multi-layer layout and CMP topography prediction in any of the embodiments.

[0082] As used in this description, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, partially localized, and / or distributed across two or more computers. Also, these components can execute from various computer readable media having various data structures stored thereon. The components can communicate by way of local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal).

[0083] Those of skill in the art would understand that the various illustrative logical blocks, modules, and steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or a combination of computer software and electronic hardware. The choice of hardware and software implementation would depend on the specific application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

[0084] Those of skill in the art would understand that, for the described convenience and brevity, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiment, which will not be described here.

[0085] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative, for example, the division of units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some interface, indirect coupling or communication connection between devices or units, which can be electrical, mechanical or other forms.

[0086] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e., may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0087] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can exist physically, or two or more units can be integrated into one unit.

[0088] In the above embodiments, the functions of each functional unit can be implemented by software, hardware, firmware, or any combination thereof, in whole or in part. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the flow or function according to the embodiments of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another, for example, computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be magnetic media (such as floppy disk, hard disk, magnetic tape), optical media (such as high-density digital video disc (digital video disc, DVD), or semiconductor media (such as solid state disk (solid state disk, SSD), etc.

[0089] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0090] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0091] In summary, the method, device, medium, program product and terminal based on the collaborative etching compensation of multi-layer layout and CMP topography prediction provided by the present application comprise: obtaining layout data of a current layer layout, a previous layer layout and a next layer layout in a multi-layer layout; performing feature extraction on the layout data of the multi-layer layout to obtain feature data of the multi-layer layout; performing computational fluid dynamics and mechanical wear simulation based on the feature data of the multi-layer layout by using a CMP process topography simulation model to obtain three-dimensional profile height data of a wafer surface after CMP; inputting the three-dimensional profile height data of the wafer surface after CMP and the feature data of the multi-layer layout into a lithography imaging model and an etching process simulation model to iteratively optimize and compensate mask patterns of the current layer layout to generate mask patterns of the current layer layout after optimization and compensation.

[0092] The present application fuses multi-layer layout information and CMP topography prediction in depth, comprehensively considers process coupling effects between multi-layer layouts and chemical mechanical polishing topography changes, establishes an accurate simulation model, realizes collaborative optimization across process links, and significantly improves etching compensation accuracy. The present application is suitable for advanced process technology and can effectively solve the pattern distortion problem caused by process interlayer interaction and chemical mechanical polishing topography effects, and significantly improve the precision and yield of chip manufacturing. Therefore, the present application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0093] The above embodiments are only illustrative of the principles of the present application and its effects, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A collaborative etch compensation method based on multi-layer layout and CMP topography prediction, characterized in that, The method comprises the following steps: obtain the layout data of the current layer, the previous layer and the next layer of the multi-layer layout; extract features from the layout data of the multi-layer layout to obtain feature data of the multi-layer layout; simulate the computational fluid dynamics and mechanical wear based on the feature data of the multi-layer layout using a CMP process topography simulation model to obtain three-dimensional profile height data of the wafer surface after CMP; input the three-dimensional profile height data of the wafer surface after CMP and the feature data of the multi-layer layout into a lithography imaging model and an etching process simulation model to iteratively optimize and compensate the mask pattern of the current layer to generate the mask pattern of the current layer after optimization and compensation; the process comprises: establishing a focal plane compensation function based on the three-dimensional profile height data of the wafer surface after CMP and the photoresist thickness, and dynamically compensating the focal plane according to the focal plane compensation function during the lithography simulation of the current layer in the lithography imaging simulation model to obtain the compensated lithography imaging simulation image; input the compensated lithography imaging simulation image and the feature data of the next layer into the etching process simulation model to obtain the etching simulation layout of the current layer; based on a preset optimization function, calculate the error between the etching simulation layout of the current layer and the mask pattern of the current layer, and perform iterative optimization and compensation operation according to the error to generate the mask pattern of the current layer after optimization and compensation.

2. The method of claim 1, wherein, The process of extracting features from the layout data of the multi-layer layout to obtain the feature data of the multi-layer layout comprises: identify key features from the layout data of the multi-layer layout to obtain key feature identification results of each layer; establish an interlayer alignment mapping relationship according to the key feature identification results of each layer, and extract interlayer feature data between the multi-layer layout according to the interlayer alignment mapping relationship; use the key feature identification results of each layer and the interlayer feature data between the multi-layer layout as the feature data of the multi-layer layout.

3. The method of claim 2, wherein the method further comprises: The key feature identification results of each layer include: the initial line width and spacing of the pattern of the current layer, the pattern density distribution of the next layer, and the pattern density distribution of the projection overlapping area of the previous layer on the current layer.

4. The method of claim 1, wherein, The formula of the focal plane compensation function is: ； wherein, is the coordinate of any position on the wafer surface, is the back focus plane after compensation, is the reference focus plane, is the CMP topography height of any position on the wafer surface, is the photoresist thickness.

5. The method of claim 1, wherein, The preset optimization function includes: edge placement error.

6. A collaborative etch compensation device based on multi-layered layout and CMP topography prediction, characterized in that, The method comprises the following steps: a layout data acquisition module is configured to obtain the layout data of the current layer, the previous layer and the next layer of the multi-layer layout; a feature extraction module is configured to extract features from the layout data of the multi-layer layout to obtain feature data of the multi-layer layout; a CMP topography simulation module is configured to simulate the computational fluid dynamics and mechanical wear based on the feature data of the multi-layer layout using a CMP process topography simulation model to obtain three-dimensional profile height data of the wafer surface after CMP; an optimization and compensation module is configured to input the three-dimensional profile height data of the wafer surface after CMP and the feature data of the multi-layer layout into a lithography imaging model and an etching process simulation model to iteratively optimize and compensate the mask pattern of the current layer to generate the mask pattern of the current layer after optimization and compensation. The process comprises: establishing a focal plane compensation function based on three-dimensional profile height data of a wafer surface after CMP and photoresist thickness; in a lithography simulation process of a current layer layout on a lithography imaging simulation model, performing dynamic focal plane compensation according to the focal plane compensation function to obtain a compensated lithography imaging simulation graph; inputting the compensated lithography imaging simulation graph and feature data of a next layer layout into an etching process simulation model to obtain an etching simulation layout of the current layer layout; calculating an error between the etching simulation layout of the current layer layout and a mask pattern of the current layer layout based on a preset optimization function, and performing iterative optimization and compensation operations according to the error to generate an optimized and compensated mask pattern of the current layer layout.

7. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the collaborative etching compensation method based on multi-layer layout and CMP topography prediction according to any one of claims 1 to 5.

8. A computer program product, characterised in that, The computer program product comprises computer program code, and when the computer program code is executed on a computer, the computer program code causes the computer to implement the collaborative etching compensation method based on multi-layer layout and CMP topography prediction according to any one of claims 1 to 5.

9. An electronic terminal comprising a memory, a processor and a computer program stored on the memory, characterized in that, The processor executes the computer program to implement the collaborative etching compensation method based on multi-layer layout and CMP topography prediction according to any one of claims 1 to 5.

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