Package substrate optimization method, computer equipment and storage medium

Abstract

The invention relates to a packaging substrate optimization method, computer equipment and a storage medium, and the method comprises the steps: providing an initial packaging substrate which comprises a layer-adding wiring layer and a semiconductor chip electrically connected with the layer-adding wiring layer, the layer-adding wiring layer comprises a signal layer, and a power supply plane layer and a ground plane layer which are respectively positioned on two opposite side surfaces of the signal layer, the signal layer comprises a plurality of signal lines, the power supply plane layer comprises a plurality of reference power supply planes, the ground plane layer comprises a reference ground plane, and the semiconductor chip is electrically connected with the corresponding signal lines in the layer-adding wiring layer; obtaining a target power supply plane, wherein the target power supply plane is at least one reference power supply plane which has the greatest influence on the signal far-end crosstalk resonance; replacing a part of the target power supply plane with a reconstructed ground plane, and electrically connecting the reconstructed ground plane with a reference ground plane in the layer-adding wiring layer through a backflow ground hole to form the packaging substrate. Far-end crosstalk is reduced, and signal integrity is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor packaging, and in particular to a method for optimizing signal far-end crosstalk resonance in a packaging substrate, a computer device and a storage medium. BACKGROUND

[0002] In order to meet the increasing data rate of memory channels, higher requirements are put forward for signal integrity and timing. In a multi-core CPU (Central Processing Unit) environment, the increase in the number of memory channels provides sufficient "data throughput" for the memory system, but also means that the number of layers of the packaging substrate increases to meet the wiring requirements. In view of the cost reduction demand of the multi-layer packaging substrate stack architecture, the inner interconnection system needs to adopt a power plane-ground plane mixed reference topology, that is, one side of the trace strip line refers to the ground plane and the other side needs to refer to the power plane. Due to the limited resources of the power plane, there are often multiple power planes in the same layer with fragmented planes, which leads to unstable transmission line coupling field distribution and a sharp increase in resonance modes in a specific frequency band. In terms of signal quality, the far-end crosstalk at a certain frequency point will produce a high resonance peak, resulting in that the far-end crosstalk frequency domain index in the working frequency band of the memory signal does not meet the requirements, and the signal integrity is affected. SUMMARY

[0003] Based on this, the present application provides a method for optimizing signal far-end crosstalk resonance in a packaging substrate, a computer device and a storage medium, thereby reducing the influence of far-end crosstalk resonance on the transmission signal in the signal line, and improving the signal integrity and channel performance.

[0004] In a first aspect, an embodiment of the present application provides a method for optimizing signal far-end crosstalk resonance in a packaging substrate, comprising:

[0005] providing an initial packaging substrate, the initial packaging substrate comprising a layer-increased wiring layer and a semiconductor chip electrically connected to the layer-increased wiring layer, the layer-increased wiring layer comprising a signal layer and a power plane layer and a ground plane layer located on opposite surfaces of the signal layer, the signal layer comprising a plurality of signal lines, the power plane layer comprising a plurality of reference power planes, and the ground plane layer comprising a reference ground plane, the semiconductor chip being electrically connected to a corresponding signal line in the layer-increased wiring layer;

[0006] obtaining a target power plane, the target power plane being at least one reference power plane having the greatest influence on signal far-end crosstalk resonance;

[0007] replacing part of the target power planes with a reconstructed ground plane, and the reconstructed ground plane being electrically connected to the reference ground plane through a reflow ground hole passing through the signal layer, to form a packaging substrate.

[0008] In some embodiments of the present application, the layer-increased wiring layer is a single layer or a plurality of layers.

[0009] When there are multiple layers of add-on wiring layers, the corresponding signal lines in two adjacent add-on wiring layers are electrically connected, and the semiconductor chip is electrically connected to the corresponding signal lines in the topmost add-on wiring layer.

[0010] When the number of add-on wiring layers is multi-layered, the target power plane is at least one reference power plane among the different add-on wiring layers that have the greatest impact on the far-end crosstalk resonance of the signal, and at least one target power plane is replaced with a reconstructed ground plane. Each reconstructed ground plane is electrically connected to the reference ground plane in the add-on wiring layer through a return ground via through the signal layer in the corresponding add-on wiring layer to form a package substrate.

[0011] In some embodiments of this application, when the number of add-on wiring layers is multi-layered, the corresponding signal lines in two adjacent add-on wiring layers are electrically connected through via connection structures that penetrate the power plane layer and the ground plane layer.

[0012] The semiconductor chip includes multiple bumps, each of which is electrically connected to a corresponding via connection structure in the add-on wiring layer;

[0013] The initial packaging substrate also includes a core board, which includes an upper surface and a lower surface opposite to each other. The core board has multiple through-hole interconnect structures that penetrate the upper and lower surfaces of the core board. Some signal lines in the augmentation wiring layer that are in contact with the core board are electrically connected to the corresponding through-hole interconnect structures.

[0014] The addition wiring layer is located on the upper or lower surface of the chip board, or part of the addition wiring layer is located on the upper surface of the chip board and part of the addition wiring layer is located on the lower surface of the chip.

[0015] In some embodiments of this application, the process of obtaining the target power plane includes:

[0016] Select multiple adjacent signal lines as target signal lines;

[0017] Use the reference power plane that is directly opposite the target signal line as the reference power plane to be tested;

[0018] Replace the reference power plane under test with the test ground plane, and electrically connect the test ground plane to the reference ground plane in the same layer of the add-on wiring layer through the test return ground via the corresponding layer.

[0019] Obtain the first far-end crosstalk simulation result and the second far-end crosstalk simulation result. The first far-end crosstalk simulation result is the far-end crosstalk simulation result before the reference power plane under test is replaced with the test ground plane, and the second far-end crosstalk simulation result is the far-end crosstalk simulation result after the reference power plane under test is replaced with the test ground plane.

[0020] Determine whether there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result. If there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result, then the corresponding reference power plane to be tested is taken as the target power plane.

[0021] In some embodiments of this application, the first far-end crosstalk simulation results and the second far-end crosstalk simulation results include far-end crosstalk resonance curves.

[0022] In some embodiments of this application, determining whether there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result includes: determining whether there is a difference between the far-end crosstalk resonance curves corresponding to the first far-end crosstalk simulation result and the second far-end crosstalk simulation result.

[0023] If the far-end crosstalk simulation results and the far-end crosstalk simulation results are different, then the corresponding reference power plane to be tested will be taken as the target power plane.

[0024] In some embodiments of this application, when there are multiple reference power planes directly opposite the target signal line, all multiple reference power planes are used as reference power planes to be tested, thus obtaining multiple reference power planes to be tested.

[0025] Each reference power plane to be tested is replaced with a test ground plane in turn, and the first far-end crosstalk simulation result and the second far-end crosstalk simulation result are obtained in turn. Then, it is determined whether there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result.

[0026] In some embodiments of this application, the size of the reconstructed ground plane is larger than the distribution size of the target signal line.

[0027] In some embodiments of this application, the target signal line includes multiple signal lines for transmitting a complete byte of data, or the target signal line includes multiple signal lines for serving as a complete transmission subchannel.

[0028] In some embodiments of this application, the target signal line includes all signal lines necessary for transmitting a complete byte of data and for managing and synchronizing the data transmission.

[0029] In some embodiments of this application, a complete transmission subchannel includes a complete byte channel, an error correction code signal channel, and address and command signal channels.

[0030] In some embodiments of this application, adjacent reference power planes are insulated from each other, and adjacent reference power planes and reconfigured ground planes are insulated from each other.

[0031] The return ground via is made of metal and is insulated from the target signal line.

[0032] There are multiple return flow holes and test return flow holes;

[0033] Multiple return ground vias and multiple test return ground vias are located around the target signal line.

[0034] Secondly, embodiments of this application also provide a packaging substrate, comprising:

[0035] The addition wiring layer and the semiconductor chip electrically connected to the addition wiring layer, the addition wiring layer including a signal layer and a power plane layer and a ground plane layer located on opposite sides of the signal layer, wherein,

[0036] The signal layer includes several signal lines, and the signal lines include the target signal line;

[0037] The power plane layer includes at least one reference power plane and at least one reconfigurable ground plane, with the reconfigurable ground plane located on one side of the reference power plane and directly opposite the target signal line in the signal layer;

[0038] The ground plane layer includes a reference ground plane, and the reconstructed ground plane is electrically connected to the reference ground plane through a return ground hole passing through the signal layer.

[0039] In some embodiments of this application, the number of layers in the additional wiring layer is a single layer or multiple layers;

[0040] When there are multiple layers of add-on wiring layers, the corresponding signal lines in two adjacent add-on wiring layers are electrically connected, and the semiconductor chip is electrically connected to the corresponding signal line in the topmost add-on wiring layer.

[0041] In some embodiments of this application, when the number of add-on wiring layers is multi-layered, the target signal line is located in the signal layer of at least one add-on wiring layer; and the power plane layer of at least one add-on wiring layer having the target signal line has a reconfigured ground plane.

[0042] In some embodiments of this application, the initial packaging substrate further includes a core board, which includes an opposing upper surface and a lower surface. The core board has a plurality of through-hole interconnect structures penetrating the upper and lower surfaces of the core board. A portion of the signal lines in the augmentation wiring layer that contacts the core board are electrically connected to the corresponding through-hole interconnect structures.

[0043] The addition wiring layer is located on the upper or lower surface of the chip board, or part of the addition wiring layer is located on the upper surface of the chip board and part of the addition wiring layer is located on the lower surface of the chip.

[0044] In some embodiments of this application, the target signal line includes multiple signal lines for transmitting a complete byte of data, or the target signal line includes multiple signal lines for serving as a complete transmission subchannel.

[0045] In some embodiments of this application, adjacent reference power planes are insulated from each other, and adjacent reference power planes and reconfigured ground planes are insulated from each other.

[0046] The return ground via is made of metal and is insulated from the target signal line.

[0047] There are multiple return ground holes; these multiple return ground holes are located around the target signal line.

[0048] Thirdly, embodiments of this application also provide a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the aforementioned method.

[0049] Fourthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the aforementioned method.

[0050] The embodiments of this application may have, or at least have, the following advantages:

[0051] The method for optimizing signal far-end crosstalk resonance in the packaging substrate in this application embodiment involves providing an initial packaging substrate; obtaining a target power plane, which is at least one reference power plane that has the greatest impact on signal far-end crosstalk resonance; replacing part of the target power plane with a reconstructed ground plane, and electrically connecting the reconstructed ground plane to a reference ground plane in the add-on wiring layer through a return ground via passing through the signal layer to form the packaging substrate. In this application, the combination of the aforementioned steps achieves the following technical effects:

[0052] (1) Solve the far-end crosstalk resonance: By performing local plane reconstruction on the target power plane (replacing it with the reconstructed ground plane), a partitioned structure with "power-ground hybrid reference" and "local dual ground reference" coexisting is formed, which improves the coupling path of the reconstructed electromagnetic field, optimizes the signal return flow, reduces the far-end crosstalk value in the working frequency band, and improves the signal integrity.

[0053] (2) Maintain power integrity: The reconstructed power plane can still serve as a low-impedance loop in the power network, the impedance curve of the power distribution network remains unchanged, and power indicators such as time-domain Ripple are not affected, thus avoiding power performance degradation due to signal optimization.

[0054] (3) Cost and performance balance: "Dual ground reference" is implemented only in local key areas, without increasing the number of substrate layers or changing the entire substrate to dual ground reference, thus meeting the cost reduction requirements of multilayer substrates.

[0055] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 A flowchart illustrating an optimization method for signal far-end crosstalk resonance in a packaging substrate provided in some embodiments of this application;

[0058] Figure 2 A schematic cross-sectional view of the initial packaging substrate in the optimization method for signal far-end crosstalk resonance in the packaging substrate provided in some embodiments of this application;

[0059] Figure 3 A schematic cross-sectional view of the target power plane obtained in the optimization method for signal far-end crosstalk resonance in the packaging substrate provided in some embodiments of this application;

[0060] Figure 4 A partial three-dimensional structural diagram of the target power plane obtained in the optimization method for signal far-end crosstalk resonance in the packaging substrate provided in some embodiments of this application;

[0061] Figure 5 A schematic diagram of the cross-sectional structure after replacing part of the target power plane with a reconstructed ground plane in the optimization method for signal far-end crosstalk resonance in the packaging substrate provided in some embodiments of this application;

[0062] Figure 6 A schematic diagram of a partial three-dimensional structure after replacing part of the target power plane with a reconstructed ground plane in the optimization method for signal far-end crosstalk resonance in the packaging substrate provided in some embodiments of this application;

[0063] Figure 7 A schematic diagram of the structure of an optimization device for signal far-end crosstalk resonance in a packaging substrate provided in some embodiments of this application;

[0064] Figure 8 The simulation results of far-end crosstalk of the signal are compared between the results before local reconstruction (before modification) and after using the method of this application (after modification);

[0065] Figure 9 The figure shows a comparison of the power integrity simulation results of signal far-end crosstalk before and after using this method (after modification).

[0066] Explanation of reference numerals in the attached figures:

[0067] Core board 101; Add-on wiring layer 102; Ground plane layer 103; Reconstructed ground plane 103r; Signal layer 104; Target signal line 104t; Power plane layer 105; First reference power plane 105a; Second reference power plane 105b; Target power plane 105t; Dielectric layer 106; Via connection structure 107; Through-hole interconnect structure 108; Return ground via 109; Semiconductor chip 201. Detailed Implementation

[0068] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0069] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0070] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, reference types, and / or portions, these elements, components, areas, layers, reference types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, reference type, or portion from another element, component, area, layer, reference type, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, reference type, or portion discussed below may be referred to as a second element, component, area, layer, or portion.

[0071] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0072] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0073] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0074] This application first provides an optimization method for signal far-end crosstalk resonance in a packaging substrate. Figure 1 This is a flowchart illustrating an optimization method for signal far-end crosstalk resonance in a packaging substrate provided in some embodiments of this application.

[0075] refer to Figure 1 An optimization method for signal far-end crosstalk resonance in a packaging substrate, comprising the following steps:

[0076] Step S101: Provide an initial packaging substrate. The initial packaging substrate includes an add-on wiring layer and a semiconductor chip electrically connected to the add-on wiring layer. The add-on wiring layer includes a signal layer and a power plane layer and a ground plane layer located on opposite sides of the signal layer. The signal layer includes a plurality of signal lines. The power plane layer includes a plurality of reference power planes. The ground plane layer includes a reference ground plane. The semiconductor chip is electrically connected to the corresponding signal lines in the add-on wiring layer.

[0077] Step S102: Obtain the target power plane, which is at least one reference power plane that has the greatest impact on the far-end crosstalk resonance of the signal.

[0078] In step S103, a portion of the target power plane is replaced with a reconstructed ground plane, and the reconstructed ground plane is electrically connected to the reference ground plane through a return ground via passing through the signal layer to form a package substrate.

[0079] The aforementioned process will now be described in detail with reference to the accompanying drawings.

[0080] First, refer to Figure 1 In conjunction with references Figure 2 In step S101, an initial packaging substrate is provided. The initial packaging substrate includes an add-on wiring layer 102 and a semiconductor chip 201 electrically connected to the add-on wiring layer 102. The add-on wiring layer 102 includes a signal layer 104 and a power plane layer 105 and a ground plane layer 103 located on opposite sides of the signal layer 104, respectively. The signal layer 104 includes a plurality of signal lines, the power plane layer 105 includes a plurality of reference power planes, and the ground plane layer 103 includes a reference ground plane. The semiconductor chip 201 is electrically connected to the corresponding signal lines in the add-on wiring layer 102.

[0081] The initial packaging substrate is a packaging substrate that needs to be optimized for far-end crosstalk resonance. Far-end crosstalk (FEXT) refers to the electromagnetic coupling interference signal measured at the receiving end (far end) of the adjacent interfered line when the interfering source line transmits a signal at its transmitting end (near end).

[0082] In some embodiments, the initial packaging substrate further includes a core board 101, which includes opposing upper and lower surfaces. The material of the core board 101 may include glass or silicon, or other suitable core board materials.

[0083] In some embodiments, the addition wiring layer 102 may be located on the upper or lower surface of the chip board 101, or a portion of the addition wiring layer 102 may be located on the upper surface of the chip board 101, and a portion of the addition wiring layer 102 may be located on the lower surface of the chip. The number of addition wiring layers 102 may be single or multiple. In one specific example, a single or multiple addition wiring layers 102 are located on the upper surface of the chip board 101. In another specific example, a single or multiple addition wiring layers 102 are located on the lower surface of the chip board 101. In yet another specific example, a single or multiple addition wiring layers 102 are located on both the upper and lower surfaces of the chip board 101. In one example, as... Figure 2 As shown, the multilayer addition layer wiring layer 102 is located on the upper surface of the core board 101, and the multilayer addition layer wiring layer 102 is located on the lower surface of the core board 101.

[0084] The add-on wiring layer 102 includes a signal layer 104 and a power plane layer 105 and a ground plane layer 103 located on opposite sides of the signal layer 104. The signal layer 104 has several signal lines used to transmit electrical signals. The signal lines are made of metals, specifically one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. Adjacent signal lines in the signal layer 104 are isolated by a dielectric layer 106. The dielectric layer can be an inorganic material (such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride) or an organic material (such as resin).

[0085] Ground plane layer 103 serves as a reference equipotential plane for the circuit, typically used for signal return paths, providing electromagnetic shielding and a reference potential. In some embodiments, ground plane layer 103 includes a reference ground plane, which is a large block or a single piece of metal connected to the system's reference ground (0V potential), providing a common return path for all signals.

[0086] The power plane layer 105 is used to supply power to corresponding terminals (such as corresponding bumps 202) of the semiconductor chip 201. In some embodiments, the power plane layer 105 includes a plurality of reference power planes (such as... Figure 1 The first reference power plane 105a and the second reference power plane 105b shown are insulated from each other, specifically through a dielectric layer. Multiple reference power planes are used to supply voltages to different terminals. The voltages supplied by the multiple reference power planes can be the same or different. In one example, the supplied voltage can be 0.4V, 0.5V, 0.66V, 0.8V, 1.0V, 1.2V, 1.4V, 1.5V, 1.8V, 2.0V, 2.2V, 2.5V, 3.3V, or other values. In some embodiments, the material of the reference power plane is a metal, specifically one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. Adjacent reference power planes can be isolated from each other through a dielectric layer 106.

[0087] In some embodiments, the signal layer 104 and the power plane layer 105 can be isolated by a dielectric layer 106, and the signal layer 104 and the ground plane layer 103 can be isolated by a dielectric layer 106.

[0088] In some embodiments, when the number of layers of the add-on wiring layer 102 is multiple, adjacent add-on wiring layers 102 may share a power plane layer 105 or a ground plane layer 103, such as... Figure 2As shown, some adjacent add-on wiring layers 102 share a power plane layer 105, and some adjacent add-on wiring layers 102 share a ground plane layer 103. In other embodiments, adjacent add-on wiring layers 102 may not share a power plane layer 105 or a ground plane layer 103, and each add-on wiring layer 102 has a power plane layer 105, a signal layer 104, and a ground plane layer 103.

[0089] In some embodiments, when the number of layers of the add-on wiring layer 102 is multi-layered, the corresponding signal lines in two adjacent add-on wiring layers 102 are electrically connected, and the semiconductor chip 201 is electrically connected to the corresponding signal lines in the topmost add-on wiring layer 102 (the topmost add-on wiring layer 102 is an add-on wiring layer 102 that is in contact with the semiconductor chip 201).

[0090] In some embodiments, when the number of layers in the add-on wiring layer 102 is multi-layered, the corresponding signal lines in two adjacent add-on wiring layers 102 are electrically connected through via connection structures 107 that penetrate the power plane layer 105 and the ground plane layer 103. The via connection structures 107 are insulated from the surroundings through the dielectric layer 106. The core board 101 has a plurality of through-hole interconnect structures 108 that penetrate the upper and lower surfaces of the core board 101. Some signal lines in the add-on wiring layer 102 that are in contact with the core board 101 are electrically connected to the corresponding through-hole interconnect structures 108. In one example, the material of the via connection structure 107 and the through-hole interconnect structure 108 is a metal, specifically one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0091] The semiconductor chip 201 includes a plurality of bumps 202, each bump 202 being electrically connected to a corresponding via connection structure 107 in the add-on wiring layer 102.

[0092] Semiconductor chip 201 generates electrical signals, which are transmitted through corresponding signal lines, via connection structures 107, and through-hole interconnect structures 108 in the add-on wiring layer 102. In one example, such as Figure 1 As shown, the electrical signals generated by the semiconductor chip 201 can be transmitted from the upper surface of the core board 101 to the lower surface of the core board 101 through corresponding bumps 202, corresponding via connection structures 107, corresponding signal lines, and corresponding through-hole interconnect structures 108. It should be noted that... Figure 1 The example shown only illustrates one signal transmission path and should not limit the scope of protection of this application. In other embodiments, multiple signal transmission paths may be included.

[0093] In some embodiments, the semiconductor chip 201 may include logic chips and / or memory chips. In some embodiments, the logic chip may include, but is not limited to, gate arrays, cell substrate arrays, embedded arrays, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), graphics processing units (GPUs), central processing units (CPUs), microprocessor units (MPUs), microcontroller units (MCUs), logic integrated circuits (ICs), application processors (APs), display driver ICs (DDIs), radio frequency (RF) chips, power supply chips, or complementary metal-oxide-semiconductor (CMOS) image sensors. In some embodiments, the memory chip may include, but is not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase-change memory (PRAM), resistive random access memory (RRAM), non-volatile memory chips (such as flash memory), or high-bandwidth memory (HBM).

[0094] Next, refer to Figure 1 In conjunction with references Figure 3 and Figure 4 Step S102 is performed to obtain the target power plane 105t, which is at least one reference power plane that has the greatest impact on the far-end crosstalk resonance of the signal.

[0095] In some embodiments, the process of obtaining the target power plane 105t includes:

[0096] Select multiple adjacent signal lines as the target signal line 104t;

[0097] The reference power plane that is directly opposite the target signal line 104t is taken as the reference power plane to be tested;

[0098] Replace the reference power plane under test with the test ground plane, and the test ground plane is electrically connected to the reference ground plane in the same layer of the add-on wiring layer 102 through the test return ground via the corresponding signal layer 104.

[0099] Obtain the first far-end crosstalk simulation result and the second far-end crosstalk simulation result. The first far-end crosstalk simulation result is the far-end crosstalk simulation result before the reference power plane under test is replaced with the test ground plane, and the second far-end crosstalk simulation result is the far-end crosstalk simulation result after the reference power plane under test is replaced with the test ground plane.

[0100] Determine whether there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result. If there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result, then the corresponding reference power plane to be tested is taken as the target power plane 105t.

[0101] In some embodiments, there are multiple test return ground vias; the multiple test return ground vias are located around the target signal line 104t. The test return ground vias are made of metal and do not have electrical contact with the target signal line 104t.

[0102] In some embodiments, the first far-end crosstalk simulation result and the second far-end crosstalk simulation result include far-end crosstalk resonance curves. Determining whether there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result includes determining whether there are differences in the far-end crosstalk resonance curves corresponding to the first far-end crosstalk simulation result and the second far-end crosstalk simulation result;

[0103] If the far-end crosstalk simulation results and the far-end crosstalk simulation results correspond to different far-end crosstalk resonance curves, then the corresponding reference power plane to be tested is taken as the target power plane 105t. This achieves precise positioning of the target power plane 105t.

[0104] In a specific example, when the trends of the far-end crosstalk resonance curves corresponding to the first far-end crosstalk simulation result and the far-end crosstalk resonance curves corresponding to the second far-end crosstalk simulation result are the same or similar, that is, there is no difference or difference between the far-end crosstalk resonance curves corresponding to the first far-end crosstalk simulation result and the far-end crosstalk resonance curves corresponding to the second far-end crosstalk simulation result, then the corresponding reference power plane to be tested is not or should not be used as the target power plane. When the trends of the far-end crosstalk resonance curves corresponding to the first far-end crosstalk simulation result and the far-end crosstalk resonance curves corresponding to the second far-end crosstalk simulation result are different (and there is a large difference in the far-end crosstalk values ​​corresponding to certain far-end crosstalk frequency points), and the far-end crosstalk resonance curve corresponding to the second far-end crosstalk simulation result is significantly smoother and the resonance in the operating frequency band disappears, that is, there is a difference or difference between the far-end crosstalk resonance curves corresponding to the first far-end crosstalk simulation result and the far-end crosstalk resonance curves corresponding to the second far-end crosstalk simulation result, then the corresponding reference power plane to be tested is used as the target power plane.

[0105] In some embodiments, when the number of layers of the add-on wiring layer 102 is multiple, the target power plane 105t is at least one reference power plane among the different add-on wiring layers 102 that have the greatest impact on the far-end crosstalk resonance of the signal, that is, the obtained target power plane 105t can be multiple.

[0106] In some embodiments, when there are multiple reference power planes directly opposite the target signal line 104t, all multiple reference power planes are used as reference power planes to be tested, thus obtaining multiple reference power planes to be tested.

[0107] Each reference power plane under test is sequentially replaced with a test ground plane, and the first and second far-end crosstalk simulation results are obtained sequentially. The discrepancies between the first and second far-end crosstalk simulation results are then determined to further improve the accuracy of the number and location of the obtained target power planes 105t.

[0108] In some embodiments, the target signal line 104t includes multiple signal lines for transmitting a complete byte of data. In a specific embodiment, the target signal line 104t includes all signal lines necessary for transmitting a complete byte of data and for managing and synchronizing the data transmission. For example, a complete byte refers to all signal lines necessary for transmitting one byte (e.g., 8 bits) of data and for managing and synchronizing the data transmission on a memory (e.g., DDR memory, Double Data Rate, DDR) interface. In a specific example, a complete byte typically consists of 8 data signals DQ (Data), an error-correcting code signal ECC (Error-Correcting Code), and corresponding data clock signals DQS (Data Strobe) differential signals (possibly one or two pairs). For some DDR types, it may also include a data mask DM (Data Mask) or a data bus inversion mask DBIM (Data Bus Inversion Mask) line.

[0109] In other embodiments, the target signal line 104t includes multiple signal lines for use as a complete transmission subchannel. In one specific embodiment, a complete transmission subchannel includes a complete byte channel, an error correction code signal channel, and address and command signal channels. For example, a standard 64-bit DDR channel is physically and logically composed of two complete 32-bit subchannels, each of which contains four complete byte channels + one ECC byte and the corresponding address and command signals for that subchannel.

[0110] Next, refer to Figure 1 In conjunction with references Figure 5 and Figure 6In step S103, a portion of the target power plane 105t is replaced with a reconstructed ground plane 103r, and the reconstructed ground plane 103r is electrically connected to the reference ground plane in the add-on wiring layer 102 through the return ground via 109 passing through the signal layer 104 to form a package substrate.

[0111] In some embodiments, the size of the reconstructed ground plane 103r is larger than the distribution size of the target signal line 104t, and the reconstructed ground plane 103r is electrically connected to the reference ground plane in the add-on wiring layer 102 through the return ground via 109. This improves the connectivity of the return path. Adjacent reference power planes and the reconstructed ground plane 103r are insulated from each other, specifically through a dielectric layer.

[0112] In some embodiments, there are multiple return ground vias 109; the multiple return ground vias 109 are located around the target signal line 104t. The return ground vias 109 are made of metal, and the return ground vias 109 do not have electrical contact with the target signal line 104t, that is, the return ground vias 109 and the target signal line 104t are insulated from each other, specifically, the insulation can be achieved through a dielectric layer.

[0113] In some embodiments, when the number of layers of the add-on wiring layer 102 is multi-layered, the target power plane 105t is at least one reference power plane among the different add-on wiring layers 102 that have the greatest impact on the far-end crosstalk resonance of the signal, and at least one target power plane 105t is replaced by a reconstructed ground plane 103r. Each reconstructed ground plane 103r is electrically connected to the reference ground plane in the add-on wiring layer 102 through a return ground via 109 passing through the signal layer 104 in the corresponding add-on wiring layer to form a package substrate.

[0114] In this application, the combination of the aforementioned steps S102 and S103 achieves the following technical effects:

[0115] (1) Solve the far-end crosstalk resonance: By performing local plane reconstruction on the target power plane 105t (replacing it with the reconstructed ground plane 103r), a partitioned structure with "power-ground hybrid reference" and "local dual ground reference" coexisting is formed, which improves the reconstructed electromagnetic field coupling path, optimizes signal return, reduces the far-end crosstalk value in the working frequency band, and improves signal integrity.

[0116] (2) Maintain power integrity: The reconstructed power plane can still serve as a low-impedance loop in the power network, the impedance curve of the power distribution network remains unchanged, and power indicators such as time-domain Ripple are not affected, thus avoiding power performance degradation due to signal optimization.

[0117] (3) Cost and performance balance: "Dual ground reference" is implemented only in local key areas, without increasing the number of substrate layers or changing the entire substrate to dual ground reference, thus meeting the cost reduction requirements of multilayer substrates.

[0118] Figure 8 The figure shows a comparison of simulation results of far-end crosstalk of the signal before and after using the method of this application. Figure 9 This is a comparison of simulation results for power integrity regarding signal far-end crosstalk between the system without local reconstruction (before modification) and after using this method (after modification). Figure 8 As shown, after using the method of this application, the far-end crosstalk resonance condition of the signal has changed, and the far-end crosstalk meets the requirement of less than -27 dB within the operating frequency band. Figure 9 As shown, after using the method of this application, the power network impedance curve after local reconstruction remains almost unchanged, and the power integrity such as the time-domain ripple is not affected in the operating state.

[0119] Some embodiments of this application also provide optimization devices for far-end crosstalk resonance in the package substrate, see reference. Figure 7 ,include:

[0120] An initial packaging substrate providing unit 301 is provided. The initial packaging substrate includes an add-on wiring layer 102 and a semiconductor chip 201 electrically connected to the add-on wiring layer 102. The add-on wiring layer 102 includes a signal layer 104 and a power plane layer 105 and a ground plane layer 103 located on opposite sides of the signal layer 104, respectively. The signal layer 104 includes a plurality of signal lines, the power plane layer 105 includes a plurality of reference power planes, and the ground plane layer 103 includes a reference ground plane. The semiconductor chip 201 is electrically connected to the corresponding signal lines in the add-on wiring layer 102.

[0121] The target power plane acquisition unit 302 is used to acquire the target power plane 105t, which is at least one reference power plane that has the greatest impact on the far-end crosstalk resonance of the signal.

[0122] The reconfiguration unit 302 is used to replace the target power plane 105t with the reconfigured ground plane 103r, and the reconfigured ground plane 103r is electrically connected to the reference ground plane in the add-on wiring layer 102 through the return ground via 109 through the signal layer 104.

[0123] In some embodiments, the target power plane acquisition unit 302 includes a selection unit, a replacement unit, a simulation result acquisition unit, and a judgment unit. The process of acquiring the target power plane 105t includes:

[0124] The selected unit selects multiple adjacent signal lines as target signal lines 104t, and uses the reference power plane directly opposite the target signal line 104t as the reference power plane to be tested.

[0125] The replacement unit replaces the reference power plane to be tested with the test ground plane, and the test ground plane is electrically connected to the reference ground plane in the same layer of the add-on wiring layer 102 through a test return ground via passing through the corresponding signal layer.

[0126] The simulation result acquisition unit obtains the first far-end crosstalk simulation result and the second far-end crosstalk simulation result. The first far-end crosstalk simulation result is the far-end crosstalk simulation result before the reference power plane under test is replaced with the test ground plane, and the second far-end crosstalk simulation result is the far-end crosstalk simulation result after the reference power plane under test is replaced with the test ground plane.

[0127] The judgment unit determines whether there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result. If there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result, the corresponding reference power plane to be tested is taken as the target power plane 105t.

[0128] In some embodiments, the simulation results obtained by the simulation result acquisition unit include the first far-end crosstalk simulation results and the second far-end crosstalk simulation results, which include far-end crosstalk resonance curves.

[0129] In some embodiments, the determination unit determines whether there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result, including: determining whether there is a difference between the far-end crosstalk resonance curves corresponding to the first far-end crosstalk simulation result and the second far-end crosstalk simulation result.

[0130] If the far-end crosstalk simulation results and the far-end crosstalk simulation results are different, then the corresponding reference power plane to be tested will be taken as the target power plane 105t.

[0131] In some embodiments, when there are multiple reference power planes directly opposite the target signal line 104t, the selection unit uses all of the multiple reference power planes as reference power planes to be tested, thereby obtaining multiple reference power planes to be tested.

[0132] The replacement unit sequentially replaces each reference power plane under test with a test ground plane, the simulation result acquisition unit sequentially obtains the first far-end crosstalk simulation result and the second far-end crosstalk simulation result, and the judgment unit sequentially judges whether there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result.

[0133] In some embodiments, the size of the reconstructed ground plane 103r is larger than the distribution size of the target signal line 104t.

[0134] In some embodiments, the target signal line 104t includes multiple signal lines for transmitting a complete byte of data, or the target signal line 104t includes multiple signal lines for serving as a complete transmission subchannel.

[0135] In some embodiments, the target signal line 104t includes all signal lines necessary for transmitting a complete byte of data and for managing and synchronizing the data transmission.

[0136] In some embodiments, a complete transmission subchannel includes a complete byte channel, an error correction code signal channel, and address and command signal channels.

[0137] In some embodiments, the number of return ground holes 109 and test return ground holes is multiple;

[0138] Multiple return ground vias 109 and multiple test return ground vias are located around the target signal line 104t.

[0139] This application also provides a packaging substrate, in conjunction with reference to the following embodiments. Figure 5 and Figure 6 ,include:

[0140] The addition wiring layer 102 and the semiconductor chip 201 electrically connected to the addition wiring layer 102 are provided. The addition wiring layer 102 includes a signal layer 104 and a power plane layer 105 and a ground plane layer 103 located on opposite sides of the signal layer 104, respectively.

[0141] The signal layer 104 includes several signal lines, including the target signal line 104t;

[0142] The power plane layer 105 includes at least one reference power plane and at least one reconfigured ground plane 103r. The reconfigured ground plane 103r is located on one side of the reference power plane and is directly opposite to the target signal line 104t in the signal layer 104.

[0143] The ground plane layer 103 includes a reference ground plane, and the reconstructed ground plane 103r is electrically connected to the reference ground plane in the add-on wiring layer 102 through the return ground via 109 passing through the signal layer 104.

[0144] In some embodiments, the number of layers in the additional wiring layer 102 is a single layer or multiple layers;

[0145] When the number of layers of the add-on wiring layer 102 is multiple, the corresponding signal lines in two adjacent add-on wiring layers 102 are electrically connected, and the semiconductor chip 201 is electrically connected to the corresponding signal line in the topmost add-on wiring layer 102.

[0146] In some embodiments, when the number of layers of the add-on wiring layer 102 is multiple, the target signal line is located in the signal layer 104 of at least one add-on wiring layer 102; and each of the power plane layers 105 of at least one add-on wiring layer 102 having the target signal line has a reconfigured ground plane 103r.

[0147] In some embodiments, the initial packaging substrate further includes a core board 101, which includes an opposing upper surface and a lower surface. The core board 101 has a plurality of through-hole interconnect structures 108 penetrating the upper and lower surfaces of the core board 101. A portion of the signal lines in the augmentation wiring layer 102 that contacts the core board 101 are electrically connected to the corresponding through-hole interconnect structures 108.

[0148] The additional wiring layer 102 is located on the upper or lower surface of the core board, or part of the additional wiring layer 102 is located on the upper surface of the core board 101 and part of the additional wiring layer 102 is located on the lower surface of the chip.

[0149] In some embodiments, the target signal line 104t includes multiple signal lines for transmitting a complete byte of data, or the target signal line 104t includes multiple signal lines for serving as a complete transmission subchannel.

[0150] In some embodiments, adjacent reference power planes are insulated from each other, and adjacent reference power planes are insulated from the reconfigured ground plane 103r.

[0151] The return ground hole 109 is made of metal and is insulated from the target signal line 104t.

[0152] There are multiple return ground holes 109; multiple return ground holes 109 are located around the target signal line 104t.

[0153] This application also provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the method described above.

[0154] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the aforementioned method.

[0155] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, graphics processors, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these. The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0156] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0157] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0158] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An optimization method for signal far-end crosstalk resonance in a packaging substrate, characterized in that, include: An initial packaging substrate is provided, the initial packaging substrate including an add-on wiring layer and a semiconductor chip electrically connected to the add-on wiring layer, the add-on wiring layer including a signal layer and a power plane layer and a ground plane layer respectively located on opposite sides of the signal layer, the signal layer including a plurality of signal lines, the power plane layer including a plurality of reference power planes, the ground plane layer including a reference ground plane, and the semiconductor chip electrically connected to the corresponding signal lines in the add-on wiring layer; Obtain the target power plane, which is at least one reference power plane that has the greatest impact on the far-end crosstalk resonance of the signal. A portion of the target power plane is replaced with a reconstructed ground plane, and the reconstructed ground plane is electrically connected to the reference ground plane through a return ground via through the signal layer to form a package substrate.

2. The optimization method for signal far-end crosstalk resonance in the packaging substrate according to claim 1, characterized in that, The number of layers in the additional wiring layer can be a single layer or multiple layers; When the number of the add-on wiring layers is multiple, the corresponding signal lines in two adjacent add-on wiring layers are electrically connected, and the semiconductor chip is electrically connected to the corresponding signal line in the topmost add-on wiring layer. When the number of layers of the add-on wiring layer is multi-layered, the target power plane is at least one reference power plane among the different add-on wiring layers that have the greatest impact on the far-end crosstalk resonance of the signal, and at least one of the target power planes is replaced with a reconstructed ground plane. Each reconstructed ground plane is electrically connected to the reference ground plane in the add-on wiring layer through a return ground via of the signal layer in the corresponding add-on wiring layer to form a package substrate.

3. The optimization method for signal far-end crosstalk resonance in the packaging substrate according to claim 2, characterized in that, When the number of layers of the add-on wiring layer is multiple, the corresponding signal lines in two adjacent add-on wiring layers are electrically connected through a via connection structure that passes through the power plane layer and the ground plane layer. The semiconductor chip includes a plurality of bumps, each of which is electrically connected to a corresponding via connection structure in the augmentation wiring layer. The initial packaging substrate further includes a core board, which includes an upper surface and a lower surface opposite to each other. The core board has a plurality of through-hole interconnect structures penetrating the upper and lower surfaces of the core board. Some signal lines in the augmentation wiring layer that are in contact with the core board are electrically connected to the corresponding through-hole interconnect structures. The added wiring layer is located on the upper or lower surface of the core board, or part of the added wiring layer is located on the upper surface of the core board and part of the added wiring layer is located on the lower surface of the chip.

4. The optimization method for signal far-end crosstalk resonance in the packaging substrate according to claim 2, characterized in that, The process of obtaining the target power plane includes: Select multiple adjacent signal lines as target signal lines; The reference power plane that is directly opposite the target signal line is used as the reference power plane to be tested; The reference power plane to be tested is replaced with a test ground plane, and the test ground plane is electrically connected to the reference ground plane in the same layer of the add-on wiring layer through a test return ground via the corresponding signal layer. Obtain the first far-end crosstalk simulation result and the second far-end crosstalk simulation result. The first far-end crosstalk simulation result is the far-end crosstalk simulation result before the reference power plane to be tested is replaced with the test ground plane, and the second far-end crosstalk simulation result is the far-end crosstalk simulation result after the reference power plane to be tested is replaced with the test ground plane. Determine whether there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result. If there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result, then the corresponding reference power plane to be tested is taken as the target power plane.

5. The method for optimizing signal far-end crosstalk resonance in the packaging substrate according to claim 4, characterized in that, The simulation results of the first and second far-end crosstalk include the far-end crosstalk resonance curves.

6. The optimization method for signal far-end crosstalk resonance in the packaging substrate according to claim 5, characterized in that, Determining whether there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result includes: determining whether there are differences in the far-end crosstalk resonance curves corresponding to the first far-end crosstalk simulation result and the second far-end crosstalk simulation result; If the far-end crosstalk simulation results and the far-end crosstalk simulation results correspond to different far-end crosstalk resonance curves, then the corresponding reference power plane to be tested shall be taken as the target power plane.

7. The method for optimizing signal far-end crosstalk resonance in a packaging substrate according to claim 6, characterized in that, When there are multiple reference power planes facing the target signal line, all of the multiple reference power planes are used as reference power planes to be tested, and multiple reference power planes to be tested are obtained. Each of the reference power planes to be tested is replaced with the test ground plane in sequence, and the first far-end crosstalk simulation result and the second far-end crosstalk simulation result are obtained in sequence. Then, it is determined whether there is a difference between the first far-end crosstalk simulation result and the second far-end crosstalk simulation result.

8. The method for optimizing signal far-end crosstalk resonance in the packaging substrate according to claim 4, characterized in that, The size of the reconstructed ground plane is larger than the distribution size of the target signal line.

9. The method for optimizing signal far-end crosstalk resonance in a packaged substrate according to claim 8, characterized in that, The target signal line includes multiple signal lines for transmitting a complete byte of data, or the target signal line includes multiple signal lines for serving as a complete transmission sub-channel.

10. The method for optimizing signal far-end crosstalk resonance in a packaged substrate according to claim 9, characterized in that, The target signal line includes all the signal lines necessary for transmitting a complete byte of data and for managing and synchronizing that data transmission.

11. The method for optimizing signal far-end crosstalk resonance in a packaged substrate according to claim 9, characterized in that, A complete transmission subchannel includes a complete byte channel, an error correction code signal channel, and address and command signal channels.

12. The method for optimizing signal far-end crosstalk resonance in a packaged substrate according to claim 4, characterized in that, The adjacent reference power planes are insulated from each other, and the adjacent reference power planes and the reconstructed ground plane are insulated from each other. The return ground hole is made of metal and is insulated from the target signal line. The number of the return ground vias and the number of the test return ground vias are multiple; the multiple return ground vias and the multiple test return ground vias are located around the target signal line.

13. A packaging substrate, characterized in that, include: The addition wiring layer and the semiconductor chip electrically connected to the addition wiring layer, wherein the addition wiring layer includes a signal layer and a power plane layer and a ground plane layer located on opposite sides of the signal layer, respectively. The signal layer includes a plurality of signal lines, and the signal lines include target signal lines; The power plane layer includes at least one reference power plane and at least one reconfigurable ground plane, wherein the reconfigurable ground plane is located on one side of the reference power plane and is directly opposite the target signal line in the signal layer; The ground plane layer includes a reference ground plane, and the reconstructed ground plane is electrically connected to the reference ground plane through a return ground via passing through the signal layer.

14. The packaging substrate according to claim 13, characterized in that, The number of layers in the additional wiring layer can be a single layer or multiple layers; When the number of the add-on wiring layers is multi-layered, the corresponding signal lines in two adjacent add-on wiring layers are electrically connected, and the semiconductor chip is electrically connected to the corresponding signal line in the topmost add-on wiring layer.

15. The packaging substrate according to claim 14, characterized in that, When the number of layers of the add-on wiring layer is multiple, the target signal line is located in the signal layer of at least one add-on wiring layer; the reconstructed ground plane is present in the power plane layer of at least one add-on wiring layer having the target signal line.

16. The packaging substrate according to claim 14, characterized in that, The initial packaging substrate further includes a core board, which includes an upper surface and a lower surface opposite to each other. The core board has a plurality of through-hole interconnect structures penetrating the upper and lower surfaces of the core board. Some signal lines in the augmentation wiring layer that are in contact with the core board are electrically connected to the corresponding through-hole interconnect structures. The added wiring layer is located on the upper or lower surface of the core board, or part of the added wiring layer is located on the upper surface of the core board and part of the added wiring layer is located on the lower surface of the chip.

17. The packaging substrate according to claim 13 or 14, characterized in that, The target signal line includes multiple signal lines for transmitting a complete byte of data, or the target signal line includes multiple signal lines for serving as a complete transmission sub-channel.

18. The packaging substrate according to claim 13 or 14, characterized in that, The adjacent reference power planes are insulated from each other, and the adjacent reference power planes and the reconstructed ground plane are insulated from each other. The return ground hole is made of metal and is insulated from the target signal line. The number of return ground holes is multiple; the multiple return ground holes are located around the target signal line.

19. A computer device, characterized in that, The method includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method according to any one of claims 1-12.

20. A computer-readable storage medium, characterized in that, It stores a computer program thereon, which, when executed by a processor, implements the steps of the method described in any one of claims 1-12.

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