Fast charging chip cascade circuit and control method thereof

Abstract

The embodiment of the invention discloses a fast charging chip cascade circuit and a control method thereof, and relates to the technical field of switching power supplies, the fast charging chip cascade circuit comprises an AC / DC conversion loop and at least two fast charging chips; the fast charging chip comprises a logic control module, a cascade communication module and a constant voltage loop. The cascade communication module is provided with a cascade pin, a signal receiving pin and a signal sending pin, and the cascade pins of all the quick charge chips are electrically connected; the input end of the logic control module is electrically connected with a signal receiving pin and a signal sending pin in a corresponding fast charging chip, the output end of the logic control module is electrically connected with the constant voltage loop, and the constant voltage loop is electrically connected with the alternating current and direct current conversion loop. The voltage regulation conflict in the cascade state is effectively avoided, and the voltage regulation accuracy of the output voltage is improved.

Description

Technical Field

[0001] This invention relates to the field of fast charging equipment technology, and in particular to a fast charging chip cascade circuit and its control method. Background Technology

[0002] In traditional fast charging devices, there is a lack of effective state interaction and collaborative control mechanisms between cascaded fast charging chips. When there are conflicts in the locked states of fast charging chips, problems such as voltage regulation disorder and unstable output voltage are likely to occur. This makes it impossible to accurately adapt to the voltage requirements of different charging scenarios, affecting fast charging efficiency and charging safety. Summary of the Invention

[0003] The technical problem to be solved by the embodiments of the present invention is that there is voltage regulation conflict in the existing fast charging chip cascading scheme. Specifically, in the scenario of fast charging chip cascading, the constant voltage closed loops of each level of the chip interfere with each other, causing one end to be restrained by other end loops when it needs to boost voltage and thus unable to boost voltage independently, thereby failing to meet the single-end fast charging requirements.

[0004] To address the aforementioned problems, this invention discloses a fast-charging chip cascade circuit and its control method. This effectively avoids voltage regulation conflicts in the cascaded state and improves the accuracy of output voltage regulation.

[0005] On one hand, the present invention provides a fast charging chip cascade circuit, which includes an AC / DC conversion loop and at least two fast charging chips; each fast charging chip includes a logic control module, a cascaded communication module, and a constant voltage loop; the cascaded communication module is provided with cascade pins, signal receiving pins, and signal transmitting pins, and the cascade pins of all the fast charging chips are electrically connected; the input terminal of the logic control module is electrically connected to the signal receiving pin and the signal transmitting pin of the corresponding fast charging chip, respectively, and the output terminal of the logic control module is electrically connected to the constant voltage loop, which is electrically connected to the AC / DC conversion loop.

[0006] A further technical solution is that the cascaded communication module also includes a voltage detection unit and a switch. The voltage detection unit is electrically connected to the cascade pins and the signal receiving pins of the corresponding fast charging chip, respectively. The switch is electrically connected to the cascade pins, the signal transmitting pins, and the power supply of the corresponding fast charging chip, respectively.

[0007] A further technical solution is that the constant voltage loop includes an operational transconductance amplifier and a MOSFET, and the MOSFET is electrically connected to the operational transconductance amplifier and the AC / DC conversion loop, respectively.

[0008] A further technical solution is that the operational transconductance amplifier is provided with an AC / DC conversion enable control terminal, which is electrically connected to the output terminal of the logic control module in the corresponding fast charging chip.

[0009] A further technical solution is that the operational transconductance amplifier is also provided with an output terminal, and the output terminal of the operational transconductance amplifier is electrically connected to the control terminal of the MOS transistor.

[0010] A further technical solution is that the fast charging chip integrates a feedback resistor, which is electrically connected to the constant voltage loop and the AC / DC conversion loop respectively.

[0011] A further technical solution is that the operational transconductance amplifier is further provided with a first input terminal and a second input terminal, the first input terminal being electrically connected to the feedback resistor, and the second input terminal being electrically connected to the reference voltage terminal inside the fast charging chip.

[0012] On the other hand, the present invention also provides a control method for a fast charging chip cascade circuit as described in any of the above embodiments, the control method for the fast charging chip cascade circuit comprising: The built-in logic control module collects the input signals from the signal receiving pins and the output signals from the signal transmitting pins within the corresponding fast charging chip. The AC / DC conversion loop is driven to output a first voltage or a second voltage based on the input signal and the output signal.

[0013] Compared with the prior art, the technical effects achieved by the embodiments of the present invention include: This invention enables state interaction between multiple fast charging chips through a cascaded communication module. Combined with a logic control module, it precisely adjusts the output voltage based on the locking status of the fast charging chip itself and adjacent chips, effectively avoiding voltage regulation conflicts in a cascaded configuration, improving voltage regulation accuracy, and preventing independent voltage boosting by other loops when one end needs boosting, thus meeting single-end fast charging requirements. Simultaneously, it adapts to both current-sinking and reference-based voltage regulation structures, broadening the circuit's application scenarios and ensuring high efficiency and safety during fast charging. By integrating a feedback resistor within the fast charging chip, it eliminates the need for an external feedback resistor, reducing the number of components, lowering hardware costs, and simplifying circuit layout. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A structural block diagram of a fast charging chip cascade circuit provided in an embodiment of the present invention; Figure 2 A schematic diagram of a cascaded communication module provided in an embodiment of the present invention; Figure 3 A schematic diagram of a fast charging chip provided in an embodiment of the present invention; Figure 4 A schematic diagram of a fast charging chip cascade circuit provided in an embodiment of the present invention; Figure 5 A schematic diagram of another fast charging chip cascade circuit provided in an embodiment of the present invention; Figure 6 A flowchart illustrating a control method for a fast charging chip cascade circuit provided in an embodiment of the present invention; Figure 7 A schematic diagram of a sub-flow of a control method for a fast charging chip cascade circuit provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the logic control method of the logic control module provided in an embodiment of the present invention.

[0016] Figure Labels 1. AC / DC conversion loop; 2. Fast charging chip; 21. Logic control module; 22. Cascaded communication module; 23. Constant voltage loop. Detailed Implementation

[0017] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Similar component reference numerals in the drawings represent similar components. Obviously, the embodiments described below are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0018] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0019] It should also be understood that the terminology used in this specification of embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the invention. As used in this specification of embodiments of the invention and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0020] See Figure 1-5 This invention provides a fast-charging chip cascade circuit. The fast-charging chip cascade circuit includes an AC / DC conversion loop 1 and at least two fast-charging chips 2. Each fast-charging chip 2 includes a logic control module 21, a cascaded communication module 22, and a constant voltage loop 23. The cascaded communication module 22 has cascade pins, signal receiving pins, and signal transmitting pins, and all cascade pins of the fast-charging chips 2 are electrically connected. The input terminal of the logic control module 21 is electrically connected to the signal receiving pin and signal transmitting pin of the corresponding fast-charging chip 2, respectively. The output terminal of the logic control module 21 is electrically connected to the constant voltage loop 23, and the constant voltage loop 23 is electrically connected to the AC / DC conversion loop 1. Specific descriptions of each component are as follows: In this embodiment, the AC / DC conversion loop 1 is used to convert the 220V AC power input from the power grid into DC voltage, providing a basic voltage source for subsequent voltage regulation; the fast charging chip 2 integrates logic control, cascade communication, and constant voltage regulation functions, and multiple fast charging chips 2 are cascaded to meet the voltage regulation needs of various scenarios; the logic control module 21 adopts an MCU microcontroller unit, which serves as the "control core" of the fast charging chip 2, and is responsible for collecting pin signals and driving the constant voltage loop 23 to work; the cascade communication module 22 realizes the status interaction between at least two fast charging chips 2, the LINK pin is the cascade signal transmission channel, the XPI pin is used to receive status signals from other fast charging chips 2, and the XPO pin is used to send its own status signal; the constant voltage loop 23 is used to perform voltage regulation, receive the control signals from the logic control module 21, and realize precise and stable control of the output voltage.

[0021] Specifically, taking the cascaded connection of two fast charging chips as an example, the cascaded fast charging chip circuit includes an AC / DC conversion loop 1 and two fast charging chips 2, chip A and chip B. Each fast charging chip 2 has a built-in logic control module 21, a cascaded communication module 22, and a constant voltage loop 23. The cascaded communication module 22 is equipped with a cascade pin LINK, a signal receiving pin XPI, and a signal transmitting pin XPO. The LINK pin of chip A and the LINK pin of chip B are directly electrically connected through wires to form a cascaded communication link. The input terminal of the logic control module 21 of chip A is electrically connected to its own XPI pin, XPO pin, and the signal feedback terminal of the AC / DC conversion loop 1, and the output terminal is electrically connected to its own constant voltage loop 23. Understandably, the connection relationship of the logic control module 21 of chip B is the same as that of chip A.

[0022] In a specific example, the logic control module 21 of the fast charging chip 2 uses the logic control method based on the XPI and XPO signals. (See [link to example]). Figure 8 When the local fast charging chip 2 is in 00 mode, it indicates that neither the local fast charging chip 2 nor the cascaded peer fast charging chip 2 is locked, or there is no interconnected fast charging chip 2. At this time, the fast charging chip 2 can work in normal mode, and the AC / DC output ( Figure 4, Figure 5 The VIN value will be controlled at 5V. When the local fast charging chip 2 is in mode 10, it indicates that local fast charging chip 2 is locked, and the cascaded peer fast charging chip 2 is unlocked. At this time, local fast charging chip 2 can freely boost the voltage for fast charging. When local fast charging chip 2 is in mode 01, it indicates that local fast charging chip 2 is unlocked, the cascaded peer fast charging chip 2 is locked, and the cascaded peer fast charging chip 2 may need to control the voltage boost of fast charging chip 2. At this time, the EN_ACDC of local fast charging chip 2 will be pulled low to break the loop, and the output voltage will be controlled by the cascaded peer fast charging chip 2. In particular, if local fast charging chip 2 has overvoltage protection or other functions, it also needs to be controlled by EN_ACDC to prevent accidental triggering of the internal overvoltage protection. When local fast charging chip 2 is in mode 11, it indicates that both local fast charging chip 2 and the cascaded peer fast charging chip 2 are locked. At this time, the output of both fast charging chips 2 will maintain the default operating mode of 5V.

[0023] In a specific example, when chip A is in 00 mode, chip A is not locked and chip B is not locked either; when chip A is in 01 mode, chip A is not locked and chip B is locked; when chip A is in 10 mode, chip A is locked and chip B is not locked; when chip A is in 11 mode, chip A is locked and chip B is locked. Understandably, when chip B is in the corresponding mode, its logic is the same as that of chip A.

[0024] The cascaded communication module 22 enables status interaction between multiple fast charging chips 2. In conjunction with the logic control module 21, the output voltage is precisely adjusted according to the locking status of the local fast charging chip 2 and the cascaded peer fast charging chips 2. This effectively avoids voltage regulation conflicts in the cascaded state, improves voltage regulation accuracy, and prevents the independent voltage boosting that can be hindered by other peer loops when one end needs to boost voltage, thus meeting the single-end fast charging requirements. At the same time, it is compatible with both sink current voltage regulation and reference voltage regulation structures, broadening the application scenarios of the circuit and ensuring the efficiency and safety of the fast charging process.

[0025] See also Figure 1-5 In this embodiment, the cascaded communication module 22 further includes a voltage detection unit and a switch. The voltage detection unit is electrically connected to the cascade pin and the signal receiving pin of the corresponding fast charging chip 2, respectively. The switch is electrically connected to the cascade pin, the signal transmitting pin and the power supply of the corresponding fast charging chip 2, respectively.

[0026] In this embodiment, the voltage detection unit includes a voltage comparator, for example, with a threshold voltage set to 1.8V, used to detect voltage changes on the LINK pin and convert the analog voltage signal into a digital level signal. The switch includes an NMOS transistor switch with an on-resistance of less than 1Ω and a fast response speed, used to control the connection and disconnection of the power supply and the LINK pin, thus enabling the transmission of status signals. The power supply VCC is the internal regulated power supply of the fast charging chip 2, providing a stable power supply to the switch and ensuring the reliability of status signal transmission.

[0027] Specifically, the cascaded communication module 22 includes a voltage detection unit and a switch. One end of the voltage detection unit is electrically connected to the LINK pin of chip A, and the other end is electrically connected to the XPI pin of chip A. One end of the switch is electrically connected to the LINK pin of chip A, and the other end is electrically connected to the XPO pin of chip A. The power supply end of the switch is electrically connected to the 3.3V power supply VCC (not shown in the figure) inside the fast charging chip 2. Understandably, the structure of the cascaded communication module 22 of chip B is completely identical to that of chip A. When the XPO pin of chip A outputs a high level (locked state, this signal is issued by the fast charging protocol when fast charging is detected), the switch is turned on, and the 3.3V power supply is transmitted to the LINK pin through the switch, causing the voltage of the LINK pin to rise. After the voltage detection unit of chip B detects the change in the voltage of the LINK pin, it transmits the signal to the XPI pin to realize status feedback.

[0028] By combining the voltage detection unit with the switch, accurate detection and signal interaction of the cascaded state are achieved, solving the problem of ambiguous state judgment in traditional cascaded circuits. The modular design makes the function of the cascaded communication module 22 clearer and the signal transmission path clearer, improving the accuracy and response speed of state interaction between the two fast charging chips.

[0029] Furthermore, the constant voltage loop 23 includes an operational transconductance amplifier and a MOSFET, the MOSFET being electrically connected to the operational transconductance amplifier and the AC / DC conversion loop 1, respectively.

[0030] In this embodiment, the operational transconductance amplifier is used to convert voltage difference into current; the MOSFET is used to receive the drive signal from the operational transconductance amplifier and adjust the circuit impedance.

[0031] Specifically, the constant voltage loop 23 of chip A includes an operational transconductance amplifier and a MOSFET. The drain of the MOSFET is electrically connected to the voltage regulation terminal of AC / DC conversion loop 1, the source is grounded, and the gate is electrically connected to the output terminal of the operational transconductance amplifier. The power supply terminal of the operational transconductance amplifier is electrically connected to the internal 5V power supply of fast charging chip 2, and the ground terminal is grounded. The constant voltage loop 23 of chip B also includes an operational transconductance amplifier and a MOSFET, with the same connection relationship as chip A. The operational transconductance amplifier converts the voltage difference into an output current, driving the MOSFET to adjust its conduction state, thereby changing the output voltage of AC / DC conversion loop 1.

[0032] The combination of operational transconductance amplifier and MOSFET achieves efficient voltage regulation, solving the problems of low voltage regulation accuracy and slow response in traditional constant voltage circuits; standardized component selection and connection methods improve circuit compatibility and mass production feasibility.

[0033] Furthermore, the operational transconductance amplifier is provided with an AC / DC conversion enable control terminal, which is electrically connected to the output terminal of the logic control module 21 in the corresponding fast charging chip 2.

[0034] In this embodiment, the AC / DC conversion enable control terminal is the function enable pin of the operational transconductance amplifier, which is active high (start) and inactive low (off), and is used to receive control signals from the logic control module 21.

[0035] Specifically, the operational transconductance amplifier has an AC / DC conversion enable control terminal, which is electrically connected to the output terminal of the logic control module 21 of chip A; the operational transconductance amplifier also has an AC / DC conversion enable control terminal, which is electrically connected to the output terminal of the logic control module 21 of chip B. When the logic control module 21 outputs a high level, the AC / DC conversion enable control terminal receives a high level, and the operational transconductance amplifier starts working; when the logic control module 21 outputs a low level, the AC / DC conversion enable control terminal receives a low level, and the operational transconductance amplifier stops working.

[0036] The enable control terminal enables precise start-stop control of the operational transconductance amplifier, allowing the constant voltage loop 23 to flexibly switch operating modes according to the cascade state. This solves the problems of power consumption waste and regulation conflict caused by the continuous operation of the traditional constant voltage loop 23. The enable control logic is simple and reliable, improving the energy efficiency ratio of the circuit.

[0037] Furthermore, the operational transconductance amplifier also has an output terminal, which is electrically connected to the control terminal of the MOS transistor.

[0038] Specifically, the output of the operational transconductance amplifier is directly electrically connected to the gate of the MOSFET via a wire.

[0039] Furthermore, the fast charging chip 2 integrates a feedback resistor, which is electrically connected to the constant voltage loop 23 and the AC / DC conversion loop 1, respectively.

[0040] In this embodiment, the feedback resistor is used to divide the output voltage of the AC-DC conversion loop 1 to generate a voltage sampling signal. The feedback resistor has a voltage divider structure. By proportionally allocating the pull-up and pull-down resistors, the high voltage is converted into a low voltage signal that can be detected by the constant voltage loop 23.

[0041] Specifically, chip A integrates a feedback resistor, which is a voltage divider resistor structure including a series pull-up resistor and a pull-down resistor. One end of the pull-up resistor is electrically connected to the output terminal of AC / DC conversion loop 1, and one end of the pull-down resistor is grounded. The intermediate node is electrically connected to the signal input terminal of constant voltage loop 23. Chip B integrates a feedback resistor, and its structure and parameters are the same as those of the feedback resistor in chip A.

[0042] By integrating the feedback resistor into the fast charging chip 2, the external feedback resistor in the traditional solution is eliminated, reducing the number of components, lowering hardware costs and layout space; the integrated resistor has higher precision and stability, improving the accuracy of voltage sampling and providing a guarantee for precise voltage regulation.

[0043] Furthermore, the operational transconductance amplifier also has a first input terminal and a second input terminal. The first input terminal is electrically connected to the feedback resistor, and the second input terminal is electrically connected to the reference voltage terminal inside the fast charging chip 2.

[0044] In this embodiment, the first input terminal is a non-inverting input terminal, used to receive the voltage sampling signal output by the feedback resistor, providing an actual voltage reference for voltage comparison. The second input terminal is an inverting input terminal, used to receive the reference voltage signal, providing a target voltage reference for voltage comparison. The reference voltage terminal provides a stable reference voltage.

[0045] Specifically, the first input terminal of the operational transconductance amplifier is electrically connected to the intermediate node of the feedback resistor to receive the voltage sampling signal after voltage division; the second input terminal is electrically connected to the reference voltage terminal VREF inside chip A.

[0046] The direct input of the voltage sampling signal and the reference voltage signal enables the operational transconductance amplifier to accurately detect the voltage difference, solving the voltage regulation deviation problem caused by signal transmission loss in traditional voltage regulation circuits; the stable reference voltage ensures the accuracy of voltage comparison and improves the overall voltage regulation accuracy.

[0047] See Figure 6 The present invention also provides a control method for a fast charging chip cascade circuit as described in any of the above embodiments, the control method for the fast charging chip cascade circuit comprising the following steps S101-S102: S101 collects the input signal from the signal receiving pin and the output signal from the signal transmitting pin within the corresponding fast charging chip 2 through its built-in logic control module 21.

[0048] In this embodiment, the logic control module 21 acquires the level signals of the XPI and XPO pins through the built-in ADC module.

[0049] Specifically, the logic control module 21 of chip A collects the input signal of its own XPI pin (the input signal of the XPI pin is emitted from the XPO pin of chip B via the LINK pin) and the output signal of its own XPO pin in real time; the logic control module 21 of chip B collects the input signal of its own XPI pin (the input signal of the XPI pin is emitted from the XPO pin of chip A via the LINK pin) and the output signal of its own XPO pin in real time.

[0050] S102, drive the AC / DC conversion loop 1 to output a first voltage or a second voltage according to the input signal and the output signal.

[0051] In this embodiment, the logic control module 21 outputs a corresponding control signal to the constant voltage loop 23 based on the signal combination judgment result, thereby adjusting the output voltage of the AC-DC conversion loop 1.

[0052] Specifically, the logic control module 21, based on the two sets of signals collected, controls the working state of the constant voltage loop 23 to drive the AC-DC conversion loop 1 to output the first voltage (5V) or the second voltage (10V).

[0053] Furthermore, the second voltage is greater than the first voltage, see [reference needed]. Figure 7 The above step S102 includes steps S201-S205: S201, determine whether the output signal is locked.

[0054] S202, if the output signal is not locked, drive the AC / DC conversion loop 1 to output the first voltage.

[0055] S203, if the output signal is locked, determine whether the input signal is locked.

[0056] S204, if the output signal is locked and the input signal is locked, drive the AC / DC conversion loop 1 to output the first voltage.

[0057] S205, if the output signal is locked and the input signal is not locked, drive the AC / DC conversion loop 1 to output the second voltage.

[0058] In this embodiment, a signal lockout indicates that the pin outputs a high level (3.3V), signifying that the fast charging chip 2 needs to perform boost regulation or maintain a specific operating state. A signal unlocked indicates that the pin outputs a low level (0V), signifying that the fast charging chip 2 maintains its default operating state.

[0059] Specifically, the first voltage is set to 5V, and the second voltage is set to 10V. When the XPO pin output signal of chip A is unlocked (low level), the logic control module 21 drives the AC / DC conversion loop 1 to output 5V; when the XPO pin output signal of chip A is locked (high level), and the XPI pin input signal is locked (high level, i.e., chip B is locked), the logic control module 21 drives the AC / DC conversion loop 1 to output 5V; when the XPO pin output signal of chip A is locked (high level), and the XPI pin input signal is unlocked (low level, i.e., chip B is not locked), the logic control module 21 drives the AC / DC conversion loop 1 to output 10V. The voltage regulation logic of chip B is the same as that of chip A.

[0060] The voltage regulation rules for the locked state of fast charging chip 2 cover all core operating conditions in cascaded scenarios, effectively avoiding voltage regulation conflicts between fast charging chips 2; the settings of the first voltage and the second voltage adapt to the needs of conventional fast charging, improving the practicality and versatility of the method.

[0061] Furthermore, this control method is applicable to any of the following circuit structures: Method 1: See Figure 4 When the constant voltage loop 23 adopts the pumping current voltage regulation structure, the first voltage or the second voltage can be driven to the AC-DC conversion loop 1 by adjusting the pumping current and combining the voltage division effect of the feedback resistor.

[0062] Method 2: See Figure 5 When the constant voltage loop 23 adopts a reference voltage regulation structure, the AC-DC conversion loop 1 is driven to output the first voltage or the second voltage by adjusting the internal reference voltage and cooperating with the voltage division effect of the feedback resistor.

[0063] Specifically, the pump-current voltage regulation structure adjusts the current to change the circuit load characteristics, thereby achieving voltage regulation, and is suitable for high-current fast charging scenarios. The reference voltage regulation structure adjusts the reference voltage to change the target voltage reference, thereby achieving voltage regulation, and is suitable for high-precision voltage regulation scenarios.

[0064] It is compatible with two mainstream voltage regulation structures, which broadens the application scenarios of the circuit. Users can choose the appropriate voltage regulation method according to their actual needs. Both methods are combined with the voltage division effect of feedback resistors to ensure voltage regulation accuracy and solve the problem of poor adaptability of traditional voltage regulation methods.

[0065] Furthermore, when the other fast charging chips 2 are locked, the input signal is locked.

[0066] In this embodiment, there is an application scenario where multiple fast charging chips are cascaded together.

[0067] Specifically, taking chips A, B, and C as an example, when the logic control module 21 of chip A detects that the input signal of its own XPI pin is high, it determines that the other fast charging chips 2 (chip B and / or chip C) are in a locked state; when it detects that the input signal of the XPI pin is low, it determines that neither chip B nor chip C is locked.

[0068] The judgment logic is simple and reliable with a fast response speed, which solves the problem of ambiguous state judgment of fast charging chip 2 in traditional cascaded circuits; the unified judgment standard ensures the coordination and consistency among multiple fast charging chips 2, and provides accurate state basis for precise voltage regulation.

[0069] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0070] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0071] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0072] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0073] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0074] The above description describes specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A fast charging chip cascade circuit, characterized in that, Includes an AC / DC conversion loop and at least two fast charging chips; The fast charging chip includes a logic control module, a cascaded communication module, and a constant voltage loop. The cascaded communication module is provided with cascaded pins, signal receiving pins and signal transmitting pins, and all the cascaded pins of the fast charging chips are electrically connected; The input terminal of the logic control module is electrically connected to the signal receiving pin and the signal transmitting pin in the corresponding fast charging chip, respectively. The output terminal of the logic control module is electrically connected to the constant voltage loop, and the constant voltage loop is electrically connected to the AC-DC conversion loop.

2. The fast charging chip cascade circuit according to claim 1, characterized in that, The cascaded communication module also includes a voltage detection unit and a switch. The voltage detection unit is electrically connected to the cascade pins and the signal receiving pins of the corresponding fast charging chip, respectively. The switch is electrically connected to the cascade pins, the signal transmitting pins, and the power supply of the corresponding fast charging chip, respectively.

3. The fast charging chip cascade circuit according to claim 1, characterized in that, The constant voltage loop includes an operational transconductance amplifier and a MOSFET, and the MOSFET is electrically connected to the operational transconductance amplifier and the AC / DC conversion loop, respectively.

4. The fast charging chip cascade circuit according to claim 3, characterized in that, The operational transconductance amplifier is provided with an AC / DC conversion enable control terminal, which is electrically connected to the output terminal of the logic control module in the corresponding fast charging chip.

5. The fast charging chip cascade circuit according to claim 3, characterized in that, The operational transconductance amplifier also has an output terminal, which is electrically connected to the control terminal of the MOS transistor.

6. The fast charging chip cascade circuit according to claim 3, characterized in that, The fast charging chip integrates a feedback resistor, which is electrically connected to the constant voltage loop and the AC / DC conversion loop.

7. The fast charging chip cascade circuit according to claim 6, characterized in that, The operational transconductance amplifier also has a first input terminal and a second input terminal. The first input terminal is electrically connected to the feedback resistor, and the second input terminal is electrically connected to the reference voltage terminal inside the fast charging chip.

8. A control method for a fast-charging chip cascade circuit as described in any one of claims 1-7, characterized in that, Includes the following steps: The built-in logic control module collects the input signals from the signal receiving pins and the output signals from the signal transmitting pins within the corresponding fast charging chip. The AC / DC conversion loop is driven to output a first voltage or a second voltage based on the input signal and the output signal.

9. The control method for the fast charging chip cascade circuit according to claim 8, characterized in that, The second voltage is greater than the first voltage, and the step of driving the AC / DC conversion loop to output the first voltage or the second voltage according to the input signal and the output signal includes: When the output signal is not locked, the AC / DC conversion loop is driven to output the first voltage; When the output signal is locked and the input signal is locked, the AC / DC conversion loop is driven to output a first voltage; When the output signal is locked and the input signal is unlocked, the AC / DC conversion loop is driven to output a second voltage.

10. The control method for the fast charging chip cascade circuit according to claim 9, characterized in that, The drive AC / DC conversion loop outputs a first voltage or a second voltage, including any of the following methods: When the constant voltage loop adopts the pumping current voltage regulation structure, by adjusting the pumping current and combining the voltage division effect of the feedback resistor, the AC-DC conversion loop can be driven to output the first voltage or the second voltage. When the constant voltage loop adopts a reference voltage regulation structure, the first or second voltage can be driven to be output by adjusting the internal reference voltage in conjunction with the voltage division effect of the feedback resistor.

11. The control method for the fast charging chip cascade circuit according to claim 9, characterized in that, When other fast charging chips are locked, the input signal is locked.

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