Wireless power transmission system of multi-level inverter based on pulse amplitude modulation and control method

Abstract

The wireless electric energy transmission system of the PMM-based multi-level inverter comprises a controller, a driving circuit, a sampling circuit, a direct-current voltage source, a flying capacitor type n-level inverter circuit, a transmitting end compensation circuit, a transmitting coil, a receiving coil, a receiving end compensation circuit, a diode rectifying circuit, a direct-current side capacitor and a load. N is a natural number larger than 2, the direct-current voltage source is connected with the flying capacitance type n-level inverter circuit, and the midpoint of a bridge arm of the flying capacitance type n-level inverter circuit is connected with the transmitting end compensation circuit. The transmitting end compensating circuit, the transmitting coil, the receiving coil, the receiving end compensating circuit, the diode rectifying circuit and the direct-current side capacitor are sequentially connected, the direct-current side capacitor is connected with a load in parallel, the two ends of the flying capacitor are connected with the input end of the sampling circuit, and the output end of the sampling circuit is connected with the input end of the controller. The output end of the controller is connected with the input end of the driving circuit, and the driving circuit drives the flying capacitor type n-level inverter circuit. A corresponding method is also disclosed.

Description

TECHNICAL FIELD

[0001] The present application discloses generally relates to the field of wireless power transfer. In particular, it relates to a pulse magnitude modulation (PMM) method based on delta-sigma, a flying capacitor voltage balancing method based on token conversion, and a wireless power transfer system and control method of a multi-level inverter based on PMM. BACKGROUND

[0002] Due to electrical isolation, safety, convenience and better user experience, wireless power transfer (WPT) technology has been applied to a wide range of fields such as micro robots, electric toothbrushes, electric vehicles and high-speed train charging. Among them, high-power high-frequency WPT systems are increasingly attracting industry attention.

[0003] According to the structure of the inverter, the method of increasing the power of the converter can be divided into three categories: multi-converter parallel, multi-phase bridge arm parallel and multi-level inverter. The first and second methods require matching transformers or coupled inductors. In contrast, multi-level inverters have the advantages of increasing input voltage, reducing voltage stress of each semiconductor device and high reliability. In addition, the WPT system based on multi-level inverter can eliminate the coupled transformer, and its structure is simpler than that of the multi-converter parallel WPT system. However, the switching loss and capacitor voltage balancing of the multi-level inverter are the key to the stable operation of the system. In order to reduce the power loss of the multi-level inverter, it is necessary to further study the zero voltage switching (ZVS) and capacitor voltage balancing method of the WPT system based on the multi-level inverter.

[0004] In recent years, there have been various modulation methods for WPT systems using two-level inverters, including pulse width modulation (PWM), hybrid modulation, pulse density modulation (PDM), and pulse frequency modulation (PFM). Among them, PDM and PFM have been widely studied and applied to WPT systems, which can realize soft switching of two-level converters and have the advantages of small DC-side output voltage fluctuation. However, the above modulation methods are not suitable for WPT systems based on multilevel inverters. The application of multilevel converters in WPT systems is relatively new. Existing research [1] has proposed a multi-channel WPT system based on a T-type multilevel inverter with PWM, which balances the neutral point voltage by exchanging switching signals, but there is a hard switching problem. In addition, [2] a digital modulation method for a wireless power transfer system based on a modular multilevel converter has been proposed, but its output voltage is discontinuous, and the capacitor balancing method for multilevel inverters with arbitrary voltage levels is still unclear. In addition, it is not suitable for other multilevel inverters, such as T-type or flying capacitor type multilevel inverters. Summary of the Invention

[0005] To overcome the problems of high switching losses and capacitor voltage balance in WPT applications using multilevel inverter technology, this invention provides a pulse amplitude modulation method for flying capacitor multilevel inverters (WPTs), which ensures continuous voltage output and zero-voltage switching in WPTs based on multilevel inverters. Furthermore, this invention provides a capacitor voltage balancing method based on token switching, which can achieve capacitor voltage balance in flying capacitor inverters of any level.

[0006] According to a first aspect of this disclosure, a wireless power transfer system based on a PMM multilevel inverter is provided. The system includes a controller, a drive circuit, a sampling circuit, a DC voltage source, a flying capacitor type n-level inverter circuit, a transmitter compensation circuit, a transmitter coil, a receiver coil, a receiver compensation circuit, a diode rectifier circuit, a DC-side capacitor, and a load. Here, n is a natural number greater than 2. The DC voltage source is connected to the flying capacitor type n-level inverter circuit. The midpoint of the bridge arm of the flying capacitor type n-level inverter circuit is connected to the transmitter compensation circuit. The transmitter compensation circuit, transmitter coil, receiver coil, receiver compensation circuit, diode rectifier circuit, and DC-side capacitor are connected sequentially. The DC-side capacitor is connected in parallel with the load. The two ends of the flying capacitor of the flying capacitor type n-level inverter circuit are connected to the input terminal of the sampling circuit. The output terminal of the sampling circuit is connected to the input terminal of the controller. The output of the controller is connected to the input terminal of the drive circuit. The drive circuit is used to drive the flying capacitor type n-level inverter circuit.

[0007] In some embodiments, the controller includes a Δ-∑-based PMM modulator.

[0008] In some embodiments, the Δ-∑-based PMM modulator includes an adder, an integrator, a quantizer, a latch, and a multiplier connected in sequence, wherein:

[0009] Given the modulated wave command signal δ PMM * With the output δ of the latch PMM1 As input to the adder, the output of the adder is e, where e = v PMM * -δ PMM1 , where δ PMM1 The initial value is 0;

[0010] e and a square wave signal A with an initial value of 0 are used as inputs to the integrator. In each control cycle, let A = 1 - A, and the output of the integrator is u, u = Ke / s, where K is the integration coefficient of the integrator and s is the Laplace operator.

[0011] u is used as the input to the quantizer, and the output of the quantizer is δ. PMM ;

[0012] δ PMM As the input to the latch, the output of the latch is δ. PMM1 The latch is implemented as follows: Define a variable g, which is initialized to 0; if g ≤ 0, then δ PMM1 =δ PMM If g = 1, then g = g - 1, δ PMM1 Remain unchanged;

[0013] δ PMM1 The multiplier takes a square wave signal A as input and outputs y, where y = δ. PMM1 ×A,y serves as the output of a PMM modulator based on Δ-∑.

[0014] In some embodiments, the quantizer is implemented as follows:

[0015]

[0016] Where m = 1, 2, ..., n-2.

[0017] In some embodiments, the controller further includes a token-based fly-through capacitor voltage balancer.

[0018] In some embodiments, the sampling circuit samples the voltage of the flying capacitor in the flying capacitor type n-level inverter circuit to obtain sampled voltages u1, u2, u3, ..., u n-2 Wherein, the sampling voltages are u1, u2, u3, ..., un-2 The output y of the Δ-Σ based PMM modulator is used as the input to the token rotation based flying capacitor voltage balancer.

[0019] In some embodiments, a priority symbol j is defined with an initial value of 1, and the token rotation based flying capacitor voltage balancer performs the following steps in each control period:

[0020] (1) Determine if 0 < y < 1: If so, then j = j - 1, and go to step (2); otherwise j remains unchanged, and go to step (3);

[0021] (2) Determine if j < 0: If so, then j = n - 3, and go to step (3); otherwise go to step (3);

[0022] (3) Based on the sampled voltages u1, u2, u3, …, u n-2 , obtain a1, a2, a3, …, a n-2 , and let the array A n = [a1, a2, a3, …, a n-2 ;

[0023] (4) Based on the array A n and j, obtain the optimal output array B n , where B n =

[0024] [b1, b2, b3, …, b n-1 ;

[0025] (5) Based on the optimal output array B n and y, obtain the switching signals S w1 to S wn-1 ;

[0026] (6) The switching signals S w1 to S wn-1 are used as the input to the drive circuit, and the output of the drive circuit controls the turning on or off of the switching tubes of the flying capacitor type n-level inverter circuit.

[0027] In some embodiments, the method for obtaining a1, a2, a3, …, a n-2 based on the sampled voltages u1, u2, u3, …, u n-2 [[ID=​​​​​​​​​​In some embodiments, step (4) involves using array A. n And j, to obtain the optimal output array B n The steps are as follows:

[0031] (4-1) Determine A n (0)>0, if so, then B n (0) is 0, B n (1) is 1, otherwise it is B. n (0) is 1, B n (1) is 0; then, determine A. n (1)>0, if so, then B n (2) is 1, otherwise B n (2) is 0; continue to judge A. n (2)>0, if so then B n (3) is 1, otherwise B n (3) If it is 0, use this pattern to judge A sequentially. n (3)>0, A n (4)>0,…,A n (n-2)>0, thus obtaining the optimal output array B. n ;

[0032] (4-2) Based on the priority symbol j, determine A n (j)>0, if so, then B n (j) is 1, otherwise B n (j) is 0.

[0033] In some embodiments, step (5) is based on the optimal output array B. n And y obtains the switch signal S w1 To S wn-1 The steps are as follows:

[0034] (5-1) Calculate the switching signal S based on y. w1 To S wn-1 The number of 1s in the middle is defined as m, and its calculation method is as follows:

[0035] m = y(n-1)

[0036] Where y is composed of “1”, “(n-2) / (n-1)”, “(n-3) / (n-1)”, … and “0”, and m is composed of “n-1”, “n-2”, …, “1” and “0”;

[0037] (5-2) Calculate B n The number of 1s in the sequence is defined as t, and its calculation method is as follows:

[0038] t = b1 + b2 + b3 + ... + b n-1

[0039] (5-3) Determine the magnitude relationship between m and t:

[0040] If m = t, then go to step (5-4);

[0041] If m > t, then in the reverse direction of the capacitor charge and discharge priority sequence, b1, b2, b3, …, b n-1 Rearrange them, and the rearrangement method is: when j = 1, b1, b2, b3, …, b n-1 Are arranged as b n-1 -b n-2 -b n-3 -…-b2 - b1, otherwise arranged as b j-1 -b j-2 -…-b2 - b1 - b n-1 -b n-2 -…-b j ; Then judge whether it is 1 from left to right according to this sequence. If it is 1, change it to 0 until m - t 1s become 0;

[0042] If m < t, then in the reverse direction of the capacitor charge and discharge priority sequence,

[0043] b1, b2, b3, …, b n-1 Rearrange them, and the rearrangement method is: when j = 1,

[0044] b1, b2, b3, …, b n-1 Are arranged as b n-1 -b n-2 -b n-3 -…-b2 - b1, otherwise arranged as b j-1 -b j-2 -…-b2 - b1 - b n-1 -b n-2 -…-b j ; Then judge whether it is 0 in turn according to this sequence. If it is 0, change it to 1 until t - m 0s become 1;

[0045] (5-4) Obtain the switching signal S w1 = b1, S w2 = b2, …, S wn-1 [[ID=Z66]]= b n-1 .

[0046] According to the second aspect of the present disclosure, there is provided a control method for a wireless power transmission system of a multi-level inverter based on PMM as described above. Among them, the control method includes a PMM method based on Δ-Σ, and the PMM method based on Δ-Σ includes the following steps:

[0047] (1) Define a square wave signal A, set its initial value to 0, and in each control period, set A = 1 - A;

[0048] (2) The given modulation wave command signal δ PMM * and the output δ of the latch PMM1 are subtracted by an adder to obtain the input e of the integrator, e = δ PMM * - δ PMM1 , where the initial value of δ PMM1 is 0;

[0049] [[ID=​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​(2) Determine if j < 0: If yes, then j = n - 3, go to step (3); otherwise go to step (3);

[0059] (3) The sampling voltages u1, u2, u3, ..., u are based on the voltage of the flying capacitor in the flying capacitor type n-level inverter circuit. n-2 We get a1, a2, a3, ..., a n-2 Let array A n =[a1,a2,a3,…,a n-2 ];

[0060] (4) Based on array A n And j, to obtain the optimal output array B n Among them, B n =

[0061] [b1,b2,b3,…,b n-1 ];

[0062] (5) Based on the optimal output array B n And y, to obtain the switching signal S w1 To S wn-1 ;

[0063] (6) Switch signal S w1 To S wn-1 As the input to the drive circuit, the output of the drive circuit controls the switching transistor of the flying capacitor type n-level inverter circuit to turn on or off.

[0064] In some embodiments, step (2) is based on the sampled voltages u1, u2, u3, ..., u n-2 We get a1, a2, a3, ..., a n-2 The method is as follows:

[0065]

[0066] Where m is 1, 2, ..., n-2, V dc This represents the steady-state value of the DC-side voltage of the flying capacitor type n-level inverter circuit.

[0067] In some embodiments, step (4) is based on array A n And j, to obtain the optimal output array B n The steps are as follows:

[0068] (4-1) Determine A n (0)>0, if so, then B n (0) is 0, B n (1) is 1, otherwise it is B. n (0) is 1, B n (1) is 0; then, determine A.n (1)>0, if so, then B n (2) is 1, otherwise B n (2) is 0; continue to judge A. n (2)>0, if so then B n (3) is 1, otherwise B n (3) If it is 0, use this pattern to judge A sequentially. n (3)>0, A n (4)>0,…,A n (n-2)>0, thus obtaining the optimal output array B. n ;

[0069] (4-2) Based on the priority symbol j, determine A n (j)>0, if so, then B n (j) is 1, otherwise B n (j) is 0.

[0070] In some embodiments, step (5) is based on the optimal output array B. n The switching signal S is obtained from y. w1 To S wn-1 The steps are as follows:

[0071] (5-1) Calculate the switching signal S based on y. w1 To S wn-1 The number of 1s in the middle is defined as m, and its calculation method is as follows:

[0072] m = y(n-1)

[0073] Where y is composed of “1”, “(n-2) / (n-1)”, “(n-3) / (n-1)”, … and “0”, and m is composed of “n-1”, “n-2”, …, “1” and “0”;

[0074] (5-2) Calculate B n The number of 1s in the sequence is defined as t, and its calculation method is as follows:

[0075] t = b1 + b2 + b3 + ... + b n-1

[0076] (5-3) Determine the relationship between m and t:

[0077] If m = t, then proceed to step (5-4);

[0078] If m>t, then follow the reverse direction of the capacitor charging / discharging priority sequence: b1, b2, b3, ..., b n-1 The arrangement is as follows: when j=1, b1, b2, b3, ..., b n-1 Arranged as bn-1 -b n-2 -b n-3 -…-b2 - b1, otherwise arranged as b j-1 -b j-2 -…-b2 - b1 - b n-1 -b n-2 -…-b j ; Then, judge whether it is 1 from left to right according to this sequence. If it is 1, change it to 0 until m - t 1s become 0;

[0079] If m < t, according to the reverse direction of the capacitor charge - discharge priority sequence, arrange

[0080] b1, b2, b3, …, b n-1 Rearrange, and the rearrangement method is: when j = 1,

[0081] b1, b2, b3, …, b n-1 arranged as b n-1 -b n-2 -b n-3 -…-b2 - b1, otherwise arranged as b j-1 -b j-2 -…-b2 - b1 - b n-1 -b n-2 -…-b j ; Then, judge whether it is 0 in turn according to this sequence. If it is 0, change it to 1 until t - m 0s become 1;

[0082] (5 - 4) Obtain the switching signal S w1 = b1, S w2 = b2, …, S wn-1 = b n-1 .

[0083] According to the fourth aspect of the present disclosure, a Δ - Σ - based PMM method is provided. This method is implemented on a Δ - Σ - based PMM modulator including an adder, an integrator, a quantizer, a latch, and a multiplier connected in sequence. This method includes the following steps:

[0084] (1) Define a square - wave signal A, let its initial value be 0, and in each control cycle, let A = 1 - A;

[0085] (2) The given modulation - wave command signal δ PMM * and the output δ PMM1 of the latch are subtracted by an adder to obtain the input e of the integrator, e = δ PMM * - δ PMM1 , where the initial value of δ PMM1 is 0;

[0086] (3) Based on the input e of the integrator, obtain the output u of the integrator, where u = Ke / s, where K is the integration coefficient of the integrator and s is the Laplace operator;

[0087] (4) Use the output u of the integrator as the input of the quantizer to obtain the output δ of the quantizer PMM ;

[0088] (5) Use the output δ of the quantizer PMM as the input of the latch to obtain the output δ of the latch PMM1 , where the implementation of the latch is as follows: Define a variable g with an initial value of 0; if g ≤ 0, then δ PMM1 = δ PMM , and g = 1; otherwise, g = g - 1 and δ PMM1 remains unchanged;

[0089] (6) Multiply the output δ of the latch PMM1 by the square wave signal A to obtain the output y of the Δ-Σ based PMM method.

[0090] In some embodiments, the implementation of the quantizer is as follows:

[0091]

[0092] where m = 1, 2,..., n - 2.

[0093] According to the fifth aspect of the present disclosure, a capacitor voltage balancing method based on token rotation is provided, where a priority symbol j is defined with an initial value of 1, the output of the Δ-Σ based pulse amplitude modulation (PMM) modulator is y, and the flying capacitor voltage balancing method based on token rotation performs the following steps according to the control period:

[0094] (1) Determine 0 < y < 1: If so, then j = j - 1 and go to step (2); otherwise j remains unchanged and go to step (3);

[0095] (2) Determine j < 0: If so, then j = n - 3 and go to step (3); otherwise go to step (3);

[0096] (3) Based on the sampling voltages u1, u2, u3,..., u n-2 of the voltages of the flying capacitors of the flying capacitor type n-level inverter circuit, obtain a1, a2, a3,..., a n-2 , and let the array A n = [a1, a2, a3,..., a n-2 ;

[0097] (4) Based on the array A n and j, obtain the optimal output array Bn Among them, B n =

[0098] [b1,b2,b3,…,b n-1 ];

[0099] (5) Based on the optimal output array B n And y, to obtain the switching signal S w1 To S wn-1 ;

[0100] (6) Switch signal S w1 To S wn-1 As the input to the drive circuit, the output of the drive circuit controls the switching transistor of the flying capacitor type n-level inverter circuit to turn on or off.

[0101] In some embodiments, step (2) is based on the sampled voltages u1, u2, u3, ..., u n-2 We get a1, a2, a3, ..., a n-2 The method is as follows:

[0102]

[0103] Where m is 1, 2, 3, ..., n-2, V dc This represents the steady-state value of the DC-side voltage of the flying capacitor type n-level inverter circuit.

[0104] In some embodiments, step (4) is based on array A n And j, to obtain the optimal output array B n The steps are as follows:

[0105] (4-1) Determine A n (0)>0, if so, then B n (0) is 0, B n (1) is 1, otherwise it is B. n (0) is 1, B n (1) is 0; then, determine A. n (1)>0, if so, then B n (2) is 1, otherwise B n (2) is 0; continue to judge A. n (2)>0, if so then B n (3) is 1, otherwise B n (3) If it is 0, use this pattern to judge A sequentially. n (3)>0, A n (4)>0,…,A n (n-2)>0, thus obtaining the optimal output array B. n ;

[0106] (4-2) Determine A based on the priority symbol j n (j) > 0, if so, then B n (j) is 1, otherwise B n (j) is 0.

[0107] In some embodiments, in step (5), according to the optimal output array B n and y to obtain the switching signal S w1 to S wn-1 The steps are as follows:

[0108] (5-1) Calculate the switching signal S w1 to S wn-1 The number of 1s in it, and define this number as m. The calculation method is as follows

[0109] m = y(n - 1)

[0110] where y consists of "1", "(n - 2) / (n - 1)", "(n - 3) / (n - 1)",..., and "0", and m consists of "n - 1", "n - 2",..., "1", and "0";

[0111] (5-2) Calculate the number of 1s in B n Define it as t. The calculation method is as follows:

[0112] t = b1 + b2 + b3 + … b n-1

[0113] (5-3) Determine the size relationship between m and t:

[0114] If m = t, then go to step (5-4);

[0115] If m > t, then in the reverse direction of the capacitor charge and discharge priority sequence, b1, b2, b3,..., b n-1 Rearrange. The rearrangement method is: when j = 1, b1, b2, b3,..., b n-1 Are arranged as b n-1 -b n-2 -b n-3 -…-b2 - b1, otherwise arranged as b j-1 -b j-2 -…-b2 - b1 - b n-1 -b n-2 -…-b j ; Then judge whether it is 1 from left to right according to this sequence. If it is 1, change it to 0 until m - t 1s become 0;

[0116] If m < t, then in the reverse direction of the capacitor charge and discharge priority sequence, b1, b2, b3,..., b n-1The arrangement is as follows: when j=1, b1, b2, b3, ..., b n-1 Arranged as b n-1 -b n-2 -b n-3 -…-b2-b1, otherwise arrange as b j-1 -b j-2 -…-b2-b1-b n-1 -b n-2 -…-b j Then, based on this sequence, determine whether each value is 0. If it is 0, change it to 1, until tm zeros are changed to 1.

[0117] (5-4) Obtain the switching signal S w1 =b1,S w2 =b2,…,S wn-1 =b n-1 .

[0118] The invention is provided to present the selected concepts in a simplified form, which will be further described in the following detailed description. This disclosure is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter. Other aspects and advantages of the invention will be illustrated by the following examples. Attached Figure Description

[0119] The accompanying drawings contain figures to further illustrate and explain the above and other aspects, advantages, and features of the invention disclosed herein. It will be understood that these drawings depict only certain embodiments of the invention disclosed and are not intended to limit its scope. It will also be understood that these drawings are illustrative for simplicity and clarity and are not necessarily shown to scale. The disclosure will now be described and explained with additional specificity and detail using the accompanying drawings, in which:

[0120] Figure 1 A schematic diagram of a wireless power transfer system for a PMM-based flying capacitor n-level inverter according to an embodiment of the present invention is shown.

[0121] Figure 2 A schematic diagram of a Δ-∑-based PMM modulator according to an embodiment of the present invention is shown;

[0122] Figure 3 A flowchart illustrating the execution steps of a token-based flying capacitor voltage balancer according to an embodiment of the present invention is shown.

[0123] Figure 4 A charging and discharging priority sequence diagram of a flying capacitor based on token rotation according to an embodiment of the present invention is shown;

[0124] Figure 5A schematic diagram showing experimental results of the flying capacitor voltage of a seven-level inverter for a wireless power transfer system according to an embodiment of the present invention is illustrated.

[0125] Figure 6 δ is shown according to an embodiment disclosed in the present invention. PMM * =0.95 and δ PMM * A schematic diagram of the experimental results of voltage and current of the flying capacitor seven-level inverter in the wireless power transmission system 100 under the condition of 0.6. Detailed Implementation

[0126] Embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, one or more examples of which are illustrated. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as being more preferred or advantageous than other implementations. Furthermore, each example is provided by way of explanation rather than limitation. Indeed, it will be apparent to those skilled in the art that modifications and variations can be made to this technology without departing from the scope or spirit of the claimed technology. For example, features shown or described as part of one embodiment may be used with another embodiment to produce yet another embodiment. Therefore, this disclosure is intended to cover such modifications and variations within the scope of the appended claims and their equivalents. Numerical and alphabetic designations are used in the detailed description to denote features in the drawings. Similar or analogous designations in the drawings and specification are used to refer to similar or analogous parts in this disclosure.

[0127] As used herein, the terms “first,” “second,” and “third” are used interchangeably to distinguish one component from another, rather than to indicate the position or importance of a single component. The singular expressions “a,” “an,” and “the” also include plural cases, unless the context explicitly specifies otherwise. The terms “coupled,” “fixed,” “connected,” etc., refer to direct coupling, fixing, or connection, as well as indirect coupling, fixing, or connection through one or more intermediate components or features, unless otherwise specified herein. The terms “comprising,” “including,” “constituting,” “having,” or any other variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, article, or apparatus that includes a set of features is not necessarily limited to those features, but may include features not expressly listed or other features inherent to such a process, method, article, or apparatus. Furthermore, unless expressly stated to the contrary, “or” is inclusive rather than exclusive. For example, any of the following satisfy conditions A or B: A is true (or exists) and B is false (or does not exist); A is false (or does not exist) and B is true (or exists); and both A and B are true (or exist).

[0128] Terms indicating approximation, such as “approximately,” “roughly,” “approximately,” or “substantially,” include values ​​that are within 10% larger or smaller than the described value. When used in the context of angles or directions, these terms include values ​​that are within 10 degrees larger or smaller than the described angle or direction. For example, “roughly vertical” includes directions that deviate from vertical by within 10 degrees in any direction (e.g., clockwise or counterclockwise).

[0129] The benefits, other advantages, and solutions to problems are described below with reference to specific embodiments. However, the benefits, advantages, solutions to problems, and any features that may cause any benefit, advantage, or solution to occur or become more apparent should not be construed as key, essential, or necessary features of any or all claims. The scope of this disclosure is intended to cover modifications and additions to the steps within a reasonable range.

[0130] Figure 1 A schematic diagram of a wireless power transfer system 100 based on a PMM-driven n-level inverter according to an embodiment of the present disclosure is shown, where n is a natural number greater than 2. The wireless power transfer system 100 comprises a controller, a drive circuit, a sampling circuit, and a DC voltage source (with a steady-state voltage value of V). dc DC side capacitor (C) dc1 C dc2 C dc ), flying capacitor type multilevel inverter circuit, emitter compensation circuit (C) t ), transmitting coil (L) t ), receiving coil (L) r ), Receiver compensation circuit (C) r It consists of a diode rectifier circuit (D1~D4). Figure 1 In this embodiment, the DC voltage source is connected to a flying capacitor type n-level inverter circuit. The flying capacitor type n-level inverter circuit includes switching transistors S1, S2, S3, ..., S... n-1 and and flying capacitor C f1 C f2 C f3 ,…,C fn-2 Among them, the switching transistor S1 and The first group of upper and lower bridge arms, switch S2 and The second set of upper and lower bridge arms are formed, ..., the switching transistor S n-2 and This constitutes the (n-2)th group of upper and lower bridge arms, and the switching transistor S. n-1 and This forms the (n-1)th group of upper and lower bridge arms. Each group of upper and lower bridge arms is connected in parallel with the DC voltage source. A flying capacitor is connected in series at the midpoint of the upper and lower bridge arms in groups 1 to (n-2) counting from the DC voltage source side. For example, a flying capacitor C is connected in series at the midpoint of the upper and lower bridge arms in group 1. f1 A flying capacitor C is connected in series at the midpoint of the upper and lower bridge arms of the second group. f2 ..., a flying capacitor C is connected in series at the midpoint of the upper and lower bridge arms of the (n-2)th group. fn-2 .

[0131] The midpoint of the upper and lower bridge arms in the (n-1)th group is connected to the transmit compensation circuit (C). t Connect the input terminal of the transmitter compensation circuit (C). t ), transmitting coil (L) t ), receiving coil (L) r ), Receiver compensation circuit (C) r ), diode rectifiers (D1~D4) and output DC-side capacitors (C) dc The input terminals of the n-2 sampling circuits are connected sequentially to the flying capacitor C. f1 C f2 C f3 ,…,C fn-2 The two ends are connected, and the output of the sampling circuit is connected to the input of the controller. The controller outputs the switching signals (S) to control each switching transistor. w1 S w2 S wn-1 and It is connected to the input terminal of the drive circuit. The drive circuit is used to drive the switching state of each switch in the n-level inverter circuit.

[0132] like Figure 1 As shown, C dc1 and C dc2 These are the DC-side capacitors at the input terminals. u1, u2, u3, ..., u n-2 For the flying capacitor C f1 C f2 C f3 ,…,C fn-2 The voltage value. L t and L r These are the inductances of the transmitter and receiver coils, respectively; while R t and R r These represent the equivalent series resistances of the transmitter and receiver sections, respectively. M represents the mutual inductance between the primary and secondary coils. C t and C r These are the series compensation capacitors for the transmitting compensation circuit and the receiving compensation circuit, respectively. R dc and C dcThese are the DC link load of the diode rectifier and the DC-side capacitor at the output terminal, respectively. This multilevel inverter is powered by a DC input voltage source (steady-state voltage value is V). dc Power is supplied to drive the series resonant circuit (L) t and C t ).

[0133] In a preferred embodiment, the controller comprises two parts: a Δ-Σ-based PMM modulator 200 and a token-switching-based flying capacitor voltage balancer 300. Those skilled in the art will understand that the Δ-Σ-based PMM modulator 200 and the token-switching-based flying capacitor voltage balancer 300 disclosed herein can also be used, individually or in combination, in other types of circuits.

[0134] Figure 2 A schematic diagram of a Δ-∑-based PMM modulator 200 according to an embodiment of the present invention is shown. The Δ-∑-based PMM modulator 200 enables wide-range soft switching of the wireless power transfer system 100 without the need for auxiliary circuitry. The Δ-∑-based PMM modulator 200 includes an adder 210, an integrator 220, a quantizer 230, a latch 240, and a multiplier 250. Figure 2 As shown, a square wave signal A is first defined, with an initial value of 0. In each control cycle, A = 1 - A. The input signal to adder 210 includes a given modulation command signal δ from the Δ-∑ PMM modulator 200. PMM * In adder 210, δ PMM * With the output δ of the latch PMM1 The difference is calculated, and the output signal is e, where e = δ. PMM * -δ PMM1 The output of adder 210 is connected to the input of integrator 220. The rising edge of the square wave signal A input to integrator 220 triggers integrator 220. Integrator 220 outputs u, u = Ke / s, where K is the integration coefficient of the integrator and s is the Laplace operator. The output of integrator 220 is connected to the input of quantizer 230 to obtain the output δ of quantizer 230. PMM The output of quantizer 230 is connected to the input of latch 240 to obtain the output δ of latch 240. PMM1 The output of latch 240 is connected to the input of multiplier 250, and simultaneously fed back to the input of adder 210 (as described above). The pulse of square wave signal A is also connected to the input of multiplier 250. The output of multiplier 250 is y, where y = δ. PMM1 ×A, the modulated wave y is the output of the Δ-∑ PMM modulator 200.

[0135] The quantizer of the Δ-∑ PMM modulator 200 is calculated using the following formula, where m = 1, 2, ..., n-2:

[0136]

[0137] The output δ of the latch PMM1 With input δ PMM The following relationship exists:

[0138] Define a variable g, with an initial value of 0. If g ≤ 0, then δ PMM1 =δ PMM If g = 1, then g = g - 1, δ PMM1 It remains unchanged.

[0139] The modulated wave y can be used as Figure 1 The input of the token-based flying capacitor voltage balancer 300.

[0140] Figure 3 A flowchart illustrating the execution steps of a token-based flying capacitor voltage balancer 300 according to an embodiment of the present invention is shown. The token-based flying capacitor voltage balancer 300 is applicable to any number n multilevel inverters and can balance all capacitor voltages while resisting step dynamics. The input signals of the token-based flying capacitor voltage balancer 300 are y, u1, u2, u3, ..., u n-2 Wherein, the modulated wave y is the output signal of the PMM modulator 200, u1, u2, u3, ..., u n-2 yes Figure 1 Zhongfei cross capacitor C f1 C f2 C f3 ,…,C fn-2 The voltage sample value.

[0141] Figure 4 A charging / discharging priority sequence diagram of a flying capacitor based on token rotation according to an embodiment of the present invention is shown. The token position represents the highest priority for charging / discharging that capacitor, such as... Figure 4 As shown in subgraph (a), the tokens cycle counterclockwise, C fn-2 Arrive at C f1 At this time, the priority order of capacitor charging and discharging is C. f1 >C f2 >C f3 >…>C fn-2 In the next control cycle, if y is not equal to 0 or 1, the token will cycle counterclockwise, as follows. Figure 4 As shown in subgraph (b), from C f1 Arrive at C fn-2 At this time, the priority order of capacitor charging and discharging is C.fn-2 >C f1 >C f2 >C f3 >…>C fn-3 .

[0142] First, define Figure 3 The priority symbol j is initialized to 1, and token rotation is implemented using the priority symbol j. Steps S310 to S330 can be executed cyclically according to the control cycle. In step S310, when j = 1, C f1 It has the highest charge / discharge priority; the priority for capacitor charge / discharge is C. f1 >C f2 >C f3 >…>C fm >…>C fn-2 . Figure 3 The output modulation wave y of the wave generator shown is composed of "1", "(n-2) / (n-1)", "(n-3) / (n-1)", ... and "0". For example, when n = 7, y is composed of 1, 5 / 6, 4 / 6, 3 / 6, 2 / 6, 1 / 6, and 0. When the modulation wave y is 1, the voltage level of the n-level inverter is V. dc Switch state variable "S" w1 S w2 S w3 …S wn-1 "Select '111…111'; when the modulation wave y is 0, the voltage level of the n-level inverter is 0, and the switch state variable 'S'..." w1 S w2 S w3 …S wn-1 The selection is "000…000". In these two switching states, no capacitor is charging or discharging. Therefore, the token position is retained only when y is 1 or 0, meaning the switching state of each switch remains unchanged, and the corresponding flying capacitor does not charge or discharge. Therefore, j is decremented by 1 only when the modulation wave y is not 1 or 0 to change the priority order; otherwise, proceed to step S320. After decrementing j by 1, it is determined whether j is less than 0. If so, j is reset to n-3, and step S320 continues; otherwise, proceed directly to step S320.

[0143] Execute step S320 as follows: Based on the input sampled voltages u1, u2, u3, ..., u n-2 We get a1, a2, a3, ..., a n-2 The method is as follows, let array A n =[a1,a2,a3,…,a n-2 ]:

[0144]

[0145] Where m is 1, 2, 3, ..., n-2, V dc This represents the steady-state value of the DC-side voltage of the flying capacitor type n-level converter circuit.

[0146] Then, firstly according to A n Obtain the optimal output array B n The steps are as follows, where B n =[b1,b2,b3,…,b n-1 ]: Determine A n (0)>0, if so, then B n (0) is 0, B n (1) is 1, otherwise it is B. n (0) is 1, B n (1) is 0. Then, determine A. n (1)>0, if so, then B n (2) is 1, otherwise B n (2) is 0. Continue to judge A. n (2)>0, if so then B n (3) is 1, otherwise B n (3) is 0. Use this pattern to sequentially determine A. n (3)>0, A n (4)>0,…,A n (n-2)>0, thus obtaining the optimal b1,b2,b3,…,b n-1 Subsequently, based on the priority symbol j, and then according to A... n (j) Modify B n (j). The specific method for modification is as follows: Determine A n (j)>0, if so, then it corresponds to B. n (j) is 1, otherwise it is B. n (j) is 0.

[0147] Execute step S330, based on the optimal output array B n The switching signal S is obtained by modulating the wave y. w1 To S wn-1 ,as follows:

[0148] Calculate the switch signal S w1 To S wn-1 The number of 1s in the array is finite, and this number is defined as m. The calculation method is as follows:

[0149] m = y(n-1)

[0150] Where y is composed of “1”, “(n-2) / (n-1)”, “(n-3) / (n-1)”, … and “0”; m is composed of “n-1”, “n-2”, …, “1” and “0”.

[0151] Then calculate the number of 1s in b1, b2, b3, …, b n-1 , defined as t, and its calculation method is as follows:

[0152] t = b1 + b2 + b3 + … + b n-1

[0153] Judge the size relationship between m and t, where sub-steps (1)-(3) are alternative options and do not follow an order:

[0154] (1) If m = t, then b1, b2, b3, …, b n-1 remain unchanged;

[0155] (2) If m > t, then arrange b1, b2, b3, …, b in the reverse direction of the capacitor charge and discharge priority sequence n-1 , and its arrangement method is: when j = 1, b1, b2, b3, …, b n-1 is arranged as b n-1 -b n-2 -b n-3 -… - b2 - b1, otherwise it is arranged as b j-1 -b j-2 -… - b2 - b1 - b n-1 -b n-2 -… - b j ; then sequentially judge whether each of them is 1 according to this sequence. If it is 1, change it to 0 until m - t 1s become 0;

[0156] (3) If m < t, then arrange b1, b2, b3, …, b in the reverse direction of the capacitor charge and discharge priority sequence n-1 , and its arrangement method is: when j = 1, b1, b2, b3, …, b n-1 is arranged as b n-1 -b n-2 -b n-3 -… - b2 - b1, otherwise it is arranged as b j-1 -b j-2 -… - b2 - b1 - b n-1 -b n-2 -… - b j ; then sequentially judge whether each of them is 0 according to this sequence. If it is 0, change it to 1 until t - m 0s become 1;

[0157] After judging the size relationship between m and t and executing one of sub-steps (1)-(3), let the switch signal S w1 = b1, S w2 = b2, …, S wn-1 = b n-1Each of these controls the operating state of the switching transistor in a one-to-one correspondence. Finally, according to S... w1 To S wn-1 The switching signal, through the drive circuit, controls the switching circuit of the flying capacitor type n-level inverter to turn on or off.

[0158] Figure 5 A schematic diagram illustrating experimental results of the flying capacitor voltage of a seven-level inverter for a wireless power transfer system 100 according to an embodiment of the present invention is shown. In sub-figure (a), δ... PMM * =0.8, δ in subgraph (b) PMM * =0.2. According to Figure 5 It can be observed that all capacitor voltages can be quickly balanced to the reference value, and the start-up time of all capacitors is less than 0.42 seconds. Figure 5 The token-based capacitor voltage balancing method according to this disclosure is verified to be effective for wireless power transmission systems based on flying capacitor type n-level inverters.

[0159] Figure 6 Subgraphs (a) and (b) respectively illustrate the δ according to embodiments disclosed in the present invention. PMM * =0.95 and δ PMM * A schematic diagram showing the simulation results of the transmitter voltage and current of the wireless power transfer system 100 when n=7 and n=0.6. PMM Defined as the fundamental component of the output voltage of a multilevel flying capacitor converter and 2V dc The ratio of / π, δ PMM * It can be represented as

[0160]

[0161] Where N1 and N2 represent the number of two voltage pulses with similar amplitudes within the minimum modulation period, and δ1 and δ2 represent the amplitudes of the two voltage pulses with similar amplitudes and V. dc The ratio of .

[0162] according to Figure 6 Subgraphs (a) and (b) show that for different δ PMM * Both can achieve ZVS.

[0163] This invention proposes a Δ-∑ PMM modulation method, a token-based capacitor voltage balancing method, and a wireless power transfer system and control method for a PMM-based multilevel inverter.

[0164] The systems and methods disclosed in this invention are easy to implement. The Δ-∑ PMM modulator method can simultaneously achieve wide-range voltage output and ZVS, reducing switching losses and can be used in high-voltage, high-power applications, such as high-voltage wireless power transmission systems. The token-switching flying capacitor voltage balancing method can be used in flying capacitor multilevel inverters with any number of levels and can balance all flying capacitor voltages at a reference value.

[0165] This invention discloses solutions to the problems of flying capacitor voltage balance and high switching losses in high-voltage wireless power transmission applications of flying capacitor multilevel inverters. The system and method disclosed in this invention can be applied to fields such as wireless charging of electric vehicles and medium- and high-voltage DC microgrids.

[0166] This specification uses examples to disclose, including best practices, and to enable any person skilled in the art to practice this disclosure, including making and using any apparatus or system and methods of performing any combination. The patent scope of this invention is defined by the claims, but may include other examples that would occur to a person skilled in the art. The scope of the claims covers such other examples if they include structural elements that are not distinct from the literal expression of the claims, or if they include equivalent structural elements that are not substantially different from the literal expression of the claims.

[0167] References

[0168] The following is a list of references occasionally cited in this specification. All publications in each of these references are incorporated herein by reference in their entirety.

[0169] [1]Y.Liu, C.Liu,

[0170] [2]W.V.Wang,D.J.Thrimawithana,F.Lin and G.A.Covic,“An MMC-based IPTsystem with integrated magnetics and ZVS operations,”IEEE Trans.PowerElectron.,vol.37,no.2,pp.2425-2436,Feb.2022.

Claims

1. A wireless power transmission system based on a pulse amplitude modulation (PMM) multilevel inverter, the system comprising a controller, a drive circuit, a sampling circuit, a DC voltage source, a flying capacitor type n-level inverter circuit, a transmitter compensation circuit, a transmitter coil, a receiver coil, a receiver compensation circuit, a diode rectifier circuit, and a DC-side capacitor and load, wherein, n is a natural number greater than 2. The DC voltage source is connected to the flying-capacitor type n-level inverter circuit. The midpoint of the bridge arm of the flying-capacitor type n-level inverter circuit is connected to the transmitter compensation circuit. The transmitter compensation circuit, the transmitting coil, the receiving coil, the receiver compensation circuit, the diode rectifier circuit, and the DC-side capacitor are connected in sequence. The DC-side capacitor is connected in parallel with the load. The two ends of the flying capacitor of the flying-capacitor type n-level inverter circuit are connected to the input end of the sampling circuit. The output end of the sampling circuit is connected to the input end of the controller. The output of the controller is connected to the input end of the drive circuit. The drive circuit is used to drive the flying-capacitor type n-level inverter circuit.

2. The wireless power transmission system according to claim 1, wherein, The controller includes a Δ-Σ based PMM modulator.

3. The wireless power transmission system according to claim 2, wherein, The Δ-Σ based PMM modulator includes an adder, an integrator, a quantizer, a latch, and a multiplier connected in sequence, where: Given the modulated wave command signal δ PMM * With the output δ of the latch PMM1 As input to the adder, the output of the adder is e, where e = δ PMM * -δ PMM1 , where δ PMM1 The initial value is 0; e and the square-wave signal A with an initial value of 0 are used as the inputs of the integrator. In each control period, let A = 1 - A. The output of the integrator is u, and u = Ke / s, where K is the integration coefficient of the integrator and s is the Laplace operator. u is used as the input to the quantizer, and the output of the quantizer is δ. PMM ; δ PMM As the input to the latch, the output of the latch is δ PMM1 The latch is implemented as follows: Define a variable g, with an initial value of 0; if g ≤ 0, then δ PMM1 =δ PMM If g = 1, then g = g - 1, δ PMM1 Remain unchanged; δ PMM1 The square wave signal A is used as the input to the multiplier, and the output of the multiplier is y, where y = δ. PMM1 ×A,y is the output of the Δ-∑-based PMM modulator.

4. The wireless power transmission system according to claim 3, wherein, The implementation method of the quantizer is as follows: where m = 1, 2, …, n - 2.

5. The wireless power transmission system according to claim 2, wherein, The controller further includes a token-rotation based flying-capacitor voltage balancer.

6. The wireless power transmission system according to claim 5, wherein, The sampling circuit samples the voltage of the flying capacitor in the flying capacitor type n-level inverter circuit to obtain the sampled voltages u1, u2, u3, ..., u n-2 Wherein, the sampling voltages u1, u2, u3, ..., u n-2 The output y of the Δ-∑-based PMM modulator is used as the input of the token-rotating flying capacitor voltage balancer.

7. The wireless power transmission system according to claim 6, wherein, Define the priority symbol j and let its initial value be 1. The token-rotation based flying-capacitor voltage balancer performs the following steps according to the control period: (1) Judge 0 < y < 1: If so, then j = j - 1, and go to step (2); otherwise j remains unchanged, and go to step (3); (2) Judge j < 0: If so, then j = n - 3, and go to step (3); otherwise go to step (3); (3) Based on the sampling voltages u1, u2, u3, ..., u n-2 We get a1, a2, a3, ..., a n-2 Let array A n =[a1,a2,a3,…,a n-2 ]; (4) Based on array A n And j, to obtain the optimal output array B n Among them, B n =[b1,b2,b3,…,b n-1 ]; (5) Based on the optimal output array B n And y, to obtain the switching signal S w1 To S wn-1 ; (6) The switching signal S w1 To S wn-1 As an input to the driving circuit, the output of the driving circuit controls the switching transistor of the flying capacitor type n-level inverter circuit to turn on or off.

8. The wireless power transmission system according to claim 7, wherein, In step (2), based on the sampled voltages u1, u2, u3, ..., u n-2 We get a1, a2, a3, ..., a n-2 The method is as follows: Where m is 1, 2, ..., n-2, V dc This is the steady-state value of the DC-side voltage of the flying capacitor type n-level inverter circuit.

9. The wireless power transmission system according to claim 7, wherein, In step (4), based on array A n And j, to obtain the optimal output array B n The steps are as follows: (4-1) Determine A n (0)>0, if so, then B n (0) is 0, B n (1) is 1, otherwise it is B. n (0) is 1, B n (1) is 0; then, determine A. n (1)>0, if so then B n (2) is 1, otherwise B n (2) is 0; continue to judge A. n (2)>0, if so then B n (3) is 1, otherwise B n (3) If it is 0, use this pattern to judge A sequentially. n (3)>0, A n (4)>0,…,A n (n-2)>0, thus obtaining the optimal output array B. n ; (4-2) Based on the priority symbol j, determine A n (j)>0, if so, then B n (j) is 1, otherwise B n (j) is 0.

10. The wireless power transmission system according to claim 7, wherein, In step (5), the optimal output array B is used as described. n And y obtains the switch signal S w1 To S wn-1 The steps are as follows: (5-1) Calculate the switching signal S based on y. w1 To S wn-1 The number of 1s in the middle is defined as m, and its calculation method is as follows: m = y(n - 1) where y consists of "1", "(n - 2) / (n - 1)", "(n - 3) / (n - 1)", …, and "0", and m consists of "n - 1", "n - 2", …, "1", and "0"; (5-2) Calculate B n The number of 1s in the sequence is defined as t, and its calculation method is as follows: t=b1+b2+b3+…b n-1 (5 - 3) Judge the magnitude relationship between m and t: If m = t, then go to step (5 - 4); If m > t, then in the reverse direction of the capacitor charge and discharge priority sequence b1,b2,b3,…,b n-1 The arrangement is as follows: when j=1, b1, b2, b3, ..., b n-1 Arranged as b n-1 -b n-2 -b n-3 -…-b2-b1, otherwise arrange as b j-1 -b j-2 -…-b2-b1-b n-1 -b n-2 -…-b j Then, based on this sequence, determine from left to right whether it is 1. If it is 1, change it to 0, until mt 1s become 0; If m < t, then in the reverse direction of the capacitor charge and discharge priority sequence, b1, b2, b3, …, b n-1 are rearranged. The rearrangement method is as follows: When j = 1, b1, b2, b3, …, b n-1 are arranged as b n-1 -b n-2 -b n-3 -…-b2 - b1, otherwise they are arranged as b j-1 -b j-2 -…-b2 - b1 - b n-1 -b n-2 -…-b j ; then sequentially determine whether each of them is 0 according to this sequence. If it is 0, change it to 1 until t - m zeros are changed to 1; (5-4) Obtain the switching signal S w1 =b1,S w2 =b2,…,S wn-1 =b n-1 .

11. A control method for a wireless power transfer system based on a multilevel inverter with pulse amplitude modulation (PMM) as described in claim 1, wherein, The control method includes a Δ-Σ based PMM method. The Δ-Σ based PMM method includes the following steps: (1) Define the square-wave signal A and let its initial value be 0. In each control period, let A = 1 - A; (2) The given modulation wave command signal δ PMM * With the output δ of the latch PMM1 The input e of the integrator is obtained by subtracting from the adder, where e = δ. PMM * -δ PMM1 ,in, v PMM1 The initial value is 0; (3) According to the input e of the integrator, obtain the output u of the integrator, u = Ke / s, where K is the integration coefficient of the integrator and s is the Laplace operator; (4) Using the output u of the integrator as the input of the quantizer, the output δ of the quantizer is obtained. PMM ; (5) Output δ from the quantizer PMM As the input to the latch, the output δ of the latch is obtained. PMM1 The latch is implemented as follows: Define a variable g, with an initial value of 0; if g ≤ 0, then δ PMM1 =δ PMM If g = 1, then g = g - 1, δ PMM1 Remain unchanged; (6) Set the output v of the latch PMM1 Multiplying the square wave signal A by the output y of the PMM method based on Δ-∑ is obtained.

12. The control method according to claim 11, wherein, The implementation method of the quantizer is as follows: where m = 1, 2, …, n - 2.

13. A control method for a wireless power transfer system based on a multilevel inverter using pulse amplitude modulation (PMM) as described in claim 1, the control method comprising a Δ-∑-based PMM method with output y and a token-rotation-based flying capacitor voltage balancing method, wherein... Define the priority symbol j and let its initial value be 1. The token-rotation based flying-capacitor voltage balancing method performs the following steps according to the control period: (1) Judge 0 < y < 1: If so, then j = j - 1, and go to step (2); otherwise j remains unchanged, and go to step (3); (2) Judge j < 0: If so, then j = n - 3, go to step (3); otherwise go to step (3); (3) Based on the sampling voltages u1, u2, u3, ..., u of the flying capacitor of the flying capacitor type n-level inverter circuit, the sampling voltages are obtained. n-2 We get a1, a2, a3, ..., a n-2 Let the array A n [a1,a2,a3,…,a] n-2 ]; (4) Based on array A n And j, to obtain the optimal output array B n Among them, B n =[b1,b2,b3,…,b n-1 ]; (5) Based on the optimal output array B n And y, to obtain the switching signal S w1 To S wn-1 ; (6) The switching signal S w1 To S wn-1 As an input to the driving circuit, the output of the driving circuit controls the switching transistor of the flying capacitor type n-level inverter circuit to turn on or off.

14. The control method according to claim 13, wherein, In step (2), based on the sampled voltages u1, u2, u3, ..., u n-2 We get a1, a2, a3, ..., a n-2 The method is as follows: Where m is 1, 2, ..., n-2, V dc This is the steady-state value of the DC-side voltage of the flying capacitor type n-level inverter circuit.

15. The control method according to claim 13, wherein, In step (4), based on array A n And j, to obtain the optimal output array B n The steps are as follows: (4-1) Determine A n (0)>0, if so, then B n (0) is 0, B n (1) is 1, otherwise it is B. n (0) is 1, B n (1) is 0; then, determine A. n (1)>0, if so then B n (2) is 1, otherwise B n (2) is 0; continue to judge A. n (2)>0, if so then B n (3) is 1, otherwise B n (3) If it is 0, use this pattern to judge A sequentially. n (3)>0, A n (4)>0,…,A n (n-2)>0, thus obtaining the optimal output array B. n ; (4-2) Based on the priority symbol j, determine A n (j)>0, if so, then B n (j) is 1, otherwise B n (j) is 0.

16. The control method according to claim 13, wherein, In step (5), the optimal output array B is used as described. n The switching signal S is obtained from y. w1 To S wn-1 The steps are as follows: (5-1) Calculate the switching signal S based on y. w1 To S wn-1 The number of 1s in the middle is defined as m, and its calculation method is as follows: m = y(n - 1) where y consists of "1", "(n - 2) / (n - 1)", "(n - 3) / (n - 1)", … and "0", and m consists of "n - 1", "n - 2", …, "1" and "0"; (5-2) Calculate B n The number of 1s in the sequence is defined as t, and its calculation method is as follows: t=b1+b2+b3+…b n-1 (5 - 3) Judge the magnitude relationship between m and t: If m = t, then go to step (5 - 4); If m > t, then in the reverse direction of the capacitor charge - discharge priority sequence, b1,b2,b3,…,b n-1 The arrangement is as follows: when j=1, b1, b2, b3, ..., b n-1 Arranged as b n-1 -b n-2 -b n-3 -…-b2-b1, otherwise arrange as b j-1 -b j-2 -…-b2-b1-b n-1 -b n-2 -…-b j Then, based on this sequence, determine from left to right whether it is 1. If it is 1, change it to 0, until mt 1s are changed to 0. If m < t, then in the reverse direction of the capacitor charge and discharge priority sequence, b1, b2, b3, …, b n-1 are rearranged. The rearrangement method is as follows: when j = 1, b1, b2, b3, …, b n-1 are arranged as b n-1 -b n-2 -b n-3 -…-b2 - b1; otherwise, they are arranged as b j-1 -b j-2 -…-b2 - b1 - b n-1 -b n-2 -…-b j ; then, according to this sequence, it is successively judged whether it is 0. If it is 0, it is changed to 1 until t - m zeros are changed to 1; (5-4) Obtain the switching signal S w1 =b1,S w2 =b2,…,S wn-1 =b n-1 .

17. A pulse - amplitude modulation PMM method based on Δ - ∑, the method is implemented on a Δ - ∑ - based PMM modulator including an adder, an integrator, a quantizer, a latch and a multiplier connected in sequence, and the method includes the following steps: (1) Define a square - wave signal A, let its initial value be 0, and in each control period, let A = 1 - A; (2) The given modulation wave command signal δ PMM * With the output δ of the latch PMM1 The input e of the integrator is obtained by subtracting from the adder, where e = δ. PMM * -δ PMM1 ,in, δ PMM1 The initial value is 0; (3) According to the input e of the integrator, obtain the output u of the integrator, u = Ke / s, where K is the integration coefficient of the integrator and s is the Laplace operator; (4) Using the output u of the integrator as the input of the quantizer, the output δ of the quantizer is obtained. PMM ; (5) Output δ from the quantizer PMM As the input to the latch, the output δ of the latch is obtained. PMM1 The latch is implemented as follows: Define a variable g, with an initial value of 0; if g ≤ 0, then δ PMM1 =δ PMM If g = 1, then g = g - 1, δ PMM1 Remain unchanged; (6) Set the output v of the latch PMM1 Multiplying the square wave signal A by the output y of the PMM method based on Δ-∑ is obtained.

18. The method according to claim 17, wherein, The implementation method of the quantizer is as follows: where m = 1, 2, …, n - 2.

19. A capacitor voltage balancing method based on token switching, wherein, Define a priority symbol j, let its initial value be 1, the output of the Δ - ∑ - based pulse - amplitude modulation PMM modulator is y, and the flying - capacitor voltage balancing method based on token rotation implements the following steps according to the control period: (1) Judge 0 < y < 1: If so, then j = j - 1, go to step (2); otherwise j remains unchanged, go to step (3); (2) Judge j < 0: If so, then j = n - 3, go to step (3); otherwise go to step (3); (3) The sampling voltages u1, u2, u3, ..., u are based on the voltage of the flying capacitor in the flying capacitor type n-level inverter circuit. n-2 We get a1, a2, a3, ..., a n-2 Let the array A n [a1,a2,a3,…,a] n-2 ]; (4) Based on array A n And j, to obtain the optimal output array B n Among them, B n =[b1,b2,b3,…,b n-1 ]; (5) Based on the optimal output array B n And y, to obtain the switching signal S w1 To S wn-1 ; (6) The switching signal S w1 To S wn-1 As an input to the drive circuit, the output of the drive circuit controls the switching of the switching transistor of the flying capacitor type n-level inverter circuit to turn on or off.

20. The capacitor voltage balancing method according to claim 19, wherein, In step (2), based on the sampled voltages u1, u2, u3, ..., u n-2 We get a1, a2, a3, ..., a n-2 The method is as follows: Where m is 1, 2, ..., n-2, V dc This is the steady-state value of the DC-side voltage of the flying capacitor type n-level inverter circuit.

21. The capacitor voltage balancing method according to claim 19, wherein, In step (4), based on array A n And j, to obtain the optimal output array B n The steps are as follows: (4-1) Determine A n (0)>0, if so, then B n (0) is 0, B n (1) is 1, otherwise it is B. n (0) is 1, B n (1) is 0; then, determine A. n (1)>0, if so then B n (2) is 1, otherwise B n (2) is 0; continue to judge A. n (2)>0, if so then B n (3) is 1, otherwise B n (3) If it is 0, use this pattern to judge A sequentially. n (3)>0, A n (4)>0,…,A n (n-2)>0, thus obtaining the optimal output array B. n ; (4-2) Based on the priority symbol j, determine A n (j)>0, if so, then B n (j) is 1, otherwise B n (j) is 0.

22. The control method according to claim 19, wherein, In step (5), the optimal output array B is used as described. n The switching signal S is obtained from y. w1 To S wn-1 The steps are as follows: (5-1) Calculate the switching signal S based on y. w1 To S wn-1 The number of 1s in the middle is defined as m, and its calculation method is as follows: m = y(n - 1) where y consists of "1", "(n - 2) / (n - 1)", "(n - 3) / (n - 1)", … and "0", and m consists of "n - 1", "n - 2", …, "1" and "0"; (5-2) Calculate B n The number of 1s in the sequence is defined as t, and its calculation method is as follows: t=b1+b2+b3+…b n-1 (5 - 3) Judge the magnitude relationship between m and t: If m = t, then go to step (5 - 4); If m > t, then in the reverse direction of the capacitor charge - discharge priority sequence, b1,b2,b3,…,b n-1 The arrangement is as follows: when j=1, b1, b2, b3, ..., b n-1 Arranged as b n-1 -b n-2 -b n-3 -…-b2-b1, otherwise arrange as b j-1 -b j-2 -…-b2-b1-b n-1 -b n-2 -…-b j Then, based on this sequence, determine from left to right whether it is 1. If it is 1, change it to 0, until mt 1s are changed to 0. If m < t, then in the reverse direction of the capacitance charge and discharge priority sequence, b1, b2, b3, …, b n-1 are rearranged. The rearrangement method is as follows: When j = 1, b1, b2, b3, …, b n-1 are arranged as b n-1 -b n-2 -b n-3 -…-b2 - b1, otherwise they are arranged as b j-1 -b j-2 -…-b2 - b1 - b n-1 -b n-2 -…-b j ; then sequentially determine whether each of them is 0 according to this sequence. If it is 0, change it to 1 until t - m zeros are changed to 1; (5-4) Obtain the switching signal S w1 =b1,S w2 =b2,…,S wn-1 =b n-1 .

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