LLC-DCX parameter optimization design method considering backflow power factor

Abstract

The invention discloses an LLC-DCX parameter optimization design method considering a backflow power factor, and relates to the technical field of power electronics, and the method comprises the following steps: S1, determining the transformation ratio and switching frequency of a transformer according to design requirements; s2, establishing an FHA model containing equivalent parasitic capacitance; s3, optimizing the excitation inductance and the dead time based on the total loss relation curve; s4, representing the backflow power by using the time lag so as to optimize the resonance parameter; and S5, correcting and judging parameters, ensuring that the sum of the total loss of the switching device and the backflow power is minimum, and completing global optimization. The method aims at solving the problems that the device loss rises and the system efficiency is reduced due to the fact that the backflow power is increased, through systematic optimization, the backflow power can be remarkably restrained, the device loss is reduced, and finally the optimal transmission efficiency of the converter is achieved.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to an LLC-DCX parameter optimization design method that takes into account the return power factor. Background Technology

[0002] Resonant converters have become a hot topic in engineering applications and research in recent years due to their advantages such as high efficiency, high power density, and low electromagnetic interference. The LLC resonant converter, as one of the most basic resonant topologies, has the core advantage of achieving high conversion efficiency through soft switching. When the switching frequency f of the LLC resonant converter... s Approaching the resonant frequency f r When operating in this mode, the transformer achieves its highest efficiency, and its operating characteristics are similar to those of a transformer, hence it is also called an LLC DC transformer (LLC-DC Transformer, LLC-DCX). However, when the inductor and capacitor resonate, a phase shift between voltage and current occurs, inevitably causing backflow power during operation. Increased backflow power significantly increases the current stress and conduction losses of the switching devices, thereby reducing the overall system efficiency.

[0003] Currently, the methods proposed to suppress the backflow power problem of resonant converters can be mainly divided into three categories: 1. Optimizing control strategies; 2. Improving topology; 3. Optimizing resonant parameters.

[0004] Reducing the phase shift between resonant current and voltage by improving the control strategy requires establishing an accurate time-domain model to calculate multiple control variables in real time. This makes the control strategy difficult to implement and prone to losing soft-switching characteristics. Introducing additional resonant parameters or using dynamic resonant parameter control increases the system's degrees of freedom and can effectively reduce backflow power, but it also increases the complexity of modeling and analysis due to the added components or structures, reducing the accuracy of the model. Therefore, to address the efficiency optimization problem of resonant converters, backflow power can be fundamentally suppressed through the optimized design of resonant parameters. However, current parameter optimization methods for backflow power are still constrained by the traditional LLC resonant parameter design approach, often relying on the fundamental frequency approximation method (FHA) model, mainly addressing the voltage gain range requirements of closed-loop control. When this method is used for open-loop fixed-frequency LLC-DCX converters, it not only fails to maximize the suppression of backflow power but also fails to fully utilize its advantages as a DC transformer.

[0005] Current related patents are mostly single-objective optimizations, failing to achieve multi-objective collaborative optimization for the open-loop fixed-frequency characteristics of LLC-DCX. Comparative document CN120090453A focuses on soft-switching protection of CLLC converters, achieving this only through magnetizing inductor optimization, without addressing the open-loop fixed-frequency scenario of LLC-DCX and return current power, and lacks global parameter optimization; CN117833684A analyzes the relationship between CLLC return current power and resonant parameters, but for closed-loop control, it does not introduce an equivalent parasitic capacitance correction model, and lacks joint optimization of losses and return current power; CN108631597A aims to minimize the conduction loss of the LLC converter, only adapting to voltage gain, without considering return current power and LLC-DCX characteristics. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing technologies by providing a parameter optimization design method for LLC-DCX that considers the return power factor. Compared to traditional parameter design methods, this method considers the impact of return power on the efficiency of the LLC-DCX converter, balancing return power suppression with power device loss optimization, thereby achieving optimal transmission efficiency. This patent establishes an FHA model containing equivalent parasitic capacitance, optimizes the magnetizing inductance, dead time, and resonant parameters respectively, and finally corrects the parameters to ensure that the sum of total device loss and return power is minimized. This process achieves the effects of suppressing return power, reducing device losses, and improving model accuracy, thus realizing global optimization and high-efficiency transmission of the LLC-DCX converter.

[0007] To achieve the above objectives, the present invention employs the following technical solution:

[0008] An LLC-DCX parameter optimization design method considering return power factor includes the following steps:

[0009] Step S1: Determine the transformer turns ratio and switching frequency according to the LLC-DCX converter design requirements;

[0010] Step S2: Based on the transformer and secondary-side switching devices designed for the LLC-DCX converter, establish an equivalent parasitic capacitance C. eq The FHA model;

[0011] Step S3: Based on the formula for the effective value of the conduction current of the primary and secondary switching devices and the calculation method for the turn-off loss of the primary switching transistor, obtain the total loss P of the switching devices. loss With dead time t dead Relationship curve P loss =f1(t dead Select the option corresponding to the total loss P of the switching device. loss Minimum dead time t dead And calculate the excitation inductance L at this time according to the formula. m ;

[0012] Step S4: Based on the input impedance formula of the LLC resonant equivalent circuit, utilize the time t that the resonant current lags behind the input voltage of the resonant cavity. lag Characterizing the return power P back , to obtain t lag With resonant inductor L r Relationship curve t lag =f2(L r The curve is selected to correspond to the time t that the resonant current lags behind the input voltage of the resonant cavity. lag Minimum resonant inductance L r And calculate the excitation inductance C at this time according to the formula. r ;

[0013] Step S5: Determine the obtained t lag With t dead Size, if t dead >t lag Then make t respectively lag =t dead and t dead =t lag Calculate the total loss P of the switching device for the two sets of parameters. loss and return power P back The sum of P all and P all2 Select the set of parameters with the smaller loss and choose the corresponding excitation inductance L. m Dead time t dead Resonant inductor L r and resonant capacitor C r As the optimal parameter, complete the global optimization design; if t dead ≤t lag Then directly select t dead ≤t lag Excitation inductance L at time m Dead time t dead Resonant inductor L r and resonant capacitor C r As the optimal parameters, complete the global optimization design.

[0014] Furthermore, in step S1, the transformer turns ratio n and switching frequency f are determined according to the LLC-DCX converter design requirements. s .

[0015] Furthermore, step S2 takes into account the parasitic capacitance C. eq The FHA model, based on the transformer and secondary-side switching devices designed for the LLC-DCX converter, obtains the equivalent capacitance C of the secondary-side MOSFET output capacitor to the primary side of the transformer under full-wave rectification conditions. p_mos The equivalent capacitance value is:

[0016]

[0017] Among them, C j is the output capacitor of the secondary-side MOSFET, and n is the transformer turns ratio.

[0018] Furthermore, in step S2, the parasitic capacitance C is taken into account. eq The FHA model is used to obtain the equivalent parasitic capacitance C based on the transformer and secondary switching devices designed for the LLC-DCX converter. eq The equivalent capacitance value is:

[0019] C eq =C po +C so_eq +C ps_eq +C p_mos

[0020] Among them, C po C is the primary winding capacitance. so_eq C is the equivalent capacitance of the capacitance between the secondary windings referred to the primary winding of the transformer. ps_eq C is the equivalent capacitance of the capacitance between the primary and secondary windings referred to the primary winding of the transformer. p_mos The output capacitance of the secondary-side MOSFET under full-wave rectification is equivalent to the equivalent capacitance of the transformer primary side. Furthermore, in step S3, under the primary-side ZVS condition, the total switching device loss P... loss Represented as:

[0021] P loss =I 2 rms_p R ds_p +I 2 rms_s R ds_s +P off

[0022] Among them, I rms_p I is the effective value of the primary current. rms_s P is the effective value of the secondary current. off R is the turn-off loss of the primary-side switch. ds_p R is the on-resistance of the primary-side switch. ds_s This is the on-resistance of the secondary-side switch.

[0023] Furthermore, in step S3, under the condition of primary-side ZVS, the excitation inductance L m The effective value of the primary current I rms_p Effective value of secondary current I rms_s and the turn-off loss P of the primary-side switch off With dead time t dead The relationship is represented as:

[0024]

[0025]

[0026] Among them, V o The output voltage is given by n, where n is the transformer turns ratio and T is the output voltage. o T is the actual on-time of the MOSFET. s =T o +2t dead R is the switching cycle of the primary and secondary switching transistors. L C is the equivalent load resistance. j For the output capacitor of the secondary-side MOSFET, t f f is the turn-off time of the primary-side switch. s This represents the switching frequency of the primary and secondary side switching transistors.

[0027] Furthermore, in step S3, under the condition of ZVS on the primary edge, I rms_p I rms_s P off From dead time t dead The total loss P of the switching device is determined. loss With dead time t dead Relationship curve P loss =f1(t dead According to the relationship curve P loss =f1(t dead ), select the one corresponding to the total loss P of the switching device loss Minimum dead time t dead And calculate the excitation inductance L at this time according to the formula. m .

[0028] Furthermore, in step S4, the input impedance Z of the LLC resonant equivalent circuit... in for:

[0029] Z in =Z Lr +Z Cr +Z m / / R L / / Z eq

[0030] Among them, Z Lr Z is the resonant inductor impedance value. Cr Z is the impedance value of the resonant capacitor. m R is the magnetizing inductance resistance value. L Z is the equivalent load resistance. eq This is the equivalent parasitic capacitance impedance value.

[0031] Furthermore, in step S4, the resonant current lags behind the input voltage of the resonant cavity by a time t. lag With resonant inductor L r The relationship between them is:

[0032]

[0033] Among them, L r C is the resonant inductance value. r f is the resonant capacitance value. s Let θ be the switching frequency of the switching transistor, and θ be the phase lag between the resonant current and the input voltage of the resonant cavity. in Re(Z) represents the imaginary part of the input impedance. in ) represents the real part of the input impedance.

[0034] Furthermore, in step S4, the input impedance Z of the LLC resonant equivalent circuit... in From the resonant inductor L r and resonant capacitor C r The time t that the resonant current lags behind the input voltage of the resonant cavity is determined. lag With resonant inductor L r There exists a relationship curve t lag =f2(L r According to the relationship curve t lag =f2(L r ), select the time t corresponding to the resonant current lagging behind the input voltage of the resonant cavity. lag Minimum resonant inductance L r And calculate the resonant capacitance C at this time according to the formula. r .

[0035] Furthermore, in step S4, the resonant capacitor C r With resonant inductor L r The relationship between them is:

[0036]

[0037] Among them, L r C is the resonant inductance value. r f is the resonant capacitance value. s This refers to the switching frequency of the switching transistor. Furthermore, in step S5, the return power P... back for:

[0038]

[0039] Among them, V DS i is the drain-source voltage of the primary-side switching transistor. Lr For the resonant inductor current, v Cr V is the voltage across the resonant capacitor. oThe output voltage is given by n, where n is the transformer turns ratio and T is the output voltage. s f is the switching period of the primary and secondary switching transistors. s This represents the switching frequency of the primary and secondary side switching transistors.

[0040] Furthermore, in step S5, the obtained t is determined. lag With t dead Size, if t dead >t lag Then take t respectively lag1 =t dead1 =t dead and t dead2 =t lag2 =t lag Calculate the total loss P of the switching device for the two sets of parameters. loss and return power P back The sum of P all and P all2 If P all ≤P all2 Then, based on the relationship curve t lag =f2(L r Matching corresponds to t lag1 resonant inductance L r1 and resonant capacitor C r1 Select resonant inductor L r1 and resonant capacitor C r1 The excitation inductance L obtained in step S3 m Dead time t dead As the optimal parameter, if P all >P all2 Then according to the magnetizing inductance L m The expression matching corresponds to t dead2 L m2 Select excitation inductor L m2 and dead zone time t dead2 The resonant inductance L obtained in step S4 r Resonant capacitor C r As the optimal parameter; if t dead ≤t lag Then directly select t dead ≤t lag Excitation inductance L at time m Dead time t dead Resonant inductor L r and resonant capacitor C r As the optimal parameters, complete the global optimization design.

[0041] Compared with the prior art, the present invention can achieve the following beneficial effects:

[0042] (1) This invention addresses the problem of reduced efficiency caused by backflow power in LLC-DCX converters. It uses the time that the resonant current lags behind the input voltage of the resonant cavity to characterize the backflow power, establishes the relationship curve between this time and the resonant inductor and resonant capacitor, and suppresses the backflow power from the source by optimizing these two resonant parameters. This adapts to the open-loop fixed-frequency characteristics of LLC-DCX and effectively improves the converter's transmission efficiency.

[0043] (2) Under the condition of zero voltage conduction on the primary side, this invention combines the formula of the effective value of the conduction current of the primary and secondary switching devices and the calculation method of the turn-off loss to establish the relationship curve between the total loss of the switching device and the excitation inductance and dead time. Based on this, the optimal excitation inductance and dead time are selected, which reduces the device conduction loss and turn-off loss and ensures the stable operation of the switching device.

[0044] (3) This invention establishes an FHA model that considers equivalent parasitic capacitance, accurately calculates the transformer primary winding capacitance, the equivalent capacitance of the secondary winding converted to the primary side, and the equivalent capacitance of the secondary MOS transistor output capacitance converted to the primary side, and incorporates these parasitic parameters into the model analysis, eliminating the error caused by neglecting parasitic parameters in the traditional FHA model, making the model more in line with actual working conditions, and providing accurate data support for subsequent parameter optimization.

[0045] (4) The present invention determines the magnitude of the resonant current lag time and dead time through the parameter correction link, and calculates the sum of the total loss of the switching device and the return power after correcting the relevant parameters, ensuring that the sum of the two is smaller, realizing global parameter collaborative optimization, avoiding the efficiency improvement limitations caused by single target optimization in the prior art, and significantly improving the converter transmission efficiency. Attached Figure Description

[0046] Figure 1 This is a flowchart of an LLC-DCX parameter optimization design method considering the return power factor proposed in this invention;

[0047] Figure 2 This is a schematic diagram of the main circuit of the half-bridge LLC-DCX converter considering parasitic capacitance in this invention;

[0048] Figure 3 The parasitic capacitance C is considered in this invention. eq FHA model diagram;

[0049] Figure 4 The total loss P of the switching device in this invention loss With dead time t dead Relationship curve diagram;

[0050] Figure 5 This is a schematic diagram of the return power of the half-bridge LLC-DCX in this invention;

[0051] Figure 6The resonant current lag time t in this invention lag With resonant inductor L r Relationship curve t lag =f2(L r )curve;

[0052] Figure 7 The resonant current lag time t of this invention lag Simulation results;

[0053] Figure 8 The resonant current lag time t in the traditional method lag Simulation results. Detailed Implementation

[0054] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. The technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] Combination Figure 1 This invention proposes a parameter optimization design method for LLC-DCX considering the return power factor, comprising the following steps:

[0056] Step S1: Determine the transformer turns ratio and switching frequency according to the LLC-DCX converter design requirements;

[0057] Step S2: Based on the transformer and secondary-side switching devices designed for the LLC-DCX converter, establish an equivalent parasitic capacitance C. eq The FHA model;

[0058] Step S3: Based on the formula for the effective value of the conduction current of the primary and secondary switching devices and the calculation method for the turn-off loss of the primary switching transistor, obtain the total loss P of the switching devices. loss With dead time t dead Relationship curve P loss =f1(t dead Select the option corresponding to the total loss P of the switching device. loss Minimum dead time t dead And calculate the excitation inductance L at this time according to the formula. m ;

[0059] Step S4: Based on the input impedance formula of the LLC resonant equivalent circuit, utilize the time t that the resonant current lags behind the input voltage of the resonant cavity. lag Characterizing the return power P back , to obtain t lag With resonant inductor Lr Relationship curve t lag =f2(L r The curve is selected to correspond to the time t that the resonant current lags behind the input voltage of the resonant cavity. lag Minimum resonant inductance L r And calculate the excitation inductance C at this time according to the formula. r ;

[0060] Step S5: Determine the obtained t lag With t dead Size, if t dead >t lag Then make t respectively lag =t dead and t dead =t lag Calculate the total loss P of the switching device for the two sets of parameters. loss and return power P back The sum of P all and P all2 Select the set of parameters with the smaller loss and choose the corresponding excitation inductance L. m Dead time t dead Resonant inductor L r and resonant capacitor C r As the optimal parameter, complete the global optimization design; if t dead ≤t lag Then directly select t dead ≤t lag Excitation inductance L at time m Dead time t dead Resonant inductor L r and resonant capacitor C r As the optimal parameters, complete the global optimization design.

[0061] The schematic diagram of the main circuit of the half-bridge LLC-DCX converter considering parasitic capacitance in this invention is shown below. Figure 2 As shown, based on the actual transformer and secondary-side switching devices designed for the LLC-DCX converter, the equivalent capacitance C of the secondary-side MOSFET output capacitor to the primary side of the transformer under full-wave rectification conditions is obtained. p_mos The equivalent capacitance value is:

[0062]

[0063] Among them, C j is the output capacitor of the secondary-side MOSFET, and n is the transformer turns ratio.

[0064] The equivalent parasitic capacitance C is obtained based on the actual transformer and secondary switching devices of the LLC-DCX converter design. eq The equivalent capacitance value is:

[0065] C eq =C po +C so_eq +C ps_eq +C p_mos

[0066] Among them, C po C is the primary winding capacitance. so_eq C is the equivalent capacitance of the capacitance between the secondary windings referred to the primary winding of the transformer. ps_eq C is the equivalent capacitance of the capacitance between the primary and secondary windings referred to the primary winding of the transformer. p_mos This is the equivalent capacitance of the secondary-side MOSFET output capacitor to the primary side of the transformer under full-wave rectification conditions.

[0067] Finally, the equivalent FHA model of the main circuit of the half-bridge LLC-DCX converter considering parasitic capacitance is obtained as follows: Figure 3 As shown.

[0068] Under the condition of primary-side ZVS, the total loss P of the switching device loss Represented as:

[0069] P loss =I 2 rms_p R ds_p +I 2 rms_s R ds_s +P off

[0070] Among them, I rms_p I is the effective value of the primary current. rms_s P is the effective value of the secondary current. off R is the turn-off loss of the primary-side switch. ds_p R is the on-resistance of the primary-side switch. ds_s This is the on-resistance of the secondary-side switch.

[0071] L m I rms_p I rms_s and P off With dead time t dead The relationship is represented as:

[0072]

[0073]

[0074] Among them, V o The output voltage is given by n, where n is the transformer turns ratio and T is the output voltage. o T is the actual on-time of the MOSFET. s =T o +2tdead R is the switching cycle of the primary and secondary switching transistors. L C is the equivalent load resistance. j For the output capacitor of the secondary-side MOSFET, t f f is the turn-off time of the primary-side switch. s This represents the switching frequency of the primary and secondary side switching transistors.

[0075] The total loss P of the switching device was calculated. loss With dead time t dead Relationship curve diagram as follows Figure 4 As shown. According to the relationship curve P loss =f1(t dead ), select the one corresponding to the total loss P of the switching device loss Minimum dead time t dead And calculate the excitation inductance L at this time according to the formula. m .

[0076] Figure 5 This is a schematic diagram of the return power of the half-bridge LLC-DCX in this invention, where the return power P is... back The magnitude of the resonant current lags behind the input voltage of the resonant cavity by the time t. lag Proportional, using t lag Characterizing the return power P back .

[0077] The input impedance Z of the LLC resonant equivalent circuit in for:

[0078] Z in =Z Lr +Z Cr +Z m / / R L / / Z eq

[0079] Among them, Z Lr Z is the resonant inductor impedance value. Cr Z is the impedance value of the resonant capacitor. m R is the magnetizing inductance resistance value. L Z is the equivalent load resistance. eq This is the equivalent parasitic capacitance impedance value.

[0080] The resonant current lags behind the input voltage of the resonant cavity by a time t. lag With resonant inductor L r The relationship between them is:

[0081]

[0082] Among them, f sLet θ be the switching frequency of the switching transistor, and θ be the phase lag between the resonant current and the input voltage of the resonant cavity. in Re(Z) represents the imaginary part of the input impedance. in ) represents the real part of the input impedance.

[0083] The input impedance Z of the LLC resonant equivalent circuit in From the resonant inductor L r and resonant capacitor C r The time t that the resonant current lags behind the input voltage of the resonant cavity is determined. lag With resonant inductor L r There exists a relationship curve t lag =f2(L r According to the relationship curve t lag =f2(L r ), select the time t corresponding to the resonant current lagging behind the input voltage of the resonant cavity. lag Minimum resonant inductance L r And calculate the resonant capacitance C at this time according to the formula. r .

[0084] Resonant capacitor C r With resonant inductor L r The relationship between them is:

[0085]

[0086] Among them, L r C is the resonant inductance value. r f is the resonant capacitance value. s This represents the switching frequency of the switching transistor.

[0087] Return power P back for:

[0088]

[0089] Among them, V DS i is the drain-source voltage of the primary-side switching transistor. Lr For the resonant inductor current, v Cr V is the voltage across the resonant capacitor. o The output voltage is given by n, where n is the transformer turns ratio and T is the output voltage. s f is the switching period of the primary and secondary switching transistors. s This represents the switching frequency of the primary and secondary side switching transistors.

[0090] The obtained t lag With t dead Size, if t dead >t lg Then take t respectively lag1 =t dead1 =tdead and t dead2 =t lag2 =t lag Calculate the total loss P of the switching device for the two sets of parameters. loss and return power P back The sum of P all and P all2 If P all ≤P all2 Then, based on the relationship curve t lag =f2(L r Matching corresponds to t lag1 resonant inductance L r1 and resonant capacitor C r1 Select resonant inductor L r1 and resonant capacitor C r1 The excitation inductance L obtained in step S3 m Dead time t dead As the optimal parameter, if P all >P all2 Then according to the magnetizing inductance L m The expression matching corresponds to t dead2 L m2 Select excitation inductor L m2 and dead zone time t dead2 The resonant inductance L obtained in step S4 r Resonant capacitor C r As the optimal parameter; if t dead ≤t lag Then directly select t dead ≤t lag Excitation inductance L at time m Dead time t dead Resonant inductor L r and resonant capacitor C r As the optimal parameters, complete the global optimization design.

[0091] Based on the above theoretical analysis, simulation comparisons were conducted, and the main technical indicators are shown in Table 1. The comparison images of the main technical indicators obtained from the simulations are shown below. Figure 7 and Figure 8 As shown.

[0092] Table 1 Comparison of Converter Specifications

[0093]

[0094] Simulation results show that, under the same performance parameters, the parameters optimized using this patent can reduce the resonant current lag time t compared to traditional methods. lag The length was shortened by 77%, significantly reducing the return power P of the LLC resonant equivalent circuit. back .

[0095] The above descriptions are merely preferred embodiments of this application, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A parameter optimization design method for LLC-DCX considering return power factor, characterized in that, Includes the following steps: Step S1: Determine the transformer turns ratio n and switching frequency f according to the LLC-DCX converter design requirements. s ; Step S2: Based on the transformer and secondary-side switching devices designed for the LLC-DCX converter, establish an equivalent parasitic capacitance C. eq The FHA model; Step S3: Based on the formula for the effective value of the conduction current of the primary and secondary switching devices and the calculation method for the turn-off loss of the primary switching transistor, obtain the total loss P of the switching devices. loss With dead time t dead Relationship curve P loss =f1(t dead Select the option corresponding to the total loss P of the switching device. loss Minimum dead time t dead And calculate the excitation inductance L at this time according to the formula. m ; Step S4: Based on the input impedance formula of the LLC resonant equivalent circuit, utilize the time t that the resonant current lags behind the input voltage of the resonant cavity. lag Characterizing the return power P back , to obtain t lag With resonant inductor L r Relationship curve t lag =f2(L r The curve is selected to correspond to the time t that the resonant current lags behind the input voltage of the resonant cavity. lag Minimum resonant inductance L r And calculate the excitation inductance C at this time according to the formula. r ; Step S5: Determine the obtained t lag With t dead Size, if t dead >t lag Then make t respectively lag =t dead and t dead =t lag Calculate the total loss P of the switching device for the two sets of parameters. loss and return power P back The sum of P all and P all2 Select the set of parameters with the smaller loss and choose the corresponding excitation inductance L. m Dead time t dead Resonant inductor L r and resonant capacitor C r As the optimal parameter, complete the global optimization design; if t dead ≤t lag Then directly select t dead ≤t lag Excitation inductance L at time m Dead time t dead Resonant inductor L r and resonant capacitor C r As the optimal parameters, complete the global optimization design.

2. The LLC-DCX parameter optimization design method considering return power factor according to claim 1, characterized in that, Step S2 takes into account the parasitic capacitance C. eq The FHA model, based on the transformer and secondary-side switching devices designed for the LLC-DCX converter, obtains the equivalent capacitance C of the secondary-side MOSFET output capacitor to the primary side of the transformer under full-wave rectification conditions. p_mos The equivalent capacitance value is: Among them, C j is the output capacitor of the secondary-side MOSFET, and n is the transformer turns ratio.

3. The LLC-DCX parameter optimization design method considering return power factor according to claim 1, characterized in that, Step S2 takes into account the parasitic capacitance C. eq The FHA model is used to obtain the equivalent parasitic capacitance C based on the transformer and secondary switching devices designed for the LLC-DCX converter. eq The equivalent capacitance value is: C eq =C po +C so_eq +C ps_eq +C p_mos Among them, C po C is the primary winding capacitance. so_eq C is the equivalent capacitance of the capacitance between the secondary windings referred to the primary winding of the transformer. ps_eq C is the equivalent capacitance of the capacitance between the primary and secondary windings referred to the primary winding of the transformer. p_mos This is the equivalent capacitance of the secondary-side MOSFET output capacitor to the primary side of the transformer under full-wave rectification conditions.

4. The LLC-DCX parameter optimization design method considering return power factor according to claim 1, characterized in that, In step S3, under the condition that the primary side ZVS is satisfied, the total loss P of the switching device loss Represented as: P loss =I 2 rms_p R ds_p +I 2 rms_s R ds_s +P off Among them, I rms_p I is the effective value of the primary current. rms_s P is the effective value of the secondary current. off R is the turn-off loss of the primary-side switch. ds_p R is the on-resistance of the primary-side switch. ds_s This is the on-resistance of the secondary-side switch.

5. The LLC-DCX parameter optimization design method considering return power factor according to claim 1, characterized in that, In step S3, under the condition that the primary side ZVS is satisfied, the excitation inductance L m The effective value of the primary current I rms_p Effective value of secondary current I rms_s and the turn-off loss P of the primary-side switch off With dead time t dead The relationship is represented as: Among them, V o The output voltage is given by n, where n is the transformer turns ratio and T is the output voltage. o T is the actual on-time of the MOSFET. s =T o +2t dead R is the switching cycle of the primary and secondary switching transistors. L C is the equivalent load resistance. j For the output capacitor of the secondary-side MOSFET, t f f is the turn-off time of the primary-side switch. s This represents the switching frequency of the primary and secondary side switching transistors.

6. The LLC-DCX parameter optimization design method considering return power factor according to claim 1, characterized in that, In step S3, under the condition that the original edge ZVS is satisfied, I rms_p I rms_s P off From dead time t dead The total loss P of the switching device is determined. loss With dead time t dead Relationship curve P loss =f1(t dead According to the relationship curve P loss =f1(t dead ), select the one corresponding to the total loss P of the switching device loss Minimum dead time t dead And calculate the excitation inductance L at this time according to the formula. m .

7. The LLC-DCX parameter optimization design method considering return power factor according to claim 1, characterized in that, The input impedance Z of the LLC resonant equivalent circuit in step S4 in for: WITH in =Z Lr +Z Cr +Z m / / R L / / WITH eq Among them, Z Lr Z is the resonant inductor impedance value. Cr Z is the impedance value of the resonant capacitor. m R is the magnetizing inductance resistance value. L Z is the equivalent load resistance. eq This is the equivalent parasitic capacitance impedance value; The resonant current lags behind the input voltage of the resonant cavity by a time t. lag With resonant inductor L r The relationship between them is: Among them, L r C is the resonant inductance value. r f is the resonant capacitance value. s Let θ be the switching frequency of the switching transistor, and θ be the phase lag between the resonant current and the input voltage of the resonant cavity. in Re(Z) represents the imaginary part of the input impedance. in ) represents the real part of the input impedance.

8. The LLC-DCX parameter optimization design method considering return power factor according to claim 1, characterized in that, The input impedance Z of the LLC resonant equivalent circuit in step S4 in From the resonant inductor L r and resonant capacitor C r The time t that the resonant current lags behind the input voltage of the resonant cavity is determined. lag With resonant inductor L r There exists a relationship curve t lag =f2(L r According to the relationship curve t lag =f2(L r ), select the time t corresponding to the resonant current lagging behind the input voltage of the resonant cavity. lag Minimum resonant inductance L r And calculate the resonant capacitance C at this time according to the formula. r Resonant capacitor C r With resonant inductor L r The relationship between them is: Among them, L r C is the resonant inductance value. r f is the resonant capacitance value. s This represents the switching frequency of the switching transistor.

9. The LLC-DCX parameter optimization design method considering return power factor according to claim 1, characterized in that, In step S5, the return power P back for: Among them, V DS i is the drain-source voltage of the primary-side switching transistor. Lr For the resonant inductor current, v Cr V is the voltage across the resonant capacitor. o The output voltage is given by n, where n is the transformer turns ratio and T is the output voltage. s f is the switching period of the primary and secondary switching transistors. s This represents the switching frequency of the primary and secondary side switching transistors.

10. The LLC-DCX parameter optimization design method considering return power factor according to claim 1, characterized in that, The t obtained in step S5 lag With t dead Size, if t dead >t lag Then take t respectively lag1 =t dead1 =t dead and t dead2 =t lag2 =t lag Calculate the total loss P of the switching device for the two sets of parameters. loss and return power P back The sum of P all and P all2 If P all ≤P all2 Then, based on the relationship curve t lag =f2(L r Matching corresponds to t lag1 resonant inductance L r1 and resonant capacitor C r1 Select resonant inductor L r1 and resonant capacitor C r1 The excitation inductance L obtained in step S3 m Dead time t dead As the optimal parameter, if P all >P all2 Then according to the excitation inductance L m The expression matching corresponds to t dead2 L m2 Select excitation inductor L m2 and dead zone time t dead2 The resonant inductance L obtained in step S4 r Resonant capacitor C r As the optimal parameter; if t dead ≤t lag Then directly select t dead ≤t lag Excitation inductance L at time m Dead time t dead Resonant inductor L r and resonant capacitor C r As the optimal parameters, complete the global optimization design.

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