Three-phase control with delay compensation for power converters

Abstract

The invention relates to three-phase control with delay compensation for power converters. In some embodiments, a controller for a power converter having a plurality of switches and at least one inductor is provided. The controller includes circuitry configured to: control the power converter according to an operating mode having a first phase in which the controller controls the plurality of switches in a first switching state and a second phase in which the controller controls the plurality of switches in a second switching state; and in response to one or more conditions for transitioning from the first phase to the second phase being not satisfied during a cycle of the operating mode: during the cycle, entering an intermediate phase between the first phase and the second phase by controlling the plurality of switches in a third switching state; and adjusting the duration of the phase following the intermediate phase.

Description

[0001] Cross-references to related applications

[0002] This application is a partial continuation and claims the benefit of U.S. Patent Application No. 18 / 440,349, filed February 13, 2024, which is a continuation and claims the benefit of U.S. Patent Application No. 18 / 180,886, filed March 9, 2023 and published as U.S. Patent No. 11,949,383; U.S. Patent Application No. 18 / 180,886, filed September 4, 2020 and published April 25, 2023 as U.S. Patent No. 11,637,531; and U.S. Patent Application No. 17 / 012,821, claims the benefit of U.S. Provisional Patent Application No. 62 / 896,143, filed September 5, 2019. The contents of the above applications are incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This application relates to a controller for a power converter and a method for controlling a power converter, and more specifically to a three-phase control with delay compensation for a power converter. Background Technology

[0004] The efficiency of a radio frequency (RF) power amplifier (PA) can be improved through “supply modulation” (or “drain modulation” or “collector modulation”), in which the supply voltage provided to the PA is dynamically adjusted over time according to the RF signal being synthesized (“modulation”). For maximum efficiency improvement, the supply voltage can be discretely (i.e., between discrete voltage levels) or continuously adjusted on a short timescale to track or dynamically adapt to variations in the amplitude (or envelope) of the RF signal—such as when data is encoded into the RF signal or when the RF signal amplitude is expected to change with a high envelope bandwidth (e.g., in envelope tracking, advanced envelope tracking, polarity modulation, “Class G” power amplification, multi-stage backoff, multi-stage LINC, asymmetric multi-stage out-of-phase, etc.). The supply voltage (or voltage level) provided to the PA can also be adapted to accommodate long-term variations in the desired RF envelope. This is sometimes referred to as “adaptive bias”. For example, such “long-term variation” can be associated with adjusting the transmitter output strength to reduce and ideally minimize errors in data transmission, or with adjusting the transmitter output strength to change RF “traffic” variations, etc.

[0005] "Continuous" power supply modulation (e.g., "envelope tracking" or "adaptive bias") can be advantageously implemented by dynamically selecting an intermediate voltage from a set of discrete power supply voltages and then further adjusting (e.g., stepwise reducing) the intermediate voltage to produce a continuously variable power supply voltage to be provided to a power amplifier. Some RF amplifier systems utilize "discrete" power supply modulation (or discrete "drain modulation"), in which the power supply voltage is switched between a set of discrete voltage levels, possibly including additional filtering or modulation to shape the voltage transitions between levels. This type of system is known and includes "Class-G" amplifiers, multi-level LINC (MLINC) power amplifiers, asymmetric multi-level outphasing (AMO) power amplifiers, multi-level back-off amplifiers (including "asymmetric multi-level back-off" amplifiers), and digital polar transmitters, among others.

[0006] Hybrid systems utilizing a combination of continuous and discrete power supply modulation can also be implemented. Figure 1 An overview of an illustrative system architecture for an RF amplifier system utilizing power supply modulation is shown, in which a power supply modulator switches between multiple voltages generated by a multi-output power supply generator. (Aspects of signal processing and control for such a system are not shown). Figure 1 An example implementation of an architecture particularly suitable for discrete power supply modulation is also shown in FIG. SUMMARY

[0007] Concepts, systems, circuits, and techniques for power management are described. In particular, concepts, systems, circuits, and techniques for power management are described that are directed to innovations in the design and control of power supply generators including multi-output power supply generators. The concepts, systems, circuits, and techniques described herein can be used for a variety of applications, including but not limited to mobile handset applications as well as many other power management applications.

[0008] According to one aspect of the concepts described herein, techniques for controlling a magnetic regulation stage include: turning on a first set of switches of the magnetic regulation stage to implement a desired mode of operation; and in response to a condition not being met for transitioning to a second phase of the first mode of operation, automatically entering at least one intermediate N-phase mode by turning on at least a selected different second set of switches.

[0009] With this particular arrangement, a control method is provided that allows for a more efficient transfer of energy from the input of the magnetic regulation stage to the output of the magnetic regulation stage, particularly for voltage conversion ratios close to one.

[0010] In embodiments, improvements in the design and control of multi-output power supply generators and their use in multi-level power supplies for radio frequency (RF) systems, including but not limited to RF power amplifier (PA) systems, are described. These advanced aspects can be particularly valuable in situations where some form of buck-boost power conversion is required (e.g., to synthesize an output voltage that can be higher or lower than an available input voltage). The described concepts, systems, circuits, and techniques can also be applied to other applications where buck-boost power conversion is employed.

[0011] According to one aspect of the concepts described herein, a multi-output power supply generator includes a magnetic regulation stage coupled to a multi-output switched capacitor circuit. The magnetic regulation stage regulates one power supply generator output that is also an input to the switched capacitor circuit, which supplies other outputs of the multi-output power supply generator. The magnetic regulation stage is configured to operate in at least one intermediate phase between a first phase and a last phase of a magnetic regulation stage operating mode.

[0012] With this particular arrangement, a multi-output power supply generator suitable for use as part of an RF amplifier system is provided. Utilizing a controllable magnetic stage to regulate the voltage at one or more outputs of the multi-output power supply generator, while the voltage at other outputs of the multi-output power supply generator (i.e., the outputs that are not controlled by the magnetic stage) is determined by the operation of the switched capacitor stage, provides a flexible multi-output power supply generator. Moreover, by utilizing multiple voltages provided by the switched capacitor stage, stress on devices (e.g., active devices) and inductive elements in the magnetic regulation stage is reduced. In embodiments, the magnetic regulation stage can be provided as a buck-boost magnetic regulation stage.

[0013] According to another aspect of the concepts described herein, a hybrid magnetic / switched capacitor multi-output power supply generator includes a multi-output switched capacitor stage and a magnetic regulation stage that accesses two or more ports of the switched capacitor stage.

[0014] With this particular arrangement, a multi-output power supply generator with buck-boost capability is provided with reduced device and inductor stress compared to prior art approaches.

[0015] According to yet another aspect of the concepts described herein, a hybrid magnetic / switched capacitor multi-output power supply generator includes a multi-output switched capacitor stage and a magnetic regulation stage. The magnetic regulation stage includes an inductive element having a first terminal and a second terminal and a means for switching one or both terminals of the inductive element to a plurality of ports of the switched capacitor stage.

[0016] With this particular arrangement, a multi-output power supply generator is provided with reduced inductor stress / size, wider operating range capability, improved efficiency, and better control characteristics.

[0017] According to another aspect of the concept described herein, a method for controlling a magnetic conditioning stage having a first operating mode and a second final operating mode within a switching cycle of a magnetic conditioning stage includes: turning on a first set of switches of the magnetic conditioning stage to achieve a desired operating mode; and automatically entering at least one intermediate N-phase mode by turning on at least one selected different second set of switches in response to a condition that the transition to the first operating mode is not met.

[0018] In one implementation, the method further includes selecting a desired operating mode. Selecting the desired operating mode in one implementation includes selecting the desired operating mode while considering one or more of the following: signal hysteresis; and conversion ratio hysteresis.

[0019] In implementation, selecting the desired operating mode also includes setting a minimum and / or maximum duration for residing in the mode once the mode is selected.

[0020] According to another aspect of the concept described herein, the N-phase control method for the magnetic level includes: at the beginning of a cycle, turning on a switch to initiate one of the following: a buck operation mode and a boost operation mode; and automatically entering one of the following in response to the failure to meet a desired condition within a specified time or a specified duty cycle: an N-phase buck + buck-boost mode, in which the switch configuration is changed to provide boost capability; or an N-phase boost + buck-boost mode, in which the switch configuration is changed to provide buck capability.

[0021] In this implementation, in response to the achievement of the desired conditions, the system enters the final switching state of the magnetic adjustment stage switching cycle.

[0022] According to another aspect of the concept described herein, the three-phase control method for the magnetic level includes: at the beginning of the cycle, for the first phase, turning on the first set of switches in the magnetic level to achieve a step-down mode during the first phase at the beginning of the cycle; observing the current i through the inductor in the magnetic level. L The observed inductor current i L Compare with the target current; in response to reaching the conduction duration D UM The inductor current i before T L When the target current is reached, the second set of switches is turned on to enter the second phase of the cycle; in response to the inductor current i L The conduction duration of the first phase exceeds a specified value (D) before the target current is reached. UM T), the first phase ends and the third set of switches is automatically turned on to enter the intermediate phase corresponding to, for example, the buck + buck-boost operation mode.

[0023] The first phase, intermediate phase, and second phase are sometimes referred to herein as "Phase 1," "Phase 1A," and "Phase 2," respectively.

[0024] The target current can be defined as a reference value (e.g., a value preprogrammed, set, or otherwise provided to the controller) corresponding to at least one of: a peak current, an average current, a valley current, or a peak / average / valley current minus a compensation ramp. In the case of a peak current, the target current can be represented as i P In the case of a valley current, the target current can be represented as i V .

[0025] According to some embodiments, the on duration D UM T can be defined by a limit duty cycle (D UM ) and a cycle period (T) such that D UM T is the maximum duration of the first phase of the cycle. In other embodiments, the limit duty cycle can be referred to as D ON or D MAX and similarly used to limit the maximum duration of the first phase before entering the intermediate phase.

[0026] In embodiments, in response to the inductor current i L reaching the target current in the intermediate phase, the second set of switches is turned on to enter the second phase of the cycle.

[0027] In embodiments, the method further includes making a decision at the start of the switching cycle based on one or more inputs to start the cycle in (1) a buck mode or (2) a boost mode.

[0028] In embodiments, the method further includes operating the boost mode in a valley current mode control.

[0029] In embodiments, the method further includes providing an offset in the current mode compensator that is different depending on whether the cycle is started in the buck mode or the boost mode.

[0030] In embodiments, automatically turning on the third set of switches to enter the buck+ buck-boost mode includes changing the switching configuration of the magnetic stage to implement a boost state.

[0031] According to yet another aspect of the concepts described herein, a three-phase control method for a magnetic stage includes: at the start of a cycle, for a first phase, turning on a first set of switches in the magnetic stage to implement a boost mode during the first phase at the start of the cycle; observing a current i L through an inductor in the magnetic stage; comparing the observed inductor current i L to a target current; in response to the inductor current i UM reaching an on duration D T before reaching the target current, turning on a second set of switches in the magnetic stage to enter a second phase of the cycle.L When the target current is reached, the second set of switches is turned on (e.g., q). B q D Phase 2 of the cycle is entered; and in response to the inductor current i L The conduction duration of phase 1 exceeds the specified value (D) before the target current is reached. UM T), end phase 1 and automatically turn on the third group of switches to enter the boost + buck - boost mode.

[0032] In one implementation, automatically turning on the third set of switches to enter the boost + buck - boost mode includes changing the switching configuration of the magnetic poles to achieve a buck state.

[0033] According to one aspect of this disclosure, a controller is provided for a power converter having a plurality of switches and at least one inductor, the controller comprising a circuit system configured to: control the power converter according to at least one operating mode having at least a first phase and a second phase, wherein in the first phase, the controller controls the plurality of switches to a first switching state, and wherein in the second phase, the controller controls the plurality of switches to a second switching state; and in response to one or more conditions for switching from the first phase to the second phase not being met during a cycle of at least one operating mode: during the cycle, entering an intermediate phase between the first and second phases by controlling the plurality of switches to a third switching state; and adjusting the duration of the phase following the intermediate phase by a value ΔT.

[0034] In some implementations, the duration-adjusted phase is part of a cycle that enters an intermediate phase, such that the cycle duration is also adjusted. In some implementations, the duration-adjusted phase is the second phase of the cycle. In some implementations, the controller is configured to adjust the phase duration by overriding the start of the next cycle to maintain the second switching state for a duration of value ΔT.

[0035] In some embodiments, ΔT is selected based at least in part on at least one of the following: the voltage conversion ratio of the power converter; the output voltage of the power converter; the current value of at least one inductor; and the power level of the power converter. In some embodiments, ΔT is selected based at least in part on at least one of the following: a reference value; a measured value; and a command value. In some embodiments, ΔT is selected to approximate |V|. L1A / V L2 | proportional, where V L1A It is the voltage across at least one inductor during the intermediate phase, and V L2It is the voltage across at least one inductor during the second phase. In some embodiments, ΔT is selected to be approximately equal to the minimum achievable duration of the intermediate phase. In some embodiments, ΔT is selected using at least one of the following: a programmed set of values; and a lookup table (LUT). In some embodiments, adaptive feedforward is used to determine ΔT.

[0036] According to another aspect of this disclosure, a controller is provided for a power converter having a plurality of switches and at least one inductor, the controller comprising a circuit system configured to: control the power converter according to at least one operating mode having at least a first phase and a second phase, wherein in the first phase, the controller controls the plurality of switches to a first switching state, and wherein in the second phase, the controller controls the plurality of switches to a second switching state; in response to one or more conditions for switching from the first phase to the second phase not being met during a cycle of the at least one operating mode, to achieve three-phase operation by controlling the plurality of switches to a third switching state during the cycle to enter an intermediate phase between the first and second phases; and to selectively suppress three-phase operation for one or more other cycles of the at least one operating mode.

[0037] In some implementations, one or more conditions for switching from the first phase to the second phase include whether the current of at least one inductor is limited by a duty cycle D. UM The target current is reached before the duration defined by the cycle period T, wherein the circuit system is configured to dynamically adjust the limiting duty cycle D. UM To suppress three-phase operation against one or more other cycles. In some embodiments, the circuit system is configured to selectively suppress three-phase operation at least in part based on the use of a state machine. In some embodiments, the circuit system is configured to selectively suppress three-phase operation at least in part based on the use of a comparator. In some embodiments, the circuit system is configured to selectively suppress three-phase operation at least in part based on at least one of the following: the voltage conversion ratio of the power converter; the output voltage of the power converter; the current value of at least one inductor; and the power level of the power converter. In some embodiments, the circuit system is configured to selectively suppress three-phase operation at least in part based on at least one of the following: a reference value; a measured value; and a commanded value.

[0038] According to another aspect of this disclosure, a method is provided for controlling a power converter according to an operating mode having at least a first phase and a second phase, the method comprising: turning on one or more first switches of the power converter to realize a first phase of the operating mode; and realizing three-phase operation by turning on one or more second switches of the power converter to enter an intermediate phase between the first and second phases during the cycle in response to one or more conditions for switching from the first phase of the operating mode to the second phase of the operating mode not being met during a cycle of at least one operating mode; entering the second phase in response to one or more conditions for switching to the second phase being met; and taking one or more actions to compensate for excess volt-seconds applied to the inductors of the power converter during the cycle.

[0039] In some embodiments, one or more actions for compensating for excess volt-seconds include adjusting the duration of the phase following the intermediate phase. In some embodiments, adjusting the phase duration includes covering the start of the next cycle to maintain the switching state associated with the second phase for a duration ΔT. In some embodiments, one or more actions for compensating for excess volt-seconds include selectively suppressing three-phase operation. Attached Figure Description

[0040] The foregoing features can be more fully understood from the following description of the accompanying drawings, in which:

[0041] Figure 1 This is a block diagram of a radio frequency (RF) power amplifier (PA) system that utilizes multiple power supply levels;

[0042] Figure 2 This is a block diagram of an example RF amplifier system that includes a multi-output power generator, a single-inductor multi-output boost converter, a parallel power modulator, and an LC filter.

[0043] Figure 3 This is a partial schematic diagram of a multi-output power generator, which includes a magnetic regulation stage followed by a multi-output switched capacitor circuit.

[0044] Figure 3A This is a block diagram of an RF system that includes a multi-output power generator;

[0045] Figure 4 This is a schematic diagram illustrating a hybrid magnetic / switched capacitor multi-output power generator;

[0046] Figure 4A yes Figure 4 A schematic diagram of an example implementation of the circuit, wherein the magnetic adjustment stage references a specific voltage level of the multi-output magnetic stage;

[0047] Figure 5This is a schematic diagram of an example hybrid magnetic / switched capacitor multi-output power generator;

[0048] Figure 6 This is a schematic diagram of an example model for a power generator with a magnetic regulation stage having buck-boost capability;

[0049] Figure 7 and Figure 7A These are example waveforms for buck converters with current-mode control and extended buck + buck-boost modes;

[0050] Figure 8 and Figure 8A This is an example waveform for "boost start" operation with extended three-phase operation and peak current mode control;

[0051] Figure 9 and Figure 9A This is an example waveform for "boost start" operation with extended three-phase operation and valley current mode control;

[0052] Figure 10 This is a flowchart of an example process for controlling the magnetic conditioning stage of a multi-output power generator;

[0053] Figure 11 This is a graph showing the time versus current for peak current mode control in the extended buck + buck-boost mode;

[0054] Figure 12 This is a graph showing the time versus current for valley current mode control used in boost mode operation;

[0055] Figure 13 This is a block diagram illustrating an example implementation of a multi-mode controller, where an offset is added to the compensator output when switching from valley current mode control to peak current mode control;

[0056] Figure 14A It is a graph showing the operation of the system in three-phase mode without considering delay effects;

[0057] Figure 14B It is a graph showing the operation of a system in three-phase mode by compensating for the minimum three-phase duration by extending the cycle period during the three-phase cycle;

[0058] Figure 14C It is a graph showing the operation of a system in three-phase mode that compensates for the minimum three-phase duration by providing a compensating "coverage" duration in any cycle after entering the three-phase operation cycle;

[0059] Figure 15 This is a state transition diagram showing a state machine that can be used to control entry into three-phase operation; and

[0060] Figure 16 This is a schematic diagram illustrating a comparator-based implementation of three-phase conversion control. Detailed Implementation

[0061] Combination Figures 2 to 13 This document describes concepts, circuits, systems, and techniques useful in the design and control of power generators (including, but not limited to, multi-output power generators), which can be useful in a variety of applications, including but not limited to wireless and mobile applications. It should be noted that while specific examples are described herein, such examples are provided only to facilitate clarity of the broad concepts seeking protection and are not intended to be, nor should they be, limited. Rather, it should be understood that the concepts, techniques, systems, and circuits described herein can also be used and / or adapted and / or applied in many other power management applications.

[0062] Now refer to Figure 2 The radio frequency (RF) transmission system 10 includes a multi-output power generator (shown herein as a single-inductor multi-output boost converter), a parallel power modulator 15, and an optional filter 16 (shown herein as an LC filter). Generally, the multi-output power generator 12 has an input configured to be coupled to an energy source 11 (shown herein as a DC voltage source), and the multi-output power generator 12 generates multiple voltages at its output. The multi-output power modulator 15 switches between the multiple voltages generated by the multi-output power generator 12. The output of the parallel power modulator 15 is coupled to the power supply terminal 17a of the power amplifier 17. Therefore, the power modulator 15 provides a power supply voltage to the power amplifier power supply terminal 17a.

[0063] The multi-output power generator 12 includes Figure 2The diagram shows an inductor element as a single inductor L, which has a first (or input) terminal coupled to an energy source 11 and a second (or output) terminal coupled to a first terminal or node 13 of a switching network, which includes switches S1, S2, S3 providing multiple switchable signal paths. In this example, the switching network includes three signal paths (or "branches") 14a, 14b, 14c, each of which includes at least one switch. In this example embodiment, signal path 14a includes switch S1, signal path 14b includes switch S2, and signal path 14c includes switch S3. The first terminal of each switch is coupled to node 13. The multi-output power generator also includes a fourth switch S4, which has a first terminal coupled to node 13 and a second terminal coupled to ground. The multi-output power generator also includes a capacitor stack comprising multiple capacitors. In this example, the capacitor stack includes three (3) capacitors C1, C2, C3, wherein capacitor C1 has a first terminal coupled to the second terminal of switch S1. Capacitor C2 has a first terminal coupled to the second terminal of capacitor C1 and a second terminal coupled to the first terminal of capacitor C3. The second terminal of capacitor C3 is coupled to the second terminal switch S3.

[0064] Figure 1 and Figure 2 The RF system (which may be, for example, an RF power amplifier system) shown in the figure has two subsystems: (1) a “power generator” that can synthesize multiple power supply voltages from a single input source and can regulate one or more of these power supply voltages, and (2) one or more “power modulators” that can switch between the power supply voltages provided by the power generator at a rate that enables the modulated power supply voltage to be provided to the RF amplifier (which may be, for example, an RF power amplifier).

[0065] The specific implementation of the power generator 12 and the power modulator subsystem 20 can depend on a variety of factors, including but not limited to: the power level, voltage level, and application space of the RF amplifier system.

[0066] However, based on the concepts described herein, for many mobile applications, it may be desirable to monolithically integrate the electronics for both the power generator and the power modulator onto a single semiconductor die (e.g., in CMOS processes). Furthermore, in some cases, it may be desirable to integrate the electronics for the multi-output power generator, power modulator, and power amplifier onto a single die. In other cases, it may be desirable to implement the semiconductor elements for the multi-output power generator and (one or more) power modulators on separate semiconductor dies, allowing these elements to be placed in desired or specific locations within the system module. In still other cases (especially at high power), it may be desirable to implement the subsystem using discrete components connected to one or more printed circuit boards. It should be understood that a variety of different switching circuits can be used to implement the power modulator subsystem.

[0067] As will be described herein, multi-output power generators can be implemented using various methods. For example, a power generator can be implemented using multiple individual converters, multi-output magnetic converters, multi-output switched-capacitor converters, and hybrid magnetic / switched-capacitor converters that provide a ratiometric set of output voltages, as well as hybrid magnetic / switched-capacitor converters that provide other distributions of multiple output voltages.

[0068] As will also be described herein, many useful power generator designs can utilize a magnetic regulation stage that can provide one or more regulated output voltages from a variable input voltage (e.g., such as a battery). Additional output voltages can be synthesized, for example, through some additional power conversion circuitry such as switched capacitor circuitry, additional switch-mode magnetic power converters, or via linear regulators.

[0069] For example, Figure 3 A multi-output power generator 20 is shown, comprising a buck-boost magnetic regulation stage 22 (shown herein as a 4-switch buck-boost magnetic regulation stage), followed by a multi-output switched-capacitor circuit 24. Generally, the magnetic regulation stage 22 regulates one power generator output, which is also the input to the switched-capacitor circuit 24, which supplies the other outputs of the multi-output power generator. This design is suitable for use in RF amplifier systems such as… Figure 1 and Figure 2 Part of the system shown in the image.

[0070] Specifically, a voltage V is established at the output terminal 23 of the magnetic regulating stage 22. R And it is coupled to one of the outputs of the power generator via path 25, and also coupled to the input of the switched capacitor circuit 24. In this exemplary embodiment, a voltage V is established across the optional capacitor C1. RIt should be understood that capacitor C1 may be inside or outside the magnetic adjustment stage 22 (i.e., capacitor C1 may or may not be considered part of the magnetic adjustment stage 22).

[0071] The output terminal 23 of the magnetic adjustment stage is coupled back to the controller 21. Therefore, the controller 21 receives the feedback signal.

[0072] Although in this example embodiment, controller 21 is shown coupled to magnetic adjustment stage output 23, in other embodiments, controller 21 may detect one or more of the following: magnetic adjustment stage input signal; magnetic adjustment stage output signal; one or more reference signals; or one or more target signals. In other embodiments, the detected signals, or signals otherwise provided to controller 21, may be discrete-time signals (i.e., digital signals) or continuous-time signals (i.e., analog signals). In other embodiments, input / output signals may include one of the following: measured input / output voltage; or measured input / output current; or measured inductor current. In other embodiments, one or more reference signals may include one or more reference voltages or one or more reference currents. In other embodiments, one or more target signals may include one or more target voltages or one or more target currents. In other embodiments, the signal may be a voltage signal or a current signal, and may be a measured signal, an estimated signal, or a derived signal. An example of a derived signal is one with a compensation signal (e.g., which may then be with a current signal i). L Combining some calculated current signals) combined with actual (e.g., measured) current signals (e.g., i L Another example of a derived signal is an actual (e.g., measured) voltage signal combined with a compensation signal (e.g., some calculated voltage signal that can then be combined with a voltage signal).

[0073] The switched capacitor circuit 24 supplies at least some of the other outputs of the multi-output power generator 20. That is, the switched capacitor circuit 24 is configured to supply outputs V1 to V2 of the multi-output power generator. k At least some of the outputs are not supplied via the magnetic regulation stage 22. Output voltages V1 to V... k The output voltage provided by the switched capacitor circuit 24 can be proportionally related to a certain reference voltage. For example, the output voltage V1 to V... k The output voltage provided by the switched capacitor circuit 24 can be compared with the voltage V regulated by the magnetic regulating stage. R Proportional correlation. Therefore, the magnetic stage 22 can be controlled to (at one time) regulate the voltage at at least one output, while the operation of the switched capacitor stage 24 determines the other outputs V1 to V2.k (That is, output V1 to V) k The voltage at the output (which is not controlled by the magnetic pole 22).

[0074] In this implementation, output terminal 23 can be (directly or indirectly) coupled to one of the power generator output terminals 26a to 26K, thereby converting voltage V R Coupled to one of the output terminals of the power generator. For example, in one illustrative embodiment and as... Figure 3 As schematically shown, if node 23 (where a voltage V exists) R If coupled to the output terminal 25j of the power generator, the voltage level V j Corresponding to voltage level V R In one implementation, output terminal 23 may be left uncoupled to any of the power generator output terminals 26a to 26K.

[0075] In this implementation, output terminal 23 can be selectively coupled to one or more of the output terminals of the power generator, thereby converting voltage V... R Coupled to a selected output terminal among K power generator output terminals 26a to 26K, where K is an integer greater than two (2). In an embodiment, voltage V5 can be coupled to other output terminals among output terminals 26a to 26K. The following will combine... Figure 4 , Figure 4A and Figure 5 Descriptive and illustrative implementation methods.

[0076] It should be understood that for a given set of magnetic regulation stage circuit devices and elements with specified voltage and current ratings (or limits) (e.g., transistor q of magnetic regulation stage 22), A to q D The stress on these circuit devices and components (and inductor L) can be reduced by utilizing multiple voltages provided by the switched capacitor stage 24. That is, by utilizing multiple voltages provided by the switched capacitor stage 24, the voltage across the magnetic level circuit devices and the current through the inductor are less than the voltage and current that would appear across the magnetic level circuit devices and components without using multiple voltages. Since the voltage and current appearing across the magnetic level circuit devices and components are smaller when using multiple voltages, the magnetic level circuit devices and components are considered to have less stress (i.e., the stress on these circuit devices and components is less than the stress that would exist without using multiple voltages).

[0077] For example, transistor q B q C Coupled to node V2, the magnetic modulation stage transistor q is reduced. A to q DThe voltage stress occurs because the voltage across the transistor in the magnetic regulation stage is the difference between voltage V5 and voltage V2. This contrasts with the previously described method, which does not utilize multiple voltages and therefore uses the full voltage V5 across the magnetic regulation stage transistor. For the same reason, the current through the magnetic stage inductive element (e.g., inductor L) is also reduced using the multiple voltage method.

[0078] Alternatively, utilizing multiple voltages provided by the switched capacitor stage 24 allows for the selection of transistors and inductors with lower voltage and current ratings (i.e., inductors whose current rating or inductance value is lower than that required by inductors in systems that do not utilize multiple voltages). For example, a CMOS power FET may have an associated maximum drain-to-source voltage (in some MOSFETs, this may be a rated voltage such as 1.8V, 3.3V, or 5V), and exceeding this limit may damage the device. Furthermore, high gate-to-source voltages typically shorten (and in some cases significantly shorten) the lifetime of a MOSFET. Additionally, power MOSFETs may have a maximum specified drain-to-source voltage (when off), exceeding which may cause breakdown. Exceeding the breakdown voltage causes the device to turn on, which can potentially damage the device and other circuit elements due to excessive power dissipation. Therefore, it is advantageous to reduce stress on components.

[0079] Now refer to Figure 3A The accompanying figures are provided with the same reference numerals. Figure 3 Using the same components, the RF system includes a multi-output power generator 20, which has components configured to be coupled to an energy source (shown here as an input voltage V). IN (This can be the input terminal of a DC voltage source). Combined with the above... Figure 3 In the manner described, the multi-output power generator 20 generates multiple voltages at its output terminals 20a to 20K. In short, a magnetic conditioning stage 22 establishes a voltage that is supplied to at least one of the input terminals of the multi-output port switched capacitor circuit 24 and the output terminals 20a to 20K of the multi-output power generator. The multi-output port switched capacitor circuit 24 generates additional voltages available at the other output terminals 20a to 20K of the multi-output power generator. A switching multi-output power modulator 30 switches between the multiple voltages generated by the multi-output power generator 20. The output terminal of the power modulator 30 is coupled to the power supply terminal 34a of the power amplifier 34. Therefore, the power modulator 30 supplies a power supply voltage to the power supply terminal 34a of the power amplifier 34.

[0080] In this example embodiment, the controller 31 may receive one or more feedback signals from any one or all of the following: received from the magnetic adjustment stage output via signal path 32; received from one or more outputs of the multi-output switched capacitor circuit 24 via signal path 32a (for clarity, Figure 3A Only one path 32a) is shown; signals are received from one or more outputs of the power modulator circuit 30 via signal path 32b. The controller 31 may also receive one or more feedback signals from the RF output of the amplifier 34.

[0081] Therefore, as described above, controller 31 can detect one or more of the following: magnetic adjustment stage input signal; magnetic adjustment stage output signal; one or more reference signals; or one or more target signals. In embodiments, the detected or otherwise provided signals to controller 31 can be discrete-time signals (i.e., digital signals) or continuous-time signals (i.e., analog signals). In embodiments, input / output signals can include one of the following: measured input / output voltage; or measured input / output current or another current such as inductor current. In embodiments, one or more reference signals can include one or more reference voltages or one or more reference currents. In embodiments, one or more target signals can include one or more target voltages or one or more target currents. In embodiments, the signals can be voltage signals or current signals, and can be measured signals, estimated signals, or derived signals.

[0082] In response to one or more feedback signals received, detected, or otherwise provided to controller 31, controller 31 directs the switching element (shown here as a field-effect transistor (FET)) of magnetic adjustment stage 22. A q B q C q D Provide control signals. The following will combine... Figures 7 to 9A Describe various control schemes.

[0083] Now refer to Figure 4The multi-output power generator 40, having a hybrid magnetic / switched capacitor architecture, includes a magnetic conditioning stage 42 having a pair of outputs 43a, 43b coupled to corresponding inputs 44a, 44b of a multi-output switched capacitor stage 44. It should be understood that while in this exemplary embodiment, the pair of magnetic conditioning stage outputs 43a, 43b are coupled to corresponding inputs of the pair of multi-output switched capacitor inputs 44a, 44b, in other embodiments, a magnetic conditioning stage with more than two outputs (i.e., three or more outputs) coupled to a corresponding number of inputs of the switched capacitor stage may be provided.

[0084] However, in Figure 4 In the example implementation, the output terminals 43a and 43b of the two magnetic regulation stages are connected to the two ports 44a and 44b of the switched capacitor stage 44 to achieve buck-boost capability. Therefore, as described above, although... Figure 1 and Figure 2 Compared to the system, Figure 3 This implementation method results in reduced device and inductor stress, but compared to Figure 3 Compared to the implementation method, Figure 4 The proposed implementation results in reduced device and inductor stress. This reduced stress can significantly benefit power generator efficiency and the performance of multi-output power generators. For the reasons stated above, transistors with lower voltage ratings and lower losses can be used for the same application, thus improving efficiency compared to existing technologies. Furthermore, for the reasons stated above, smaller inductors (and smaller inductor values) can be used for the same application (due to the lower current ripple from utilizing the aforementioned multiple voltage methods), which also leads to lower losses. In addition, the proposed control method allows for more efficient energy transfer from the input to the output of the magnetic regulation stage, particularly for voltage conversion ratios approaching one (unity).

[0085] Figure 4A It shows that it can be used with Figure 4 A specific implementation (or method of implementation) of a multi-output power generator 50 with an architecture that is the same as or similar to that shown in the figure. Figure 4A In a particular embodiment, the multi-output power generator 50 generates six (6) discrete voltage levels V1 to V6 at the corresponding output terminals of the multi-output power generator output terminals 51a to 51f.

[0086] The multi-output power generator 50 includes a magnetic regulation stage 52 that provides a first voltage level and a second voltage level at output terminals 52a and 52b. In this exemplary embodiment, the multi-output magnetic stage provides voltage level 2 at output terminal 52b and voltage level 5 at output terminal 52a. It should be understood that while in this example the multi-output magnetic stage 52 provides voltage levels 2 and 5 at the respective output terminals 52a and 52b, in other examples the multi-output magnetic stage 52 may provide other levels. For example, the multi-output magnetic stage 52 may provide any one of voltage levels V1 to V6 at output terminal 52a and any different of V1 to V6 at output terminal 52b.

[0087] The output terminals 52a and 52b of the magnetic conditioning stage 52 are coupled to the input terminals of the multi-output switched capacitor stage 54, and the output terminals of the multi-output switched capacitor stage 54 correspond to the output terminals 51a to 51f of the multi-output power generator. Figure 4A In the example, the multi-output switched capacitor stage 54 includes a non-interleaved switched capacitor circuit, which includes: a first capacitor stack including capacitors C1 to C6, a second capacitor stack including capacitors C7 to C11, and switches S1A, S1B to S6A, S6B coupled to allow capacitors C7 to C11 to switch into and / or out of the first capacitor stack.

[0088] Such a circuit architecture can be relative to the input voltage V in Both buck and boost capabilities are achieved at voltage level V5, with output terminals V1 to V6 connected via relationship V k =(k / 5)·V5 is proportionally related to the voltage level V5. It should be noted that although... Figure 4A A non-interleaved switched capacitor circuit is shown, but an interleaved version can also be used. Therefore, a trade-off can be made between the number of components and improved capacitor size and / or ripple.

[0089] Now refer to Figure 5 The multi-output power generator 60 (or more simply, "multi-output power generator") includes a magnetic regulating stage 62, which includes a first switch q connected in series between the multi-output power generator input 60a and a first terminal of the inductor L. A One or more switches (two switches q are shown in this illustrative embodiment). B q C The first terminal of inductor L is coupled to the corresponding output terminal in the magnetic regulation stage output, typically denoted as 63. In this example, switch q BThe first terminal of inductor L is coupled to the output terminal 63j of the magnetic regulation stage, and switch q is... C The first terminal of inductor L is coupled to the output terminal 63i of the magnetic regulation stage.

[0090] One or more switches (two switches q are shown in this illustrative embodiment) D q E The second terminal of inductor L is coupled to the corresponding output terminal in the magnetic regulation stage output. In this example, switch q D Couple the second terminal of inductor L to the output terminal 63K of the magnetic regulation stage, and switch q E The second terminal of inductor L is coupled to the output terminal 63j of the magnetic regulation stage.

[0091] switch q E The second terminal of inductor L is coupled to a reference potential, which is shown here as ground.

[0092] Using this configuration, the magnetic adjustment stage 62 can switch each terminal of the inductor L to multiple ports (or input / output) of the switched capacitor stage 64. In some embodiments, it may be desirable or necessary for only one terminal of the inductor (i.e., the first or second terminal, but not both terminals) to be switchably coupled between multiple ports of the switched capacitor stage (e.g., via a switching element). Therefore, it should be understood that in some embodiments, it may be desirable or necessary for only one terminal of the inductor to be switchable between multiple ports of the switched capacitor stage, while in other embodiments, it may be desirable or necessary for both terminals of the inductor to be switchable (e.g., as...). Figure 5 (As shown).

[0093] exist Figure 5 In the example implementation, switch q A q B q C q D q E They are shown as individual transistors. Of course, it should be recognized that the individual switches can be implemented in any way that allows for proper voltage blocking and current carrying capacity. That is, any suitable switching element can be used.

[0094] For example, with combination Figure 3 or Figure 4 Compared to the example circuit described, Figure 5 This example implementation enables flexible energy transfer between the input and the switched capacitor stage. Compared to existing techniques such as... Figure 1 and Figure 2 Compared with the existing technical methods shown, Figure 5The example circuit design shown can provide reduced inductor stress / size, compared to existing technology methods such as Figure 1 and Figure 2 Compared with the existing technical methods shown, Figure 5 The example circuit design shown can provide a wider operating range (in terms of both power and voltage) compared to methods that offer lower switching flexibility, such as... Figure 1 and Figure 2 Compared with the existing technical methods shown, Figure 5 The example circuit design shown can provide improved efficiency and better control characteristics.

[0095] For power generators as described above, it is desirable to provide both highly efficient conversion over a wide range of input voltages, output voltages, and power levels, and flexible control over the power generator output. In many such applications, it is desirable to provide a sufficient operating range so that a given voltage level of the multi-output power generator can be controlled to be below, above, or equal to the input voltage, which may be derived from a battery.

[0096] For example, in a system with six ratiometric outputs powered by an input voltage supplied by a lithium-ion battery and charger, an input voltage range of 2.5V to 5.5V might be typical, and it might be desirable to control the highest output voltage v6 of the power generator anywhere between 3V and 5.4V (and, in the specific case of ratiometric outputs, v5 varies between 2.5V and 4.5V, v4 between 2.0V and 3.6V, v3 between 1.5V and 2.7V, v2 between 1.0V and 1.8V, and v1 between 0.5V and 0.9V). Therefore, if a magnetic regulation stage is configured to regulate v6, it needs to be regulated to a value higher, lower, or equal to the input voltage. Similarly, a magnetic regulation stage can be designed to regulate the voltage at v6 sometimes or under certain conditions, and at other conditions, regulate the voltage at v5, and in each of these cases, buck and / or boost capabilities may be required. The flexibility to achieve this depends heavily on the available magnetic regulation power stage, such as... Figure 3 , Figure 4 or Figure 5 The magnetically regulated power stage and how to control the power stage to achieve the desired output voltage distribution in the face of input voltage variations.

[0097] The concepts, systems, circuits, and techniques described herein are also applied to the design and control of multi-output power generators and their use in multilevel power supplies for RF power amplifier systems. These advancements are particularly valuable in situations requiring some form of buck-boost power conversion (e.g., synthesizing an output voltage that may be higher or lower than the available input voltage) and can also be applied to other applications in which buck-boost power conversion is employed.

[0098] Now refer to Figure 6 The model for a power generator with a magnetic regulation stage having buck-boost capability includes a magnetic regulation stage, which includes a switch q. A q B q C q D and an inductor L, which is coupled to a switched capacitor stage, the switched capacitor stage including inductors (shown here as ideal transformers T1 and T2) and a capacitor C. eff The effect of the switched capacitor stage on the magnetic regulation stage is modeled using a circuit containing an ideal transformer, where the turns on the transformer correspond to the coupling positions from the magnetic regulation stage switch to the switched capacitor stage.

[0099] Regarding the switching and control of the magnetic adjustment stage (e.g., via a controller, as mentioned above) Figure 3A The controller 31 described is considered Figure 3 , Figure 3A and Figure 4 The magnetic regulation stage of the power generator. As mentioned above, the effects of the switched capacitor stage and the load on the magnetic regulation stage can be described as follows: Figure 6 The ideal transformer structure and effective capacitance C are shown. eff and resistance R eff To model this, we choose the turns ratio a:b of an ideal transformer to model the voltage applied to the magnetic conditioning stage by the switched capacitor stage. For example, if the magnetic conditioning stage is connected to... Figure 4A The voltage levels 5 and 2 of the switched capacitor stage shown are then... Figure 6 In this case, a = 5 and b = 2. However, if the magnetic adjustment stage is as follows... Figure 3 The connection level j and ground shown are then... Figure 6 In this case, a = j and b = 0. This makes it easy to model the behavior of the magnetic adjustment stage.

[0100] Consider (for example, Figure 3 , Figure 3A , Figure 4 , Figure 4A and Figure 6The implementation method involves dividing the control of the magnetic regulating stage within a switching cycle into two phases (each phase has a pair of switches on), where the first phase (phase 1) has a duty cycle D and the second phase (phase 2) has a duty cycle 1-D. To achieve periodic steady-state operation, one phase should have zero or a positive voltage applied across the inductor (making di...). L / dt>=0), while the other phase should have zero or negative voltage applied across the inductor (making di L / dt<=0), where the steady-state voltage makes the average voltage across the inductor zero during the switching cycle. <di L / dt>=0, where the average value is taken within the switching cycle (<>). It should be noted that there are many ways to determine the duty cycle value (e.g., it can be achieved through voltage-mode control or current-mode control, with current-mode control including, for example, average, peak, and / or valley current-mode control). For Figure 3 , Figure 4 , Figure 6 The design is illustrated in Table 1, which shows typical switching possibilities.

[0101] Table 1

[0102] Mode number Mode use Phase 1: di / dt >= 0 Phase 2: di / dt <= 0 1 Get step-down q A , q D conducting q B , q D conducting 2 Get step-up q A , q C conducting q A , q D conducting 3 Get step-down-up q A , q C conducting q B , q D conducting 4 Bypass q A , q D conducting q A , q D conducting

[0103] Table 1 shows Figure 3 , Figure 3A , Figure 4 , Figure 4A and Figure 6 The magnetic regulating stage operates in a two-phase mode during continuous conduction. Values ​​are considered for periodic steady-state operation.

[0104] The different two-phase switching modes in Table 1 offer varying capabilities in terms of the periodic steady-state voltage conversion ratio of the magnetic regulation stage. Mode 1 (“buck”) achieves an ideal voltage equal to or less than the input voltage V. in (for example, in) Figure 6 C in eff The periodic steady-state output voltage at both ends. (In reality, due to the voltage drop across the switch and inductor resistor, the maximum voltage conversion ratio V is only slightly less than 1.) out / V inIt is achievable. Mode 2 (“Boost”) achieves an output voltage ideally equal to or greater than 1. Mode 3 (“Buck-Boost”) can obtain an output voltage higher or lower than the input voltage, but compared to Mode 1 or 2, this mode imposes a relatively high degree of stress and loss on the components for a given conversion ratio. Therefore, if using Mode 3, it may be less efficient than the other modes and requires larger components. Mode 4 (“Bypass”) connects the input to the output, ideally providing a conversion ratio of 1 or slightly less than 1 due to component voltage drops. It is worth noting that, in practice, it is not possible to regulate the output voltage to be lower, equal to, or higher than the input using only buck and boost operating modes due to duty cycle limitations and parasitic component voltage drops. Therefore, some more complex control is required to achieve this.

[0105] To enable the magnetic regulating stage output to be adjusted to be below, equal to, or above the input voltage, different possibilities emerge. The first possibility is to use buck mode operation for a desired output voltage that is a certain amount below the input voltage, buck-boost mode operation for an output voltage within a certain range close to the input voltage, and boost mode operation for a desired output voltage that is a certain amount above the input voltage. Optionally, hysteresis can be incorporated during switching between operating modes to reduce mode jitter near the boundaries. A limitation of this method is its use of buck-boost operation, which is both highly inefficient and requires large component sizes (e.g., large physical inductors) due to the significant indirect energy transfer involved.

[0106] The second possibility is to operate in buck mode for desired output voltages below the input voltage by a certain amount, and in boost mode for desired output voltages above the input voltage by a certain amount, then switch to bypass mode when the desired output approaches the available input voltage. Similarly, mode jitter near the boundary can be reduced by incorporating hysteresis during switching between operating modes. The main advantage of this possibility is that bypass mode is quite efficient (because it does not introduce switching or gating losses) and has low electromagnetic interference generation (due to the absence of switching), thus providing some desired system characteristics when it is active. However, the main disadvantage of this operating mode is that the output voltage cannot be precisely controlled during bypass operation, which is generally undesirable from a system perspective.

[0107] When a magnetic regulation stage is provided that can switch at least one terminal of an inductor to multiple ports of a switched capacitor stage, a third possibility arises (e.g., as...). Figure 5(As shown). In this case, the switching between which terminals of the switched capacitor stage is performed in two-phase operation can be adjusted according to the required output voltage. The advantage of this technique is that the magnetic regulation stage can remain in a highly efficient and regulated mode (e.g., buck and / or boost modes) as long as the connections used achieve the desired operating range. The disadvantage of this technique is that "multi-connection" capability may be preferred to achieve other objectives (e.g., minimizing inductor size / stress, extending operating range, etc.).

[0108] A fourth possibility is to extend the operation of the magnetic regulation stage from a two-phase operating mode to an N-phase operating mode for at least some desired voltage conversion ratios. For example, in an implementation, three or more sets of switching states can be utilized within the switching cycle of the magnetic regulation stage (i.e., N sets of switching states can be utilized within the switching cycle of the magnetic regulation stage, where N is an integer greater than or equal to 3). Such an operating mode (e.g., using three or more sets of switching states) can be referred to as “N-phase” control. When using three sets of switching states, such an operating mode can be referred to as “three-phase” control. N-phase and three-phase control can be implemented in various ways, and several examples are described below.

[0109] The advantage of this method (i.e., the N-phase control method) is that, compared to the first, second, and third possibilities described above, it can provide more efficient voltage conversion for conversion ratios <1, =1, and >1, while retaining a wide operating range and low component stress. It is particularly desirable to implement this fourth possibility efficiently and compactly with a relatively simple control circuit system that retains other desired capabilities (e.g., current-mode control, high regulation bandwidth, simple compensation with smooth mode transitions, etc.). Achieving a smooth transition between conventional two-phase control and N-phase operating modes (e.g., three-phase operating modes) is also valuable.

[0110] It should be understood that although the N-phase operating mode concept disclosed herein is sometimes described in the context of a three-phase operating mode, such reference is only for the purpose of facilitating clarity in the description of the broad concept for which protection is sought, and is not intended to be, and should not be construed as, restrictive. Therefore, after reading the description provided herein, it will now be apparent to those skilled in the art that the concepts and techniques described herein can be extended to each cycle of N phases by selecting groups of conducting switches to achieve N different switching states.

[0111] In implementations, a group of switches may include one or more switches, and preferably two or more switches. Although some examples provided herein include switch groups containing two or more switches, those skilled in the art will understand how many switches are included in a group of switches after reading the examples and descriptions provided herein. Typically, a switch group may include M switches, where M is an integer greater than 2.

[0112] Current-mode control with mode switching can be implemented in the context of these multiple operating modes. Peak current control can be selected if the first phase is di / dt > 0, and valley current mode control can be selected if the first phase is di / dt < 0. At the beginning of each cycle, the desired operating mode can be selected (e.g., based on the actual input / output voltage, reference, or target voltage, etc.), such as one of the modes listed in Table 1. The desired first-phase switch pair is then turned on (which switches are selected depends on the desired two-phase mode, e.g., as shown in Table 1) and the inductor current is observed. For peak current control, the second phase is entered when the inductor current reaches the target current (defined as the target peak current or the peak current minus the compensation ramp value), until the end of the cycle. (Conversely, for valley control, the inductor current reaches the target current, defined as the target valley current or the valley current plus the compensation ramp value.) An outer loop can be used to regulate the output voltage. It is worth noting that peak current mode control can be selected for one mode (e.g., buck mode) and valley current mode control for another mode (e.g., boost mode) to provide smaller transients in the compensator when moving from one mode to another.

[0113] Selecting a mode at the start of each switching cycle is a natural choice. However, other possibilities exist. A mode can be selected and maintained for a specified duration (e.g., a set number of cycles), or the mode can be changed on a basis that does not correspond to a set number of cycles. Hysteresis (e.g., hysteresis of voltage, conversion ratio, etc.) can also be included in the mode selection decision (e.g., as one of several factors to consider), and / or once a mode is selected, a minimum or maximum duration for residing in that mode can be set.

[0114] In some cases, extended three-phase control techniques for the magnetic stage are described, which naturally extend to three-phase operation when required, while providing efficient operation and simple controller implementation. This enables efficient operation of the magnetic regulating stage across a wide range of voltage conversion ratios. It can be used with voltage-mode control, current-mode control, or other methods.

[0115] First, it explains how the buck operation mode with peak current mode control can be naturally extended to a three-phase "buck + buck-boost" mode, thus providing it with the ability to achieve a voltage conversion ratio greater than 1. When paired with boost mode, this achieves seamless coverage of voltage conversion ratios from less than 1 to greater than 1 without requiring pure buck-boost mode operation. Then, it provides an explanation of how to similarly implement different three-phase operation modes, allowing designers to choose from two-phase and extended three-phase modes to achieve specific objectives.

[0116] For systems using three-phase buck + buck-boost operation, in some cases, a design with both boost and buck modes can be used, where the buck mode can be automatically extended to a "buck + buck-boost" three-phase mode via current-mode control. At the beginning of each switching cycle, an initial decision regarding which mode to start in (e.g., buck or boost) can be made using the input and output voltages (or reference voltage). If boost mode is selected at the beginning of the cycle, operation can be performed as with conventional boost mode control (e.g., using voltage-mode control, peak current control, valley current control, etc.).

[0117] If you select the buck mode (extended buck + buck-boost available) at the beginning of the loop, the loop operation is as follows: Figure 7 and Figure 7A As shown (with as) Figure 3 , Figure 3A , Figure 4 , Figure 4A and Figure 6 (Switch markings shown). Consider the case of peak current mode control (with extended three-phase operation).

[0118] Figure 7 and Figure 7A This is an example waveform for buck converters with current-mode control, as well as extended buck + buck-boost modes. At the beginning of the cycle, the switch used to initiate the buck operation cycle is turned on. If the desired conditions are not met within a specified time or duty cycle (e.g., for peak current control), the system can automatically switch to a "three-phase" buck + buck-boost mode and change the switch configuration to provide boost capability. When the desired conditions are met, the system enters the final switching state of the cycle.

[0119] At the beginning of the cycle (for "buck start"), the following procedure can be followed. At the beginning of the cycle for phase 1, turn on the appropriate switch (e.g., q). A q D And observe the inductor current i. L 79. And compare it with the target current. Figure 7 and Figure 7A In this case, the target current refers to the peak current ip 76 minus the slope M c The compensation slope is shown in line 78. Figure 7 As shown, if the inductor current i L 79. When the specified conduction duration D is reached UM If the target current of 78 is reached before T, then phase 2 is entered, and the appropriate phase 2 switch is turned on for the remainder of the cycle (e.g., q). B q D ).like Figure 7A As shown, if in i L 79. The duration of phase 1 (in terms of time or phase 1 duty cycle) before reaching the target current 78 exceeds the specified on-time D. UM If T is selected, Phase 1 ends and automatically enters the buck + buck-boost mode ("Phase 1A"). The switch configuration is changed to boost mode (e.g., q). A q C And the inductor current i L 79 continues to be observed and compared with the target current 78. If the inductor current i L If the target current 78 is reached before the end of the cycle, then phase 2 is entered, and the appropriate phase 2 switch (e.g., q) is turned on for the remainder of the cycle. B q D In other implementations, the conduction duration can be expressed as D. ON T or D MAX T.

[0120] Compared to the buck-only operation mode, the extended three-phase operation (buck + buck-boost) described above enables a wider range of voltage conversion ratios. For example, considering... Figure 4A The topology, in pure buck mode, can achieve an achievable voltage level of 5 (V5), up to:

[0121]

[0122] (It is less than or equal to V) IN However, with the inclusion of extended buck + buck-boost operations, voltages can be achieved as high as:

[0123]

[0124] It is greater than V IN For example, by selecting D UM With a value of 0.9, it is ideal to maintain operation in pure buck mode to achieve up to 0.9375V. IN The voltage is V5, but by extending to buck + buck-boost mode, it can reach up to 1.064V. INThe voltage. By selecting an appropriate D UM The desired full-range voltage conversion ratio (e.g., <, =, > 1) can be achieved using only boost mode and buck / buck+buck-boost operation modes. Similar voltage operating ranges can be easily developed for related topologies and three-mode operation.

[0125] The advantage of this extended "buck + buck-boost" operating mode implementation is that the compensation ramp slope M used for slope compensation in the basic buck operating mode under peak current control is... c This will also generate stable ripple dynamics for the extended "buck + buck-boost" operating mode.

[0126] In the extended three-phase control principle, a method can be described for seamlessly extending a basic two-phase operating mode to three-phase operation. At the beginning of the cycle of phase 1 in the basic two-phase operating mode, an appropriate switch is turned on. If the specified on-time within the cycle is reached (e.g., D...),... max If the condition for entering phase 2 is met before T), then phase 2 is entered, and the appropriate phase 2 switch is turned on for the remainder of the cycle. In this case, the basic 2-phase operation mode is maintained. If the specified on-time within the cycle (e.g., D) is reached... max If the conditions for entering the basic operating mode have not been met before (T), then when the specified conduction duration (D) is reached... max When T), the system enters the extended operating mode. At this time, the switch state becomes the "three-phase" state (represented as phase 1A). If the condition for entering the basic operating mode (phase 2) is met after entering the extended operating mode but before the end of the cycle, the last phase of the three-state operation is activated, and the appropriate switch is turned on for the remainder of the cycle. In many cases, the last phase will be the same as phase 2 in the basic two-phase operating mode, but this is not the case in all systems.

[0127] It should be noted that for this extended three-phase operation, in addition to considering the basic conditions for switching between two phases as in two-phase operation (e.g., the duty cycle achieved in phase 1 for voltage-mode control, or the current crossover achieved in phase 1 for current-mode control), a second condition (e.g., the specified maximum duration D in phase 1) is also examined. maxThe second condition can be evaluated / checked using timers, ramps, and voltage comparisons, or via other means. Comparisons can be made during the first part / phase of the cycle, the second part / phase of the cycle, or both. Implicit comparisons rather than duration-specific comparisons can also be performed, such as comparisons of voltage or current ripple or distribution using waveforms of converters and / or other synthesized signals. In all these cases, the proposed method provides an extension from a simple implementation of two-phase to three-phase operating modes and can offer an extended range of achievable voltage conversions.

[0128] The proposed method allows the converter to use one or more two-phase operating modes, as well as one or more modes for extended three-phase operation, wherein the initial operating mode is selected at the beginning of each cycle (or on some other basis) according to the operating conditions. This provides a highly flexible way to implement various operating modes to seamlessly cover a wide range of voltage ranges or operating conditions.

[0129] In other cases, other modes with extended three-phase operation can be described. Figure 8 and Figure 8A This is an example waveform of "boost start" operation with extended three-phase control under peak current mode control. This mode is applicable to, for example, at least... Figure 3 , Figure 3A , Figure 4 , Figure 4A and Figure 6 The design involves entering phase 1 at the beginning of the loop and switching q. A and q C On. This state continues until the inductor current i L 84 rises to the target current indicated by line 82, at which point phase 2 is entered and switch q is activated. A and q D Turn on. Depending on the output voltage value, the slope of the inductor current in phase 2 can be negative (e.g., for pure boost mode) or positive (in which case, boost + buck - boost mode is required). For example... Figure 8A As shown, if time D is reached in the loop M At time T, i L If 84 does not drop below the target current, then enter phase 2B and switch q. B and q D It conducts for the duration of the cycle. In this case, the availability of extended three-phase operation is achieved below V. INThe steady-state output voltage is impossible in pure 2-phase boost mode. Therefore, the full voltage range (conversion ratio <, =, > 1) can be covered using only buck mode and boost + buck - boost operation modes. The advantage of this implementation is that it allows peak current control decisions to be made solely by sensing the current of switch A (e.g., using a sensing FET). The disadvantage of this implementation is that both pairs of switches need to be switched at the end of the loop in extended operation, thus increasing the overall switching losses from other possibilities.

[0130] Figure 9 and Figure 9A This is an example waveform of "boost start" operation with extended three-phase operation under valley current mode control. This mode is also applicable to, for example, at least... Figure 3 , Figure 3A , Figure 4 , Figure 4A and Figure 6 The design involves entering phase 1 at the beginning of the loop and switching q. A and q D Conduction. (As shown) Figure 9 As shown, if at arrival time D ON Before T, the inductor current i L If the current drops to the target current shown by line 92, then phase 2 is entered at the intersection, and switch q... A and q D It conducts for the remainder of the switching cycle. (This is basic 2-phase operation.) For example... Figure 9A As shown, if in i L 90% of the time D is reached before the target current drops. ON If T is selected, then extended three-phase operation is initiated at that point, and switch q is activated. B and q D On (represented as phase 1A). This continues until the end of the loop, or until i... L The current drops to the target current at 90°, at which point it enters phase 2 until the cycle ends.

[0131] Figure 10 It is shown that, for example, it can be done in Figure 3 Within systems and especially in systems such as combination Figure 3 A flowchart illustrating the processing implemented within the controller 21. Rectangular elements (by...) Figure 10 Element 70 in this document is represented as a "processing box" and represents a computer software instruction or instruction set. The diamond element (represented by...) Figure 10Element 74 in the flowchart is referred to herein as a "decision box" and represents a computer software instruction or group of instructions that affects the execution of the computer software instructions represented by the processing block. Alternatively, processing boxes and decision boxes may represent steps performed by functionally equivalent circuits such as digital signal processor circuits or application-specific integrated circuits (ASICs). The flowchart does not depict the syntax of any particular programming language. Rather, the flowchart illustrates the functional information required by those skilled in the art to manufacture circuits or generate computer software to perform specific functions. It should be noted that many routine elements such as loops and variable initialization, as well as the use of temporary variables, are not shown. Those skilled in the art will understand that, unless otherwise stated, the specific sequence of boxes described is illustrative only and can be varied without departing from the spirit of the described concept, structure, and technique. Therefore, unless otherwise stated, the boxes described below are unordered, meaning that the functions represented by the boxes can be performed in any convenient or desired order where possible.

[0132] Now go to Figure 10 The processing begins with the detected signal. This should be combined with at least the above. Figure 3 and Figure 3A As described, the signal can be any form of current or voltage signal (e.g., digital / analog signal, measurement / estimation / derived signal, input / output / reference / target signal). Processing proceeds to processing block 102, where, in response to the detected signal (e.g., to a controller such as those described above), Figure 3 , Figure 3A The feedback signals of the controllers 21 and 31 described herein, and the switches (e.g., switch groups) are set to their on states to establish the desired operating mode for the magnetic adjustment stage. For example, the controllers may provide signals that bias the switches or transistor groups to their on states (i.e., their on states) while biasing other switches or other transistor groups to their off states (i.e., their off states) for the start of a cycle for phase 1.

[0133] Then, the process proceeds to decision block 104, where a determination is made as to whether one or more conditions are met when the magnetic adjustment stage is operating in its phase 1 mode. If a determination is made that one or more conditions are not met, the process proceeds to processing block 106, where an intermediate N-phase mode is selected. The intermediate N-phase mode is an operating mode of the magnetic adjustment stage that is neither the phase 1 mode nor the phase 2 mode of the magnetic adjustment stage during the magnetic adjustment stage switching cycle. Then, the process proceeds to processing block 108, where the selected N-phase mode is entered (i.e., by switching the selected transistor group in the magnetic adjustment stage), causing the magnetic adjustment stage to operate in N-phase mode (i.e., the operating mode of the magnetic adjustment stage changes from the phase 1 operating mode to the N-phase operating mode).

[0134] Then, the process returns to decision block 104, where a determination is made regarding whether one or more conditions are met when the magnetic adjustment stage is operating in N-phase operation mode. If a determination is made that one or more conditions are not met, the process returns again to processing block 106, where an intermediate N-phase operation mode is selected. The selected N-phase operation mode may or may not be the same as the previously selected N-phase operation mode. In other words, one or more intermediate phase operation modes (i.e., N-phase operation modes, where N is an integer greater than 1) may exist between the first and second phase operation modes of the magnetic adjustment stage. Therefore, decision block 104 and processing blocks 106 and 108 form a loop in which one or more N-phase operation modes of the magnetic adjustment stage are entered until a determination is made in decision block 104 that the conditions for entering phase 2 of the magnetic adjustment stage switching cycle are met. Once a determination is made in decision block 104 that the conditions for entering the magnetic adjustment stage switching cycle for phase 2 are met, the process proceeds to processing block 110, where the final switching state in the magnetic adjustment stage for phase 2 operation is entered.

[0135] As mentioned above, the concepts described herein are particularly effective when using a combination of peak current mode control and valley current mode control. Specifically, buck and extended buck+buck-boost modes can utilize peak current mode control, while boost mode can effectively utilize valley current mode control (CMC). The switching waveforms of these two modes are shown in... Figure 11 and Figure 12 As shown in the image.

[0136] Now refer to Figure 11 and Figure 12 The time versus current graph illustrates peak current mode control in the extended buck + buck-boost modes. Figure 11), and the time versus current graph shows the valley current mode control used for boost mode operation ( ), Figure 12 ).

[0137] It will be understood that, in buck / buck+buck-boost mode, the output of the (single) compensator can be alternatively... cmd Used directly as i p Furthermore, in boost mode, a negative offset -Δi is added. comp To generate i v Alternatively, a first offset can be added in boost mode and a second offset in buck + buck-boost mode, as long as the difference between the two offsets is the desired value Δi. comp .

[0138] In peak current mode control, the compensator commands the peak current i p In valley mode control, the compensator commands the valley current i v Then, during the transition between the extended buck + buck-boost and boost modes, the meaning of the compensator output value changes, as does the expected value provided by the compensator to achieve periodic steady-state operation. If the value provided by the compensator to the current controller remains unchanged when the mode changes between the extended buck + buck-boost and boost modes, transients will exist during converter reset and compensator output value adjustment. To achieve a “disturbance-free” (or nearly disturbance-free) transition between modes using a single compensator, an offset can be introduced in the value provided by the compensator to the inner loop in one of the two modes. For general cases, the command i in the extended buck + buck-boost mode can be found. p i in boost mode v The exact compensator variation between the two is obtained, but the resulting expression and its implementation are somewhat complex. However, a simplified compensator offset variation can be used to achieve fast, disturbance-free system performance.

[0139] Considering that mode switching occurs when the voltage conversion ratio is very close to 1 (e.g., V5 = V), IN When ), a simplified expression can be found. (Constrain V) M =V5=V IN The offset (in terms of current command) required for compensation between peak current mode command and valley current mode command is:

[0140]

[0141] A further, even simpler, approximation can be provided, which is not a function of the input / output voltage:

[0142] Δi comp =i p -i v≈[M co +M cu ]·T

[0143] In other words, if an offset equal to the sum of the compensation slope magnitudes is added (or the same compensation slope magnitude M is used in each mode), c The typical value is 2·M c If this is the case, then a transfer with almost no disturbance can be expected. This applies to V5 = V IN The approximation is reasonable because the ripple current becomes zero in boost mode, and the valley mode duty cycle (the valley mode duty cycle in the first time period, where the inductor current decreases) becomes 1. Therefore, we can expect to be able to use a single compensator and simply use the compensator output directly as i in boost mode. v And when in buck mode / extended buck + buck-boost mode, add a positive offset Δi comp This implementation method is in Figure 13 As shown in the image.

[0144] Now refer to Figure 13 This illustrates an example implementation of a multi-mode controller, where an offset is added to the compensator output when switching from valley current mode control to peak current mode control. The multi-mode controller includes a differential (or subtractor) circuit that receives a reference voltage V at its first input. REF A sampling voltage V5 is provided at its second input terminal, and an error voltage V is provided at its output terminal. ERR Error voltage V ERR Corresponding to the reference voltage V REF The difference between the sampled voltage V5 and the voltage V5 (in Figure 13 In the example circuit, V ERR =V REF –V5).

[0145] Error signal V ERR This is provided to the input terminal of the compensator circuit (shown here as the core of the compensator). The compensator generates a command signal (shown here as the command current signal i). cmd The command signal is then provided to the adder (or summer) circuit, which receives the command signal at its first input and an offset signal (shown here as the offset current signal i) at its second input. offset In peak current mode control, the compensator commands the peak current i at its output. p In valley mode control, the compensator commands the valley current i at its output. vThen, as the compensator shifts between extended buck + buck-boost and boost modes, the meaning of the compensator output value changes, as does the expected value that the compensator provides to achieve periodic steady-state operation.

[0146] Peak / valley current signal i v / i p The signal is supplied to the input of the peak / valley current mode control (CMC) power stage. The controlled power stage provides an output signal (shown here as the output voltage signal V5) at its output. As described above, the output signal value is detected and provided to the input of the differential circuit (e.g., as a feedback signal).

[0147] It will be understood that, in buck / buck+buck-boost mode, the output of the (single) compensator can be alternatively... cmd Used directly as i p Furthermore, in boost mode, a negative offset -Δi is added. comp To generate i v Alternatively, a first offset can be added in boost mode and a second offset in buck + buck-boost mode, as long as the difference between the two offsets is the desired value Δi. comp .

[0148] Go to Figures 14A to 14C For near-limit duty cycle D ON The duty cycle D, due to non-ideality, can sometimes cause "mode chatter," where the duty cycle is less than D. ON D leads to two-phase operation and is greater than D. ON The duty cycle D results in three-phase operation. For example, when the duty cycle D (e.g., the desired steady-state duty cycle) is slightly higher or lower than D... ON At the same time, some cycles will result in three-phase operation, while others will result in two-phase operation. Mode jitter can be observed as small-signal chaos or subharmonic oscillations in the output voltage switching ripple. Increased AC ripple and low-frequency ripple (i.e., a fraction of the switching frequency) are detrimental to regulation and efficiency performance.

[0149] In some cases, such mode jitter with three-phase control can be attributed to comparator delay, gate drive delay, or factors affecting the three-phase region (e.g., Figures 14A to 14C The other propagation delay is the minimum realizable duration of "phase 1A" in the diagram. In other words, there exists a minimum time for the converter to switch from phase 1A to phase 2, referred to in this paper as the minimum realizable three-phase region duration or T. min,1A Typically, it is expected in D ON The duration of the three-phase region starting at point T is related to the inductor current i. LThe cycle ends when it intersects with the target current, thus applying the desired amount of volt-seconds to the inductor. Such a scenario results in zero net volt-seconds applied to the inductor within a single cycle, such as... Figure 14A As shown (i.e., i) L (The cycle begins and ends with the same current). Figure 14B The minimum achievable three-phase region duration T shown min,1A Applying a minimum amount of volt-seconds to an inductor may result in an excess volt-second, which could be greater or less than the desired value. The term "excess volt-second" is used herein to refer to a volt-second error independent of polarity (i.e., a positive or negative volt-second error). In one cycle, too many or too few volt-seconds may be applied to the minimum duration three-phase region, such that the condition D>D may not be satisfied in subsequent cycles. ON This results in two-phase operation. Therefore, the converter may jitter between two-phase and three-phase operation in an attempt to achieve long-term volt-second balance.

[0150] Those skilled in the art will understand that other non-idealities in the controller implementation (besides the minimum achievable three-phase region duration) can lead to excessive volt-seconds, and thus mode jitter. Various techniques for compensating for excessive volt-seconds and thus reducing (and ideally eliminating) mode jitter are discussed below.

[0151] One approach to address the minimum achievable three-phase region duration limitation (and other non-idealities in circuit implementation) is to compensate for excess volt-seconds applied during three-phase operation with volt-seconds of opposite polarity during another operating phase. For example, excess volt-seconds applied during phase 1A (e.g., the minimum achievable three-phase region duration limitation) can be compensated for by extending phase 2 by some duration to partially or completely eliminate the excess volt-seconds.

[0152] Another method is to adjust the duty cycle limit D. ON This is to prevent the controller from entering three-phase operation when mode jitter may occur. For example, D can be reduced. ON To ensure that the desired three-phase duration is always greater than or equal to the minimum three-phase duration (i.e., to ensure that the inductor current i... L It will not be less than T min,1A (intersecting with / reaching the target current within the time limit).

[0153] According to another approach, three-phase operation can be dynamically disabled (or suppressed) when conditions indicate that mode jitter will occur, for example, when the desired three-phase region duration will be less than the minimum permissible three-phase duration. More generally, the controller can prevent the power converter from using three-phase operation at operating points where mode jitter may occur.

[0154] Figure 14AA power converter operating in periodic steady state is depicted, and for this power converter, the minimum three-phase duration is not an issue. Figure 1400 shows the peak current i. p 1402, Target Current; 1404, Inductor Current i L 1406, and phases 1, 1A, and 2. In the cycle of duration T shown, phase 1 begins and the inductor voltage is V. L1 When the inductor current i L Before 1406 intersects with the target current 1404, phase 1A is in D. ON Starting at point T. During phase 1A, the inductor voltage is V. L1A When the inductor current i L Phase 2 begins when current 1406 intersects with the target current 1404. During phase 2, the inductor voltage is V. L2 For the inductance L of an inductor, use the relationship V L / L=di / dt, the inductor current i during phase 1, phase 1A and phase 2. L The slopes of 1406 are V L1 / L、V L1A / L and V L2 / L. Phase 2 ends at T, ideally with zero net volt-seconds applied during the cycle. Figure 14A In the example, the duty cycle D is greater than D0. ON Therefore, it indicates three-phase operation.

[0155] As operating conditions change, D can be higher or lower than D. ON The value varies within a range. Consider that D is only slightly greater than D0. ON In this scenario, the inductor current i L 1406 can intersect with the target current 1404 almost immediately upon entering the three-phase region (i.e., phase 1A). In this case, the desired duration of the three-phase region can be very short.

[0156] Now refer to Figure 14B The same reference numerals are used to illustrate the figures shown. Figure 14A Using the same components, Figure 1420 illustrates the behavior of a power converter with a non-ideal minimum achievable three-phase region duration. Under the depicted operating conditions, D is only slightly larger than D0. ON Thus, the inductor current 1406 intersects the target current 1404 almost immediately after entering the three-phase region (i.e., phase 1A). However, the minimum achievable three-phase duration T... min,1A Extending the three-phase duration adds excessive volt-seconds to the inductor. Due to the minimum achievable three-phase duration, the minimum volt-seconds applied to the inductor during that phase is Δλ. 1A =VL1A T min,1A In this example, the loop ends at time T with an excessive number of volts and seconds.

[0157] Figure 14B A technique for compensating for excess volt-seconds caused by, for example, the minimum achievable three-phase region duration is also shown. Here, the phase 2 region can be extended by ΔT beyond T, increasing the negative volt-seconds and compensating for the excess volt-seconds of phase 1A. More specifically, the switching cycle period can be extended by ΔT, such that the cycle period is T. ext = T + ΔT. When the desired three-phase duration is less than the minimum achievable three-phase region duration, the value of ΔT can be determined or selected to reduce (and ideally eliminate) excess net volt-seconds on the inductor within a cycle. In this way, mode jitter can be reduced and ideally eliminated. Various techniques for selecting ΔT are described below.

[0158] Figure 14C This demonstrates another technique for providing excess volt-second compensation. Instead of extending the three-phase cycle time beyond T (e.g., Figure 14B As shown), volt-second compensation can be performed in subsequent loops. Figure 14C Two switching cycles are partially illustrated, with the first cycle ending at time T and the second (subsequent) cycle beginning at time T. In this example, the first cycle ends with excess volt-seconds because the minimum achievable three-phase region duration exceeds the desired three-phase duration operation. This excess is compensated by extending phase 2 of the first cycle by a duration ΔT into the second cycle. More specifically, at the beginning of the second cycle, the controller overrides its normal control to continue operation in phase 2. After a duration ΔT, the controller resumes normal control, causing phase 1 of the second cycle to begin, as shown. In this way, mode jitter can be reduced / eliminated without changing the switching cycle duration T.

[0159] Figure 14B and Figure 14C A technique for compensating for excess volt-seconds is illustrated, which involves adjusting the duration of a phase after the minimum duration three-phase region. However, the general concepts, structures, and techniques sought to be protected herein are not limited to this method. Typically, any phase (before or after the accumulated excess volt-seconds) can be adjusted to compensate for the excess volt-seconds.

[0160] In some cases, it can be applied during each three-phase cycle. Figure 14B and / or Figure 14C One or more of the compensation techniques.

[0161] exist Figure 14B and Figure 14CIn this implementation, an extended duration ΔT is used to mitigate excess volt-seconds caused by non-ideal power converter control methods. In some implementations, the extended duration ΔT can be precisely determined based on a reference voltage (e.g., a programmed, commanded, or otherwise known), an actual measured voltage, or a combination thereof. For example, ΔT can be selected (e.g., ideally selected) to take the following values:

[0162] ΔT=|V L1A / V L2 |T min，1A

[0163] This is to reduce (and ideally eliminate) excess net volt-seconds on the inductor within the cycle when the desired three-phase duration is less than the minimum achievable three-phase region duration. In the case of a buck-boost converter, this can be achieved by using V... LA1 =V IN and V L2 =V O,REF To complete, where V IN It can be the input voltage (the measured voltage), and V O,REF It can be the desired output voltage (reference voltage).

[0164] In other implementations, the extended duration ΔT can be selected approximatingly based on a lookup table (LUT) or using pre-programmed values. In one example, the input-output voltage ratio can be provided to the LUT, which outputs ΔT (e.g., optimal ΔT). In another example, in a design such as a three-phase four-switch buck-boost converter, where V... in ≈V out The duration ΔT can be extended by setting ΔT = t min,1A As an approximation, ΔT is used to provide improved minimum mode jitter. As another example, ΔT can be selected from a programmed set of values, which may or may not depend on the system operating point. In other implementations, ΔT can be adaptively selected, for example, using adaptive feedforward.

[0165] Although Figures 14A to 14C An example of peak current control is shown, but the general concepts, structures, and techniques described with it can be applied to other types of control, such as valley current control and average current control.

[0166] Go to Figure 15Another way to reduce (and ideally eliminate) mode jitter is to dynamically enable / disable three-phase operation at the operating points where jitter may occur. The decision to enter three-phase operation should only be made if, at a given operating point in periodic steady-state operation, the desired volt-seconds for the three-phase region exceed the volt-seconds imposed by the minimum achievable three-phase region duration. In some examples, the decision to dynamically enable / disable three-phase operation can be made at the beginning of the switching cycle (i.e., t = 0). In other examples, it can be made before the three-phase region can begin (i.e., t = 0). <D UM T) makes this decision at any point in the loop. This method of selectively enabling / disabling three-phase operation is referred to in this paper as "three-phase conversion control".

[0167] For example, three-phase switching control can be implemented by dynamically enabling / disabling three-phase operation based on one or more of the actual or reference values ​​of voltage conversion ratio, output voltage, inductor or output current value, or power level. In some examples, the conditions used to select enabling / disabling three-phase operation can be subject to hysteresis, so that stable operation can be achieved with a given mode for small changes in operating conditions.

[0168] Figure 15 An example of a state machine 1500 that can be used to implement three-phase transition control according to some embodiments is shown. Utilizing Figure 15 The method shown is based on the expected voltage conversion ratio (e.g., V). o,ref / V in Dynamically enable (state 1504) or disable (state 1502) three-phase operation. Values ​​used in signal processing for the state machine can be based on reference voltages (e.g., programmed, commanded, or otherwise known), actually measured voltages, or a combination thereof. In this example, V o,ref The output setpoint voltage (reference voltage) corresponds to both known and commanded values, and V can be measured. in In some implementations, V o,ref It can be pre-programmed.

[0169] When three-phase is disabled (state 1502), the power converter operates in two-phase mode. When three-phase is enabled (state 1504), the converter can enter the three-phase operating region based on the operating waveform. More specifically, when state machine 1500 is in state 1504, the controller can use three-phase control techniques to control the converter, including any of the various three-phase control techniques described herein.

[0170] like Figure 15 As shown, if V o,ref / V inBelow the first limit value (Limit1), three-phase operation is disabled, and the forced circuit maintains two-phase operation. If V o,ref / V in exceeds Limit1 (V o,ref / V in >Limit1), three-phase operation (status 1504) is enabled, enabling entry into three phases based on the circuit waveform (e.g., as Figure 14A shown). Three-phase operation can remain enabled until V o,ref / V in drops below the second limit value Limit2 (V o,ref / V in <Limit2), at which point three-phase operation is disabled again (status 1502). In some examples, the state machine 1500 can be initialized to status 1502 or start from status 1502.

[0171] By suppressing three-phase operation until V o,ref / V in exceeds Limit2 - where the limit values Limit2 and Limit1 are selected such that stable three-phase operation (e.g., without mode dithering) can be achieved for V o,ref / V in >Limit1 and V o,ref / V in >Limit2 - the operating region with a lower expected conversion ratio where dithering would occur can be avoided. Different limit values Limit1 and Limit2 set hysteresis in suppressing three-phase operation. To eliminate hysteresis, Limit1 and Limit2 can be set equal. In some cases, it may be desirable to set Limit1 > Limit2, where Limit1 - Limit2 defines the hysteresis band. For example, the values of Limit1 and Limit2 can be pre-programmed within the controller.

[0172] As an example of such an operation with buck + buck - boost operation in a 4-switch buck - boost converter, consider the following. Set the three-phase boundary D UM = 0.7, the first limit value Limit1 = V o,ref / V in = 0.92, and the second limit value Limit2 = V o,ref / V in = 0.9. Assume that the converter does not exhibit mode dithering for three-phase operation with a conversion ratio higher than 0.9, which will prevent mode dithering for three-phase operation with a conversion ratio slightly higher than D UM = 0.7.

[0173] Those skilled in the art can understand that, although according to Figure 15The state machine in the diagram describes the operations for enabling and disabling three-phase operation, but this functionality can be implemented (at least in part) using, for example, comparator circuitry. Introducing a hysteresis in the comparator threshold can optionally be used to set different limits for enabling and disabling three-phase operation. Furthermore, transitions to one or more states in the state machine may need to occur synchronously at some point during the switching cycle (i.e., at the beginning of t=0), or asynchronously with the switching cycle and only based on the conditions required by the state machine.

[0174] Figure 16 An example of a comparator-based implementation of three-phase transition control is shown. Circuit 1600 includes a first voltage V proportional to the desired voltage transition ratio for receiving. x (For example, V) x =V o,ref / V in The first input terminal 1602 and the second voltage V are used to receive the second voltage V. Limbase The second input terminal is 1604. For example, V Limbase V can be set to enable three-phase operation x The baseline limit of the value range. Circuit 1600 also includes a first resistor 1606, RH1, a second resistor 1608, RH2, a comparator 1610, and an output terminal 1612 connected as shown. Circuit 1600 is configured to provide a ground reference output voltage V at output terminal 1612. en .

[0175] Resistor R can be selected H1 and R H2 To set the hysteresis in three-phase operation. For example, if R H1 =0 and R is not installed H2 (Infinite impedance), then V Limit1 =V Limit2 =V Limbase (where V) Limit1 and V Limit2 They correspond to Figure 15 (The voltages of Limit1 and Limit2). As another example, if R H1 and R H2 If they are finite and non-zero, then they provide a lag such that V x The comparison point has a higher value than V. Limbase threshold V limit1 and below V limit1 V limit2 For example, the comparator power supply voltage and resistor R H1 and R H2 Limited by.

[0176] In some implementations, the output voltage V enThe change can subsequently occur at any point in the switching cycle (e.g., t=0 or t=0). <D UM At point T, the voltage is latched into the memory element synchronously with the switching cycle, so that the output voltage V en It remains unchanged during certain portions of the switching cycle. In other embodiments, the output voltage V en It can be filtered and then used, or used directly (without filtering) to enable and disable three-phase operation at any point in the switching cycle.

[0177] Figure 15 State machines and Figure 16 The transition in the comparator-based implementation is based on the expected voltage conversion ratio V. o,ref / V in The limit. However, it will be recognized that the transformation can be based on different criteria, such as the actual voltage conversion ratio V. o / V in (where V) o and V in It can be set by (a measurement quantity), or otherwise based on input or output voltage, reference voltage, current, power, or other standards that can be used to offset the aforementioned limitations of the actual circuit implementation.

[0178] In some implementations, the three-phase transition control may alternatively or additionally limit the duty cycle D by dynamically selecting. UM / D ON This is achieved. For example, in a three-phase converter using buck + buck-boost operation, for values ​​up to the boundary value D... UM,bndy The expected conversion ratio (i.e., the ratio of the reference output voltage to the input voltage) for the first range can be selected by D. UM =D um,1 The first (highest) value, where D UM,bndy <D um,1 For values ​​greater than D UM,bndy The expected voltage conversion ratio can be selected by choosing D. UM =D um,2 Different smaller values ​​of D. um,2 This makes the steady-state transition ratio equal to or higher than D. um,bndy In three-phase mode operation, the converter will operate in steady state in three-phase mode (with a limited duty cycle D). um,2 There is no pattern jitter. The hysteresis can be further incorporated into D. UM In the selection of boundary values, D um,bndy The change depends on whether D was selected. UM =D um,1 Or D UM =D um,2 This operation can also be implemented using one or more comparators.

[0179] The various N-phase control technologies, circuits, and structures disclosed in this article include, but are not limited to, those in… Figure 7 , Figure 7A , Figure 8 , Figure 8A , Figure 9 , Figure 9A , Figure 10 , Figure 13 , Figure 14A To C, Figure 15 and Figure 16 Those described in the context of the power conversion / power generator system, such as controllers... Figure 3 Controller 21 and / or Figure 3A The controller 31 is implemented within the controller or otherwise utilized by the controller.

[0180] As used herein, the terms "processor" and "controller" are used to describe an electronic circuit system that performs a function, operation, or sequence of operations. Functions, operations, or sequences of operations may be hard-coded into electronic circuitry or soft-coded by means of instructions stored in a memory device. Functions, operations, or sequences of operations may be performed using digital values ​​or analog signals. In some embodiments, the processor or controller may be implemented in an application-specific integrated circuit (ASIC), which may be an analog ASIC or a digital ASIC, in a microprocessor with associated program memory, in a digital signal processor (DSP), and / or in discrete electronic circuitry that may be analog or digital. A processor or controller may include an internal processor or module that performs a portion of a function, operation, or sequence of operations. Similarly, a module may include an internal processor or internal module that performs a portion of a module's function, operation, or sequence of operations. A single processor or other unit may implement the functions of the various means recited in the claims.

[0181] This document describes various embodiments of the concepts, systems, devices, structures, and techniques for which protection is sought, with reference to the accompanying drawings. Alternative embodiments may be designed without departing from the scope of the concepts, systems, devices, structures, and techniques described herein. It should be noted that various connections and positional relationships (e.g., above, below, adjacent, etc.) are depicted between elements in the following description and drawings. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and the described concepts, systems, devices, structures, and techniques are not intended to be limiting in this regard. Therefore, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships.

[0182] As an example of an indirect positional relationship, the reference in this specification to the formation of layer "A" on layer "B" includes the case where one or more intermediate layers (e.g., layer "C") are located between layer "A" and layer "B," provided that the relevant characteristics and functions of layers "A" and "B" are not substantially altered by the intermediate layers. The following definitions and abbreviations will be used to interpret the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing," or any other variations thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus comprising a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such compositions, mixtures, processes, methods, articles, or apparatuses.

[0183] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or design described herein as "exemplary" is not necessarily to be construed as preferred or superior to other implementations or designs. The terms "one or more" and "a plurality of" should be understood to include any integer greater than or equal to 1, i.e., 1, 2, 3, 4, etc. The term "multiple" should be understood to include any integer greater than or equal to 2, i.e., 2, 3, 4, 5, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0184] References to "one embodiment," "implementation," "exemplary embodiment," etc., in the specification indicate that the described embodiment may include specific features, structures, or characteristics; however, each embodiment may include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly stated or not, the influence of other embodiments on such feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0185] For the purposes of this description, terms such as “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom” (to name just a few), and their derivatives, shall refer to the structures and methods described as oriented as shown in the accompanying drawings. The terms “cover,” “top,” “on top,” “positioned on top,” or “positioned on top” mean that a first element, such as a first structure, exists on a second element, such as a second structure, wherein an intermediate element, such as an interface structure, may exist between the first and second elements. The term “direct contact” means that the first element (e.g., the first structure) and the second element (e.g., the second structure) are connected without any intermediate elements. Such terms are sometimes referred to as directional or positional terms.

[0186] The use of ordinal terms such as “first,” “second,” and “third” to modify a claim element does not imply any priority, precedence, or order of one claim element relative to another, or any temporal order of the actions of the method of execution. Rather, it serves only as a label to distinguish one claim element with a specific name from another element with the same name (but only for the purpose of using ordinal terms) to differentiate claim elements.

[0187] In some embodiments, the terms "about" and "approximately" may be used to indicate values ​​within ±20% of a target value, within ±10% of a target value, within ±5% of a target value, and within ±2% of a target value. The terms "about" and "approximately" may include the target value. The term "substantially equal" may be used to refer to values ​​that are within ±20% of each other in some embodiments, within ±10% of each other in some embodiments, within ±5% of each other in some embodiments, and within ±2% of each other in some embodiments.

[0188] The term "substantially" can be used to refer to a value within ±20% of the comparative measure in some embodiments, within ±10% in some embodiments, within ±5% in some embodiments, and within ±2% in some embodiments. For example, "substantially" perpendicular to the second direction can refer to a first direction within ±20% of the second direction at a 90° angle in some embodiments, within ±10% of the second direction at a 90° angle in some embodiments, within ±5% of the second direction at a 90° angle in some embodiments, and within ±2% of the second direction at a 90° angle in some embodiments.

[0189] It should be understood that the disclosed subject matter is not limited in its application to the construction details and arrangement of the components set forth in the following description or shown in the accompanying drawings. The disclosed subject matter can have other embodiments and can be practiced and implemented in various ways.

[0190] Furthermore, it should be understood that the wording and terminology used herein are for descriptive purposes and should not be considered restrictive. Therefore, those skilled in the art will understand that the concepts upon which this disclosure is based can readily be used as the basis for designing other structures, methods, and systems for achieving several of the purposes of the disclosed subject matter. Consequently, the claims should be considered to include such equivalent constructions, provided they do not depart from the spirit and scope of the disclosed subject matter.

[0191] Although the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it should be understood that this disclosure is by way of example only, and many changes may be made to the details of the implementation of the disclosed subject matter without departing from the spirit and scope of the disclosed subject matter.

[0192] All publications and references cited in this article are incorporated herein by reference in their entirety.

[0193] The content for which protection is sought is attached.

Claims

1. A controller for a power converter having a plurality of switches and at least one inductor, the controller comprising a circuit system configured to: The power converter is controlled according to at least one operating mode having at least a first phase and a second phase, wherein, In the first phase, the controller controls the plurality of switches to be in a first switching state; wherein, in the second phase, the controller controls the plurality of switches to be in a second switching state; and In response to the failure to meet one or more conditions for transitioning from the first phase to the second phase during a cycle of the at least one operating mode: During the cycle, the intermediate phase between the first phase and the second phase is entered by controlling the plurality of switches to be in a third switching state; and Adjust the duration of the phase following the intermediate phase by the value ΔT.

2. The controller according to claim 1, wherein, The phase with adjusted duration is part of the cycle in which the intermediate phase is entered, such that the time period of the cycle is also adjusted.

3. The controller according to claim 1, wherein, The phase with adjusted duration is the second phase of the cycle.

4. The controller according to claim 1, wherein, The controller is configured to adjust the duration of the phase by overriding the start of the next cycle to maintain the second switching state for the duration of the value ΔT.

5. The controller according to claim 1, wherein, ΔT is selected based at least in part on one of the following: The voltage conversion ratio of the power converter; The output voltage of the power converter; The current value of the at least one inductor; and The power level of the power converter.

6. The controller according to claim 1, wherein, ΔT is selected based at least in part on one of the following: Reference value; The measured value; and The value of the command.

7. The controller according to claim 1, wherein, ΔT is chosen to approximate |V L1A / V L2 | proportional, where V L1A V is the voltage across the at least one inductor during the intermediate phase, and V L2 It is the voltage across the at least one inductor during the second phase.

8. The controller according to claim 1, wherein, ΔT was chosen to be approximately equal to the minimum achievable duration of the intermediate phase.

9. The controller according to claim 1, wherein, Use at least one of the following to select ΔT: A set of values ​​in programming; and Look up the table LUT.

10. The controller according to claim 1, wherein, Adaptive feedforward is used to determine ΔT.

11. A controller for a power converter having a plurality of switches and at least one inductor, the controller comprising a circuit system configured to: The power converter is controlled according to at least one operating mode having at least a first phase and a second phase, wherein, In the first phase, the controller controls the plurality of switches to be in a first switching state, and in the second phase, the controller controls the plurality of switches to be in a second switching state. In response to the failure to meet one or more conditions for switching from the first phase to the second phase during a cycle of at least one operating mode, three-phase operation is achieved by controlling the plurality of switches to a third switching state during the cycle to enter an intermediate phase between the first phase and the second phase; and For one or more other cycles of the at least one operating mode, the three-phase operation is selectively suppressed.

12. The controller according to claim 11, wherein, The one or more conditions used for switching from the first phase to the second phase include whether the current of the at least one inductor is limited by the duty cycle D. UM The target current is reached before the duration defined by the cycle period T, wherein the circuit system is configured to dynamically adjust the limiting duty cycle D. UM To suppress the three-phase operation for one or more other cycles.

13. The controller according to claim 11, wherein, The circuit system is configured to selectively suppress the three-phase operation, at least in part based on the use of a state machine.

14. The controller according to claim 11, wherein, The circuit system is configured to selectively suppress the three-phase operation, at least in part, based on the use of comparators.

15. The controller according to claim 11, wherein, The circuit system is configured to selectively suppress the three-phase operation based at least in part on at least one of the following: The voltage conversion ratio of the power converter; The output voltage of the power converter; The current value of the at least one inductor; and The power level of the power converter.

16. The controller according to claim 11, wherein, The circuit system is configured to selectively suppress the three-phase operation based at least in part on at least one of the following: Reference value; The measured value; and The value of the command.

17. A method for controlling a power converter according to an operating mode having at least a first phase and a second phase, the method comprising: Turn on one or more first switches of the power converter to realize the first phase of the operating mode; as well as In response to the failure to meet one or more conditions for switching from the first phase of the operating mode to the second phase of the operating mode during a cycle of the operating mode, three-phase operation is achieved by turning on one or more second switches of the power converter during the cycle to enter an intermediate phase between the first phase and the second phase. In response to the satisfaction of one or more conditions for transitioning to the second phase, the system enters the second phase; as well as One or more actions are taken to compensate for the excess volt-seconds applied to the inductor of the power converter during the cycle.

18. The method according to claim 17, wherein, The one or more actions used to compensate for excess volt-seconds include adjusting the duration of the phase following the intermediate phase.

19. The method according to claim 18, wherein, Adjusting the duration of the phase includes covering the start of the next cycle to maintain the switching state associated with the second phase for a duration ΔT.

20. The method of claim 17, wherein, The one or more actions used to compensate for excess volt-seconds include selectively suppressing the three-phase operation.

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