Heterogeneous integrated filter preparation method and heterogeneous integrated filter

Abstract

The invention relates to the technical field of semiconductors, in particular to a preparation method of a heterogeneous integrated filter and the heterogeneous integrated filter, and the method comprises the steps that a first lower electrode and a second lower electrode are deposited on a base substrate, and the first lower electrode covers a concave structure arranged on the base substrate; the second lower electrode is thicker than the first lower electrode; depositing a piezoelectric layer on the base substrate, wherein the piezoelectric layer covers the first lower electrode and the second lower electrode; depositing a first upper electrode and a second upper electrode on the piezoelectric layer; projection parts of the first upper electrode, the piezoelectric layer, the first lower electrode and the sunken structure on the base layer substrate are overlapped to form an active area for resonance; and projection parts of the second upper electrode, the piezoelectric layer and the second lower electrode on the base substrate are overlapped to form a passive area for a capacitor. According to the invention, integration of a high-performance thin-electrode acoustic resonator and a low-loss thick-electrode capacitor can be realized, and the problem that the performance of passive elements in a high-frequency filter is limited is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for fabricating a heterogeneous integrated filter and a heterogeneous integrated filter. Background Technology

[0002] In the design of heterogeneous integrated filters for high-frequency applications (such as above 5GHz), passive components are usually integrated in the blank areas of the device. This not only significantly improves chip area utilization and reduces overall cost, but also reduces interconnect length through on-chip integration, thereby reducing parasitic resistance and inductance, and improving the Q value of passive components and the electromagnetic performance of the overall filter.

[0003] To ensure acoustic performance and frequency accuracy, the upper and lower electrodes of high-frequency thin-film bulk acoustic resonators (FBARs) typically need to be extremely thin (generally ≤200nm, or even below 150nm). However, traditional on-chip capacitors (especially high-density MIM capacitors) typically require a lower electrode thickness of over 1000nm to reduce equivalent series resistance, improve Q value, and increase capacitance density. Current technologies using the same thin electrode layer as both the capacitor and resonator electrodes in the fabrication process result in excessively high capacitor structure resistance, a significant decrease in Q value, and deterioration of electromagnetic performance, making it difficult to meet the performance requirements of high-frequency filters for passive components. Summary of the Invention

[0004] The purpose of this application is to provide a method for fabricating a heterogeneous integrated filter and a heterogeneous integrated filter, which can realize the integration of a high-performance thin-electrode acoustic resonator and a low-loss thick-electrode capacitor, and solve the problem of limited performance of passive components in high-frequency filters.

[0005] This application is implemented as follows: In a first aspect, this application provides a method for fabricating a heterogeneous integrated filter, comprising: A first lower electrode and a second lower electrode are deposited on a base substrate, wherein the first lower electrode covers a recessed structure disposed on the base substrate; the thickness of the second lower electrode is greater than the thickness of the first lower electrode. A piezoelectric layer is deposited on the base substrate, the piezoelectric layer covering the first lower electrode and the second lower electrode; A first upper electrode and a second upper electrode are deposited on the piezoelectric layer; the projection portions of the first upper electrode, the piezoelectric layer, the first lower electrode, and the recessed structure on the substrate overlap to form an active region for resonance; the projection portions of the second upper electrode, the piezoelectric layer, and the second lower electrode on the substrate overlap to form a passive region for capacitance. A first metal structure is provided that is connected to the first lower electrode and the first upper electrode respectively to form a resonator; a second metal structure is provided that is connected to the second lower electrode and the second upper electrode respectively to form a capacitor.

[0006] As an optional implementation, the deposition of a first lower electrode and a second lower electrode on a base substrate, wherein the first lower electrode covers a recessed structure disposed on the base substrate; and the thickness of the second lower electrode is greater than the thickness of the first lower electrode, includes: A first lower electrode and a bottom electrode of uniform thickness are deposited on a base substrate; A thickened electrode is deposited on the bottom electrode to form a second lower electrode.

[0007] As an optional implementation, the deposition of a first lower electrode and a second lower electrode on a base substrate, wherein the first lower electrode covers a recessed structure disposed on the base substrate; and the thickness of the second lower electrode is greater than the thickness of the first lower electrode, includes: After depositing a first lower electrode on the base substrate, a second lower electrode is deposited on the base substrate; or, after depositing a second lower electrode on the base substrate, a first lower electrode is deposited on the base substrate.

[0008] As an optional implementation, the deposition of a piezoelectric layer on the base substrate, the piezoelectric layer covering the first lower electrode and the second lower electrode, includes: The thickness of the piezoelectric layer on the second lower electrode is greater than the thickness of the piezoelectric layer on the first lower electrode.

[0009] As an optional implementation, the first metal structure connected to the first lower electrode and the first upper electrode respectively forms a resonator; the second metal structure connected to the second lower electrode and the second upper electrode respectively forms a capacitor; and further includes: Patterned windows that expose the base substrate are formed by etching on the piezoelectric layer; A third metal structure is deposited within the patterned window to form an inductor.

[0010] As an optional implementation, after the first metal structure connected to the first lower electrode and the first upper electrode respectively forms a resonator; and the second metal structure connected to the second lower electrode and the second upper electrode respectively forms a capacitor, the method further includes: Provide a cover plate substrate; A cover plate capacitor is fabricated on the surface of the cover plate substrate; A bonding structure is provided on the surface of the cover plate substrate where the cover plate capacitor is disposed, and the bonding structure is bonded to the base substrate.

[0011] As an optional implementation, the fabrication of the cover plate capacitor on the surface of the cover plate substrate includes: The surface of the cover plate substrate is subjected to CMP treatment to make the surface planarize.

[0012] As an optional implementation, the step of forming a bonding structure on the surface of the cover plate substrate where the cover plate capacitor is formed, and bonding it to the base substrate through the bonding structure, includes: A protective layer is deposited on the surface of the cover plate substrate, the protective layer covering the cover plate capacitor; A raised metal block is provided on the surface of the protective layer, and the surface of the raised metal block facing away from the cover plate substrate is flush with the surface of the protective layer on the cover plate capacitor. A bonding structure is provided on the raised metal block; The cover plate substrate is placed parallel to the base substrate and bonded to the base substrate through the bonding structure.

[0013] Secondly, this application provides a heterogeneous integrated filter, including a base substrate; a first lower electrode and a second lower electrode are deposited on the base substrate, the first lower electrode covering a recessed structure disposed on the base substrate; a piezoelectric layer is deposited on the base substrate, the piezoelectric layer covering the first lower electrode and the second lower electrode; a first upper electrode and a second upper electrode are deposited on the piezoelectric layer; the projection portions of the first upper electrode, the piezoelectric layer, the first lower electrode, and the recessed structure on the base substrate overlap to form an active region for resonance; the projection portions of the second upper electrode, the piezoelectric layer, and the second lower electrode on the base substrate overlap to form a passive region for capacitance; the first lower electrode and the first upper electrode are respectively led out through a disposed first metal structure to form a resonator; the second lower electrode and the second upper electrode are respectively led out through a disposed second metal structure to form a capacitor; the thickness of the second lower electrode is greater than the thickness of the first lower electrode.

[0014] As an optional implementation, the thickness of the piezoelectric layer on the second lower electrode is greater than the thickness of the piezoelectric layer on the first lower electrode.

[0015] The beneficial effects of this application include: The heterogeneous integrated filter fabrication method and the heterogeneous integrated filter provided in this application effectively solve the problems of low capacitance Q value, high resistance, and performance degradation caused by sharing thin electrodes in traditional processes by setting optimized first and second lower electrodes on the same chip. This solution achieves monolithic collaborative integration of a high-frequency resonator and a high-performance passive capacitor without adding complex heterogeneous integration steps. On the one hand, it ensures the acoustic characteristics and frequency accuracy required by the FBAR in the frequency band above 5GHz; on the other hand, it significantly improves the quality factor, capacitance density, and conductivity of the on-chip capacitors. Simultaneously, by integrating capacitors in the blank areas of the device, the interconnect length is shortened, and parasitic resistance and inductance are reduced, thereby improving the overall electromagnetic performance, area utilization, and cost-effectiveness of the filter, meeting the requirements of high-frequency communication systems for high-performance, highly integrated RF front-ends. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is one of the structural schematic diagrams of the heterogeneous integrated filter according to an embodiment of this application; Figure 2 This is a second schematic diagram of the heterogeneous integrated filter structure according to an embodiment of this application; Figure 3 This is the third schematic diagram of the heterogeneous integrated filter structure according to an embodiment of this application; Figure 4 This is the fourth schematic diagram of the heterogeneous integrated filter in the embodiments of this application; Figure 5 This is the fifth schematic diagram of the heterogeneous integrated filter in the embodiments of this application; Figure 6 This is the sixth schematic diagram of the heterogeneous integrated filter in the embodiments of this application; Figure 7 This is the seventh schematic diagram of the heterogeneous integrated filter in the embodiments of this application.

[0018] icon: 100 - Base substrate; 101 - First lower electrode; 102 - Second lower electrode; 103 - Recessed structure; 104 - Piezoelectric layer; 105 - First upper electrode; 106 - Second upper electrode; 107 - First metal structure; 108 - Second metal structure; 109 - Bottom electrode; 110 - Thickened electrode; 111 - Third metal structure; 112 - Cover substrate; 113 - Cover capacitor; 114 - Bonding structure; 115 - Protective layer; 116 - Elevated metal block. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0023] In the design of heterogeneous integrated filters for high-frequency applications (such as above 5GHz), passive components are usually integrated in the blank areas of the device. This not only significantly improves chip area utilization and reduces overall cost, but also reduces interconnect length through on-chip integration, thereby reducing parasitic resistance and inductance, and improving the Q value of passive components and the electromagnetic performance of the overall filter.

[0024] To ensure acoustic performance and frequency accuracy, the upper and lower electrodes of high-frequency thin-film bulk acoustic resonators (FBARs) typically need to be extremely thin (generally ≤200nm, or even below 150nm). However, traditional on-chip capacitors (especially high-density MIM capacitors) typically require a lower electrode thickness of over 1000nm to reduce equivalent series resistance, improve Q value, and increase capacitance density. Current technologies using the same thin electrode layer as both the capacitor and resonator electrodes in the fabrication process result in excessively high capacitor structure resistance, a significant decrease in Q value, and deterioration of electromagnetic performance, making it difficult to meet the performance requirements of high-frequency filters for passive components.

[0025] To address the aforementioned technical problems, this application provides a method for fabricating a heterogeneous integrated filter and a heterogeneous integrated filter.

[0026] The heterogeneous integrated filter fabrication method provided in this application includes: Reference Figure 1As shown, a first lower electrode 101 and a second lower electrode 102 are deposited on a base substrate 100. The first lower electrode 101 covers the recessed structure 103 provided on the base substrate 100. The thickness of the second lower electrode 102 is greater than the thickness of the first lower electrode 101. A piezoelectric layer 104 is deposited on the base substrate 100, and the piezoelectric layer 104 covers the first lower electrode 101 and the second lower electrode 102. A first upper electrode 105 and a second upper electrode 106 are deposited on the piezoelectric layer 104; the projection portions of the first upper electrode 105, the piezoelectric layer 104, the first lower electrode 101, and the recessed structure 103 on the substrate 100 overlap to form an active region for resonance; the projection portions of the second upper electrode 106, the piezoelectric layer 104, and the second lower electrode 102 on the substrate 100 overlap to form a passive region for capacitance. A first metal structure 107 is provided, which is connected to the first lower electrode 101 and the first upper electrode 105 respectively, to form a resonator; a second metal structure 108 is provided, which is connected to the second lower electrode 102 and the second upper electrode 106 respectively, to form a capacitor.

[0027] It should be noted that, through differentiated electrode thickness design, the performance of the resonator and on-chip capacitor are optimized in the same process flow: for the high-frequency FBAR resonator, an ultra-thin first lower electrode (≤200nm) is used to ensure acoustic vibration characteristics and frequency accuracy; while for high Q value, high density MIM capacitor, a significantly thicker second lower electrode 102 (≥1000nm) is used to reduce equivalent series resistance, improve capacitance density and quality factor.

[0028] In this embodiment, two types of lower electrodes with different thicknesses are simultaneously fabricated on a substrate 100. The first lower electrode 101 is covered by a recessed structure 103 to form an acoustic cavity, and the second lower electrode 102 is a planar thick-film structure used for the capacitor. Integration is then completed by sharing the same piezoelectric layer 104 and separately patterned upper electrodes. This method achieves heterogeneous but monolithic integration of the active region of the resonator and the passive region of the capacitor. It avoids the performance trade-offs caused by traditional shared electrodes, fully utilizes the blank areas of the chip to improve area efficiency, shortens interconnect paths, effectively suppresses parasitic effects, and significantly improves the overall electromagnetic performance and integration density of the high-frequency filter.

[0029] This application embodiment effectively solves the problems of low Q value, high resistance, and performance degradation caused by the shared thin electrodes in traditional processes by setting a first lower electrode 101 for the FBAR resonator and a second lower electrode 102 for the on-chip capacitor on the same chip with optimized thickness. This solution achieves monolithic collaborative integration of a high-frequency resonator and a high-performance passive capacitor without adding complex heterogeneous integration steps. On the one hand, it ensures the acoustic characteristics and frequency accuracy required by the FBAR in the frequency band above 5GHz; on the other hand, it significantly improves the quality factor (Q value), capacitance density, and conductivity of the on-chip capacitor. Simultaneously, by integrating capacitors in the blank areas of the device, the interconnect length is shortened, and parasitic resistance and inductance are reduced, thereby improving the overall electromagnetic performance, area utilization, and cost-effectiveness of the filter, meeting the requirements of high-frequency communication systems for high-performance, highly integrated RF front-ends.

[0030] As an optional implementation, a first lower electrode 101 and a second lower electrode 102 are deposited on a base substrate 100, wherein the first lower electrode 101 covers the recessed structure 103 disposed on the base substrate 100; the thickness of the second lower electrode 102 is greater than the thickness of the first lower electrode 101; including: Reference Figure 2 As shown, a first lower electrode 101 and a bottom electrode 109 of uniform thickness are deposited on a base substrate 100; Reference Figure 3 As shown, a thickened electrode 110 is deposited on the bottom electrode 109 to form a second lower electrode 102.

[0031] It should be noted that, in this embodiment, a first lower electrode 101 and a bottom electrode 109 of uniform thickness are firstly deposited simultaneously on the substrate 100. Then, a thickening electrode 110 is selectively deposited only in the area of ​​the bottom electrode 109, thereby forming a thicker second lower electrode 102. This method, while maintaining process compatibility and simplifying the process, precisely meets the requirements of high-frequency FBARs for ultra-thin electrodes (≤200nm) to maintain acoustic performance, and on-chip capacitors for thick electrodes (≥1000nm) to reduce series resistance, increase Q value, and improve capacitance density. This achieves efficient heterogeneous integration of the resonator's active region and the capacitor's passive region on the same chip, not only avoiding the performance compromises caused by traditional shared electrodes, but also improving area utilization, reducing interconnect parasitic effects, and significantly enhancing the overall electromagnetic performance and integration of the high-frequency filter.

[0032] Unlike the above embodiments, a first lower electrode 101 and a second lower electrode 102 are deposited on the base substrate 100, wherein the first lower electrode 101 covers the recessed structure 103 provided on the base substrate 100; the thickness of the second lower electrode 102 is greater than the thickness of the first lower electrode 101; including: Reference Figure 4As shown, after depositing the first lower electrode 101 on the substrate 100, referring to Figure 5 As shown, a second lower electrode 102 is deposited on the substrate 100; or, after depositing the second lower electrode 102 on the substrate 100, a first lower electrode 101 is deposited on the substrate 100.

[0033] In this embodiment, a first lower electrode 101 and a second lower electrode 102 with different thicknesses are formed by step-by-step, independent deposition: first, a first lower electrode 101 for the FBAR resonator is deposited on the substrate 100, the first lower electrode 101 covers the recessed structure 103 and has a thin thickness, usually ≤200nm, and then a second lower electrode 102 for the on-chip capacitor is deposited, with a thickness ≥1000nm, or vice versa.

[0034] The process described in this application does not rely on a single electrode layer to perform both functions, thus completely decoupling the acoustic requirements of the resonator for ultra-thin electrodes from the capacitor's requirements for low impedance and high Q value of thick electrodes. This application precisely ensures the frequency accuracy and vibration efficiency of high-frequency FBARs while significantly improving the quality factor and capacitance density of integrated capacitors. Simultaneously, the flexible deposition sequence adapts to different materials and process windows, enhancing manufacturing compatibility and ultimately achieving a high-performance, highly integrated heterogeneous filter, effectively reducing parasitic effects and improving chip area utilization.

[0035] As an optional implementation, a piezoelectric layer 104 is deposited on the base substrate 100, the piezoelectric layer 104 covering the first lower electrode 101 and the second lower electrode 102, including: The thickness of the piezoelectric layer 104 on the second lower electrode 102 is greater than the thickness of the piezoelectric layer 104 on the first lower electrode 101.

[0036] It should be noted that in the piezoelectric layer 104 covering the first lower electrode 101 and the second lower electrode 102, the thickness of the piezoelectric layer 104 on the region of the second lower electrode 102 is greater than the thickness of the piezoelectric layer 104 on the region of the first lower electrode 101.

[0037] It should be noted that increasing the thickness of the piezoelectric layer 104, used as the dielectric of the MIM capacitor, effectively improves the dielectric strength, thereby enhancing the capacitor's breakdown voltage withstand capability. Simultaneously, a thicker piezoelectric layer 104 significantly improves the acoustic impedance mismatch in this region and suppresses bulk acoustic resonance modes, preventing parasitic resonances in the capacitor structure at high frequencies and ensuring stable operation in a pure capacitor state above 5 GHz. The resonator region retains a thinner piezoelectric layer 104 to maintain accurate resonant frequency and high electromechanical coupling efficiency. This differentiated piezoelectric layer 104 design achieves independent optimization of active resonant and passive capacitor functions within the same integration process, balancing high-frequency performance, reliability, and integration density.

[0038] When the entire piezoelectric layer 104 is thick, a thicker piezoelectric layer 104 or other insulating layer can be deposited on the second lower electrode 102, which is the passive region of the capacitor, to improve the breakdown voltage, suppress parasitic resonance, or optimize capacitor performance. Examples include silicon dioxide, silicon nitride, and aluminum oxide.

[0039] As an optional implementation, a first metal structure 107 is provided, connected to the first lower electrode 101 and the first upper electrode 105 respectively, to form a resonator; a second metal structure 108 is provided, connected to the second lower electrode 102 and the second upper electrode 106 respectively, to form a capacitor; and further includes: Patterned windows that expose the base substrate 100 are formed on the piezoelectric layer 104 by etching; Reference Figure 1 As shown, a third metal structure 111 is deposited within a patterned window to form an inductor.

[0040] It should be noted that, in this embodiment, a patterned window penetrating the piezoelectric layer 104 and exposing the base substrate 100 is formed by etching on the piezoelectric layer 104, and a third metal structure 111 is deposited within this window, thereby monolithically integrating an on-chip inductor. Highly conductive metals (such as Cu, Al, or Au) are directly anchored to the base substrate 100 using deep holes or trench windows, constructing inductor elements with three-dimensional spiral, planar spiral, or through-hole structures. Since the inductor region does not depend on the piezoelectric material and is far from the acoustic active region, interference with FBAR resonant performance can be avoided. Simultaneously, this inductor, along with the aforementioned high-performance resonator and high-Q capacitor, is co-integrated on the same chip, forming a complete passive filter network, significantly reducing the need for off-chip discrete components, shortening interconnect paths, and reducing parasitic effects, thereby improving the overall performance, integration, and miniaturization level of the high-frequency filter.

[0041] As an optional implementation, after providing a first metal structure 107 connected to the first lower electrode 101 and the first upper electrode 105 respectively to form a resonator; and providing a second metal structure 108 connected to the second lower electrode 102 and the second upper electrode 106 respectively to form a capacitor, the method further includes: Reference Figure 6 As shown, a cover plate substrate 112 is provided; Reference Figure 6 As shown, a cover plate capacitor 113 is fabricated on the surface of the cover plate substrate 112; Reference Figure 7 As shown, a bonding structure 114 is provided on the surface of the cover capacitor 113 on the cover substrate 112, and is bonded to the base substrate 100 through the bonding structure 114.

[0042] This application embodiment fabricates an additional cover capacitor 113 on the cover substrate 112 and uses a bonding structure 114 to perform three-dimensional bonding between the cover substrate 112 and the base substrate 100 where the resonator and capacitor have been integrated, thereby achieving vertical stacked heterogeneous integration. This application embodiment introduces high-performance on-chip capacitors and packaged embedded capacitors simultaneously through wafer-level packaging, further improving the density of passive components and system integration. At the same time, the bonding layer provides hermetic protection and shortens the interconnect path, thereby optimizing the overall performance and miniaturization level of the high-frequency filter.

[0043] As an optional implementation, a cover capacitor 113 is fabricated on the surface of the cover substrate 112, including: The surface of the cover plate substrate 112 is subjected to CMP treatment to make the surface planarize.

[0044] It should be noted that, in this embodiment of the application, before fabricating the cover capacitor 113 on the surface of the cover substrate 112, a chemical mechanical polishing treatment is first performed on it to achieve a highly flat surface. The flat substrate surface can ensure that the thickness of the subsequently deposited capacitor electrode and dielectric layer is uniform and the interface continuity is good, effectively avoiding electric field concentration, breakdown voltage drop or patterning defects caused by surface undulations, thereby improving the reliability, consistency and quality factor (Q value) of the cover capacitor 113, and providing a high-quality bonding and device foundation for high-precision three-dimensional heterogeneous integration.

[0045] As an optional implementation, a bonding structure 114 is formed on the surface of the cover capacitor 113 on the cover substrate 112, and bonded to the base substrate 100 through the bonding structure 114, including: Reference Figure 6 As shown, a protective layer 115 is deposited on the surface of the cover plate substrate 112, and the protective layer 115 covers the cover plate capacitor 113. Reference Figure 6 , Figure 7 As shown, a raised metal block 116 is provided on the surface of the protective layer 115, and the surface of the raised metal block 116 facing away from the cover plate substrate 112 is flush with the surface of the protective layer 115 on the cover plate capacitor 113. A bonding structure 114 is provided on the raised metal block 116; The cover plate substrate 112 is placed parallel to the base substrate 100 and bonded to the base substrate 100 through the bonding structure 114.

[0046] In this embodiment, a protective layer 115 covering the cover capacitor 113 is provided on the cover substrate 112, and a raised metal block 116 flush with the protective layer 115 is formed on its surface. Then, a bonding structure 114 is constructed on the raised metal block 116 to achieve reliable bonding with the base substrate 100.

[0047] It should be noted that in this embodiment, the raised metal block 116 compensates for the surface height difference caused by the protrusion of the cover capacitor 113, ensuring that the bonding interface remains coplanar. This guarantees uniform pressure distribution and good contact during the bonding process, preventing voids or misalignments. Simultaneously, the protective layer 115 effectively isolates and protects the cover capacitor 113 from damage or contamination during the bonding process. This structure balances the requirements of capacitor performance protection and high-precision wafer-level bonding in three-dimensional integration, improving the yield, reliability, and high-frequency performance consistency of heterogeneous integrated filters.

[0048] Reference Figure 1 As shown, this application provides a heterogeneous integrated filter, including a substrate 100; a first lower electrode 101 and a second lower electrode 102 are deposited on the substrate 100, the first lower electrode 101 covering a recessed structure 103 disposed on the substrate 100; a piezoelectric layer 104 is deposited on the substrate 100, the piezoelectric layer 104 covering the first lower electrode 101 and the second lower electrode 102; a first upper electrode 105 and a second upper electrode 106 are deposited on the piezoelectric layer 104; the first upper electrode 105, the piezoelectric layer 104, the first lower electrode 101, and the recessed structure 103 are all present. The projections of the second upper electrode 106, the piezoelectric layer 104, and the second lower electrode 102 on the substrate 100 overlap to form an active region for resonance; the projections of the second upper electrode 106, the piezoelectric layer 104, and the second lower electrode 102 on the substrate 100 overlap to form a passive region for capacitance; the first lower electrode 101 and the first upper electrode 105 are respectively led out through the first metal structure 107 to form a resonator; the second lower electrode 102 and the second upper electrode 106 are respectively led out through the second metal structure 108 to form a capacitor; the thickness of the second lower electrode 102 is greater than the thickness of the first lower electrode 101.

[0049] This application provides a heterogeneous integrated filter that integrates a first lower electrode 101 and a second lower electrode 102 of different thicknesses on the same substrate 100. These electrodes serve as on-chip capacitors and are relatively thick. They share a piezoelectric layer 104 and separately patterned upper electrodes, forming an acoustically optimized resonant active region and a high-Q capacitor passive region. This structure, through differentiated electrode thickness design, satisfies both the requirements of high-frequency FBARs for ultra-thin electrodes to ensure frequency accuracy and electromechanical coupling efficiency, and the requirements of MIM capacitors for thick electrodes to reduce series resistance, increase Q value, and improve capacitance density.

[0050] The embodiments of this application avoid the performance trade-offs caused by traditional shared electrodes, significantly improve the performance of passive components and chip area utilization, shorten interconnection paths to suppress parasitic effects, thereby achieving high-performance, highly integrated, and low-cost monolithic filters in high-frequency bands above 5GHz.

[0051] As an optional implementation, the thickness of the piezoelectric layer 104 on the second lower electrode 102 is greater than the thickness of the piezoelectric layer 104 on the first lower electrode 101.

[0052] This embodiment uses a thickened piezoelectric layer 104 in the capacitor region as a high-insulation dielectric layer. This increases the dielectric strength to enhance breakdown voltage withstand capability and increases acoustic impedance mismatch, suppressing parasitic acoustic wave resonance modes and ensuring stable operation of the capacitor in a pure capacitor state at high frequencies. Meanwhile, a thinner piezoelectric layer 104 is retained in the resonator region to precisely control the resonant frequency and maintain high electromechanical coupling efficiency. This differentiated piezoelectric layer 104 thickness structure achieves independent optimization of active resonance and passive capacitor functions within the same integration process, effectively balancing high-frequency performance, reliability, and integration density.

[0053] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a heterogeneous integrated filter, characterized in that, include: A first lower electrode (101) and a second lower electrode (102) are deposited on a base substrate (100), wherein the first lower electrode (101) covers a recessed structure (103) disposed on the base substrate (100); the thickness of the second lower electrode (102) is greater than the thickness of the first lower electrode (101); A piezoelectric layer (104) is deposited on the base substrate (100), the piezoelectric layer (104) covering the first lower electrode (101) and the second lower electrode (102). A first upper electrode (105) and a second upper electrode (106) are deposited on the piezoelectric layer (104); the projection portions of the first upper electrode (105), the piezoelectric layer (104), the first lower electrode (101), and the recessed structure (103) on the substrate (100) overlap to form an active region for resonance; the projection portions of the second upper electrode (106), the piezoelectric layer (104), and the second lower electrode (102) on the substrate (100) overlap to form a passive region for capacitance; A first metal structure (107) is provided, which is connected to the first lower electrode (101) and the first upper electrode (105) respectively, to form a resonator; a second metal structure (108) is provided, which is connected to the second lower electrode (102) and the second upper electrode (106) respectively, to form a capacitor.

2. The method for fabricating a heterogeneous integrated filter according to claim 1, characterized in that, The deposition of a first lower electrode (101) and a second lower electrode (102) on a base substrate (100), wherein the first lower electrode (101) covers a recessed structure (103) disposed on the base substrate (100); the thickness of the second lower electrode (102) is greater than the thickness of the first lower electrode (101); including: A first lower electrode (101) and a bottom electrode (109) of uniform thickness are deposited on a base substrate (100). A thickened electrode (110) is deposited on the bottom electrode (109) to form a second lower electrode (102).

3. The method for fabricating a heterogeneous integrated filter according to claim 1, characterized in that, The deposition of a first lower electrode (101) and a second lower electrode (102) on a base substrate (100), wherein the first lower electrode (101) covers a recessed structure (103) disposed on the base substrate (100); the thickness of the second lower electrode (102) is greater than the thickness of the first lower electrode (101); including: After depositing a first lower electrode (101) on the base substrate (100), a second lower electrode (102) is deposited on the base substrate (100); or, after depositing a second lower electrode (102) on the base substrate (100), a first lower electrode (101) is deposited on the base substrate (100).

4. The method for fabricating a heterogeneous integrated filter according to claim 1, characterized in that, The deposition of a piezoelectric layer (104) on the base substrate (100), the piezoelectric layer (104) covering the first lower electrode (101) and the second lower electrode (102), includes: The thickness of the piezoelectric layer (104) on the second lower electrode (102) is greater than the thickness of the piezoelectric layer (104) on the first lower electrode (101).

5. The method for fabricating a heterogeneous integrated filter according to claim 1, characterized in that, The first metal structure (107) connected to the first lower electrode (101) and the first upper electrode (105) respectively forms a resonator; the second metal structure (108) connected to the second lower electrode (102) and the second upper electrode (106) respectively forms a capacitor; and further includes: A patterned window exposing the base substrate (100) is formed on the piezoelectric layer (104) by etching; A third metal structure (111) is deposited within the patterned window to form an inductor.

6. The method for fabricating a heterogeneous integrated filter according to any one of claims 1-5, characterized in that, After the first metal structure (107) is connected to the first lower electrode (101) and the first upper electrode (105) respectively to form a resonator, and the second metal structure (108) is connected to the second lower electrode (102) and the second upper electrode (106) respectively to form a capacitor, the method further includes: A cover plate substrate (112) is provided; A cover plate capacitor (113) is fabricated on the surface of the cover plate substrate (112); A bonding structure (114) is provided on the surface of the cover plate substrate (112) where the cover plate capacitor (113) is provided, and is bonded to the base substrate (100) through the bonding structure (114).

7. The method for fabricating a heterogeneous integrated filter according to claim 6, characterized in that, The fabrication of the cover plate capacitor (113) on the surface of the cover plate substrate (112) includes: The surface of the cover plate substrate (112) is subjected to CMP treatment to make the surface planarize.

8. The method for fabricating a heterogeneous integrated filter according to claim 6, characterized in that, The step of setting a bonding structure (114) on the surface of the cover capacitor (113) on the cover substrate (112) and bonding it to the base substrate (100) through the bonding structure (114) includes: A protective layer (115) is deposited on the surface of the cover plate substrate (112), the protective layer (115) covering the cover plate capacitor (113). A raised metal block (116) is provided on the surface of the protective layer (115), and the surface of the raised metal block (116) facing away from the cover plate substrate (112) is flush with the surface of the protective layer (115) on the cover plate capacitor (113); A bonding structure (114) is provided on the raised metal block (116). The cover plate substrate (112) is placed parallel to the base substrate (100) and bonded to the base substrate (100) through the bonding structure (114).

9. A heterogeneous integrated filter, characterized in that, The system includes a base substrate (100); a first lower electrode (101) and a second lower electrode (102) are deposited on the base substrate (100), the first lower electrode (101) covering a recessed structure (103) disposed on the base substrate (100); a piezoelectric layer (104) is deposited on the base substrate (100), the piezoelectric layer (104) covering the first lower electrode (101) and the second lower electrode (102); a first upper electrode (105) and a second upper electrode (106) are deposited on the piezoelectric layer (104); the first upper electrode (105), the piezoelectric layer (104), the first lower electrode (101), and the recessed structure (103) are... The projection portions of the second upper electrode (106), the piezoelectric layer (104), and the second lower electrode (102) on the substrate (100) overlap to form an active region for resonance; the projection portions of the second upper electrode (106), the piezoelectric layer (104), and the second lower electrode (102) on the substrate (100) overlap to form a passive region for capacitance; the first lower electrode (101) and the first upper electrode (105) are respectively led out through a first metal structure (107) to form a resonator; the second lower electrode (102) and the second upper electrode (106) are respectively led out through a second metal structure (108) to form a capacitor; the thickness of the second lower electrode (102) is greater than the thickness of the first lower electrode (101).

10. The heterogeneous integrated filter according to claim 9, characterized in that, The thickness of the piezoelectric layer (104) on the second lower electrode (102) is greater than the thickness of the piezoelectric layer (104) on the first lower electrode (101).

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