Piezoelectric type rapid variable parameter sensor interface integrated circuit

Abstract

The invention discloses a piezoelectric type rapid variable parameter sensor interface integrated circuit, and belongs to the technical field of sensor interfaces. The invention aims to solve the problem that the cut-off frequency of a filter circuit in an existing piezoelectric type rapid parameter sensor interface circuit cannot be adjusted, so that signal distortion is easily caused. Comprising the steps that a voltage signal obtained after a signal output by a piezoelectric type speed change parameter sensor passes through a charge amplifier module or an impedance conversion module is subjected to noise filtering through a high-pass filtering module, a high-pass filtering voltage signal is obtained, power rail conversion is conducted through a first level conversion module, and after passing through a first following buffer module, the high-pass filtering voltage signal is output; inputting to the switched capacitor filter module; the switched capacitor filter module adopts the oscillator module to adjust the cut-off frequency, performs low-pass filtering on an input signal, passes through the rail-to-rail operational amplifier module and the second level conversion module and then is transmitted to the second following buffer module, and the output of the second following buffer module is subjected to amplitude limiting by the amplitude limiting module to obtain an analog output signal. According to the invention, the cut-off frequency of the switched capacitor filter can be adjusted.

Description

Technical Field

[0001] This invention relates to an integrated circuit for a piezoelectric rapidly varying parameter sensor interface, belonging to the field of sensor interface technology. Background Technology

[0002] Piezoelectric rapid-change parameter sensors can be used to detect vibration, shock and noise parameters. They have advantages such as wide bandwidth, high sensitivity, high signal-to-noise ratio, simple structure, reliable operation and light weight, and are widely used in the measurement of vibration parameters.

[0003] Currently, the interface circuits of piezoelectric rapid-change parameter sensors suffer from insufficient noise suppression capabilities, affecting the recognition of weak signals. Simultaneously, nonlinear distortion occurs during signal processing, and improperly designed cutoff frequencies in the filter circuits can lead to the loss or distortion of harmonic components in high-frequency vibration signals. The filter circuits have limited effectiveness in suppressing low-frequency ripple, and high-frequency ripple easily superimposes with the vibration signal, affecting data accuracy. When the sensor output signal amplitude fluctuates with vibration intensity, the interface circuit's load adaptability is insufficient, easily resulting in saturation or cutoff distortion, especially noticeable in the measurement of strong transient signals such as impact signals. Furthermore, existing interface circuits exhibit poor performance stability under extreme environments. At high temperatures, the parameters of components such as operational amplifiers and capacitors drift significantly, leading to changes in circuit gain and noise levels. At low temperatures, the carrier mobility of semiconductor devices decreases, slowing signal response and even causing signal interruption. In vibration and impact environments, the solder joints of discrete components are prone to loosening, leading to poor circuit contact. If the thermal expansion coefficient of the chip packaging material does not match the substrate, internal circuit stress damage can occur, further exacerbating noise and distortion.

[0004] It is evident that the performance of the interface circuit directly impacts the accuracy of data acquisition. Taking aircraft information sampling as an example, piezoelectric vibration sensors can collect thousands of parameters during aircraft flight. The correctness of the acquisition and processing of this data directly affects the normal operation of the aircraft. Therefore, designing a high-performance dedicated interface circuit for piezoelectric vibration sensors is of great significance. Summary of the Invention

[0005] To address the problem that the cutoff frequency of the filter circuit in the existing piezoelectric rapid parameter sensor interface circuit cannot be adjusted, which easily causes signal distortion, this invention provides a piezoelectric rapid parameter sensor interface integrated circuit.

[0006] The present invention provides a piezoelectric rapid-change parameter sensor interface integrated circuit, comprising a charge amplifier module, an impedance transformation module, a high-pass filter module, a first level conversion module, a first follower buffer module, a switched capacitor filter module, an oscillator module, a rail-to-rail operational amplifier module, a second level conversion module, a second follower buffer module, and a limiting module;

[0007] The signal output by the piezoelectric rapid parameter sensor generates a charge signal through the MEMS mechanical structure. The voltage signal after the charge signal passes through the charge amplifier module or impedance transformation module is filtered out for low-frequency noise by the high-pass filter module to obtain a high-pass filtered voltage signal. The high-pass filtered voltage signal is converted to power rail by the first level conversion module, and then input to the switched capacitor filter module after passing through the first follower buffer module.

[0008] The switched capacitor filter module adjusts the cutoff frequency using an oscillator module based on the characteristics of the input signal, performs low-pass filtering on the input signal, and then amplifies the signal through a rail-to-rail operational amplifier module. After amplification, the voltage signal is converted to a power rail by a second level conversion module and then transmitted to a second follower buffer module. The output of the second follower buffer module is limited by a limiting module to obtain an analog output signal.

[0009] According to the piezoelectric rapid-change parameter sensor interface integrated circuit of the present invention, the switched capacitor filter module includes operational amplifiers A1, A2, A3, A4, A5, A6, A7, and A8; switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31, S32, S33, and S4. 34. Switches S35, S36, S37, and S38; Integrating capacitor C1, C2, C3, C4, C5, C6, C7, and C8; Interstage capacitor Ci1, C11, C12, C21, C23, C24, C32, C34, C42, C43, C45, C46, ​​C54, C56, C64, C65, C67, C68, C76, C78, ​​C86, C87, and C88;

[0010] One end of switch S2 is connected to the output of the first follower buffer module. The other end of switch S2 is simultaneously connected to one end of switch S1 and one end of interstage capacitor Ci1. The other end of switch S1 is grounded. The other end of interstage capacitor Ci1 is simultaneously connected to one end of switch S3, one end of switch S4, and one end of interstage capacitor C21. The other end of switch S4 is grounded. The other end of switch S3 is connected to the inverting input of operational amplifier A1, one end of integrating capacitor C1, and one end of switch S6. The other end of switch S6 is connected to one end of switch S5 and one end of interstage capacitor C11. The other end of switch S5 is grounded. The other end of interstage capacitor C11 is connected to one end of switch S7 and the open circuit. One end of switch S8 is connected to the other end of switch S7, which is grounded. The other end of switch S8 is connected to the other end of integrating capacitor C1, the output terminal of operational amplifier A1, and one end of switch S10. The non-inverting input terminal of operational amplifier A1 is grounded. The other end of switch S10 is connected to one end of switch S9 and one end of interstage capacitor C12. The other end of switch S9 is grounded. The other end of interstage capacitor C12 is connected to one end of switch S11, one end of switch S12, and one end of interstage capacitor C32. The other end of switch S11 is grounded. The other end of switch S12 is connected to the inverting input terminal of operational amplifier A2, one end of integrating capacitor C2, and one end of interstage capacitor C42. The other end of integrating capacitor C2 is connected to... Connect the output terminal of op-amp A2, one end of switch S14, and one end of interstage capacitor C24. The non-inverting input terminal of op-amp A2 is grounded. The other end of switch S14 is connected to the other end of interstage capacitor C21, one end of interstage capacitor C23, and one end of switch S13. The other end of switch S13 is grounded. The other end of interstage capacitor C23 is connected to one end of switch S15, one end of switch S16, and one end of interstage capacitor C43. The other end of switch S16 is grounded. The other end of switch S15 is connected to the inverting input terminal of op-amp A3 and one end of integrating capacitor C3. The non-inverting input terminal of op-amp A3 is grounded. The other end of integrating capacitor C3 is connected to the output terminal of op-amp A3 and the non-inverting input terminal of op-amp A2. One end of switch S18 is connected to one end of switch S17, the other end of interstage capacitor C32, and one end of interstage capacitor C34. The other end of switch S17 is grounded. The other end of interstage capacitor C34 is connected to one end of switch S19, one end of switch S20, and one end of interstage capacitor C54. The other end of switch S19 is grounded. The other end of switch S20 is connected to the inverting input terminal of operational amplifier A4, one end of integrating capacitor C4, the other end of interstage capacitor C24, and one end of interstage capacitor C64. The non-inverting input terminal of operational amplifier A4 is grounded. The other end of integrating capacitor C4 is connected to the output terminal of operational amplifier A4 and the other end of interstage capacitor C42.

[0011] The output of operational amplifier A4 is connected to one end of switch S22 and one end of interstage capacitor C46. The other end of switch S22 is connected to one end of switch S21, the other end of interstage capacitor C43, and one end of interstage capacitor C45. The other end of switch S21 is grounded. The other end of interstage capacitor C45 is connected to one end of switch S23, one end of switch S24, and one end of interstage capacitor C65. The other end of switch S24 is grounded. The other end of switch S23 is connected to the inverting input of operational amplifier A5 and one end of integrating capacitor C5. The non-inverting input of operational amplifier A5 is grounded. The other end of integrating capacitor C5 is connected to the output of operational amplifier A5 and one end of switch S26. The other end of switch S26 is connected to switch S25. One end of the interstage capacitor C54 and one end of the interstage capacitor C56 are connected to the other end of switch S25, and the other end of switch S25 is grounded. The other end of the interstage capacitor C56 is connected to one end of switch S27, one end of switch S28, and one end of interstage capacitor C76. The other end of switch S27 is grounded. The other end of switch S28 is connected to the inverting input of op-amp A6, one end of integrating capacitor C6, the other end of interstage capacitor C46, ​​and one end of interstage capacitor C68. The non-inverting input of op-amp A6 is grounded. The other end of integrating capacitor C6 is connected to the other end of interstage capacitor C64, one end of interstage capacitor C86, the output of op-amp A6, and one end of switch S30. The non-inverting input of op-amp A6 is grounded. Switch S30... The other end is connected to the other end of interstage capacitor C65, one end of interstage capacitor C67, and one end of switch S29. The other end of switch S29 is grounded. The other end of interstage capacitor C67 is connected to one end of interstage capacitor C87, one end of switch S31, and one end of switch S32. The other end of switch S32 is grounded. The other end of switch S31 is connected to the inverting input of operational amplifier A7 and one end of integrating capacitor C7. The non-inverting input of operational amplifier A7 is grounded. The other end of integrating capacitor C7 is connected to the output of operational amplifier A7 and one end of switch S34. The non-inverting input of operational amplifier A7 is grounded. The other end of switch S34 is connected to the other end of interstage capacitor C76, one end of switch S33, and interstage capacitor C78. One end of switch S33 is grounded, and the other end of switch S34 is grounded. The other end of interstage capacitor C78 is connected to one end of interstage capacitor C88, one end of switch S35, and one end of switch S36. The other end of switch S35 is grounded. The other end of switch S36 is connected to the other end of interstage capacitor C86, one end of integrating capacitor C8, and the inverting input of op-amp A8. The non-inverting input of op-amp A8 is grounded. The other end of integrating capacitor C8 is connected to the other end of interstage capacitor C68 and serves as the output of the switched capacitor filter module. The other end of integrating capacitor C8 is also connected to the output of op-amp A8 and one end of switch S38. The other end of switch S38 is connected to one end of switch S37, and the other end of switch S37 is grounded.

[0012] According to the piezoelectric rapid-change parameter sensor interface integrated circuit of the present invention, the oscillator module includes operational amplifiers A11, A21, and A31, NOR gates NOR1 and NOR gates NOR2, D flip-flop D1, resistors R1, R2, and R3, capacitors C100 and C200, fuses Fuse1, Fuse2, and Fuse3, PMOS transistors M1, M2, M3, and NMOS transistors M4, and switches S100, S200, S300, and S400.

[0013] The non-inverting input of operational amplifier A11 and the inverting inputs of operational amplifiers A21 and A31 are connected to the reference voltage VREF. The inverting input of operational amplifier A11 is connected to one end of resistor R1 and the source of NMOS transistor M4. The output of operational amplifier A11 is connected to the gate of NMOS transistor M4. The other end of resistor R1 is connected to one end of resistor R2. The other end of resistor R2 is connected to one end of resistor R3. The other end of resistor R3 is connected to the external resistor ROUT. Fuse1 is connected in parallel with resistor R1. fuse2 is connected in parallel with resistor R2, fuse3 is connected in parallel with resistor R3, the drain of NMOS transistor M4 is connected to the drain and gate of PMOS transistor M1, the gate of PMOS transistor M2 and the gate of PMOS transistor M3, the source of PMOS transistor M1, the source of PMOS transistor M2 and the source of PMOS transistor M3 are all connected to the power supply, the drain of PMOS transistor M2 is connected to one end of switch S100, the other end of switch S100 is connected to one end of capacitor C100 and one end of switch S200. The other end of capacitor C100 and the other end of switch S200 are grounded. The drain of PMOS transistor M3 is connected to one end of switch S400. The other end of switch S400 is connected to one end of switch S300, one end of capacitor C200 and the non-inverting input of operational amplifier A21. The other end of switch S300 and the other end of capacitor C200 are grounded. The output of operational amplifier A21 is connected to the first input of NOR gate NOR1. The output of operational amplifier A31 is connected to the first input of NOR gate NOR2. The second input of NOR gate NOR1 is connected to the output of NOR gate NOR2. The second input of NOR gate NOR2 is connected to the output of NOR gate NOR1. The output of NOR gate NOR1 is connected to the clock input of D flip-flop D1. The inverting output of D flip-flop D1 is connected to the input of D flip-flop D1. The output of D flip-flop D1 serves as the clock output of the oscillator module, controlling switches S1 to S38 in the switched capacitor filter module.

[0014] According to the piezoelectric rapid-change parameter sensor interface integrated circuit of the present invention, the clock signal output by the oscillator module generates two inverse clock signals CLK1 and CLK2 through a two-phase non-overlapping clock module, wherein clock signal CLK1 controls odd-numbered switches S1, S3, ..., S37, and clock signal CLK2 controls even-numbered switches S2, S4, ..., S38.

[0015] The piezoelectric rapid-change parameter sensor interface integrated circuit according to the present invention further includes a voltage reference module and an LDO module.

[0016] The voltage reference module provides a low-temperature drift stabilization voltage of 2.5V to the LDO module, switched-capacitor filter module, oscillator module, rail-to-rail op-amp module, and second level conversion module; the LDO module converts the 2.5V voltage to 5V to provide 5V power to the first follower buffer module, switched-capacitor filter module, oscillator module, and rail-to-rail op-amp module.

[0017] According to the piezoelectric rapid-change parameter sensor interface integrated circuit of the present invention, the integrated circuit is powered by a 24V power supply.

[0018] The first level conversion module converts the high-pass filtered voltage signal from the 24V power rail to the 5V power rail; the second level conversion module converts the amplified voltage signal from the 5V power rail to the 24V power rail.

[0019] According to the piezoelectric rapid-change parameter sensor interface integrated circuit of the present invention, the high-pass filter module is used to filter out low-frequency noise within 5Hz.

[0020] According to the piezoelectric rapid-change parameter sensor interface integrated circuit of the present invention, the first follower buffer module is used to isolate the impedance of the preceding and following stages to prevent mutual interference between the preceding and following stages.

[0021] According to the piezoelectric rapid-change parameter sensor interface integrated circuit of the present invention, the second follower buffer module is used to isolate the impedance inside and outside the integrated circuit to prevent mutual interference.

[0022] The beneficial effects of this invention are as follows: The integrated circuit described in this invention overcomes technical bottlenecks such as low-noise detection of micro-vibration signals, low-distortion ripple suppression, and environmental adaptability. It designs a high-precision piezoelectric rapid-change parameter sensor interface, which can be commercialized. It can be used for dynamic real-time micro-vibration monitoring in various fields and has strong low-temperature adaptability.

[0023] The switched-capacitor filter module of this invention has a high degree of integration. The output clock frequency of the oscillator module can be adjusted by regulating external resistors and capacitors, thereby adjusting the cutoff frequency of the switched-capacitor filter and meeting the signal processing needs of various application scenarios. Attached Figure Description

[0024] Figure 1 This is a schematic block diagram of the piezoelectric rapid-change parameter sensor interface integrated circuit described in this invention;

[0025] Figure 2 This is the circuit structure diagram of the switched capacitor filter module;

[0026] Figure 3 This is the circuit diagram of the oscillator module. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Specific Implementation Method 1: Combination Figure 1 As shown, the present invention provides a piezoelectric rapid-change parameter sensor interface integrated circuit, including a charge amplifier module 102, an impedance transformation module 103, a high-pass filter module 104, a first level conversion module 105, a first follower buffer module 106, a switched capacitor filter module 107, an oscillator module 108, a rail-to-rail operational amplifier module 109, a second level conversion module 110, a second follower buffer module 111, and a limiting module 112;

[0029] The signal output by the piezoelectric rapid parameter sensor generates a charge signal through the MEMS mechanical structure. The magnitude of the charge signal reflects the magnitude of the signal to be measured. As needed, the voltage signal after the charge signal passes through the charge amplifier module 102 or the impedance transformation module 103 is filtered out for low-frequency noise by the high-pass filter module 104 to obtain a high-pass filtered voltage signal. The high-pass filtered voltage signal is converted to power rail by the first level conversion module 105, and then input to the switched capacitor filter module 107 after passing through the first follower buffer module 106.

[0030] The switched capacitor filter module 107 adjusts the cutoff frequency using the oscillator module 108 according to the characteristics of the input signal, performs low-pass filtering on the input signal, and then amplifies the signal through the rail-to-rail operational amplifier module 109, and outputs a large swing signal. After amplification, the voltage signal is transmitted to the second follower buffer module 111 after power rail inversion by the second level conversion module 110. The output of the second follower buffer module 111 is limited by the limiting module 112 to obtain the analog output signal.

[0031] The characteristics of the input signal refer to the requirements of the corresponding sensor.

[0032] The integrated circuit described in this embodiment can be integrated into a chip to obtain a miniaturized product.

[0033] Furthermore, combined with Figure 2 As shown, the switched capacitor filter module 107 includes operational amplifiers A1, A2, A3, A4, A5, A6, A7, and A8, and switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31, S32, S33, S34, and S35. Switches S36, S37, and S38; integrating capacitors C1, C2, C3, C4, C5, C6, C7, and C8; interstage capacitors Ci1, C11, C12, C21, C23, C24, C32, C34, C42, C43, C45, C46, ​​C54, C56, C64, C65, C67, C68, C76, C78, ​​C86, C87, and C88;

[0034] One end of switch S2 is connected to the output of the first follower buffer module 106. The other end of switch S2 is simultaneously connected to one end of switch S1 and one end of interstage capacitor Ci1. The other end of switch S1 is grounded. The other end of interstage capacitor Ci1 is simultaneously connected to one end of switch S3, one end of switch S4, and one end of interstage capacitor C21. The other end of switch S4 is grounded. The other end of switch S3 is connected to the inverting input of operational amplifier A1, one end of integrating capacitor C1, and one end of switch S6. The other end of switch S6 is connected to one end of switch S5 and one end of interstage capacitor C11. The other end of switch S5 is grounded. The other end of interstage capacitor C11 is connected to one end of switch S7. One end of switch S8 is connected to the other end of switch S7, and the other end of switch S8 is grounded. The other end of switch S8 is connected to the other end of integrating capacitor C1, the output terminal of operational amplifier A1, and one end of switch S10. The non-inverting input terminal of operational amplifier A1 is grounded. The other end of switch S10 is connected to one end of switch S9 and one end of interstage capacitor C12. The other end of switch S9 is grounded. The other end of interstage capacitor C12 is connected to one end of switch S11, one end of switch S12, and one end of interstage capacitor C32. The other end of switch S11 is grounded. The other end of switch S12 is connected to the inverting input terminal of operational amplifier A2, one end of integrating capacitor C2, and one end of interstage capacitor C42. The other end of integrating capacitor C2... One end of the switch is connected to the output terminal of operational amplifier A2, one end of switch S14, and one end of interstage capacitor C24. The non-inverting input terminal of operational amplifier A2 is grounded. The other end of switch S14 is connected to the other end of interstage capacitor C21, one end of interstage capacitor C23, and one end of switch S13. The other end of switch S13 is grounded. The other end of interstage capacitor C23 is connected to one end of switch S15, one end of switch S16, and one end of interstage capacitor C43. The other end of switch S16 is grounded. The other end of switch S15 is connected to the inverting input terminal of operational amplifier A3 and one end of integrating capacitor C3. The non-inverting input terminal of operational amplifier A3 is grounded. The other end of integrating capacitor C3 is connected to the output terminal of operational amplifier A3 and... One end of switch S18 is connected to one end of switch S17, the other end of interstage capacitor C32, and one end of interstage capacitor C34. The other end of switch S17 is grounded. The other end of interstage capacitor C34 is connected to one end of switch S19, one end of switch S20, and one end of interstage capacitor C54. The other end of switch S19 is grounded. The other end of switch S20 is connected to the inverting input terminal of operational amplifier A4, one end of integrating capacitor C4, the other end of interstage capacitor C24, and one end of interstage capacitor C64. The non-inverting input terminal of operational amplifier A4 is grounded. The other end of integrating capacitor C4 is connected to the output terminal of operational amplifier A4 and the other end of interstage capacitor C42.

[0035] The output of operational amplifier A4 is connected to one end of switch S22 and one end of interstage capacitor C46. The other end of switch S22 is connected to one end of switch S21, the other end of interstage capacitor C43, and one end of interstage capacitor C45. The other end of switch S21 is grounded. The other end of interstage capacitor C45 is connected to one end of switch S23, one end of switch S24, and one end of interstage capacitor C65. The other end of switch S24 is grounded. The other end of switch S23 is connected to the inverting input of operational amplifier A5 and one end of integrating capacitor C5. The non-inverting input of operational amplifier A5 is grounded. The other end of integrating capacitor C5 is connected to the output of operational amplifier A5 and one end of switch S26. The other end of switch S26 is connected to switch S25. One end of the interstage capacitor C54 and one end of the interstage capacitor C56 are connected to the other end of switch S25, and the other end of switch S25 is grounded. The other end of the interstage capacitor C56 is connected to one end of switch S27, one end of switch S28, and one end of interstage capacitor C76. The other end of switch S27 is grounded. The other end of switch S28 is connected to the inverting input of op-amp A6, one end of integrating capacitor C6, the other end of interstage capacitor C46, ​​and one end of interstage capacitor C68. The non-inverting input of op-amp A6 is grounded. The other end of integrating capacitor C6 is connected to the other end of interstage capacitor C64, one end of interstage capacitor C86, the output of op-amp A6, and one end of switch S30. The non-inverting input of op-amp A6 is grounded. Switch S30... The other end is connected to the other end of interstage capacitor C65, one end of interstage capacitor C67, and one end of switch S29. The other end of switch S29 is grounded. The other end of interstage capacitor C67 is connected to one end of interstage capacitor C87, one end of switch S31, and one end of switch S32. The other end of switch S32 is grounded. The other end of switch S31 is connected to the inverting input of operational amplifier A7 and one end of integrating capacitor C7. The non-inverting input of operational amplifier A7 is grounded. The other end of integrating capacitor C7 is connected to the output of operational amplifier A7 and one end of switch S34. The non-inverting input of operational amplifier A7 is grounded. The other end of switch S34 is connected to the other end of interstage capacitor C76, one end of switch S33, and one end of interstage capacitor C78. One end of switch S33 is grounded. The other end of interstage capacitor C78 is connected to one end of interstage capacitor C88, one end of switch S35, and one end of switch S36. The other end of switch S35 is grounded. The other end of switch S36 is connected to the other end of interstage capacitor C86, one end of integrating capacitor C8, and the inverting input of operational amplifier A8. The non-inverting input of operational amplifier A8 is grounded. The other end of integrating capacitor C8 is connected to the other end of interstage capacitor C68 and serves as the output of switched capacitor filter module 107. The other end of integrating capacitor C8 is also connected to the output of operational amplifier A8 and one end of switch S38. The other end of switch S38 is connected to one end of switch S37. The other end of switch S37 is grounded.

[0036] Figure 2In the diagram, Vin represents the input terminal of the switched capacitor filter module 107, and Vout represents the output terminal of the switched capacitor filter module 107. A, B, C, D, and E in the diagram represent the same connection points.

[0037] Combination Figure 3 As shown, the oscillator module 108 includes operational amplifiers A11, A21, and A31, NOR gates NOR1 and NOR gates NOR2, D flip-flop D1, resistors R1, R2, and R3, capacitors C100 and C200, fuses Fuse1, Fuse2, and Fuse3, PMOS transistors M1, M2, M3, and NMOS transistors M4, and switches S100, S200, S300, and S400.

[0038] The non-inverting input of op-amp A11 and the inverting inputs of op-amps A21 and A31 are connected to the reference voltage VREF. The inverting input of op-amp A11 is connected to one end of resistor R1 and the source of NMOS transistor M4. The output of op-amp A11 is connected to the gate of NMOS transistor M4. The other end of resistor R1 is connected to one end of resistor R2. The other end of resistor R2 is connected to one end of resistor R3. The other end of resistor R3 is connected to the external resistor ROUT. Fuse1 is connected in parallel with resistor R1. e2 is connected in parallel with resistor R2, and fuse 3 is connected in parallel with resistor R3. The drain of NMOS transistor M4 is connected to the drain and gate of PMOS transistor M1, the gate of PMOS transistor M2, and the gate of PMOS transistor M3. The sources of PMOS transistors M1, M2, and M3 are all connected to the power supply. The drain of PMOS transistor M2 is connected to one end of switch S100. The other end of switch S100 is connected to one end of capacitor C100, one end of switch S200, and operational amplifier A3. The non-inverting input terminal of 1, the other end of capacitor C100 and the other end of switch S200 are grounded, the drain of PMOS transistor M3 is connected to one end of switch S400, the other end of switch S400 is connected to one end of switch S300, one end of capacitor C200 and the non-inverting input terminal of operational amplifier A21, the other end of switch S300 and the other end of capacitor C200 are grounded; the output terminal of operational amplifier A21 is connected to the first input terminal of NOR gate NOR1, the output terminal of operational amplifier A31 is connected to the first input terminal of NOR gate NOR2, the second input terminal of NOR gate NOR1 is connected to the output terminal of NOR gate NOR2, the second input terminal of NOR gate NOR2 is connected to the output terminal of NOR gate NOR1, the output terminal of NOR gate NOR1 is connected to the clock input terminal of D flip-flop D1, the inverting output terminal of D flip-flop D1 is connected to the input terminal of D flip-flop D1, and the output terminal of D flip-flop D1 serves as the clock output terminal CLKOUT of oscillator module 108 to control switches S1 to S38 in switched capacitor filter module 107.

[0039] In this embodiment, the clock signal output by the oscillator module 108 is used by a two-phase non-overlapping clock module to generate two inverted clock signals CLK1 and CLK2. Clock signal CLK1 controls odd-numbered switches S1, S3, ..., S37, and clock signal CLK2 controls even-numbered switches S2, S4, ..., S38. The two-phase non-overlapping clock module uses logic gate circuits to process the signals.

[0040] An external resistor is connected to the ROUT port of the oscillator module 108. Connecting different resistor values ​​changes the current in the NMOS transistor M4 branch, altering the current replicated by the current mirror and thus changing the oscillator's output clock frequency. This clock frequency is provided to the switched-capacitor filter module 107, thereby changing its cutoff frequency. Depending on the sensor requirements, a large resistor is connected to the ROUT port of the oscillator module 108 when a lower cutoff frequency is needed, and a small resistor is connected when a higher cutoff frequency is required.

[0041] Figure 3 CK and CKN represent two non-overlapping clock signals that control the on / off states of switches S100, S200, S300, and S400 in oscillator module 108. The CKN signal controls switches S100 and S300, and the CK signal controls switches S200 and S400.

[0042] Furthermore, combined with Figure 1 As shown, the integrated circuit also includes a voltage reference module 100 and an LDO module 101, which are used to generate various stable voltages required by the system.

[0043] The voltage reference module 100 provides a low-temperature drift stabilized voltage of 2.5V to the LDO module 101, the switched-capacitor filter module 107, the oscillator module 108, the rail-to-rail operational amplifier module 109, and the second level conversion module 110; the LDO module 101 converts the 2.5V voltage to a 5V voltage to provide a stable 5V power supply to the first follower buffer module 106, the switched-capacitor filter module 107, the oscillator module 108, and the rail-to-rail operational amplifier module 109.

[0044] The integrated circuit is powered by a 24V power supply.

[0045] The first level conversion module 105 converts the high-pass filtered voltage signal from the 24V power rail to the 5V power rail for subsequent filtering processing; the second level conversion module 110 converts the amplified voltage signal from the 5V power rail to the 24V power rail.

[0046] The high-pass filter module 104 is used to filter out low-frequency noise below 5Hz.

[0047] The first follower buffer module 106 is used to isolate the impedance of the preceding and following stages to prevent mutual interference between them.

[0048] The second follower buffer module 111 is used to isolate the internal and external impedances of the integrated circuit to prevent mutual interference.

[0049] The oscillator module 108 can provide different frequency clocks to the switched capacitor filter module 107 by adjusting the external resistors and capacitors, and the limiting module 112 is used to ensure that the output voltage signal does not exceed the expected limit voltage value.

[0050] This invention enables low-noise, high-linearity detection and amplification of impact and vibration signals, and provides adjustable cutoff frequency filtering. The output analog signal is convenient for subsequent processing and utilization.

[0051] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A piezoelectric rapid-change parameter sensor interface integrated circuit, characterized in that, It includes a charge amplifier module (102), an impedance transformation module (103), a high-pass filter module (104), a first level conversion module (105), a first follower buffer module (106), a switched capacitor filter module (107), an oscillator module (108), a rail-to-rail operational amplifier module (109), a second level conversion module (110), a second follower buffer module (111), and a limiting module (112). The signal output by the piezoelectric rapid parameter sensor generates a charge signal through the MEMS mechanical structure. The voltage signal after the charge signal passes through the charge amplifier module (102) or impedance transformation module (103) is filtered out for low-frequency noise by the high-pass filter module (104) to obtain a high-pass filtered voltage signal. The high-pass filtered voltage signal is converted to a power rail by the first level conversion module (105), and then input to the switched capacitor filter module (107) after passing through the first follower buffer module (106). The switched capacitor filter module (107) adjusts the cutoff frequency using the oscillator module (108) according to the characteristics of the input signal, performs low-pass filtering on the input signal, and then performs signal amplification processing through the rail-to-rail operational amplifier module (109). After amplification, the voltage signal is transmitted to the second follower buffer module (111) after power rail inversion conversion by the second level conversion module (110). The output of the second follower buffer module (111) is limited by the limiting module (112) to obtain the analog output signal.

2. The piezoelectric rapid-change parameter sensor interface integrated circuit according to claim 1, characterized in that, The switched capacitor filter module (107) includes operational amplifiers A1, A2, A3, A4, A5, A6, A7, and A8, and switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31, S32, S33, S34, and S35. Switches S36, S37, and S38; integrating capacitors C1, C2, C3, C4, C5, C6, C7, and C8; interstage capacitors Ci1, C11, C12, C21, C23, C24, C32, C34, C42, C43, C45, C46, ​​C54, C56, C64, C65, C67, C68, C76, C78, ​​C86, C87, and C88; One end of switch S2 is connected to the output of the first follower buffer module (106). The other end of switch S2 is simultaneously connected to one end of switch S1 and one end of interstage capacitor Ci1. The other end of switch S1 is grounded. The other end of interstage capacitor Ci1 is simultaneously connected to one end of switch S3, one end of switch S4, and one end of interstage capacitor C21. The other end of switch S4 is grounded. The other end of switch S3 is connected to the inverting input of operational amplifier A1, one end of integrating capacitor C1, and one end of switch S6. The other end of switch S6 is connected to one end of switch S5 and one end of interstage capacitor C11. The other end of switch S5 is grounded. The other end of interstage capacitor C11 is connected to switch S7. One end of switch S8 is connected to one end of switch S7, the other end of switch S7 is grounded, the other end of switch S8 is connected to the other end of integrating capacitor C1, the output terminal of operational amplifier A1, and one end of switch S10. The non-inverting input terminal of operational amplifier A1 is grounded. The other end of switch S10 is connected to one end of switch S9 and one end of interstage capacitor C12. The other end of switch S9 is grounded. The other end of interstage capacitor C12 is connected to one end of switch S11, one end of switch S12, and one end of interstage capacitor C32. The other end of switch S11 is grounded. The other end of switch S12 is connected to the inverting input terminal of operational amplifier A2, one end of integrating capacitor C2, and one end of interstage capacitor C42. The other end of integrating capacitor C2... One end of the switch is connected to the output of operational amplifier A2, one end of switch S14, and one end of interstage capacitor C24. The non-inverting input of operational amplifier A2 is grounded. The other end of switch S14 is connected to the other end of interstage capacitor C21, one end of interstage capacitor C23, and one end of switch S13. The other end of switch S13 is grounded. The other end of interstage capacitor C23 is connected to one end of switch S15, one end of switch S16, and one end of interstage capacitor C43. The other end of switch S16 is grounded. The other end of switch S15 is connected to the inverting input of operational amplifier A3 and one end of integrating capacitor C3. The non-inverting input of operational amplifier A3 is grounded. The other end of integrating capacitor C3 is connected to the output of operational amplifier A3. One end of switch S18 is connected to one end of switch S17, the other end of interstage capacitor C32, and one end of interstage capacitor C34. The other end of switch S17 is grounded. The other end of interstage capacitor C34 is connected to one end of switch S19, one end of switch S20, and one end of interstage capacitor C54. The other end of switch S19 is grounded. The other end of switch S20 is connected to the inverting input terminal of operational amplifier A4, one end of integrating capacitor C4, the other end of interstage capacitor C24, and one end of interstage capacitor C64. The non-inverting input terminal of operational amplifier A4 is grounded. The other end of integrating capacitor C4 is connected to the output terminal of operational amplifier A4 and the other end of interstage capacitor C42. The output terminal of operational amplifier A4 is connected to one end of switch S22 and one end of interstage capacitor C46. The other end of switch S22 is connected to one end of switch S21, the other end of interstage capacitor C43, and one end of interstage capacitor C45. The other end of switch S21 is grounded. The other end of interstage capacitor C45 is connected to one end of switch S23, one end of switch S24, and one end of interstage capacitor C65. The other end of switch S24 is grounded. The other end of switch S23 is connected to the inverting input terminal of operational amplifier A5 and one end of integrating capacitor C5. The non-inverting input terminal of operational amplifier A5 is grounded. The other end of integrating capacitor C5 is connected to the output terminal of operational amplifier A5 and one end of switch S26. The other end of switch S26 is connected to one end of switch S25. One end of the interstage capacitor C54 and one end of the interstage capacitor C56 are connected to the other end of switch S25, which is grounded. The other end of the interstage capacitor C56 is connected to one end of switch S27, one end of switch S28, and one end of interstage capacitor C76. The other end of switch S27 is grounded. The other end of switch S28 is connected to the inverting input of op-amp A6, one end of integrating capacitor C6, the other end of interstage capacitor C46, ​​and one end of interstage capacitor C68. The non-inverting input of op-amp A6 is grounded. The other end of integrating capacitor C6 is connected to the other end of interstage capacitor C64, one end of interstage capacitor C86, the output of op-amp A6, and one end of switch S30. The non-inverting input of op-amp A6 is grounded. The other end of switch S30 is connected to the other end of the interstage capacitor C54 and one end of interstage capacitor C56. One end of the switch is connected to the other end of interstage capacitor C65, one end of interstage capacitor C67, and one end of switch S29. The other end of switch S29 is grounded. The other end of interstage capacitor C67 is connected to one end of interstage capacitor C87, one end of switch S31, and one end of switch S32. The other end of switch S32 is grounded. The other end of switch S31 is connected to the inverting input of operational amplifier A7 and one end of integrating capacitor C7. The non-inverting input of operational amplifier A7 is grounded. The other end of integrating capacitor C7 is connected to the output of operational amplifier A7 and one end of switch S34. The non-inverting input of operational amplifier A7 is grounded. The other end of switch S34 is connected to the other end of interstage capacitor C76, one end of switch S33, and one end of interstage capacitor C78. The other end of switch S33 is grounded. The other end of interstage capacitor C78 is connected to one end of interstage capacitor C88, one end of switch S35 and one end of switch S36. The other end of switch S35 is grounded. The other end of switch S36 is connected to the other end of interstage capacitor C86, one end of integrating capacitor C8 and the inverting input of op-amp A8. The non-inverting input of op-amp A8 is grounded. The other end of integrating capacitor C8 is connected to the other end of interstage capacitor C68 and serves as the output of switched capacitor filter module (107). The other end of integrating capacitor C8 is also connected to the output of op-amp A8 and one end of switch S38. The other end of switch S38 is connected to one end of switch S37. The other end of switch S37 is grounded.

3. The piezoelectric rapid-change parameter sensor interface integrated circuit according to claim 2, characterized in that, The oscillator module (108) includes operational amplifiers A11, A21, and A31, NOR gates NOR1 and NOR gates NOR2, D flip-flop D1, resistors R1, R2, and R3, capacitors C100 and C200, fuses Fuse1, Fuse2, and Fuse3, PMOS transistors M1, M2, M3, and NMOS transistors M4, and switches S100, S200, S300, and S400. The non-inverting input of op-amp A11 and the inverting inputs of op-amps A21 and A31 are connected to the reference voltage VREF. The inverting input of op-amp A11 is connected to one end of resistor R1 and the source of NMOS transistor M4. The output of op-amp A11 is connected to the gate of NMOS transistor M4. The other end of resistor R1 is connected to one end of resistor R2. The other end of resistor R2 is connected to one end of resistor R3. The other end of resistor R3 is connected to the external resistor ROUT. Fuse1 is connected in parallel with resistor R1. e2 is connected in parallel with resistor R2, fuse 3 is connected in parallel with resistor R3, the drain of NMOS transistor M4 is connected to the drain and gate of PMOS transistor M1, the gate of PMOS transistor M2 and the gate of PMOS transistor M3, the source of PMOS transistor M1, the source of PMOS transistor M2 and the source of PMOS transistor M3 are all connected to the power supply, the drain of PMOS transistor M2 is connected to one end of switch S100, the other end of switch S100 is connected to one end of capacitor C100, one end of switch S200 and operational amplifier A. The non-inverting input terminal of 31, the other end of capacitor C100 and the other end of switch S200 are grounded, the drain of PMOS transistor M3 is connected to one end of switch S400, the other end of switch S400 is connected to one end of switch S300, one end of capacitor C200 and the non-inverting input terminal of operational amplifier A21, the other end of switch S300 and the other end of capacitor C200 are grounded; the output terminal of operational amplifier A21 is connected to the first input terminal of NOR gate NOR1, the output terminal of operational amplifier A31 is connected to the first input terminal of NOR gate NOR2, the second input terminal of NOR gate NOR1 is connected to the output terminal of NOR gate NOR2, the second input terminal of NOR gate NOR2 is connected to the output terminal of NOR gate NOR1, the output terminal of NOR gate NOR1 is connected to the clock input terminal of D flip-flop D1, the inverting output terminal of D flip-flop D1 is connected to the input terminal of D flip-flop D1, and the output terminal of D flip-flop D1 is used as the clock output terminal of oscillator module (108) to control switches S1 to S38 in switched capacitor filter module (107).

4. The piezoelectric rapid-change parameter sensor interface integrated circuit according to claim 3, characterized in that, The clock signal output by the oscillator module (108) generates two inverse clock signals CLK1 and CLK2 through the two-phase non-overlapping clock module. The clock signal CLK1 controls the odd-numbered switches S1, S3, ..., S37, and the clock signal CLK2 controls the even-numbered switches S2, S4, ..., S38.

5. The piezoelectric rapid-change parameter sensor interface integrated circuit according to claim 4, characterized in that, It also includes a voltage reference module (100) and an LDO module (101). The voltage reference module (100) provides a low-temperature drift stabilization voltage of 2.5V to the LDO module (101), the switched capacitor filter module (107), the oscillator module (108), the rail-to-rail op-amp module (109), and the second level conversion module (110); the LDO module (101) converts the 2.5V voltage to a 5V voltage to provide a 5V power supply to the first follower buffer module (106), the switched capacitor filter module (107), the oscillator module (108), and the rail-to-rail op-amp module (109).

6. The piezoelectric rapid-change parameter sensor interface integrated circuit according to claim 5, characterized in that, The integrated circuit is powered by a 24V power supply. The first level conversion module (105) converts the high-pass filtered voltage signal from the 24V power rail to the 5V power rail; The second level conversion module (110) converts the amplified voltage signal from the 5V power rail to the 24V power rail.

7. The piezoelectric rapid-change parameter sensor interface integrated circuit according to claim 1, characterized in that, The high-pass filter module (104) is used to filter out low-frequency noise within 5Hz.

8. The piezoelectric rapid-change parameter sensor interface integrated circuit according to claim 1, characterized in that, The first follower buffer module (106) is used to isolate the impedance of the preceding and following stages to prevent mutual interference between them.

9. The piezoelectric rapid-change parameter sensor interface integrated circuit according to claim 1, characterized in that, The second follower buffer module (111) is used to isolate the impedances inside and outside the integrated circuit to prevent mutual interference.

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