Indirect jump target address prediction system and method

Abstract

The invention provides an indirect jump target address prediction system and method, and relates to the technical field of processor branch prediction. The system comprises an intermediate address index table which comprises a plurality of address index table entries, and each address index table entry comprises a plurality of intermediate index addresses; when an indirect jump branch instruction is received, accessing the intermediate address index table and matching address index table entries by using the PC; the folding module is used for folding the branch jump historical information in the historical register; the multiplexer is used for selecting a middle index address from the matched address index table items according to the folding result; and the target address buffer area is used for identifying the type of the branch according to the intermediate index address of the selected indirect jump branch and generating a corresponding prediction address. Secondary prediction is carried out on the indirect jump branch, so that the accuracy of indirect jump prediction is improved; the use efficiency of the target address buffer is improved by multiplexing the indirect jump and direct jump target address buffers.

Description

Technical Field

[0001] This application relates to the technical field of processor branch prediction, and in particular to an indirect jump target address prediction system and method. Background Technology

[0002] Branch address prediction is divided into direct jump branch prediction and indirect jump branch prediction. Direct jump branches account for a large proportion, with a fixed target address, and prediction is performed using the branch's PC (Program Counter). Unlike direct jump branches, indirect jump branches, although less common, have flexible and varied target addresses, making prediction more difficult. Mainstream high-performance processors allocate independent target address buffers, independent historical information, and independent prediction algorithms (e.g., ittage) for indirect jump branches. Indexing the indirect target address buffer requires a hash of the branch PC and path history register (PRH). The same PC combined with different path history information can index and predict different branch addresses. The above process is as follows: Figure 1 As shown, direction prediction, indirect jump branch address, and direct jump branch address all use independent prediction resources.

[0003] Currently, there are two main types of designs for predicting the target address of indirect branch instructions: 1. For indirect jump branch instructions, a separate target address buffer is used, so that indirect jump branch instructions and direct jump branch instructions use their own independent target address buffers. This results in low resource utilization.

[0004] 2. Some designs use a shared target address buffer for both indirect and direct jump branches. The address buffer is indexed uniformly using the program counter (PC). These designs fail to consider the characteristics of indirect jump branches (addresses change dynamically, meaning an indirect jump branch might jump to different addresses). Accuracy cannot meet performance requirements.

[0005] In summary, current designs for predicting the target address of indirect branch instructions cannot simultaneously achieve high accuracy and efficient use of the target address buffer. Summary of the Invention

[0006] Based on this, it is necessary to provide an indirect jump target address prediction system and system to address the above-mentioned technical problems. By adopting a two-stage prediction for indirect jump branches, the first stage uses the instruction pc to access the intermediate address index table, and then selects the intermediate address index address based on the folded content as the index address of the final target address buffer, thereby improving the accuracy of indirect jump prediction; by reusing the target address buffers of indirect jump and direct jump, the utilization efficiency of the target address buffer is improved.

[0007] In a first aspect, this application provides an indirect jump target address prediction system, comprising: The intermediate address index table contains multiple address index entries, and each address index entry contains multiple intermediate index addresses. When an indirect jump branch instruction is received, the PC is used to access the intermediate address index table and match the address index entries. The folding module is used to fold the historical information of branch jumps in the history register; A multiplexer is used to select an intermediate index address from the matching address index entries based on the folding result; The target address buffer is used to identify the type of the branch and generate the corresponding predicted address based on the intermediate index address of the selected indirect jump branch.

[0008] In one embodiment, each address index entry includes: The Tag field is used to match address index entries and determine whether the current address index entry has been hit. There are n intermediate index addresses, containing set information and index information of the branch target address buffer; where 4≤n≤8, and n is an integer.

[0009] In one embodiment, the target address buffer is also used to receive the index address of the direct jump branch, identify the type of the branch based on the index address of the direct jump branch, and generate the corresponding predicted address.

[0010] In one embodiment, the target address buffer is designed in blocks, with each block implemented using independent SRAM.

[0011] In one embodiment, the number of blocks is 2a, where a is a positive integer.

[0012] In one embodiment, the data structure of each address buffer entry in the target address buffer includes an identifier bit and a predicted address of a direct jump branch or an identifier bit and a predicted address of an indirect jump branch; wherein, the identifier bit is used to identify the type of branch predicted for the address buffer entry of the current index; the predicted address of a direct jump branch includes a Tag field and an offset portion of the direct jump address; the predicted address of an indirect jump branch includes the complete predicted address.

[0013] Secondly, this application provides a method for predicting indirect jump target addresses, including: Upon receiving an indirect jump branch instruction, the PC is used to access the intermediate address index table and match the address index table entries. Fold the branch jump history information in the history register; Select the intermediate index address from the matching address index entries based on the folding result; The type of branch is identified based on the intermediate index address of the selected indirect jump branch, and the corresponding predicted address is generated.

[0014] In one embodiment, matching address index entries includes: using the Tag field to determine whether the current indirect jump branch address index entry has been hit; if it has, then the current address index entry is a matching address index entry.

[0015] In one embodiment, selecting an intermediate index address from the matching address index entries based on the folding result includes: Divide the range of numbers corresponding to the length of the folded historical information into n equal segments, with each intermediate index address corresponding to a segment of the range of numbers. The intermediate index value corresponding to the range of numbers containing the length of the original historical information is used as the selected intermediate index address.

[0016] This application employs the aforementioned indirect jump target address prediction system and method, which has the following beneficial effects: 1. By using two-stage prediction for indirect jump branches, the first stage uses the instruction pc to access the intermediate address index table, and then selects the intermediate address index based on the folded content, which is used as the index address of the final target address buffer, thereby improving the accuracy of indirect jump prediction. 2. Improve the efficiency of the target address buffer by reusing the target address buffers for indirect and direct jumps. Attached Figure Description

[0017] Figure 1 This is a system architecture diagram of a traditional predictive indirect jump in one embodiment; Figure 2 This is a structural diagram of the indirect jump target address prediction system of this application in one embodiment; Figure 3 This is a schematic diagram of an intermediate address index table in one embodiment; Figure 4 Here is a structural diagram of the target address buffer in one embodiment; Figure 5 This is a schematic diagram of the data structure of an address buffer item in one embodiment; Figure 6This is a schematic diagram illustrating the workflow of the indirect jump target address prediction system of this application in one embodiment; Figure 7 This is a diagram illustrating an example of indirect branching in one embodiment; Figure 8 This is an example diagram of the current predicted address of jalr in one embodiment. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] The indirect jump target address prediction system of this application aims to solve the problem that existing indirect jump target address prediction technologies cannot simultaneously achieve high accuracy and efficient use of the target address buffer. Its core architecture, as shown in Figure 2, mainly includes an intermediate address index table, a folding module, a multiplexer, and an integrated branch target address buffer (i.e., the "target address buffer" as described in the claims). This system achieves a dual improvement in prediction accuracy and resource utilization by reusing the target address buffer resources of both direct and indirect jumps and employing a two-level prediction mechanism for indirect jumps.

[0020] Among them, the GHR (Global History Register) and the direction predictor are general modules in the processor branch prediction system. This application directly reuses such existing modules without additional design. The technical solution can be implemented simply by adding an intermediate address index table and optimizing the structure of the traditional branch target address buffer.

[0021] The intermediate address index table contains multiple address index entries, and each address index entry contains multiple intermediate index addresses. When an indirect jump branch instruction is received, the PC is used to access the intermediate address index table and match the address index entries.

[0022] The intermediate address index table is one of the core modules for implementing two-level prediction of indirect jumps in this system. In this embodiment, it adopts a 4-way, 64-set design. In practical applications, the number of paths and group numbers can be adjusted according to processor performance requirements. It is used to store multiple intermediate index addresses corresponding to indirect jump branches, and its structure is as follows: Figure 3 As shown, a multi-way set-associative storage structure is used to store multiple intermediate index addresses corresponding to indirect jump branches.

[0023] In one embodiment, such as Figure 3 As shown, each address index entry includes: 1. The Tag field is used to match address index entries and determine whether the current address index entry has been hit. Specifically, the high 16 bits of the indirect jump branch instruction PC (Program Counter) (which can be adjusted according to the address width requirements) are used as the Tag value to match during access and determine whether the current indirect jump branch has a corresponding valid entry in the intermediate address index table (i.e., "hit").

[0024] 2. There are n intermediate index addresses, each containing set and index information of the integrated branch target address buffer, used for subsequent indexing of target addresses; where 4 ≤ n ≤ 8, and n is an integer, in this embodiment n = 4. This design can support the storage and prediction of multiple potential jump target addresses corresponding to one indirect jump branch, adapting to the dynamic changes in indirect jump addresses.

[0025] When the processor receives an indirect branch instruction (such as the jalr instruction in the RISC-V architecture), it first extracts the PC value of the instruction, accesses the intermediate address index table through the PC value, and compares it with the Tag field in the table entry. If the comparison matches, it is determined as a "hit", and the four intermediate index addresses in the table entry are output; if it does not hit, it enters the prediction failure handling process (such as using the default index or pausing prediction and waiting for the actual jump address to update the table entry).

[0026] The folding module is used to fold the historical information of branch jumps in the history register.

[0027] In this embodiment, the GHR length is 100 bits, which can cover enough historical path information to ensure the predictive relevance. Since the original GHR length is relatively long, it cannot be directly used for selecting n intermediate indices; therefore, folding and compression are required. This embodiment uses a "bitwise XOR folding" method to compress the 100-bit GHR into 10 bits. Specifically, the 100-bit GHR is divided into 10 groups of 10 bits each, and the corresponding bits in each group are XORed to obtain the final 10-bit folded result, which has a value range of 0-1023.

[0028] A multiplexer is used to select an intermediate index address from the matching address index entries based on the folding result.

[0029] The multiplexer receives the 10-bit folding result output by the folding module and selects one of the n intermediate index addresses output from the intermediate address index table as the final index address based on the result, thus realizing the mapping of "historical path - intermediate index".

[0030] In this embodiment, n=4, so the numerical range of the folded result (0-1023) is divided into 4 segments, each segment corresponding to one intermediate index address: when ghr<300 after folding, intermediate index 1 is selected; when 300≤ghr<600 after folding, intermediate index 2 is selected; when 600≤ghr<900 after folding, intermediate index 3 is selected; when 900≤ghr after folding, intermediate index 4 is selected.

[0031] If n=8 in a practical application, the folded result range is divided into 8 equal parts, with each segment corresponding to one intermediate index address. This ensures that the corresponding intermediate index can be selected under different historical paths, improving the predictive accuracy. It is worth noting that the length of the ghr, and the length after folding, are not fixed and depend on the actual design.

[0032] Target address buffer (i.e.) Figure 1 The integrated branch target address buffer is used to identify the type of the branch and generate the corresponding predicted address based on the intermediate index address of the selected indirect jump branch.

[0033] In the initial prediction phase, it's impossible to determine whether the branch instruction is an indirect or direct jump branch, nor is the address corresponding to an indirect jump branch known. Parallel access to the branch target address buffer and intermediate address index table is required. If the branch is found to be an indirect jump branch, then the branch target address needs to be accessed twice. These accesses may occur within the same cycle or in different clock cycles. Regardless, with pipelined implementation, the branch target address will be accessed twice at a specific time (these two simultaneous accesses may be for different branches). If these two accesses correspond to the same SRAM, it violates the SRAM single-port read requirement, necessitating the pause of one read request. To mitigate this scenario, we divided the target address buffer into multiple banks.

[0034] like Figure 4 and Figure 5 As shown, the target address buffer is a shared target address storage module for both direct and indirect jumps. Through structural optimization, it achieves resource reuse for both types of jumps and solves the read conflict problem of single-port SRAM. The buffer adopts a bank design, which in this embodiment is divided into 4 banks (bank0, bank1, bank2, and bank3). Each bank is implemented using independent SRAM and supports parallel access.

[0035] Specifically, such as Figure 1 and Figure 6As shown, in actual processing, the PC accesses the integrated branch target address buffer and the intermediate address index table in parallel, and performs tag matching based on the address in the branch target address buffer. If the tag matches, it determines whether the flag bit is an indirect jump branch; if the tag does not match, the address buffer is lost. When the flag bit is an indirect jump branch, the intermediate index is used to access the integrated target address buffer, and the complete predicted address is used as the predicted address of the indirect jump branch; when the flag bit is not an indirect jump branch, the direct jump address offset that matches the target address buffer is used.

[0036] Because intermediate address indexing is fast, or with pipelining techniques (e.g., the second branch is undergoing its first access while the first branch is undergoing its second access), theoretically, concurrent access to the branch target address buffer and intermediate address index table, as well as using the complete predicted address as the predicted address for indirect jump branches, could theoretically occur simultaneously in implementation. Therefore, for the target address buffer, two read requests might occur at the same time. Since the target address buffer is implemented using SRAM, which can only handle one read request at a time, four SRAMs are combined into one buffer to resolve this conflict.

[0037] This design allows address lookups for direct and indirect jumps to be executed in parallel, avoiding the conflict that a single-port SRAM can only process one index request at a time, thus ensuring prediction efficiency.

[0038] In actual processing, the number of banks can be 2a, and the corresponding number of SRAMs is 2a, where a is a positive integer.

[0039] In one embodiment, such as Figure 5 As shown, the data structure of each address buffer entry in the target address buffer includes an identifier bit and the predicted address of the direct jump branch, or the data structure of each address buffer entry in the target address buffer includes an identifier bit and the predicted address of the indirect jump branch. The identifier bit is used to identify the type of branch predicted for the address buffer entry of the current index; the predicted address of the direct jump branch includes a Tag field and an offset portion of the direct jump address; the predicted address of the indirect jump branch includes the complete predicted address.

[0040] For example, bank0 is used to store the target address of the indirect jump branch and receives the intermediate index address output by the multiplexer; bank1 is used to store the target address of the direct jump branch and receives the address directly indexed by the PC (consistent with the indexing method of traditional direct jump prediction).

[0041] Specifically, the identifier bit is used to distinguish whether the current entry stores a direct jump address or an indirect jump address; the direct jump prediction address includes a Tag field and an offset part, and the final jump address is calculated by "PC base address + offset", which is suitable for the fixed nature of direct jump addresses; the indirect jump prediction address stores the complete target address (without offset calculation), because the range of indirect jump addresses is wider and not fixed, and the Tag comparison has already been completed in the intermediate address index table, so there is no need to store the Tag field again here, saving storage resources.

[0042] This application also provides a method for predicting indirect jump target addresses, including: S100, upon receiving an indirect jump branch instruction, uses the PC to access the intermediate address index table and match the address index table entries.

[0043] During instruction execution, the processor identifies whether the current branch instruction is a direct jump or an indirect jump. For direct jump branches, the PC value is used to index and integrate the branch target address buffer's bank1. After confirming the type by the identifier bit, the predicted address is calculated by combining the Tag field and the offset. For indirect jump branches, the subsequent two-level prediction process is initiated.

[0044] In this application, the PC value of the indirect jump branch instruction is extracted, and the 64-set, 4-way storage structure of the intermediate address index table is accessed using the PC. The Tag field is compared with the Tag in the table entry. If the comparison matches (hit), the four intermediate index addresses in the table entry are output; if not, the default intermediate index (such as intermediate index 1) is used or the table entry is updated after the actual jump address is updated before prediction.

[0045] S200 folds the branch jump history information in the history register.

[0046] In this application, the 100-bit GHR is folded by bitwise XOR and compressed into a 10-bit folded result, which reflects the path characteristics of recent branch jumps.

[0047] S300: Select the intermediate index address from the matching address index entries based on the folding result.

[0048] Specifically, the multiplexer segments the 10-bit folding result into numerical segments and selects one of the four intermediate index addresses as the index address for the integrated branch target address buffer.

[0049] S400 identifies the type of branch based on the intermediate index address of the selected indirect jump branch and generates the corresponding predicted address.

[0050] The selected intermediate index address is input into bank0 of the integrated branch target address buffer. After confirming that the current entry is of the indirect jump type by the identifier bit, the stored complete target address is directly read as the predicted address of the indirect jump branch and output to complete the prediction process.

[0051] After the processor executes the indirect jump branch instruction, it obtains the actual jump address and compares it with the predicted address. If the prediction is correct, the entries in the intermediate address index table and the integrated branch target address buffer remain unchanged; if the prediction is incorrect, the actual jump address is updated in the corresponding entry (e.g., updating the indirect jump prediction address corresponding to the intermediate index address, or adding a new intermediate address index entry) to optimize the accuracy of subsequent predictions.

[0052] In one embodiment, matching address index entries includes: using the Tag field to determine whether the current indirect jump branch address index entry has been hit; if it has, then the current address index entry is a matching address index entry.

[0053] In one embodiment, selecting an intermediate index address from the matching address index entries based on the folding result includes: dividing the range of numbers corresponding to the length of the folded historical information into n equal segments, with each intermediate index address corresponding to a segment of the range of numbers; and using the intermediate index value corresponding to the range of numbers where the original historical information length is located as the selected intermediate index address.

[0054] like Figure 7 and Figure 8 As shown, taking an indirect jump branch (jalr instruction) that frequently jumps to four different target addresses (tar0, tar1, tar2, tar3) as an example, the prediction effect of this application is verified: Initially, the intermediate address index table stores the entry corresponding to the PC of the jalr instruction, containing four intermediate index addresses, corresponding to the storage locations of tar0, tar1, tar2, and tar3 in the integration branch target address buffer bank0, respectively. When the ghr folding result is 100, intermediate index 1 is selected to retrieve the address of tar0; when the ghr folding result is 300, intermediate index 2 is selected to retrieve the address of tar1; when the ghr folding result is 600, intermediate index 3 is selected to retrieve the address of tar2; and when the ghr folding result is 900, intermediate index 4 is selected to retrieve the address of tar3.

[0055] Jalr is an indirect jump instruction in the RISCV instruction set. This application uses Jalr as an example, but in practice, it is not limited to RISCV.

[0056] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0057] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An indirect jump target address prediction system, characterized in that, include: The intermediate address index table contains multiple address index entries, and each address index entry contains multiple intermediate index addresses. When an indirect jump branch instruction is received, the PC is used to access the intermediate address index table and match the address index table entries. The folding module is used to fold the historical information of branch jumps in the history register; A multiplexer is used to select an intermediate index address from the matching address index entries based on the folding result; The target address buffer is used to identify the type of the branch and generate the corresponding predicted address based on the intermediate index address of the selected indirect jump branch.

2. The system according to claim 1, characterized in that, Each address index entry includes: The Tag field is used to match address index entries and determine whether the current address index entry has been hit. There are n intermediate index addresses, containing set information and index information of the branch target address buffer; where 4≤n≤8, and n is an integer.

3. The system according to claim 1, characterized in that, The target address buffer is also used to receive the index address of the direct jump branch, identify the type of the branch based on the index address of the direct jump branch, and generate the corresponding predicted address.

4. The system according to claim 1 or 3, characterized in that, The target address buffer adopts a block design, with each block implemented using independent SRAM.

5. The system according to claim 4, characterized in that, The number of blocks is 2a, where a is a positive integer.

6. The system according to claim 1 or 3, characterized in that, The data structure of each address buffer entry in the target address buffer includes an identifier bit and the predicted address of the direct jump branch or an identifier bit and the predicted address of the indirect jump branch; wherein, the identifier bit is used to identify the type of branch predicted for the address buffer entry of the current index; the predicted address of the direct jump branch includes a Tag field and the offset part of the direct jump address; the predicted address of the indirect jump branch includes the complete predicted address.

7. A method for predicting an indirect jump target address, characterized in that, include: When an indirect jump branch instruction is received, the PC is used to access the intermediate address index table and match the address index table entries. Fold the branch jump history information in the history register; Select the intermediate index address from the matching address index entries based on the folding result; The type of branch is identified based on the intermediate index address of the selected indirect jump branch, and the corresponding predicted address is generated.

8. The method according to claim 7, characterized in that, Matching address index entries includes: using the Tag field to determine whether the current indirect jump branch address index entry has been hit; if it has, then the current address index entry is the matching address index entry.

9. The method according to claim 7, characterized in that, Based on the folding result, select the intermediate index address from the matching address index table entries, including: Divide the range of numbers corresponding to the length of the folded historical information into n equal segments, with each intermediate index address corresponding to a segment of the range of numbers. The intermediate index value corresponding to the range of numbers containing the length of the original historical information is used as the selected intermediate index address.

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