Image sensor with dynamic low-power-consumption counter architecture

Abstract

The invention discloses an image sensor with a dynamic low-power-consumption counter architecture, which relates to the field of image sensors and comprises a phase-locked loop module, a row selection module, a pixel array and a column ADC (Analog to Digital Converter), according to the column ADC, an ADC clock generation module processes an input first clock signal and then outputs a second clock signal and a third clock signal acting in an Rs interval and an Ss interval; the ramp signal generation module outputs a ramp reference signal according to the third clock signal; the comparator array module compares the pixel signal with the slope reference signal to obtain a comparator output signal; the state judgment module outputs a first state switching signal and a second state switching signal according to the comparator output signal, and the first state switching signal controls the counter and the latch operation array module. According to the image sensor, redundant power consumption generated by intervals except effective reading actions in the pixel reading process by the column ADC can be dynamically reduced and greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and more specifically to an image sensor with a dynamic low-power counter architecture. Background Technology

[0002] With the advent of the Internet of Things (IoT) era, the application scope of image sensors (CMOS Image Sensors) is becoming increasingly widespread, giving rise to many new application scenarios. Monitoring moving objects and low power consumption are two important research directions. Unlike traditional applications, the emerging fields of IoT and smart security in recent years rely more on battery power. Therefore, the power consumption of the sensor used largely determines the standby time and user experience of the device. In recent years, the pixel count of image sensors has risen to tens of millions or even hundreds of millions, and power consumption has increased exponentially with the increase in pixel count. How to reduce the dynamic power consumption of image sensors remains a major technical challenge. Summary of the Invention

[0003] The purpose of this invention is to provide an image sensor with a dynamic low-power counter architecture, which effectively reduces redundant power consumption of the image sensor outside of the effective operating range.

[0004] This invention is achieved through the following technical solution:

[0005] This invention provides an image sensor with a dynamic low-power counter architecture, comprising: a phase-locked loop module, a row selection module, a pixel array, a column ADC, and a timing control module. The phase-locked loop module is used to provide corresponding clock signals to each module after multiplying the clock signal provided by the external crystal oscillator. The row selection module is used to select a certain row of pixels and output a pixel control signal to the pixel array; The pixel array is used to acquire the light signal of the subject being photographed according to the pixel control signal, and then output the light signal to the column ADC after converting the light signal into a pixel signal. The column ADC includes: an ADC clock generation module, a ramp signal generation module, a comparator array module, and a state judgment module. The ADC clock generation module is used to process the input first clock signal and output a second clock signal and a third clock signal that operate in the Rs interval and Ss interval. The second clock signal is a counting reference clock signal provided by the counter and latch operation module, and the third clock signal is a ramp reference clock signal provided by the ramp signal generation module. The ramp signal generation module is used to output a ramp reference signal according to the third clock signal and input the ramp reference signal to the comparator array module; The comparator array module is used to compare the pixel signal and the ramp reference signal to obtain the comparator output signal; The state judgment module is used to output a first state switching signal and a second state switching signal according to the comparator output signal. The first state switching signal is used to control the counter and latch operation array module, and the second state switching signal is used to control the ADC clock generation module, the ramp signal generation module and the comparator array module. The timing control module provides timing control signals for the normal operation of the image sensor.

[0006] Furthermore, the column ADC also includes: a counter and latch operation array module, which adopts a structure of multiple columns sharing a counter unit, including a counter unit and a latch operation unit, wherein the count output of one counter unit is simultaneously supplied to multiple columns of latch operation units; The counter unit counts along with the second clock signal when comparing the pixel signal and the ramp reference signal. When the magnitude relationship between the pixel signal and the ramp reference signal is reversed, the comparator output signal flips, triggering the latch operation unit to latch the count value of the comparator output signal flip time. The counter obtains the real-time count value by counting the time length. The latching operation unit is connected to the comparator array module. When the output signal of a certain comparator flips in the Rs and Ss intervals, the latching operation unit latches the real-time count value input by the counter unit at the current time point.

[0007] Furthermore, the state determination module includes multiple first-level state determination units and a second-level state determination circuit. The first-level state determination units are used to output a first state switching signal to the second-level state determination circuit and the counter unit circuit according to the input enable signal and the comparator output signal. The second-stage state judgment circuit outputs a second state switching signal based on the input enable signal and the first state switching signal.

[0008] Furthermore, the first-level state judgment unit is composed of multiple OR gates connected in series. The number of OR gates is the same as the number of columns shared by each counter unit. One input of each OR gate is connected to the comparator output signal of the corresponding column, the other input of the first OR gate is connected to the enable signal, the output of the first OR gate is used as the input of the next OR gate, and the output of the last OR gate is used as the first state switching signal.

[0009] Furthermore, the second-level state judgment circuit is composed of multiple OR gates connected in series. The number of OR gates is the same as the number of corresponding counter units. One input terminal of each OR gate is connected to the first state switching signal, the other input terminal of the first OR gate is connected to the enable signal, the output terminal of the first OR gate serves as the input terminal of the next OR gate, and the output result of the last OR gate serves as the second state switching signal.

[0010] Furthermore, when the input enable signal is high, the state judgment module is in a closed or reset state. The first segment OR gate input of each unit of the first-level state judgment unit and one end of the first segment OR gate input of the second-level state judgment circuit are set to high level. The first state switching signal output by the first-level state judgment circuit and the second state switching signal output by the second-level state judgment circuit are both high level. In this state, the power consumption of the ADC remains normal.

[0011] Furthermore, when the input enable signal is low, the state judgment module is active. When all comparator output signals are high, each OR gate in the first state judgment unit outputs a high-level first state switching signal because of the high-level input. The first state switching signal is input to the second-stage state judgment circuit. Since each OR gate in the second-stage state judgment circuit outputs a high-level second state switching signal, the second-stage state judgment circuit outputs a high-level second state switching signal. In this state, the power consumption of the ADC remains normal.

[0012] Furthermore, when the input enable signal is low, the state judgment module is active. The comparator output signal is set from high to low, and not all comparator output signals corresponding to each first-stage state judgment unit are set to low. Since some OR gates in each unit of the first-stage state judgment unit have high inputs, the first state switching signals output by each first state judgment unit are all high. The first state switching signals are input to the second-stage state judgment circuit. Since each OR gate in the second-stage state judgment circuit has a high input, the second state switching signal output by the second-stage state judgment circuit is high. In this state, the power consumption of the ADC remains normal.

[0013] Furthermore, when the input enable signal is low, the state judgment module is active. When the comparator output signal is set from high to low, all comparator output signals corresponding to some of the first-stage state judgment units are set to low. Then, the first state switching signal output by these first-stage state judgment units is set to low, while the first state switching signal output by the remaining first-stage state judgment units remains high. The first state switching signal is input to the second-stage state judgment circuit. If some OR gate inputs in the second-stage state judgment circuit are high, the second-stage state judgment circuit outputs a second state switching signal that is high. In this state, the ADC enters the first low-power state, and the power consumption of the ADC clock generation module, the ramp signal generation module, and the comparator array module remains normal.

[0014] Furthermore, when the input enable signal is low, the state judgment module is active, all comparator output signals are set from high to low, and all comparator output signals corresponding to all first-stage state judgment units are set to low. In this state, the OR gate inputs in some units of all first-stage state judgment circuits are all low, so the first-stage state judgment unit outputs the first state switching signal and sets it to low. The first state switching signal is used as input to the second-stage state judgment circuit. All inputs in the second-stage state judgment circuit are low, so the second-stage state judgment circuit outputs the second state switching signal and sets it to low. In this state, the following ADCs enter the second low-power state, all first state switching signals are low, all counter units stop operating, and the second state switching signals are all low. In this state, the ADC clock generation module, ramp signal generation module, and comparator array module enter low-power mode.

[0015] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0016] The present invention provides an image sensor with a dynamic low-power counter architecture, which identifies the reading state of pixels through a column ADC. Depending on the brightness of the image, the sampling and flipping time of the corresponding comparator will be different. The judgment result is obtained based on the actual flipping state of the comparator output signal, thereby dynamically reducing the redundant power consumption generated by the column ADC in the area outside the effective reading action during the pixel reading process. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the structure of an image sensor with a dynamic low-power counter architecture provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the operation process of the ADC in normal operation mode in an embodiment of the present invention; Figure 3 This is a schematic diagram of the state judgment module and the counter latch operation array module in an embodiment of the present invention; Figure 4 This is a structural diagram of the status determination module; Figure 5 This is a schematic diagram of the internal structure of the status determination module; Figure 6 This is a schematic diagram of the structure of the first-level state judgment unit; Figure 7 A schematic diagram of a MOS transistor structure for an OR gate; Figure 8 This is the control timing diagram for the first-level state judgment unit; Figure 9 This is a schematic diagram of the second-level state determination circuit; Figure 10 The control timing diagram for the second-stage state judgment circuit; Figure 11 (A) in the diagram is a schematic diagram of the internal structure of the clock control module; Figure 11 (B) is a schematic diagram of the circuit structure of the LATCH circuit LT0 in the clock control module; Figure 12 This is the timing diagram for the clock control module. Figure 13 This is a schematic diagram of the structure of the counter unit in an embodiment of the present invention; Figure 14 This is a schematic diagram of the ADC clock generation module in an embodiment of the present invention; Figure 15 This is a power consumption diagram of an image sensor with a dynamic low-power counter architecture provided in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0019] Image sensor design considers full-count conditions, and the lengths of the Rs and Ss intervals are designed with a certain margin. However, excluding a few extreme cases where the maximum range is required, the ADC range will have some redundancy in most lighting scenarios. In the Rs and Ss intervals of the image sensor, after the counter array in the column ADC has latched the count values ​​of all columns, the counter continues to operate following the clock signal. In addition, the entire ADC clock path, comparator array, and ramp signal generation module will also continue to operate until the Rs / Ss interval ends. Since the column ADC operation is essentially complete at this time, this part of the power consumption is wasted. This invention proposes a structure for a circuit for judging the ADC operation status and a systematic control scheme for other related circuits, aiming to minimize the redundant power consumption of the image sensor outside the effective operation range.

[0020] like Figure 1 As shown, the first embodiment of the present invention provides an image sensor with a dynamic low-power counter architecture. Its basic working principle is a device that converts optical signals into digital electronic signals through quantization. Based on a single-slope analog-to-digital converter architecture, the image sensor 100 includes a pixel array 200, a column ADC 300, a row selection module 400, a phase-locked loop module 500, a timing control module 600, and a digital signal processing and output module 700. The column ADC 300 comprises a comparator array module 301, a state judgment module 302, a counter and latch operation array module 303, a slope signal generation module 304, and an ADC clock generation module 305. As the core part of the image sensor that completes the optical signal quantization process, the column ADC accounts for the majority of the total power consumption of the image sensor. To reduce the power consumption of the column ADC, this embodiment of the present invention adds a state judgment module to the conventional image sensor structure, enabling the column ADC to switch accordingly based on different states to achieve low power consumption.

[0021] The image sensor includes a clock system in which a low-speed reference clock CK0 is provided by an external crystal oscillator. This low-speed clock is multiplied by a phase-locked loop (PLL) module 500 to provide clock signals for various components, including but not limited to the following clock signals: a first clock signal CK1 for the ADC clock generation module (CK1 is a high-speed clock signal), and a medium-speed clock signal CK4 for the timing control module. After passing through the ADC clock generation module, CK1 outputs two high-speed clock signals, CK2 and CK3, which operate only in the Rs and Ss intervals. CK2 provides a counting reference clock signal for the counter and latch operation module 303, and CK3 provides a ramp reference clock signal for the ramp signal generation module 304.

[0022] like Figure 2 The diagram illustrates the normal operating mode of the column ADC of this image sensor. In this embodiment, the image sensor employs a CDS (Correlated Double Sampling) sampling method, with the main sampling quantization process comprising the Rs (Reset Sampling Phase) and Ss (Signal Sampling Phase). The row selection module 400 outputs pixel control signals Tx / Rx / Sx, which are connected to the pixel array. When the row selection module 400 selects a row of pixels, the amount of light signal received by the pixel array 100 is converted into a pixel signal Vpix and output to the column ADC 300. The timing control module provides timing control signals for the normal operation of the image sensor.

[0023] The ramp signal generation module 304 outputs the ramp reference signal Vramp based on the third clock signal CK3 to the comparator array module 301. The comparator array module 301 compares the pixel signal Vpix with the reference ramp signal Vramp. The reference ramp signal descends at a certain slope on the time axis. At the start of the comparison, the counter starts counting along with CK2. When the magnitude relationship between the pixel signal Vpix and the reference signal Vramp reverses, the comparator output signal Vcomp flips, triggering the latch in the counter and latch operation array module 303 to latch the count value of the Vcomp flip time. The counter quantizes the pixel signal by counting the time length (Time to Count).

[0024] like Figure 3This is a schematic diagram of the state judgment module and the counter latching operation array module in an embodiment of the present invention. The counter and latching operation array module 303 adopts the structure of a multi-column shared counter unit, which is currently mainstream in large-pixel-scale image sensors. That is, the count CNT*[x:0] output by one counter unit 3031 is simultaneously supplied to n column latching operation unit modules 3032, where n is typically set to several hundred, commonly around 500. The multi-column shared counter unit structure is a widely adopted counter architecture to address the increasing pixel count, compared to the traditional scheme of one counter per column, in order to reduce power consumption and increase operation frequency. The embodiments of the present invention propose a systematic solution based on this multi-column shared counter architecture, with the aim of further reducing power consumption.

[0025] The counter unit follows the second clock signal CK2 to perform counting operations in the Rs and Ss intervals, and outputs a real-time count value CNT*[x:0] of x+1 bits to the latching operation unit. The latching operation unit is connected to the output signal Vcomp of the comparator array module 301. When a column of comparator outputs reverses from high to low within the Rs and Ss intervals, the latching operation unit latches the count value of the counter unit at the current time point. In normal mode, the counter unit continues counting until the Rs and Ss intervals end.

[0026] like Figure 3 As shown, in this embodiment of the invention, a state judgment module 302 is added before the counter and latch operation array module 303. The output signal Vcomp of the comparator array module 301 is input to the state judgment module 302, and the state judgment module 302 outputs a first state switching signal S1 and a second state switching signal S2. The first state switching signal S1 is an m-bit enable signal, where m is the number of counter units divided in the counter and latch operation array module 303. For example, in a module with 4000 columns, where each counter shares 500 columns, m is 8. The first state switching signal S1 is connected to the corresponding numbered counter unit and controls it; the second state switching signal S2 is connected to the ADC clock generation module 305, the ramp signal generation module 304, and the comparator array module 301 and controls them.

[0027] Figure 4 This is a schematic diagram of the state judgment module 302, which includes m first-level state judgment units 3021 and a second-level state judgment circuit 3022. Figure 5 This is a schematic diagram of the internal structure of the status judgment module 302.

[0028] The first-level state judgment unit 3021 receives the enable signal LPEN and the comparator output signal Vcomp, and outputs an m-bit first state switching signal S1 connected to the second-level state judgment circuit 3022 and the counter unit circuit 3031. Furthermore, the first-level state judgment unit 3021 is divided into m counter units, and the number of comparator output signals Vcomp connected to each first-level state judgment unit corresponds to the number of shared columns of the corresponding counter. For example, first-level state judgment unit 0 is connected to the comparator output signals Vcomp[0]~[n-1] of the shared column corresponding to counter unit 0, and first-level state judgment unit m-1 is connected to the comparator output signals Vcomp[mn-n]~[mn-1] of the shared column corresponding to counter unit m. Each first-level state judgment unit outputs a first state switching signal S1 to control the corresponding counter unit. Its function is to set the first state switching signal S1 of the unit to low only after all the output signals Vcomp of the n comparators corresponding to the first-stage state judgment unit have flipped from high to low. The low state of the first state switching signal S1 enables the corresponding counter unit to stop counting. The enable signal LPEN and the first state switching signal S1 of the first-stage state judgment unit 3021 are input to the second-stage state judgment circuit 3022, and the second-stage state judgment circuit 3022 outputs the second state switching signal S2.

[0029] Figure 6 This is a schematic diagram of the first-level state judgment unit, which corresponds to the common column number n of each counter. Each first-level state judgment 3021 unit consists of n OR gates. The MOS transistor structure diagram of the OR gate is shown below. Figure 7 As shown, one input terminal IN1 of each OR gate is connected to the comparator output signal Vcomp of the corresponding column. The first input terminal IN2 is connected to the enable signal LPEN. The inputs IN2 of the second to nth segments are connected to the output terminal OUT of the previous segment. The output of the last segment of the OR gate is used as the state judgment result to output the first state switching signal S1 to the subsequent circuit (the subsequent circuit includes a counter unit and a second-stage state judgment circuit). According to the truth table of the OR gate, the output of the OR gate is only set to a low level when both outputs of the OR gate are set to a low level, otherwise the OR gate outputs a high level. Therefore, the first state switching signal S1 of the first-stage state judgment unit is set to a low level only when all OR gate inputs are set to a low level. In other states, the first state switching signal S1 is set to a high level.

[0030] Figure 8 The control timing of the first-level state judgment unit 3021 is shown, and its operation flow is as follows:

[0031] At time T0, the comparator array module outputs the comparator output signal Vcomp to complete the reset from low to high.

[0032] At time T1, the enable signal LPEN of the state judgment module changes from high level to low level, at which point the state judgment circuit enters the working state.

[0033] The interval from time point T2 to time point T4 is marked as the sampling operation interval of the column ADC. During this interval, the second clock signal CK2 and the third clock signal CK3 used by the column ADC are activated.

[0034] Within the sampling interval, the comparator's output signal Vcomp will be toggled according to the sampling results of each column. Assuming that at time T3, the n columns of the ADC corresponding to the first-level state judgment unit have completed sampling, then Vcomp[0]~[n-1] will be fully toggled. At this time, the first state switching signal S1 output by the first-level state judgment unit will change from high level to low level, indicating that the column ADC corresponding to the first-level state judgment unit has finished sampling.

[0035] At time T5, the state judgment module is reset. According to the state judgment module's enable signal LPEN changing from low to high, the first state switching signal S1 output by the first-level state judgment unit is reset to high.

[0036] Figure 9 This is a structural diagram of the second-stage state judgment circuit 3022. The second-stage state judgment circuit 3022 is composed of multiple OR gates connected in series. The number of counters configured, m, is composed of m OR gates. The MOS transistor structure diagram of the OR gate is shown below. Figure 7 As shown, one input terminal IN1 of each OR gate is connected to the output of the first-stage state judgment circuit unit 3021, which is the first state switching signal S1. The first input terminal IN2 is connected to the enable signal LPEN. The inputs IN2 of the second to m-th segments are connected to the output terminal OUT of the previous segment. The output of the last segment of the OR gate is used as the state judgment result to output the second state switching signal S2 to the subsequent circuit (the subsequent circuit includes an ADC clock generation module, a ramp signal generation module, and a comparator array module, etc.). According to the working principle of the OR gate, it can be seen that the output of the second-stage state judgment circuit, the second state switching signal S2, will only be low when all the first state switching signals S1 input terminals and LPEN terminals of the OR gates are set to low level. In other states, the output of the second state switching signal S2 will be high level.

[0037] Figure 10 The control timing of the second-stage state judgment circuit 3022 is shown, and its operation flow is as follows:

[0038] At time T0, the comparator array module outputs the comparator output signal Vcomp to complete the reset from low to high.

[0039] At time T1, the enable signal LPEN of the state judgment module changes from high level to low level, at which point the state judgment circuit enters the working state.

[0040] The interval from time point T2 to time point T4 is marked as the sampling operation interval of the column ADC. During this interval, the second clock signal CK2 and the third clock signal CK3 used by the column ADC are activated.

[0041] Within the sampling interval, the comparator output signal Vcomp will be flipped according to the sampling result of each column. After the column ADC corresponding to each first-level state judgment unit 3021 has completed sampling, the output S1 of the first-level state judgment unit 3021 will flip. Assuming that at time T3, all column ADCs have completed sampling, the comparator output signal Vcomp[0]~[mn-1] will be fully flipped. At this time, the first state switching signal S1 output by the first-level state judgment unit 3021 will all change from high level to low level, and at the same time trigger the second-level state judgment circuit 3022 to output the second state switching signal S2 from high level to low level, indicating that all column ADCs have finished sampling.

[0042] At time T5, the state judgment module 302 is reset. According to the enable signal LPEN of the state judgment module 302 changing from low level to high level, the first state switching signal S1 output by the first-level state judgment unit 3021 and the second state switching signal S2 output by the second-level state judgment circuit 3022 are reset to high level.

[0043] The status determination module 302 has the following states, as shown in Table 1: Table 1. Working Status Correspondence Table of Status Judgment Module

[0044] 1) When the enable signal LPEN is high, the state judgment module is in a closed or reset state. Since the first segment OR gate input of each unit in the first-stage state judgment circuit and one end of the first segment OR gate input of the second-stage state judgment circuit are high, based on the principle of OR gates and the series connection relationship, it is easy to see that regardless of the state of the comparator output signal Vcomp, both the first-stage and second-stage state judgment circuits will output the first state switching signal S1 and the second state switching signal S2 as high. In this state, the power consumption of the following ADC remains normal.

[0045] 2) When the enable signal LPEN is low, the state judgment module is active, and the comparator output signal Vcomp is all high. Firstly, each OR gate in the first-stage state judgment unit outputs a high level due to the presence of a high-level input, causing the first state switching signal S1 of each first-stage state judgment unit to be high. The first state switching signal S1 is then fed as input to the second-stage state judgment circuit. Because the inputs of each OR gate in the second-stage state judgment circuit are high, the second state switching signal S2 output by the second-stage state judgment circuit is high. In this state, the power consumption of the ADC remains normal.

[0046] 3) When the enable signal LPEN is low, the state judgment module is active. The comparator output signal Vcomp is set from high to low, and not all comparator outputs corresponding to the first-stage state judgment units are set low. In this state, some OR gates in each unit of the first-stage state judgment circuit output high due to the presence of high-level inputs, making the first state switching signal S1 of each first-stage state judgment unit still high. The first state switching signal S1 is fed as input to the second-stage state judgment circuit. Because the inputs of each OR gate in the second-stage state judgment circuit are high, the second state switching signal S2 output by the second-stage state judgment circuit is high. In this state, the power consumption of the following ADCs remains normal.

[0047] 4) When the enable signal LPEN is low, the state judgment module is active, and the comparator output signal Vcomp is set from high to low. All comparator outputs corresponding to some first-stage state judgment units are set low. In this state, some OR gates in the first-stage state judgment circuit output low because all inputs are low, causing the first state switching signal S1 of these first-stage state judgment units to be low, while the first state switching signal S1 of the remaining first-stage state judgment units remains high. When the first state switching signal S1 is input to the second-stage state judgment circuit, because some OR gates in the second-stage state judgment circuit have high inputs, the second state switching signal S2 of the second-stage state judgment circuit outputs high. In this state, the following ADC enters the first low-power mode. Because some first state switching signals S1 are low, the counter units corresponding to the low-level first state switching signal S1 will stop operating, while the remaining counter units continue to operate normally. Because the second state switching signal S2 remains high, the power consumption of the ADC clock generation module, ramp signal generation module, and comparator array module remains normal in this state.

[0048] 5) When the enable signal LPEN is low, the state judgment module is active, and all comparator output signals Vcomp are set from high to low. All comparator outputs corresponding to the first-stage state judgment units are set low. In this state, the OR gates in some units of the first-stage state judgment circuits output low because all inputs are low, causing the first state switching signal S1 of the first-stage state judgment unit to be set low. The first state switching signal S1 is used as input to the second-stage state judgment circuit. Since all inputs to the second-stage state judgment circuit are low, the second state switching signal S2 of the second-stage state judgment circuit is set low. In this state, the following ADCs enter the second low-power mode. Because all first state switching signals S1 are low, all counter units stop operating. Because the second state switching signal S2 is low, the ADC clock generation module, ramp signal generation module, and comparator array module also enter a low-power state in this state.

[0049] As can be seen from the above, according to the actions of the first state switching signal S1 and the second state switching signal S2 generated by the state judgment module, the counter and latch operation array module, the ADC clock generation module, the comparator array module and the ramp signal generation module will enter the low power mode accordingly, thereby enabling the column ADC to switch accordingly according to different states to enter the low power mode.

[0050] In this embodiment, the state switching action involves the counter and latch operation array module, the ADC clock generation module, the comparator array module, and the ramp signal generation module. The state switching of the counter and latch operation array module, the ADC clock generation module, and the ramp signal generation module all involve the stopping action of the clock signal. Therefore, a clock control module is provided to complete the switching of the clock signal state.

[0051] like Figure 11 As shown in (A), an embodiment of the present invention provides a clock control module including an input enable signal EN, an input clock CK, and a state switching signal S, an output enable signal ENO, and an output clock signal CKO. Its function is to stop outputting the clock when the input state switching signal S changes from high to low, and simultaneously advance the disable action of the enable signal of subsequent circuits, thereby causing the subsequent circuit modules to stop working earlier. The internal structure of the clock control module is as follows... Figure 11 As shown in (A), it consists of a LATCH circuit LT0 with the output set high after reset, two NAND gate circuits NAND1 and NAND2, and two inverter circuits I1 and I2.

[0052] Figure 11 (B) is Figure 11The LATCH circuit LT0 used in (A) consists of two tri-state inverters TI1 and TI2, a NAND gate NAND1, and an inverter I1. The LATCH circuit can exist in the following states: 1) When the reset signal RST is high, LATCH is in the working state. At this time, when CK is high, the tri-state inverter TI1 in the LATCH circuit is turned on and TI2 is turned off. At this time, the input D of LATCH can be directly passed through TI1 and NAND1, and the output Q of the LATCH circuit is equal to D; 2) When CK is low, the tri-state inverters TI1 and TI2 in the LATCH circuit are off and on. At this time, the LATCH circuit is in a holding state, and the input D cannot be transmitted to the output Q. The output Q of the LATCH circuit remains in the previous state of the input D. 3) When the reset signal RST is low, the LATCH circuit is in a reset state. The reset signal RST sets the output Q of the LATCH circuit high through the NAND gate NAND1, and is unaffected by the clock input CK and the input D.

[0053] In the clock control module, the LATCH circuit LT0 functions to synchronize the input signal with the clock and output a delayed signal. Its input D terminal is connected to the state switching signal S, the input CK terminal is connected to the clock signal CK, and the input RST terminal is connected to the enable signal input EN. Based on the various states of the LATCH circuit, it can be concluded that the input state switching signal S can only be transmitted to the output S_MASK side of the LATCH circuit LT0 when the input clock CK is low. When the level of the state switching signal S changes from high to low or low to high, after synchronizing with the clock CK of the LATCH circuit LT0, the LT0 output signal Q outputs the state switching signal S_MASK, synchronized with the falling edge of the clock CK.

[0054] The combinational logic formed by the intermediate signals S_MASK and EN, using NAND1 and I1, outputs an enable output signal ENO. The combinational logic formed by the intermediate signals S_MASK and EN, using NAND1 and I1, outputs a clock output signal CKO. When the intermediate signal S_MASK is high, the enable output signal ENO equals the enable input signal EN, and the clock output signal CKO equals the clock input signal CK. When the intermediate signal S_MASK is low, both the enable output signal ENO and the clock output signal CKO are set to low.

[0055] Figure 12 The following is a timing diagram of the clock control module. Its functions are explained below in conjunction with the timing diagram:

[0056] 1) At time T0, the input enable signal EN changes from low level to high level, and the clock control module enters the working mode from the reset mode.

[0057] 2) At time points T1 to T4, input clock signal CK, and at time T1, CKO starts to follow the action of CK.

[0058] 3) At time T2, the state switching signal S changes from high level to low level, indicating that it has entered the stop working state.

[0059] 4) At time T3, after the state switching signal S passes through the LATCH circuit LT0, it outputs a state switching signal S_MASK synchronized with the falling edge of the clock signal. After S_MASK and the clock signal CK pass through the AND logic of NAND2 and I2, the output clock CKO stops and remains low after S_MASK falls to a low level. After S_MASK and the input enable signal EN pass through the AND logic of NAND1 and I1, the output enable signal ENO remains low after S_MASK falls to a low level.

[0060] 5) At time T5, the input enable signal EN changes from high level to low level, resetting the LATCH circuit LT0, and S_MASK is reset to high level.

[0061] Figure 13 This is a structural diagram of the counter unit in this embodiment of the invention. It consists of a clock control module and a counter core circuit. The input signals include a second clock signal CK2, a counter enable signal CNT_EN, and a first state switching signal S1 output by the first-stage state judgment unit. The output signal is an x-1 bit count output signal CNT. The input signals CK2, CNT_EN, and S1 are input to the clock control module. After processing by the clock control module, CNT_CK_IN and CNT_EN_IN are output and input to the counter core circuit. Specifically, the second clock signal CK2 is connected to the clock input terminal CK of the clock control module, the counter enable signal CNT_EN is connected to the input enable signal EN terminal of the clock control module, and the first state switching signal S1 is input to the S terminal of the clock control module. The enable signal ENO output by the clock control module is connected to the actual enable signal CNT_EN_IN terminal of the counter core circuit, and the output clock signal CKO is connected to the actual clock signal CNT_CK_IN terminal of the counter core circuit. The counter core circuit can be a binary counter or a Gray code counter commonly found in existing image sensors, and its specific structure is based on existing technology.

[0062] Figure 14This is a schematic diagram of the ADC clock generation module. Its internal structure consists of a clock control module and the core circuitry of the ADC clock generation module. Its input signals include a first clock signal CK1, which generates an enable signal ADC_CKGEN_EN and a second state switching signal S2. The ADC clock generation module processes the clock signal CK1 output from the phase-locked loop module by truncation and frequency division, outputting a second clock signal CK2 and a third clock signal CK3 that operate only during the Rs and Ss phases. The second clock signal CK2 serves as the reference clock for the counter and latch operation array module, while the third clock signal CK3 serves as the reference clock for the ramp signal generation module. The second clock signal CK2 and the third clock signal CK3 are clock signals with the same phase, but depending on the specific operating mode, they can be clock signals of the same or different frequencies.

[0063] Among them, the clock control module is also based on Figure 12 The action sequence is shown. The second state switching signal S2 is connected to the S terminal of the clock control module, the reference clock CK1 is connected to the CK terminal of the clock control module, and the enable signal ADC_CKGEN_EN is connected to its EN terminal. According to the action sequence... Figure 12 When the second state switching signal S2 switches from high to low, the first clock signal CK1 is truncated (i.e., the clock output is in a fixed low-level state after S2 is low), providing the processed clock signal ADC_CKGEN_CK_IN to the core circuit of the ADC clock generation module. The enable signal ENO output by the clock control module is connected to the actual enable signal ADC_GEN_EN_IN of the core circuit of the ADC clock generation module, and the clock signal CKO output by the clock control module is connected to the actual clock signal ADC_CKGEN_CK_IN of the core circuit of the ADC clock generation module.

[0064] By switching according to the second state switching signal S2, the ADC clock generation module can stop operating in the redundant intervals of the Rs and Ss stages, reducing its power consumption. On the other hand, in the actual image sensor chip layout, the distances between the second clock signal CK2 and the third clock signal CK3 generated by the ADC clock generation module and the corresponding counter unit input and ramp signal generation module input will continuously increase as the sensor size increases. To ensure driving capability, a sufficient number of clock signal repeaters (such as those mentioned in CN216819967 U) must be configured in the clock link. These clock signal repeaters are often relatively large in size to ensure driving capability, thus consuming power during the clock signal operation interval. When the ADC clock generation module stops operating in the redundant intervals of the Rs and Ss stages, the corresponding clock signal repeaters in the clock link also stop operating, thus reducing the power consumption of the clock repeaters.

[0065] The overall workflow of the column ADC in this embodiment of the invention:

[0066] 1) Once the pixel reading operation for one row begins, the column ADC enters the reset / clear interval. During the clear interval, the comparator operates in low-power mode.

[0067] 2) After the zeroing process is completed, enter the Rs sampling interval.

[0068] 3) Within the Rs sampling interval, after the relationship between the ramp voltage signal Vramp decreasing over time and the pixel voltage signal Vpix is ​​reversed, the comparator output signal Vcomp is flipped and set to low.

[0069] 4) Within the Rs sampling interval, when all the comparator output signals Vcomp of the column ADC shared by a counter unit are toggled low, the first state switching signal S1 corresponding to that counter unit in the first-stage state judgment circuit is toggled low. The counter unit then stops operating.

[0070] 5) When all the comparator output signals Vcomp of all columns have toggled low, the second-stage state judgment circuit outputs the second state switching signal S2, which then toggles low. At this time, the ADC clock generation module stops outputting the third clock signal CK3 for ramp signal generation and the second clock signal CK2 for counters. All counter units stop working, the ramp signal generation circuit stops generating ramps and switches to a low-current, high-gain mode, and the comparator array module also enters a low-power mode.

[0071] 6) After the Rs sampling interval, the pixel voltage signal establishment interval begins. During this interval, the comparator output signal Vcomp is reset to high, and the outputs of the state judgment circuit module, the first state switching signal S1 and the second state switching signal S2, are also reset to high. The ramp signal generation module resumes normal operation mode after the second state switching signal S2 is set high. During this interval, the comparator array module maintains a low-power mode.

[0072] 7) Within the Ss sampling interval, after the relationship between the ramp voltage signal Vramp decreasing over time and the pixel voltage signal Vpix is ​​reversed, the comparator output signal Vcomp is flipped and set low.

[0073] 8) Within the Ss sampling interval, when all the comparator output signals Vcomp of the column ADC shared by a counter unit are toggled low, the first state switching signal S1 corresponding to that counter unit in the first-stage state judgment circuit is toggled low. The counter unit then stops operating.

[0074] 9) When all the comparator output signals Vcomp of all columns have toggled low, the second-stage state judgment circuit outputs the second state switching signal S2, which then toggles low. At this time, the ADC clock generation module stops outputting the third clock signal CK3 for ramp signal generation and the second clock signal CK2 for counters. All counter units stop working, the ramp signal generation circuit stops generating ramps and switches to a low-current, high-gain mode, and the comparator array module also enters a low-power mode.

[0075] 10) After the Ss sampling interval, the pixel voltage signal establishment interval begins. During this interval, the comparator output signal Vcomp is reset to high, and the outputs of the state judgment circuit module, the first state switching signal S1 and the second state switching signal S2, are also reset to high. During this interval, the ramp signal generation module and the comparator array module maintain low-power mode. The column ADC's reading operation for one row of pixels ends here.

[0076] Existing low-power image sensor solutions mostly employ an AlwaysOn-like approach, entering an ultra-low-power motion detection mode when the image remains unchanged, and only activating the normal full-pixel motion mode when the image changes. This invention, however, is a power-saving solution for the normal full-pixel motion mode. It does not conflict with the AlwaysOn approach but rather serves as a further supplement to low-power solutions. Without compromising performance, it significantly reduces redundant power consumption of the image sensor, thereby reducing power consumption in normal operating mode and further lowering the overall power consumption of the chip. This invention can be used independently in conventional image sensors or in combination with ultra-low-power image sensors employing the AlwaysOn approach. In the current era of widespread mobile devices and the Internet of Things, where devices are widely powered by batteries, it can significantly increase device battery life and has broad application value.

[0077] Figure 15 This is a power consumption diagram of the image sensor according to an embodiment of the present invention. The embodiment of the present invention determines the pixel reading state of the column ADC. Depending on the brightness of the image, the comparator sampling and flipping time will vary. Based on the judgment result of the actual comparator output signal Vcomp flipping state, the redundant power consumption generated outside the effective reading action of the column ADC during pixel reading is dynamically reduced significantly. Depending on the image brightness, it can be seen that in low brightness, the comparator flips earlier, resulting in the lowest power consumption. In high brightness, the comparator flips later, resulting in relatively higher power consumption. However, since the embodiment of the present invention also performs low-power mode processing for the comparator in areas outside the Rs and Ss sampling intervals, even in high brightness, it still reduces redundant power consumption significantly compared to the normal mode. The actual power reduction performance may vary depending on the proportion of each action interval of the actual image sensor.

[0078] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An image sensor with a dynamic low-power counter architecture, characterized in that, include: Phase-locked loop module, row selection module, pixel array, column ADC and timing control module, The phase-locked loop module is used to provide corresponding clock signals to each module after multiplying the clock signal provided by the external crystal oscillator. The row selection module is used to select a certain row of pixels and output a pixel control signal to the pixel array; The pixel array is used to acquire the light signal of the subject being photographed according to the pixel control signal, and then output the light signal to the column ADC after converting the light signal into a pixel signal. The column ADC includes: an ADC clock generation module, a ramp signal generation module, a comparator array module, and a state judgment module. The ADC clock generation module is used to process the input first clock signal and output a second clock signal and a third clock signal that operate in the Rs interval and Ss interval. The second clock signal is a counting reference clock signal provided by the counter and latch operation module, and the third clock signal is a ramp reference clock signal provided by the ramp signal generation module. The ramp signal generation module is used to output a ramp reference signal according to the third clock signal and input the ramp reference signal to the comparator array module; The comparator array module is used to compare the pixel signal and the ramp reference signal to obtain the comparator output signal; The state judgment module is used to output a first state switching signal and a second state switching signal according to the comparator output signal. The first state switching signal is used to control the counter and latch operation array module, and the second state switching signal is used to control the ADC clock generation module, the ramp signal generation module and the comparator array module. The timing control module provides timing control signals for the normal operation of the image sensor.

2. The image sensor with a dynamic low-power counter architecture according to claim 1, characterized in that, The column ADC also includes: a counter and latch operation array module, which adopts a structure of multiple columns sharing a counter unit, including a counter unit and a latch operation unit. The count output of one counter unit is simultaneously supplied to multiple columns of latch operation units. The counter unit counts along with the second clock signal when comparing the voltage signal and the ramp reference signal. When the magnitude relationship between the voltage signal and the ramp reference signal is reversed, the comparator output signal flips, triggering the latch operation unit to latch the count value of the comparator output signal flip time. The counter obtains the real-time count value by counting the time length. The latching operation unit is connected to the comparator array module. When the output signal of a certain comparator flips in the Rs and Ss intervals, the latching operation unit latches the real-time count value input by the counter unit at the current time point.

3. The image sensor with a dynamic low-power counter architecture according to claim 2, characterized in that, The state determination module includes multiple first-level state determination units and a second-level state determination circuit. The first-level state determination units are used to output a first state switching signal to the second-level state determination circuit and the counter unit circuit according to the input enable signal and the comparator output signal. The second-stage state judgment circuit outputs a second state switching signal based on the input enable signal and the first state switching signal.

4. The image sensor with a dynamic low-power counter architecture according to claim 3, characterized in that, The first-level state judgment unit is composed of multiple OR gates connected in series. The number of OR gates is the same as the number of columns shared by each counter unit. One input of each OR gate is connected to the comparator output signal of the corresponding column. The other input of the first OR gate is connected to the enable signal. The output of the first OR gate is used as the input of the next OR gate. The output of the last OR gate is used as the first state switching signal.

5. The image sensor with a dynamic low-power counter architecture according to claim 4, characterized in that, The second-level state judgment circuit is composed of multiple OR gates connected in series. The number of OR gates is the same as the number of corresponding counter units. One input of each OR gate is connected to the first state switching signal, the other input of the first OR gate is connected to the enable signal, the output of the first OR gate is used as the input of the next OR gate, and the output of the last OR gate is used as the second state switching signal.

6. The image sensor with a dynamic low-power counter architecture according to claim 5, characterized in that, When the input enable signal is high, the state judgment module is in a closed or reset state. The first segment OR gate input of each unit of the first-level state judgment unit and one end of the first segment OR gate input of the second-level state judgment circuit are set to high level. The first state switching signal output by the first-level state judgment circuit and the second state switching signal output by the second-level state judgment circuit are both high level. In this state, the power consumption of the ADC remains normal.

7. The image sensor with a dynamic low-power counter architecture according to claim 5, characterized in that, When the input enable signal is low, the state judgment module is active. When all comparator output signals are high, each OR gate in the first state judgment unit outputs a high-level first state switching signal because of the high-level input. The first state switching signal is input to the second-level state judgment circuit. If each OR gate in the second-level state judgment circuit has a high-level input, the second-level state judgment circuit outputs a high-level second state switching signal. In this state, the power consumption of the ADC remains normal.

8. The image sensor with a dynamic low-power counter architecture according to claim 5, characterized in that, When the input enable signal is low, the state judgment module is active. The comparator output signal is set from high to low, and not all comparator output signals corresponding to each first-stage state judgment unit are set to low. Since some OR gates in each unit of the first-stage state judgment unit have high inputs, the first state switching signals output by each first state judgment unit are all high. The first state switching signal is input to the second-stage state judgment circuit. Since each OR gate in the second-stage state judgment circuit has a high input, the second state switching signal output by the second-stage state judgment circuit is high. In this state, the power consumption of the ADC remains normal.

9. The image sensor with a dynamic low-power counter architecture according to claim 5, characterized in that, When the input enable signal is low, the state judgment module is active. When the comparator output signal is set from high to low, all comparator output signals corresponding to some of the first-level state judgment units are set to low. The first state switching signal output by these first-level state judgment units is set to low, while the first state switching signal output by the remaining first-level state judgment units remains high. The first state switching signal is input to the second-level state judgment circuit. If some OR gate inputs in the second-level state judgment circuit are high, the second-level state judgment circuit outputs a second state switching signal that is high. In this state, the ADC enters the first low-power state, and the power consumption of the ADC clock generation module, ramp signal generation module, and comparator array module remains normal.

10. The image sensor with a dynamic low-power counter architecture according to claim 5, characterized in that, When the input enable signal is low, the state judgment module is active, all comparator output signals are set from high to low, and all comparator output signals corresponding to all first-stage state judgment units are set to low. In this state, all OR gate inputs in some units of the first-stage state judgment circuit are low, so the first-stage state judgment unit outputs a first state switching signal and sets it to low. The first state switching signal is used as input to the second-stage state judgment circuit. All inputs in the second-stage state judgment circuit are low, so the second-stage state judgment circuit outputs a second state switching signal and sets it to low. In this state, the following ADCs enter the second low-power state, all first state switching signals are low, all counter units stop operating, and all second state switching signals are low. In this state, the ADC clock generation module, ramp signal generation module, and comparator array module enter low-power mode.

Images