ATE time parameter measurement system and method, and ATE device

Abstract

The invention provides an ATE time parameter measurement system and method and ATE equipment. The system comprises a channel mapping module and at least one time measurement unit. The channel mapping module is used for establishing a mapping relation between a preset number of target data channels in the plurality of data channels and target time measurement units in the at least one time measurement unit, the target data channels are in one-to-one correspondence with the target time measurement units, the target data channels are used for receiving signals to be measured, and the target time measurement units are used for measuring the signals to be measured. The preset number is smaller than or equal to the number of the time measuring units; the target time measurement unit is used for receiving the to-be-measured signal from the corresponding target data channel and determining a time parameter corresponding to the to-be-measured signal. Therefore, by dynamically establishing the mapping relation between the target data channel and the target time measurement unit, only hardware resources need to be allocated to actually used channels, resource waste of unused channels is avoided, the hardware resource utilization rate is greatly improved, and the system cost is reduced.

Description

Technical Field

[0001] This application belongs to the field of semiconductor testing technology, and in particular relates to an ATE time parameter measurement system, method and ATE equipment. Background Technology

[0002] Timing parameter measurement is a fundamental and critical test function in Automatic Test Equipment (ATE), and is commonly used to measure timing parameters such as signal period, frequency, and pulse width.

[0003] In related technologies, time parameter measurement schemes typically allocate an independent Time Measurement Unit (TMU) and dedicated storage resources to each physical channel.

[0004] However, in practical applications, not all channels are used at the same time. A large number of unused channels still occupy TMU hardware logic and memory storage resources, resulting in low hardware resource utilization. Summary of the Invention

[0005] This application provides an ATE time parameter measurement system, method, and ATE device, which can improve the hardware resource utilization of the ATE time parameter measurement system.

[0006] A first aspect of this application provides an ATE time parameter measurement system, including a channel mapping module and at least one time measurement unit. The channel mapping module is used to establish a mapping relationship between a preset number of target data channels among a plurality of data channels and a target time measurement unit among the at least one time measurement unit, wherein the target data channels correspond one-to-one with the target time measurement units, the target data channels are used to receive signals to be measured, and the preset number is less than or equal to the number of time measurement units. The target time measurement unit is used to receive the signals to be measured from the corresponding target data channels and determine the time parameters corresponding to the signals to be measured.

[0007] In the technical solution of this application, the mapping relationship between the target data channel and the target time measurement unit is dynamically established through the channel mapping module. This means that only the channels actually used need to be allocated hardware resources, avoiding the waste of resources in unused channels, thereby greatly improving the utilization rate of hardware resources and reducing system costs.

[0008] Optionally, in one possible implementation of the first aspect, the time parameters corresponding to the signal under test include the high-level duration and the low-level duration. The target time measurement unit is specifically used to: sample the rising edge transition time and falling edge transition time of the waveform of the signal under test to obtain sampling results; and determine the high-level duration and low-level duration corresponding to the signal under test based on the sampling results. Thus, by accurately sampling the edge transition times of the waveform of the signal under test and calculating the level duration, nanosecond-level precise measurement of the signal timing parameters is achieved, thereby providing key data support for digital circuit functional verification and performance analysis.

[0009] Optionally, in another possible implementation of the first aspect, the aforementioned ATE time parameter measurement system further includes a transmission scheduling module, a First-In-First-Out (FIFO) memory, a transmission execution module, memory, and a processing unit; the target time measurement unit is further used to send the time parameters corresponding to the signal under test to the FIFO memory; the transmission scheduling module is used to generate transmission instructions corresponding to the time parameters and send the transmission instructions to the transmission execution module; the transmission execution module is used to respond to the transmission instructions sent by the transmission scheduling module and transmit the time parameters corresponding to the signal under test in the FIFO memory to the memory; the processing unit is used to read the time parameters corresponding to the signal under test from the memory and perform data analysis based on the time parameters corresponding to the signal under test. Thus, through the collaborative work of the transmission scheduling module and the execution module, high-speed automated flow of time parameters from acquisition and caching to memory is achieved, ensuring real-time storage of time-series data without loss, thereby providing a complete and reliable data foundation for efficient data analysis by the processing unit.

[0010] Optionally, in another possible implementation of the first aspect, the aforementioned transmission scheduling module is specifically used to: generate a transmission instruction corresponding to the time parameter based on the preset address information and preset frame length parameter corresponding to the memory, and send the transmission instruction to the transmission execution module. Thus, by generating standardized transmission instructions based on the preset address and frame length parameter, a clearly structured and quickly locating data analysis foundation is provided to the processing unit.

[0011] Optionally, in another possible implementation of the first aspect, the aforementioned transmission scheduling module is specifically used to: determine whether the remaining space in the first-in-first-out (FIFO) memory is sufficient to accommodate the target data volume, wherein the target data volume is the amount of time parameter data transmitted by the target time measurement unit in the next data frame; if it is sufficient to accommodate the target data volume, generate a transmission instruction corresponding to the time parameter based on the preset address information and preset frame length parameter of the memory, and send the transmission instruction to the transmission execution module. Thus, by dynamically monitoring the remaining space in the FIFO memory and comparing it with the preset data volume, the generation and transmission of the transmission instruction are intelligently triggered, thereby ensuring that the data transmission rate and data processing capability are precisely matched, and avoiding the risk of data overflow or loss.

[0012] Optionally, in another possible implementation of the first aspect, the aforementioned ATE time parameter measurement system further includes a sampling synchronization module. This module sends a synchronization signal to each target time measurement unit, enabling each unit to synchronously determine the time parameter corresponding to the signal under test based on the synchronization signal. Thus, by sending a unified synchronization signal to all target time measurement units through the sampling synchronization module, simultaneous sampling across multiple channels is ensured, achieving a synchronization effect.

[0013] Optionally, in another possible implementation of the first aspect, the aforementioned ATE time parameter measurement system further includes a processing unit; the processing unit is used to enable each target data channel by configuring the channel and to determine each target time measurement unit. Thus, the processing unit centrally configures the channel enable and resource mapping relationships during the system initialization phase, laying the hardware foundation for subsequent measurement tasks.

[0014] A second aspect of this application provides an ATE time parameter measurement method, applied to the aforementioned ATE time parameter measurement system, the method comprising: Through the channel mapping module, a mapping relationship is established between a preset number of target data channels in multiple data channels and a target time measurement unit in at least one time measurement unit. The target data channels correspond one-to-one with the target time measurement units. The target data channels are used to receive the signal to be measured, and the preset number is less than or equal to the number of time measurement units. The target time measurement unit receives the signal to be measured from the corresponding target data channel and determines the time parameters corresponding to the signal to be measured.

[0015] Optionally, in one possible implementation of the second aspect, the above-mentioned receiving the signal under test from the corresponding target data channel through the target time measurement unit and determining the time parameters corresponding to the signal under test includes: sampling the rising edge transition time and falling edge transition time of the waveform of the signal under test to obtain the sampling result; and determining the high level duration and low level duration corresponding to the signal under test based on the sampling result.

[0016] Optionally, in another possible implementation of the second aspect, the ATE time parameter measurement system further includes a transmission scheduling module, a first-in-first-out (FIFO) memory, a transmission execution module, memory, and a processing unit; the method further includes: generating a transmission instruction corresponding to the time parameter through the transmission scheduling module and sending the transmission instruction to the transmission execution module; generating a transmission instruction corresponding to the time parameter through the transmission scheduling module and sending the transmission instruction to the transmission execution module; the transmission execution module responding to the transmission instruction sent by the transmission scheduling module and transmitting the time parameter corresponding to the signal under test in the FIFO memory to the memory; and the processing unit reading the time parameter corresponding to the signal under test from the memory and performing data analysis based on the time parameter corresponding to the signal under test.

[0017] Optionally, in another possible implementation of the second aspect, generating the transmission instruction corresponding to the time parameter and sending the transmission instruction to the transmission execution module includes: determining whether the remaining space in the first-in-first-out memory is sufficient to accommodate the target data amount, wherein the target data amount is the amount of data of the time parameter transmitted by the target time measurement unit in the next data frame; if it is sufficient to accommodate the target data amount, generating the transmission instruction corresponding to the time parameter according to the preset address information and preset frame length parameter corresponding to the memory, and sending the transmission instruction to the transmission execution module.

[0018] Optionally, in another possible implementation of the second aspect, the ATE time parameter measurement system further includes a sampling synchronization module; the method further includes: sending a synchronization signal to each target time measurement unit through the sampling synchronization module, so that each target time measurement unit synchronously determines the time parameter corresponding to the signal to be measured according to the synchronization signal.

[0019] Optionally, in another possible implementation of the second aspect, before establishing the mapping relationship between a preset number of target data channels in the plurality of data channels and the target time measurement units in the at least one time measurement unit, the method further includes: using a processing unit to enable each target data channel by configuring the channel and to determine each target time measurement unit.

[0020] A third aspect of this application provides an ATE device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the ATE time parameter measurement method described in the second aspect above.

[0021] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the ATE time parameter measurement method described in the second aspect above.

[0022] The fifth aspect of this application provides a computer program product that, when run on an ATE device, causes the ATE device to perform the ATE time parameter measurement method described in the second aspect above.

[0023] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the architecture of an ATE time parameter measurement system; Figure 2 This is a schematic diagram of the architecture of an ATE time parameter measurement system provided in an embodiment of this application; Figure 3 This is a schematic diagram of a chip comparator provided in an embodiment of this application; Figure 4 This is a schematic diagram of data interaction of the configuration bus register access interface provided in an embodiment of this application; Figure 5 This is a schematic diagram for calculating time parameters provided in an embodiment of this application; Figure 6 This is a schematic diagram of data flow during the data storage process provided in the embodiments of this application; Figure 7 This is a flowchart illustrating an ATE time parameter measurement method provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of an ATE device provided in an embodiment of this application. Detailed Implementation

[0026] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0027] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0028] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0029] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0030] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0032] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0033] In related technologies, ATE time parameter measurement schemes typically allocate an independent time measurement unit (TMU) and dedicated storage resources to each physical channel.

[0034] Figure 1 A schematic diagram of the architecture of an ATE time parameter measurement system is shown. Figure 1 As shown, each channel corresponds to a time measurement unit, and the sampling data and measurement results of each time measurement unit will occupy a block of storage resources in memory.

[0035] However, in practical applications, not all channels are used at the same time. A large number of unused channels still occupy the hardware logic and memory storage resources of the time measurement unit, resulting in low hardware resource utilization.

[0036] In view of this, embodiments of this application provide an ATE time parameter measurement system, method, and ATE device. The system includes a channel mapping module and at least one time measurement unit. The channel mapping module is used to establish a mapping relationship between a preset number of target data channels among multiple data channels and a target time measurement unit among the at least one time measurement unit. The target data channels correspond one-to-one with the target time measurement units, and the target data channels are used to receive signals to be measured. The preset number is less than or equal to the number of time measurement units. The target time measurement unit is used to receive the signals to be measured from the corresponding target data channels and determine the time parameters corresponding to the signals to be measured. Thus, by dynamically establishing the mapping relationship between target data channels and target time measurement units through the channel mapping module, hardware resources only need to be allocated to the channels actually used, avoiding resource waste from unused channels, thereby significantly improving hardware resource utilization and reducing system costs.

[0037] To illustrate the technical solution of this application, specific embodiments are described below.

[0038] Figure 2 A schematic diagram of the architecture of an ATE time parameter measurement system provided in an embodiment of this application is shown. Figure 2 As shown, the ATE time parameter measurement system (hereinafter referred to as the system for ease of explanation) is implemented based on a field programmable gate array (FPGA) and includes a channel mapping module and multiple time measurement units.

[0039] The channel mapping module is used to establish the mapping relationship between a preset number of target data channels in multiple data channels and a target time measurement unit in at least one time measurement unit.

[0040] Each target data channel corresponds to a target time measurement unit. The target data channel is used to receive the signal to be measured, and the preset number is less than or equal to the number of time measurement units.

[0041] For example, an ATE time parameter measurement system includes 32 data channels and 8 time measurement units. The number of target data channels is greater than or equal to 1 and less than or equal to 8. Assuming there are 8 target data channels, the channel mapping module can map the data from any 8 target data channels out of the 32 data channels to the corresponding 8 target time measurement units. In other words, the system can simultaneously process the signal time measurement calculations from any 8 data channels.

[0042] The signal to be measured can be converted into a digital signal by a chip comparator and then sent to the time measurement unit for measurement through a data channel.

[0043] For example, see as follows Figure 3 The diagram shows a chip comparator with two inputs: input A, which comes from the signal being measured, and input B, which is a reference voltage. Assuming input A = 3V and input B = 2V, if A is greater than B, the chip comparator will output a digital signal representing "true" or "high level," for example, output C = 1.

[0044] It should be noted that system initialization configuration is required before the channel mapping module establishes the mapping relationship. See also... Figure 2 The ATE time parameter measurement system also includes a processing unit. This unit can enable each target data channel and determine each target time measurement unit by configuring the channels. Specifically, the processing unit can configure the system's internal registers through the configuration channels, such as configuring channel enable, the number of samples, and other key information. Thus, by centrally configuring channel enable and resource mapping relationships during the system initialization phase, the processing unit lays the hardware foundation for subsequent measurement tasks.

[0045] The processing unit can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0046] In one embodiment, the ATE time parameter measurement system may further include a configuration bus, such as an Axi-Lite configuration bus. The Axi-Lite configuration bus primarily implements the standard Axi-Lite slave interface protocol. The processing unit can access the interface through the configuration bus registers to perform corresponding configurations, thereby controlling the FPGA's operating mode. For details, please refer to... Figure 4 The diagram illustrates the data interaction of the configuration bus register access interface. The general interaction flow is as follows: the master device informs the slave device of the register address to be written; the master device provides the data to be written; the slave device informs the master device whether the write operation was successful; the master device informs the slave device of the register address to be read; the slave device returns the data to be read from the master device. This process enables the configuration of the mapping relationship between the target data channel and the target time measurement unit.

[0047] You can continue to see Figure 2 The target time measurement unit is used to receive the signal to be measured from the corresponding target data channel and determine the time parameters corresponding to the signal to be measured.

[0048] The time parameters corresponding to the signal under test may include parameters such as high-level duration, low-level duration, signal period, frequency, and pulse width.

[0049] The target time measurement unit can start calculating time parameters after the FPGA receives the channel enable command from the processing unit.

[0050] In one embodiment, the ATE time parameter measurement system may further include a sampling synchronization module for sending a synchronization signal to each target time measurement unit, so that each target time measurement unit synchronously determines the time parameter corresponding to the signal to be measured based on the synchronization signal. Thus, by sending a unified synchronization signal to all target time measurement units through the sampling synchronization module, simultaneous sampling of multiple channels is ensured, achieving a synchronization effect.

[0051] In one embodiment, the process of the target time measurement unit calculating time parameters may include: firstly, sampling the rising edge transition time and falling edge transition time of the waveform of the signal under test to obtain sampling results; then, based on the sampling results, determining the high-level duration and low-level duration corresponding to the signal under test, and further marking flag bits to distinguish channel number and event type. Thus, by accurately sampling the edge transition time of the waveform of the signal under test and calculating the level duration, nanosecond-level precise measurement of signal timing parameters can be achieved, thereby providing key data support for digital circuit functional verification and performance analysis.

[0052] For example, reference can be made to... Figure 5 The time parameter calculation reference diagram shown indicates that start_cnt=0 and end_cnt=n represent the start and end times of the timestamp, respectively. The value of ch1_up_cnt1 represents the first rising edge of the channel 1 waveform, and the value of ch1_down_cnt1 represents the first falling edge of the channel 1 waveform. The value of ch1_up_cnt2 represents the second rising edge of the channel 1 waveform, and the value of ch1_down_cnt2 represents the second falling edge of the channel 1 waveform. ch1_down_cnt1-ch1_up_cnt1=15 represents the duration of the first high level of the channel 1 waveform, and (ch1_down_cnt1-ch1_up_cnt1) / (ch1_up_cnt2-ch1_up_cnt1)=1 / 2 represents the duty cycle of the first cycle of the channel 1 waveform. `ch2_down_cnt1-ch2_up_cnt1=7` indicates the duration of the first high-level signal in channel 2. `(ch2_down_cnt1-ch2_up_cnt1) / (ch2_up_cnt2-ch2_up_cnt1)=7 / 17` indicates the duty cycle of the first cycle of channel 2. `ch1_up_cnt1-ch2_up_cnt1=5` indicates that the first rising edge of channel 2 is 5 units of time earlier than the first rising edge of channel 1.

[0053] Furthermore, after obtaining the time parameter measurement results, the measurement results can be stored in a first-in-first-out (FIFO) memory. Direct Memory Access (DMA) is used to store the measurement results in memory, allowing subsequent processing units to read the measurement results from memory for post-analysis. That is, as one possible implementation of this application, refer to the following... Figure 6The diagram illustrates the data flow during the data storage process. The ATE time parameter measurement system also includes a transmission scheduling module, a first-in-first-out (FIFO) memory, a transmission execution module, memory, and a processing unit. The transmission scheduling module generates transmission instructions (e.g., DMA commands) corresponding to the time parameters and sends these instructions to the transmission execution module. The transmission execution module responds to the transmission instructions sent by the transmission scheduling module, transferring the time parameters corresponding to the signal under test from the FIFO memory to the memory. The processing unit reads the time parameters corresponding to the signal under test from the memory and performs data analysis based on these parameters. Thus, through the collaborative work of the transmission scheduling module and the execution module, high-speed automated flow of time parameters from acquisition and buffering to memory is achieved, ensuring real-time storage of time-series data without loss, and providing a complete and reliable data foundation for efficient data analysis by the processing unit.

[0054] The first-in-first-out (FIFO) memory primarily serves as a data buffer before time parameters are written to memory, preventing data loss due to rapid data sampling.

[0055] Continue to refer to Figure 6 After the FPGA receives the channel enable command from the processing unit, it enables all target time measurement units and also needs to enable the transmission scheduling module. The target time measurement units then begin measurement, obtaining time parameters and calculating the timestamp value `count` and the numerical flag `count_vld`. This data is then written into memory for buffering. After the transmission execution module receives the transmission command from the transmission scheduling module, it writes the data into memory.

[0056] Among them, the memory can be Double Data Rate Synchronous Dynamic Random Access Memory (DDR). DDR transmits data once on the rising edge and once on the falling edge of the clock signal, achieving a transmission rate twice that of traditional Synchronous Dynamic Random Access Memory (SDRAM).

[0057] In one embodiment, during system initialization, address information and frame length parameters (frame_len, i.e., sampling depth) need to be configured in advance. The address information includes a start address (ddr_start_addr) and an end address (ddr_end_addr). The transmission scheduling module is specifically used to: generate transmission instructions corresponding to time parameters based on the preset address information and preset frame length parameters in memory, and send the transmission instructions to the transmission execution module. Thus, by generating standardized transmission instructions based on preset addresses and frame length parameters, a clearly structured and quickly locatable data analysis foundation is provided to the processing unit.

[0058] In one embodiment, to prevent data loss due to excessively rapid data acquisition, the transmission scheduling module can determine whether the remaining space in the first-in-first-out (FIFO) memory is sufficient to accommodate the target data volume, which is the amount of time parameter data transmitted by the target time measurement unit in the next data frame, before generating the transmission instruction for each data frame. If the target data volume is sufficient, the transmission instruction corresponding to the time parameter is generated based on the preset address information and preset frame length parameter of the memory, and the transmission instruction is sent to the transmission execution module. Thus, by dynamically monitoring the remaining space in the FIFO memory and comparing it with the preset data volume, the generation and transmission of the transmission instruction are intelligently triggered, thereby ensuring a precise match between the data transmission rate and data processing capability, and avoiding the risk of data overflow or loss.

[0059] In this embodiment, the data calculation and storage process is repeated cyclically until all data transmission is complete. The processing unit can determine the completion of a frame of data transmission by querying the status register or waiting for an interrupt, and then read the data from memory for processing.

[0060] The ATE time parameter measurement system disclosed in the above embodiments of this application includes a channel mapping module and at least one time measurement unit. The channel mapping module is used to establish a mapping relationship between a preset number of target data channels among multiple data channels and a target time measurement unit among the at least one time measurement unit. Each target data channel corresponds one-to-one with a target time measurement unit. The target data channels are used to receive signals to be measured, and the preset number is less than or equal to the number of time measurement units. The target time measurement unit is used to receive signals to be measured from the corresponding target data channels and determine the time parameters corresponding to the signals to be measured. Therefore, by dynamically establishing the mapping relationship between target data channels and target time measurement units through the channel mapping module, hardware resources only need to be allocated to the channels actually used, avoiding resource waste from unused channels, thereby significantly improving hardware resource utilization and reducing system costs.

[0061] Reference Figure 7This document illustrates a flowchart of an ATE time parameter measurement method according to an embodiment of this application. This ATE time parameter measurement method can be applied to the aforementioned ATE time parameter measurement system, such as... Figure 7 As shown, the ATE time parameter measurement method may include the following steps: Step 701: Through the channel mapping module, establish a mapping relationship between a preset number of target data channels in multiple data channels and a target time measurement unit in at least one time measurement unit. The target data channels correspond one-to-one with the target time measurement units. The target data channels are used to receive the signal to be measured. The preset number is less than or equal to the number of time measurement units.

[0062] Step 702: Receive the signal to be measured from the corresponding target data channel through the target time measurement unit, and determine the time parameters corresponding to the signal to be measured.

[0063] The specific implementation process and principle of steps 701-702 above can be found in the detailed description of the above embodiments, and will not be repeated here.

[0064] The ATE time parameter measurement method disclosed in the above embodiments of this application dynamically establishes a mapping relationship between the target data channel and the target time measurement unit through a channel mapping module. This means that only hardware resources need to be allocated to the channels actually used, avoiding resource waste of unused channels, thereby greatly improving hardware resource utilization and reducing system costs.

[0065] Furthermore, in one possible implementation of this application embodiment, step 702 includes: sampling the rising edge transition time and falling edge transition time of the waveform of the signal under test to obtain sampling results; and determining the high-level duration and low-level duration corresponding to the signal under test based on the sampling results.

[0066] Therefore, by accurately sampling the edge transition moments of the signal waveform under test and calculating the duration of the level, nanosecond-level precise measurement of signal timing parameters can be achieved, thus providing crucial data support for digital circuit functional verification and performance analysis. The specific implementation process and principles of the above steps can be found in the detailed description of the above embodiments, and will not be repeated here.

[0067] Furthermore, in another possible implementation of this application embodiment, the above-mentioned ATE time parameter measurement system further includes a transmission scheduling module, a first-in-first-out (FIFO) memory, a transmission execution module, a memory, and a processing unit; the method further includes: generating a transmission instruction corresponding to the time parameter through the transmission scheduling module and sending the transmission instruction to the transmission execution module; generating a transmission instruction corresponding to the time parameter through the transmission scheduling module and sending the transmission instruction to the transmission execution module; the transmission execution module responding to the transmission instruction sent by the transmission scheduling module and transmitting the time parameter corresponding to the signal under test in the FIFO memory to the memory; and the processing unit reading the time parameter corresponding to the signal under test from the memory and performing data analysis based on the time parameter corresponding to the signal under test.

[0068] Therefore, through the collaborative work of the transmission scheduling module and the execution module, high-speed automated transfer of time parameters from acquisition and caching to memory is achieved, ensuring real-time storage of time-series data without loss, and thus providing a complete and reliable data foundation for efficient data analysis by the processing unit. The specific implementation process and principles of the above steps can be found in the detailed description of the above embodiments, and will not be repeated here.

[0069] Furthermore, in another possible implementation of this application embodiment, the above-mentioned generation of the transmission instruction corresponding to the time parameter and sending the transmission instruction to the transmission execution module includes: determining whether the remaining space in the first-in-first-out memory is sufficient to accommodate the target data amount, wherein the target data amount is the amount of data of the time parameter transmitted by the target time measurement unit in the next data frame; if it is sufficient to accommodate the target data amount, generating the transmission instruction corresponding to the time parameter according to the preset address information and preset frame length parameter corresponding to the memory, and sending the transmission instruction to the transmission execution module.

[0070] Therefore, by generating standardized transmission instructions based on preset address and frame length parameters, a clear and quickly locatable data analysis foundation is provided for the processing unit. The specific implementation process and principles of the above steps can be found in the detailed description of the above embodiments, and will not be repeated here.

[0071] Furthermore, in another possible implementation of the embodiments of this application, the above-mentioned ATE time parameter measurement system further includes a sampling synchronization module; the above method further includes: sending a synchronization signal to each target time measurement unit through the sampling synchronization module, so that each target time measurement unit synchronously determines the time parameter corresponding to the signal to be measured according to the synchronization signal.

[0072] Therefore, by sending a unified synchronization signal to all target time measurement units through the sampling synchronization module, simultaneous sampling of multiple channels is ensured, achieving a synchronization effect. The specific implementation process and principles of the above steps can be found in the detailed description of the above embodiments, and will not be repeated here.

[0073] Furthermore, in another possible implementation of this application embodiment, before step 701 above, the method further includes: using a processing unit to enable each target data channel by configuring the channel, and determining each target time measurement unit.

[0074] Therefore, by centrally configuring channel enable and resource mapping relationships during the system initialization phase through the processing unit, a hardware foundation is laid for subsequent measurement tasks. The specific implementation process and principles of the above steps can be found in the detailed description of the above embodiments, and will not be repeated here.

[0075] Figure 8 This is a schematic diagram of the structure of the ATE device provided in an embodiment of this application. For example... Figure 8 As shown, the ATE device 800 of this embodiment includes: at least one processor 810 ( Figure 8 The diagram shows only one processor, a memory 820, and a computer program 821 stored in the memory 820 and executable on the at least one processor 810. When the processor 810 executes the computer program 821, it implements the steps in the above-described ATE time parameter measurement method embodiment.

[0076] The ATE device 800 can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. This ATE device may include, but is not limited to, a processor 810 and a memory 820. Those skilled in the art will understand that... Figure 8 This is merely an example of ATE device 800 and does not constitute a limitation on ATE device 800. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0077] The processor 810 may be a central processing unit, or it may be other general-purpose processors, digital signal processors, application-specific integrated circuits, off-the-shelf programmable gate arrays or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0078] In some embodiments, the memory 820 may be an internal storage unit of the ATE device 800, such as a hard disk or memory of the ATE device 800. In other embodiments, the memory 820 may be an external storage device of the ATE device 800, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the ATE device 800. Furthermore, the memory 820 may include both internal and external storage units of the ATE device 800. The memory 820 is used to store the operating system, applications, boot loader, data, and other programs, such as the program code of the computer program. The memory 820 can also be used to temporarily store data that has been output or will be output.

[0079] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0081] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0082] In the embodiments provided in this application, it should be understood that the disclosed apparatus / ATE devices and methods can be implemented in other ways. For example, the apparatus / ATE device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between apparatuses or units may be electrical, mechanical, or other forms.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0085] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0086] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on the ATE device, the ATE device can implement the steps in the various method embodiments described above.

[0087] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An ATE time parameter measurement system, characterized in that, Includes a channel mapping module and at least one time measurement unit; The channel mapping module is used to establish a mapping relationship between a preset number of target data channels in multiple data channels and a target time measurement unit in the at least one time measurement unit, wherein the target data channels correspond one-to-one with the target time measurement units, the target data channels are used to receive the signal to be measured, and the preset number is less than or equal to the number of time measurement units. The target time measurement unit is used to receive the signal to be measured from the corresponding target data channel and determine the time parameter corresponding to the signal to be measured.

2. The system according to claim 1, characterized in that, The time parameters corresponding to the signal under test include the high-level duration and the low-level duration. The target time measurement unit is specifically used for: The rising edge transition time and falling edge transition time of the waveform of the signal under test are sampled to obtain the sampling result; Based on the sampling results, the high-level duration and low-level duration corresponding to the signal under test are determined.

3. The system according to claim 1, characterized in that, The ATE time parameter measurement system also includes a transmission scheduling module, a first-in-first-out memory, a transmission execution module, a memory, and a processing unit; The target time measurement unit is also used to send the time parameters corresponding to the signal to be measured to the first-in-first-out memory; The transmission scheduling module is used to generate a transmission instruction corresponding to the time parameter and send the transmission instruction to the transmission execution module; The transmission execution module is used to respond to the transmission instruction sent by the transmission scheduling module and transmit the time parameter corresponding to the signal to be tested in the first-in-first-out memory to the memory. The processing unit is used to read the time parameters corresponding to the signal under test from the memory and perform data analysis based on the time parameters corresponding to the signal under test.

4. The system according to claim 3, characterized in that, The transmission scheduling module is specifically used for: Based on the preset address information and preset frame length parameter corresponding to the memory, a transmission instruction corresponding to the time parameter is generated, and the transmission instruction is sent to the transmission execution module.

5. The system according to claim 3, characterized in that, The transmission scheduling module is specifically used for: Determine whether the remaining space in the first-in-first-out memory is sufficient to accommodate the target data amount, wherein the target data amount is the amount of data that the target time measurement unit transmits the time parameter in the next data frame; If there is sufficient space to accommodate the target data volume, a transmission instruction corresponding to the time parameter is generated based on the preset address information and preset frame length parameter corresponding to the memory, and the transmission instruction is sent to the transmission execution module.

6. The system according to any one of claims 1-5, characterized in that, The ATE time parameter measurement system also includes a sampling synchronization module; The sampling synchronization module is used to send a synchronization signal to each of the target time measurement units, so that each of the target time measurement units synchronously determines the time parameter corresponding to the signal to be measured according to the synchronization signal.

7. The system according to any one of claims 1-5, characterized in that, The ATE time parameter measurement system also includes a processing unit; The processing unit is configured to enable each of the target data channels by configuring channels, and to determine each of the target time measurement units.

8. A method for measuring ATE time parameters, characterized in that, Applied to the ATE time parameter measurement system as described in any one of claims 1-7, the method comprises: Through the channel mapping module, a mapping relationship is established between a preset number of target data channels in multiple data channels and a target time measurement unit in the at least one time measurement unit. The target data channels correspond one-to-one with the target time measurement units. The target data channels are used to receive the signal to be measured. The preset number is less than or equal to the number of time measurement units. The target time measurement unit receives the signal to be measured from the corresponding target data channel and determines the time parameter corresponding to the signal to be measured.

9. An ATE device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the method as described in claim 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in claim 8.

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