Soa test circuit and test method

Abstract

The application provides a SOA test circuit and a test method. The circuit comprises a test MOS and an auxiliary MOS. The drain end of the test MOS is connected with the drain end of the auxiliary MOS and connected with a first test pad. The substrate end of the test MOS is connected with a second test pad. The source end of the test MOS is connected with a third test pad. The gate end of the test MOS is connected with a fourth test pad. The gate end of the auxiliary MOS is connected with a fifth test pad. The source end of the auxiliary MOS is connected with the substrate end and connected with a sixth test pad. The application adds an auxiliary MOS in the test circuit. When the test MOS is damaged and the branch where the test MOS is located is opened, the branch where the auxiliary MOS is located is still connected, so that the loop where the needle tip with high potential has current flowing through is formed, thereby avoiding the accumulation of electric charge on the needle tip, protecting the needle card from damage, and reducing the high-risk SOA test into a low-risk test.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an SOA test circuit and test method. Background Technology

[0002] When testing a MOS SOA (Safe Operating Area), the Device Under Test (DUT) may eventually burn out and open-circuit. This is because voltage is continuously applied to the pin card, which cannot form a circuit. This makes it easy for static electricity to accumulate on the pin card, eventually leading to increased leakage current and damage to the pin card, resulting in increased leakage current or even burning of the pin. Summary of the Invention

[0003] The purpose of this invention is to provide an SOA test circuit and test method to reduce the risk of SOA testing and protect the pin card from damage.

[0004] To address the aforementioned technical problems, according to a first aspect of the present invention, an SOA test circuit is provided, comprising: a test MOS and an auxiliary MOS, wherein the drain terminal of the test MOS is connected to the drain terminal of the auxiliary MOS and connected to a first test pad, the substrate terminal of the test MOS is connected to a second test pad, the source terminal of the test MOS is connected to a third test pad, the gate terminal of the test MOS is connected to a fourth test pad, the gate terminal of the auxiliary MOS is connected to a fifth test pad, and the source terminal of the auxiliary MOS is connected to the substrate terminal and connected to a sixth test pad.

[0005] Optionally, in the test chip, the auxiliary MOS is arranged adjacent to the test MOS.

[0006] Optionally, when testing the auxiliary MOS, the test MOS is used as the auxiliary MOS.

[0007] Optionally, a scanning voltage Vd is applied to the first test pad, a 0V voltage is applied to the second and third test pads, a fixed voltage Vg1 is applied to the fourth test pad, a fixed voltage Vg2 is applied to the fifth test pad, and a 0V voltage is applied to the sixth test pad.

[0008] To solve the above-mentioned technical problems, according to a second aspect of the present invention, an SOA testing method is provided, which uses the SOA testing circuit as described above for testing. The testing method includes: using multiple source test units connected to multiple test pads through probes on a pin card, and providing different voltages to different test pads to measure current.

[0009] Optionally, the source test unit, the probes on the pin card, and the test pads correspond one-to-one.

[0010] Optionally, a first source test unit provides a scanning voltage Vd to the first test pad, a second source test unit provides a 0V voltage to the second test pad, a third source test unit provides a 0V voltage to the third test pad, a fourth source test unit provides a fixed voltage Vg1 to the fourth test pad, a fifth source test unit provides a fixed voltage Vg2 to the fifth test pad, and a sixth source test unit provides a 0V voltage to the sixth test pad.

[0011] Optionally, a fixed voltage Vg2 keeps the auxiliary MOS in the on state.

[0012] Optionally, under the same fixed voltage Vg1, the voltage applied to the drain of the test MOS is linearly increased from 0V to Vd, and the voltage of each test pad is measured; the fixed voltage Vg1 is changed, and the voltage applied to the drain of the test MOS is linearly increased from 0V to Vd, and the voltage of each test pad is measured.

[0013] Optionally, the voltage applied to the drain terminal of the test MOS is the drain voltage, and the sum of the currents at the source terminal and the substrate terminal of the test MOS is the drain current of the test MOS.

[0014] In summary, the SOA test circuit and method provided by this invention include a test MOS and an auxiliary MOS. The drain of the test MOS is connected to the drain of the auxiliary MOS and connected to a first test pad. The substrate of the test MOS is connected to a second test pad. The source of the test MOS is connected to a third test pad. The gate of the test MOS is connected to a fourth test pad. The gate of the auxiliary MOS is connected to a fifth test pad. The source of the auxiliary MOS is connected to the substrate and connected to a sixth test pad. Multiple source test units are connected to multiple test pads through probes on a pin card, providing different voltages to different test pads to measure current. An unexpected benefit of this invention is that by adding an auxiliary MOS to the test circuit, even if the test MOS is damaged and its branch is open, the branch containing the auxiliary MOS remains connected. This ensures that the high-potential probe tip has a current flow path, preventing charge accumulation at the probe tip, protecting the pin card from damage, and reducing high-risk SOA testing to low-risk testing.

[0015] An unexpected benefit of this invention is that it utilizes the MOS adjacent to the test MOS on the test chip as an auxiliary MOS to form the branch resistor, or selects the MOS near the test MOS on the test chip as an auxiliary MOS. This eliminates the need for external resistors, equipment modifications, and additional resistors on the layout, saving test time and improving test efficiency. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of an SOA test circuit provided in one embodiment.

[0017] Figure 2 This is a schematic diagram of testing an SOA test circuit according to an embodiment.

[0018] Figure 3 This is a schematic diagram of an SOA test circuit provided in another embodiment.

[0019] Figure 4 This is a schematic diagram of testing an SOA test circuit according to another embodiment.

[0020] Figure 5 This is a schematic diagram of an SOA test circuit provided in an embodiment of the present invention.

[0021] Figure 6 This is a schematic diagram of testing an SOA test circuit according to an embodiment of the present invention.

[0022] Figure 7 This is a schematic diagram of the drain voltage and current relationship of a test MOS provided in an embodiment of the present invention. Detailed Implementation

[0023] Figure 1 This is a schematic diagram of an SOA test circuit provided in one embodiment. Please refer to it. Figure 1 As shown, the SOA test circuit includes a test MOS (M1). The MOS (M1) includes a drain terminal (Drain1), a source terminal (Source1), a gate terminal (Gate1), and a substrate terminal (Bulk1). The drain terminal (Drain1) is connected to the first test pad P1, the substrate terminal (Bulk1) is connected to the second test pad P2, the source terminal (Source1) is connected to the third test pad P3, and the gate terminal (Gate1) is connected to the fourth test pad P4. During testing, a sweep voltage Vd is applied to the first test pad P1, a 0V voltage (i.e., Vb=0, Vs=0) is applied to the second test pad P2 and the third test pad P3, and a fixed voltage Vg is applied to the fourth test pad P4. Simultaneously, the currents Id of the first test pad P1, Ib of the second test pad P2, Is of the third test pad P3, and Ig of the fourth test pad are measured.

[0024] Figure 2 This is a schematic diagram illustrating the testing of an SOA test circuit according to one embodiment. Please refer to it. Figure 2 As shown, for Figure 1When testing the SOA test circuit shown, multiple source measure units (SMUs) are connected to the test pads via probes on the pin card. For example, the first source measure unit SMU1 is connected to the first test pad P1, the second source measure unit SMU2 is connected to the second test pad P2, the third source measure unit SMU3 is connected to the third test pad P3, and the fourth source measure unit SMU4 is connected to the fourth test pad P4.

[0025] The first source test unit SMU1 applies a sweep voltage Vd (Vd sweep, meaning the voltage varies according to a preset pattern, for example, starting from 0V and increasing by 1V each time, up to 30V) to the first test pad P1. The second source test unit SMU2 applies a 0V voltage to the second test pad P2. The third source test unit SMU3 applies a 0V voltage to the third test pad P3. The fourth source test unit SMU4 applies a fixed voltage Vg to the fourth test pad P4. Simultaneously, the current Id of the first test pad P1, the current Ib of the second test pad P2, the current Is of the third test pad P3, and the current Ig of the fourth test pad are measured to obtain the relationship between leakage voltage and leakage current, thus deriving the SOA (Safe Operating Area).

[0026] However, the MOS will eventually burn out and open circuit during testing. Since the voltage is constantly applied to the pin card, a circuit cannot be formed, making it easy for static electricity to accumulate on the pin card. This eventually leads to increased leakage current in the pin card, damage to the pin card, and situations such as increased leakage current or burning of the pin.

[0027] To address the above issues, a parallel circuit is typically added to the test circuit. Figure 3 This is a schematic diagram of an SOA test circuit provided in another embodiment. Please refer to it. Figure 3As shown, a fifth test pad P5 is added. A resistor r is added between the first test pad P1 and the fifth test pad P5. The drain terminal Drain1 of the test MOS (M1) is connected to the first test pad P1 and simultaneously connected to one side of the resistor r. The other side of the resistor r is connected to the fifth test pad P5. During testing, a sweep voltage Vd is applied to the first test pad P1, a 0V voltage (i.e., Vb=0, Vs=0) is applied to the second test pad P2 and the third test pad P3, a fixed voltage Vg is applied to the fourth test pad P4, and a 0V voltage (i.e., Vr=0) is applied to the fifth test pad P5. Simultaneously, the current Id of the first test pad P1, the current Ib of the second test pad P2, the current Is of the third test pad P3, the current Ig of the fourth test pad, and the current Ir of the fifth test pad P5 are measured.

[0028] Figure 4 This is a schematic diagram illustrating the testing of the SOA test circuit according to another embodiment. Please refer to it. Figure 4 As shown, for Figure 3 When testing the SOA test circuit shown, multiple source measure units (SMUs) are connected to the test pads via probes on the pin card. For example, the first source measure unit SMU1 is connected to the first test pad P1, the second source measure unit SMU2 is connected to the second test pad P2, the third source measure unit SMU3 is connected to the third test pad P3, the fourth source measure unit SMU4 is connected to the fourth test pad P4, and the fifth source measure unit SMU5 is connected to the fifth test pad P5.

[0029] The first source test unit SMU1 applies a sweep voltage Vd (Vd sweep, meaning the voltage varies according to a preset pattern, for example, starting from 0V and increasing by 1V each time, up to 30V) to the first test pad P1. The second source test unit SMU2 applies a 0V voltage to the second test pad P2. The third source test unit SMU3 applies a 0V voltage to the third test pad P3. The fourth source test unit SMU4 applies a fixed voltage Vg to the fourth test pad P4. The fifth source test unit SMU5 applies a 0V voltage to the fifth test pad P5. Simultaneously, the current on the five test pads is measured to obtain the relationship between leakage voltage and leakage current, thus determining the SOA (Safe Operating Area).

[0030] When the test MOS branch becomes open due to the burnout of the test MOS, the high-voltage probe (such as the probe connected to the first test pad P1) still has current flowing out through the parallel branch (the branch where the resistor r is located), that is, there is a charge flow path, so there will be no charge accumulation at the tip of the probe, thus protecting the pin card.

[0031] However, as Figure 3 The SOA test circuit shown requires a resistor r to be connected in parallel at the equipment end, which requires modification of the equipment or addition of a resistor element to the layout, increasing the complexity of the layout.

[0032] To address the aforementioned issues, research has revealed that an auxiliary MOS can be added as a branch resistor. This means that the MOS next to the test MOS can be used as a branch resistor, eliminating the need for external resistors or additional resistors on the layout.

[0033] Further research reveals that this invention provides an SOA test circuit, comprising: a test MOS and an auxiliary MOS, wherein the drain of the test MOS is connected to the drain of the auxiliary MOS and connected to a first test pad, the substrate of the test MOS is connected to a second test pad, the source of the test MOS is connected to a third test pad, the gate of the test MOS is connected to a fourth test pad, the gate of the auxiliary MOS is connected to a fifth test pad, and the source of the auxiliary MOS is connected to the substrate and connected to a sixth test pad.

[0034] Accordingly, the present invention also provides an SOA testing method, comprising: using multiple source test units connected to multiple test pads through probes on a pin card, and providing different voltages to different test pads to measure current.

[0035] The SOA test circuit and method provided by this invention add an auxiliary MOS to the test circuit. When the test MOS is damaged and its branch is open, the branch containing the auxiliary MOS remains connected, ensuring a current flow path for the high-potential probe tip. This prevents charge accumulation at the probe tip, protects the probe card from damage, and reduces the high-risk SOA test to a low-risk test. Furthermore, the MOS next to the test MOS on the test chip is used as an auxiliary MOS to form the branch resistor. This eliminates the need for external resistors, equipment modifications, and additional resistors on the layout, saving test time and improving test efficiency.

[0036] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0037] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.

[0038] Figure 5 This is a schematic diagram of an SOA test circuit provided in an embodiment of the present invention. Please refer to it. Figure 5 As shown, the SOA test circuit provided in this embodiment includes: a test MOS (M1) and an auxiliary MOS (M2), wherein the drain terminal Drain1 of the test MOS is connected to the drain terminal Drain2 of the auxiliary MOS and connected to the first test pad P1, the substrate terminal Bulk1 of the test MOS is connected to the second test pad P2, the source terminal Source1 of the test MOS is connected to the third test pad P3, the gate terminal Gate1 of the test MOS is connected to the fourth test pad P4, the gate terminal Gate2 of the auxiliary MOS is connected to the fifth test pad P5, and the source terminal Source2 of the auxiliary MOS is connected to the substrate terminal Bulk2 and connected to the sixth test pad P6.

[0039] In one embodiment of the present invention, on the test chip, the auxiliary MOS is arranged adjacent to the test MOS, that is, there are multiple MOS on the test chip. When testing one of the MOS, the other MOS adjacent to it is used as the auxiliary MOS, or any MOS near the test MOS is selected as the auxiliary MOS.

[0040] In one embodiment of the present invention, when testing the auxiliary MOS, the test MOS is used as the auxiliary MOS. That is, when testing two MOS on the test chip, the second MOS is used as the auxiliary MOS when the first one is tested (as the test MOS), and the first MOS is used as the auxiliary MOS when the second one is tested (as the test MOS). In another embodiment of the present invention, when testing the auxiliary MOS, the MOS on the other side of the auxiliary MOS is used as the auxiliary MOS. That is, when the test chip has multiple MOS, the MOS next to one of the MOS is used as the auxiliary MOS when testing one of the MOS, and then when testing the auxiliary MOS (i.e., the auxiliary MOS is used as the test MOS), the third MOS next to the auxiliary MOS is selected as the auxiliary MOS.

[0041] It should be noted that the distinction between test MOS and auxiliary MOS is to illustrate the role of MOS in test circuits. A single MOS can serve as both a test MOS and an auxiliary MOS.

[0042] Please refer to Figure 5 As shown, during testing, a scanning voltage Vd (i.e., Vdsweep, meaning the voltage varies according to a preset pattern, for example, starting from 0V and increasing by 10V each time, up to 120V) is applied to the first test pad P1. A voltage of 0V (i.e., Vb1=0, Vs1=0) is applied to the second test pad P2 and the third test pad P3. A fixed voltage Vg1 is applied to the fourth test pad P4, a fixed voltage Vg2 is applied to the fifth test pad P5, and a voltage of 0V (i.e., Vs2=Vb2=0) is applied to the sixth test pad P6. Simultaneously, the currents Id of the first test pad P1, Ib1 of the second test pad P2, Is1 of the third test pad P3, Ig1 of the fourth test pad, Ig2 of the fifth test pad P5, and Is2 and Ib2 (Is2=Ib2) of the sixth test pad P6 are measured.

[0043] By applying voltage to each test pad of the SOA test circuit and measuring the current of each test pad, the SOA of the test MOS can be obtained.

[0044] In this embodiment, an auxiliary MOS is added to the SOA test circuit. When the test MOS is damaged and its branch is open, the branch containing the auxiliary MOS remains connected. This ensures that the high-potential probe tip (e.g., the probe connected to the first test pad P1) has a current flow path, preventing charge accumulation at the probe tip, protecting the probe card from damage, and reducing the high-risk SOA test to a low-risk test. Furthermore, using a MOS adjacent to the test MOS on the test chip as an auxiliary MOS to form the branch resistor, or selecting a MOS near the test MOS on the test chip as an auxiliary MOS, eliminates the need for external resistors, equipment modifications, and additional resistors on the layout, saving test time and improving test efficiency.

[0045] Accordingly, the present invention also provides an SOA testing method, which uses the SOA testing circuit described above for testing. The testing method includes: using multiple source test units connected to multiple test pads through probes on a pin card, and providing different voltages to different test pads to measure current.

[0046] Figure 6 This is a schematic diagram illustrating the testing of an SOA test circuit according to an embodiment of the present invention. Please refer to it. Figure 6 As shown, multiple source test units are connected to test pads via probes on a pin card. In one embodiment, the source test units, probes on the pin card, and test pads correspond one-to-one. The first source test unit SMU1 is connected to the first test pad P1, the second source test unit SMU2 is connected to the second test pad P2, the third source test unit SMU3 is connected to the third test pad P3, the fourth source test unit SMU4 is connected to the fourth test pad P4, the fifth source test unit SMU5 is connected to the fifth test pad P5, and the sixth source test unit SMU6 is connected to the sixth test pad P6.

[0047] The first source test unit SMU1 provides a sweep voltage Vd to the first test pad P1. The second source test unit SMU2 applies a 0V voltage to the second test pad P2. The third source test unit SMU3 applies a 0V voltage to the third test pad P3. The fourth source test unit SMU4 applies a fixed voltage Vg1 to the fourth test pad P4. The fifth source test unit SMU5 applies a fixed voltage Vg2 to the fifth test pad P5. The sixth source test unit SMU6 provides a 0V voltage to the sixth test pad P6. The current on each test pad is then measured to obtain the relationship between leakage voltage and leakage current, thus determining the SOA (Safe Operating Area).

[0048] In this embodiment, a fixed voltage Vg2 keeps the auxiliary MOS in a conducting state; that is, the magnitude of the fixed voltage Vg2 is required to keep the auxiliary MOS in a conducting state. Under the same fixed voltage Vg1, the voltage applied to the drain of the test MOS increases linearly from 0V to Vd, and the voltage of each test pad is measured. Then, the fixed voltage Vg1 is changed, and the voltage applied to the drain of the test MOS increases linearly from 0V to Vd, and the voltage of each test pad is measured again. This yields a curve showing the relationship between the drain voltage Vd and the drain current Id of the test MOS under different fixed voltages Vg1.

[0049] The voltage applied to the first test pad P1 is the drain voltage Vd, and the drain current Id is the sum of the currents of the second test pad P2 and the third test pad P3, that is, the sum of the currents of the substrate end Bulk1 and the source end Source1, Id=Ib1+Is1.

[0050] Figure 7 This is a schematic diagram illustrating the drain voltage-current relationship of a test MOS according to an embodiment of the present invention. Please refer to it. Figure 7 As shown, by testing the SOA test circuit, the relationship curves between the drain current Id and the drain voltage Vd under different fixed voltages Vg1 (i.e., the gate voltage of the test MOS) can be obtained.

[0051] In the SOA testing method provided in this embodiment, due to the auxiliary MOS configuration, even if the test MOS is damaged and its branch is open, the branch containing the auxiliary MOS remains connected. This ensures that the high-potential probe tip has a current flow path, preventing charge accumulation at the tip and protecting the probe card from damage. This reduces the high-risk SOA test to a low-risk test. Furthermore, by using the MOS next to the test MOS on the test chip as an auxiliary MOS to form the branch resistance, no external resistors are needed, no equipment modifications are required, and no additional resistors are added to the layout, saving testing time and improving testing efficiency.

[0052] In summary, the SOA test circuit and method provided by this invention include a test MOS and an auxiliary MOS. The drain of the test MOS is connected to the drain of the auxiliary MOS and connected to a first test pad. The substrate of the test MOS is connected to a second test pad. The source of the test MOS is connected to a third test pad. The gate of the test MOS is connected to a fourth test pad. The gate of the auxiliary MOS is connected to a fifth test pad. The source of the auxiliary MOS is connected to the substrate and connected to a sixth test pad. Multiple source test units are connected to multiple test pads through probes on a pin card, providing different voltages to different test pads to measure current. An unexpected benefit of this invention is that by adding an auxiliary MOS to the test circuit, even if the test MOS is damaged and its branch is open, the branch containing the auxiliary MOS remains connected. This ensures that the high-potential probe tip has a current flow path, preventing charge accumulation at the probe tip, protecting the pin card from damage, and reducing high-risk SOA testing to low-risk testing.

[0053] An unexpected benefit of this invention is that it utilizes the MOS adjacent to the test MOS on the test chip as an auxiliary MOS to form the branch resistor, or selects the MOS near the test MOS on the test chip as an auxiliary MOS. This eliminates the need for external resistors, equipment modifications, and additional resistors on the layout, saving test time and improving test efficiency.

[0054] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A SOA test circuit, characterized by, The application relates to a test MOS and an auxiliary MOS, wherein the drain end of the test MOS is connected with the drain end of the auxiliary MOS and connected with a first test pad, the substrate end of the test MOS is connected with a second test pad, the source end of the test MOS is connected with a third test pad, the gate end of the test MOS is connected with a fourth test pad, the gate end of the auxiliary MOS is connected with a fifth test pad, and the source end of the auxiliary MOS is connected with the substrate end and connected with a sixth test pad; the auxiliary MOS is arranged adjacent to the test MOS on a test chip; a fixed voltage Vg2 is applied to the fifth test pad, and the fixed voltage Vg2 makes the auxiliary MOS in a conducting state; when the test MOS is damaged and the branch in which the test MOS is located is opened, the branch in which the auxiliary MOS is located can still be kept connected. A scanning voltage Vd is applied to the first test pad, 0V is applied to the second test pad and the third test pad, a fixed voltage Vg1 is applied to the fourth test pad, and 0V is applied to the sixth test pad.

2. The SOA test circuit of claim 1, wherein, The test method comprises the following steps: connecting the test pads with probes on a needle card by using a plurality of source test units, and providing different voltages to different test pads to measure the current.

3. A method of testing SOAs, characterized by, The source test units, the probes on the needle card and the test pads are in one-to-one correspondence.

4. The SOA testing method of claim 3, wherein, A first source test unit is used to provide the scanning voltage Vd to the first test pad, a second source test unit is used to provide 0V to the second test pad, a third source test unit is used to provide 0V to the third test pad, a fourth source test unit is used to provide the fixed voltage Vg1 to the fourth test pad, a fifth source test unit is used to provide the fixed voltage Vg2 to the fifth test pad, and a sixth source test unit is used to provide 0V to the sixth test pad.

5. The SOA testing method of claim 3, wherein, Under the same fixed voltage Vg1, the voltage applied to the drain end of the test MOS is linearly increased from 0V to Vd, and the voltages of the test pads are measured; the fixed voltage Vg1 is changed, the voltage applied to the drain end of the test MOS is linearly increased from 0V to Vd, and the voltages of the test pads are measured.

6. The SOA testing method of claim 5, wherein, The voltage applied to the drain end of the test MOS is a drain end voltage, and the sum of the current of the source end and the substrate end of the test MOS is a drain end current of the test MOS.

7. The SOA testing method of claim 5, wherein, ​

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