Multi-line pattern result matching method and chip testing machine

Abstract

The invention relates to a multi-line pattern result matching method and a chip testing machine, and the method comprises the steps: determining a corresponding mode setting parameter according to a pattern file when an upper computer carries a matching microinstruction in the pattern file; the upper computer issues the pattern file and the mode setting parameters to a test unit in the test board card; the test unit extracts a matching microinstruction and a plurality of rows of expected patterns in the pattern file, circularly multiplexes the plurality of rows of expected patterns according to the matching microinstruction, and obtains a pin matching result obtained by matching an output signal of the device to be tested; and the test unit performs corresponding matching completion processing according to the mode setting parameters and the pin matching result. Compared with the mode that the expected pattern needs to be read for matching each time in the matching process, the time delay is effectively shortened, and the testing efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a method for matching results of multiple patterns and a chip testing machine. Background Technology

[0002] During the testing of the Device Under Test (DUT), the test machine needs to match the sequence information output by the DUT and process whether the matching sequence is successful within a specified time. The operation ends upon success or timeout. This process constitutes one MatchLoop operation, and multiple MatchLoop operations can be supported within a single test item. Traditional test machine matching methods retrieve the corresponding target test vector (pattern) line by line from memory according to microinstructions. Often, one target test vector corresponds to multiple matching operations, and each time a matching operation is performed, the target test vector needs to be retrieved from memory, resulting in significant latency and low testing efficiency. Summary of the Invention

[0003] Therefore, it is necessary to provide a multi-line pattern result matching method and chip testing machine that can improve testing efficiency in response to the above problems.

[0004] The first aspect of this application provides a method for matching results of multi-line patterns, including:

[0005] When the host computer carries matching micro-instructions in the pattern file, it determines the corresponding mode setting parameters according to the pattern file.

[0006] The host computer sends the pattern file and mode setting parameters to the test unit in the test board.

[0007] The test unit extracts the matching micro-instructions and multiple lines of expected patterns from the pattern file, and repeatedly reuses the multiple lines of expected patterns according to the matching micro-instructions to obtain the pin matching result obtained by matching the output signal of the device under test.

[0008] The test unit performs the corresponding matching process based on the mode setting parameters and the pin matching result.

[0009] A second aspect of this application provides a chip testing machine, including a host computer, a test board, and a communication board. The test board includes multiple test units, each test unit is connected to the host computer through the communication board, and the channel of each test unit is connected to the pin of the device under test of the corresponding site. The chip testing machine performs multi-line pattern matching processing according to the above method.

[0010] The aforementioned multi-line pattern matching method and chip testing machine, when the host computer carries matching micro-instructions in the pattern file, determines the corresponding mode setting parameters based on the pattern file; the host computer sends the pattern file and mode setting parameters to the test unit in the test board; the test unit extracts the matching micro-instructions and multi-line expected patterns from the pattern file, and repeatedly reuses the multi-line expected patterns according to the matching micro-instructions to obtain the pin matching results obtained by matching the output signal of the device under test; the test unit performs corresponding matching completion processing according to the mode setting parameters and pin matching results. The test unit uses the matching micro-instructions to repeatedly reuse multi-line expected patterns to obtain the pin matching results obtained by matching the output signal of the device under test. Compared to reading the expected pattern for matching each time during the matching process, this effectively reduces latency and improves testing efficiency. Attached Figure Description

[0011] Figure 1 This is a flowchart of a method for matching results of multiple patterns in one embodiment;

[0012] Figure 2 This is a schematic diagram of the structure of the host computer, communication board, and test unit in one embodiment;

[0013] Figure 3 This is a schematic diagram illustrating the correspondence between the site associated with the test unit and the test unit channel in synchronous mode in one embodiment.

[0014] Figure 4 This is a schematic diagram illustrating the correspondence between the site associated with the test unit and the test unit channel in asynchronous mode in one embodiment.

[0015] Figure 5 This is a schematic diagram of matching microinstructions in one embodiment. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0017] It is understood that the term "connection" in the following embodiments should be interpreted as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., transmit electrical signals or data to each other. It should also be understood that the terms "comprising / including" or "having," etc., specify the presence of the stated features, integrals, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integrals, steps, operations, components, parts, or combinations thereof.

[0018] In one embodiment, such as Figure 1 As shown, a method for matching results of multi-line patterns is provided, including:

[0019] Step S110: When the host computer carries matching micro-instructions in the pattern file, it determines the corresponding mode setting parameters according to the pattern file.

[0020] The pattern (vector) file can be written by testers or users. The content of the pattern file will differ for different test items. Specifically, the pattern file includes row vectors, matching micro-instructions, and the desired pattern. It may also include timing parameters corresponding to the matching micro-instructions (i.e., timing information of the excitation pattern / desired pattern in the waveform output to the device under test (DUT)). Furthermore, the pattern file may include other types of micro-instructions (such as normal micro-instructions) along with their corresponding desired patterns and timing parameters. Matching micro-instructions and other types of micro-instructions can be in one or more groups to achieve one or more match operations or other corresponding operations.

[0021] The matching microinstructions can specifically include the MatchStart, MatchLoop, and EndMatch microinstructions. The operand of the MatchStart microinstruction (set from 1 to 16383, e.g., 8000) serves as the first-level loop count, and the operand of the MatchLoop microinstruction (set from 1 to 65535, e.g., 8) serves as the inner second-level loop count. One execution from MatchStart to MatchLoop, and then the second-level loop from MatchLoop to EndMatch, constitutes one complete matching loop (MatchStart loop). The site identifier is the unique identifier for each site (workstation). Each site corresponds to one Device Under Test (DUT), or in other words, each site carries one DUT. The DUT can be a chip or other electronic device that needs to be tested. For example... Figure 2As shown, the test board 300 can specifically be a digital board, containing one or more test units 310. The test unit 310 can be a functional module built based on programmable logic chips such as FPGAs to perform multi-line pattern matching operations. The test board 300 may also include a PE (Pin Electronics) chip 400. Each channel of the test unit 310 is connected to a pin (pin or terminal) of the corresponding device under test (DUT) on the site via the corresponding PE chip 400. Each channel of the test unit 310 corresponds to a pin of the DUT. In this application, the pin matching result can also be understood as the channel matching result of the test unit. The mode setting parameters are used to indicate the operating mode of the test unit 310. The operating mode will vary depending on the connection relationship between the test unit 310 and the site. The pins that the test unit matches on the site for the DUT can be understood as matching terminals or matching pins.

[0022] Specifically, the operating modes include synchronous and asynchronous modes. In synchronous mode, channels of the same test unit 310 are connected to pins of the device under test (DUT) at the same or different sites, and pins of the DUT at the same site are connected to channels of the same or different test units. For example... Figure 3 The diagram illustrates two scenarios in synchronous mode. First, taking test unit 310, which includes units FE0 and FE1, as an example, unit FE0 can connect to pins 01 to 03 of the device under test (DUT0) on site 0, and pins 01 to 03 of the device under test (DUT1) on site 1. Unit FE1 can connect to pins 01 to 03 of the device under test (DUT2) on site 2, and pins 01 to 03 of the device under test (DUT3) on site 3. Second, pin 01 of the device under test (DUT0) on site 0 can be connected to unit FE0, and pin 02 of the device under test (DUT0) on site 0 can be connected to unit FE1. In asynchronous mode, test unit 310 and sites are in a one-to-one correspondence; pins of the devices under test (DUTs) on the same site are connected to channels of the same test unit 310. For example... Figure 4As shown, taking the test unit 310, which includes units FE0 to FE3, as an example, unit FE0 corresponds to pins pin01 to pin03 of the device under test (DUT0) on site 0, unit FE1 corresponds to pins pin01 to pin03 of the device under test (DUT1) on site 1, unit FE2 corresponds to pins pin01 to pin03 of the device under test (DUT2) on site 2, and unit FE3 corresponds to pins pin01 to pin03 of the device under test (DUT3) on site 3.

[0023] After connecting the Device Under Test (DUT) on each site to the test unit 310 according to actual testing needs, the tester imports the corresponding pattern file to the host computer 100. When the host computer detects that the pattern file contains a matching micro-instruction (only one of the MatchStart, MatchLoop, and EndMatch micro-instructions needs to be detected, for example, if the MatchStart micro-instruction is detected), it analyzes whether the matching pins of the DUT on each site are connected to the same test unit 310 based on the test unit mapping parameters and the pattern file. Each site is connected to a different test unit 310. If this condition is met, it is in asynchronous mode; otherwise, it is in synchronous mode, and the corresponding mode setting parameters are obtained. The test unit mapping parameters characterize the correspondence between the sites associated with the test units 310 in different test boards 300 and the test unit channels.

[0024] The test unit mapping parameters specifically include the required test board slot number, test unit number, and the correspondence between site and test unit channel. One site corresponds to one device under test (DUT). The host computer 100, combining the test unit mapping parameters and the pin information in the pattern file, determines whether all pins of the DUT on each site are connected to the same test unit 310, and whether each site is connected to a different test unit 310. If this condition is met, it is considered asynchronous mode; otherwise, it is considered synchronous mode. This determines the mode setting parameters. For example, the expected pattern in the pattern file corresponds to the pin information of the DUT to determine the corresponding test unit channel. Then, based on the correspondence between test unit channels and sites, the correspondence between each test unit 310 and its associated site is determined, thus determining the mode setting parameters.

[0025] Specifically, the test board driver of the host computer 100 detects whether all pins of the device under test (DUT) on each site are connected to the same test unit 310, and whether the test units 310 connected to each site are different. If the test board driver of the host computer 100 determines that the test board meets this condition, it is considered to be in asynchronous mode; otherwise, it is considered to be in synchronous mode, thus determining the mode setting parameters. When running the pattern file of the corresponding test item, all test units 310 in the test board 300 are either all in synchronous mode or all in asynchronous mode. For example, when running the pattern file of the current test item, all test units 310 of each test board 300 can be in asynchronous mode, and when running the pattern file of the next test item, all test units 310 of each test board 300 can become synchronous mode.

[0026] It should be noted that all pins mentioned in this application refer to the pins / pins of the device under test (DUT) that need to be matched. The pins that need to be matched are determined by the expected pattern and its corresponding pin information in the pattern file. The pin information refers to the pin number on the DUT. The site identifier is used to enable the site that needs to be matched. The site identifier can be resolved from the test board slot number, test unit number, and the correspondence between the site and the test unit channel. Alternatively, the site identifier can be set separately on the host computer.

[0027] Step S120: The host computer sends the pattern file and mode setting parameters to the test units in the test board. Specifically, the host computer 100 communicates with the communication board 200 and transmits the pattern file and mode setting parameters to each test unit 310 in the test board 300 through the communication board 200. Further, if each test unit 310 is in synchronous mode, the host computer 100 also sends the test unit mapping parameters to the communication board 200.

[0028] In one embodiment, step S120 includes: the host computer sending mode setting parameters and a pattern file to the test unit; the test unit is configured 310 to: determine the working mode according to the mode setting parameters.

[0029] Continue to refer to Figure 2The host computer 100 configures the mode register in the test unit 310 by sending mode setting parameters through the communication board 200, for example, 1 for asynchronous mode and 0 for synchronous mode. It should be noted that multiple test units 310 within a single test board 300 can be configured in parallel to ensure that each test unit is in the same working mode. The host computer 100 also sends a pattern file to the storage module 311 of the test unit 310 through the communication board 200. The test unit 310 obtains the working mode according to the mode setting parameters in the mode register and calls the pattern file in the storage module 311 for a match operation. The storage module 311 can be RAM or other types of memory. In other embodiments, the host computer 100 can also transmit the mode setting parameters to the test unit 310 transparently through the communication board 200, and the test unit 310 directly determines the working mode.

[0030] Furthermore, in synchronous mode, the host computer 100 also sends the test unit mapping parameters to the communication board 200, so that the communication board 200 knows the mapping relationship between the site used for this matching and each channel of each test unit 310 on the corresponding test board 300, thereby determining whether each site has been successfully matched. By configuring the test unit mapping parameters on the communication board 200, and using the communication board 200 to receive the pin matching results sent by each test unit 310, converting them into site matching results, and detecting whether the pin matching is complete, it can support the joint matching of different test boards 300 (e.g., 4 or 8 test boards 300) under one test item, expanding the number of DUTs that can be tested in parallel, that is, it can be expanded to more sites.

[0031] Step S130: The test unit extracts the matching micro-instructions and multi-line expected patterns from the pattern file, and repeatedly reuses the multi-line expected patterns according to the matching micro-instructions to obtain the pin matching result obtained by matching the output signal of the device under test.

[0032] Specifically, the device under test (DUT) can output a signal based on a desired pattern. In other embodiments, it can also output a signal after power-on, i.e., the actual output level. After receiving the pattern file and mode setting parameters, the test unit 310 can extract the matching micro-instructions and the desired pattern from the pattern file and perform a matching operation after receiving the matching start command from the host computer 100. Specifically, the test unit 310 can configure the PE chip 400 by cyclically multiplexing multiple lines of the desired pattern according to the matching micro-instructions, receive the response pattern returned by the PE chip 400 after comparing the output signal of the DUT with the desired pattern, and analyze it to obtain the pin matching result of the DUT. The pin matching result refers to a pin matching success flag or a pin matching failure flag; a pin matching success flag can be represented by 1, and a pin matching failure flag can be represented by 0. In other embodiments, the test unit 310 may also include the comparison function of the PE chip 400. For example, the PE chip 400 simply transmits the output signal of the device under test (DUT) to the test unit 310. The test unit 310 compares and matches the expected pattern of multiple rows with the output signal of the DUT by cyclically multiplexing the expected pattern, and analyzes to obtain the pin matching result of the DUT.

[0033] It should be noted that both the expected pattern and the response pattern belong to the narrow sense of pattern, i.e., test vector. The expected pattern can be a sequence of HHLLX (H represents the expected input high level, L represents the expected input low level, and X represents that the input level is not important). The expected pattern can also include VOH, i.e., the expected high level output of the device under test (DUT), and VOL, i.e., the expected low level output of the DUT. The response pattern can be a sequence of 01010 (or the comparison result between the DUT output signal and the expected pattern). This is only an explanation of the pattern; the expected pattern and response pattern can be represented in other ways without restriction. Of course, if the test unit 310 performs other non-matching operations, it sends an excitation pattern to the DUT, which can be a sequence of 01010.

[0034] Taking the MatchStart, MatchLoop, and EndMatch micro-instructions as an example, the test unit 310 uses a two-level nested approach to cyclically call multiple lines of expected patterns to obtain the response pattern after matching the output signal of the device under test (DUT). By using the match micro-instructions to cyclically reuse multiple lines of expected patterns, the latency is effectively reduced compared to reading the expected pattern for matching each time during the matching process. For ease of understanding, the following explanation will focus on the test unit 310 configuring the PE chip 400 according to the cyclic reuse of multiple lines of expected patterns based on the match micro-instructions, receiving the response pattern returned by the PE chip 400 after comparing the output signal of the DUT with the expected pattern, and analyzing the pin matching result of the DUT.

[0035] In one embodiment, the pattern file further includes row vectors and timing parameters corresponding to matching microinstructions. The timing parameters refer to the timing parameters of the expected pattern. Multiple lines of the response pattern are sampled at the corresponding times of the timing parameters, which refer to positions such as 10%, 50%, and 100% of the period of the timing parameters. Step S130 includes steps 131 and 132.

[0036] Step 131: The test unit extracts the matching microinstructions, row vectors, expected patterns, and timing parameters from the pattern file. Following the order of the row vectors, it iteratively reuses multiple rows of expected patterns and timing parameters based on the matching microinstructions to configure the PE chip. Specifically, the test unit iteratively calls multiple rows of expected patterns and corresponding timing parameters in a two-level nested manner according to the order of the row vectors and the matching microinstructions; it then configures the PE chip based on the called multiple rows of expected patterns and corresponding timing parameters.

[0037] Specifically, such as Figure 2As shown, the cache module 313 can be a FIFO (First-In-First-Out) or other type of cache module. The microinstruction module 312 in the test unit 310 can extract the matching microinstructions, row vectors, expected patterns, and timing parameters corresponding to the matching microinstructions from the pattern file in the storage module 311, and send them to the cache module 313 for caching. The test unit 310 obtains the matching microinstructions, expected patterns, and timing parameters from the cache module 313 and caches them in its internal vector cache module 3141. The test unit 310 reads the matching microinstructions from the vector cache module 3141 in the order of the row vectors, and uses a two-level nested approach to iteratively call multiple rows of expected patterns and corresponding timing parameters in the vector cache module 3141. The test unit 310 performs pattern configuration on the PE chip 400 based on the called multiple rows of expected patterns and corresponding timing parameters. Compared to the microinstruction module 312 sending the expected pattern every time during the matching process, this effectively reduces latency.

[0038] The method employs a two-level nested approach to iteratively call multiple rows of expected patterns and corresponding timing parameters. This includes: using the operand of the MatchStart microinstruction as the first-level loop count and the operand of the MatchLoop microinstruction as the inner second-level loop count, iteratively calling multiple rows of expected patterns and corresponding timing parameters from the MatchStart microinstruction to the EndMatch microinstruction in the order of the row vector; wherein, the loop from the MatchStart microinstruction to the MatchLoop microinstruction is the first-level loop, and the loop from the MatchLoop microinstruction to the EndMatch microinstruction is the second-level loop.

[0039] like Figure 2 As shown, the test module 314 in the test unit 310 can read the matching microinstructions, row vectors, expected patterns and timing parameters from the cache module 313 and cache them into the internal vector cache module 3141. The multiple rows of expected patterns and corresponding timing parameters in the vector cache module 3141 are called in a two-level nested manner to configure the pattern of the PE chip 400.

[0040] Furthermore, in the test module 314, the vector cache module 3141 retrieves and caches the matching microinstructions, expected patterns, and timing parameters from the cache module 313. By using the vector cache module 3141 to cache relevant data, data does not need to be repeatedly retrieved from the cache module 313 during the matching loop, thus avoiding impacting the matching loop efficiency. The vector read / write control module 3142 reads the matching microinstructions from the vector cache module 3141 in the order of row vectors, and uses a two-level nested approach to cyclically call multiple rows of expected patterns and corresponding timing parameters from the vector cache module 3141 and send them to the driver module 3143. The driver module 3143 performs pattern configuration on the PE chip 400 based on the received multiple rows of expected patterns and corresponding timing parameters. Alternatively, the vector read / write control module 3142 can cache the matching microinstructions and expected patterns in internal RAM (the timing parameters do not change during the matching loop, so caching is not required), and use a two-level nested approach to cyclically call multiple rows of expected patterns and corresponding timing parameters corresponding to the matching microinstructions and send them to the driver module 3143.

[0041] The pattern file also contains pin information corresponding to the desired pattern. The pin information is stored from storage module 311 into cache module 313 along with the desired pattern, and then cached into vector cache module 3141. Vector read / write control module 3142 sends multiple lines of desired pattern, corresponding pin information, and corresponding timing parameters to driver module 3143. Driver module 3143 configures the PE chip 400 according to the pin information, so that the PE chip 400 compares the output signal of the corresponding pin with the desired pattern.

[0042] Step 132: The test unit receives the response pattern returned by the PE chip after comparing the output signal of the device under test (DUT) with the expected pattern, and analyzes it to obtain the pin matching result of the DUT. The response pattern represents the original comparison result of each pin. The test unit 310 can determine which pins of the DUT are successfully matched and which pins are not matched based on the response pattern and the expected pattern, thereby obtaining the pin matching result of the DUT.

[0043] In this embodiment, step 132 includes: sampling multiple rows of response patterns according to the timing parameters corresponding to each row of expected patterns. These multiple rows of response patterns are obtained by comparing the multiple rows of expected patterns and corresponding timing parameters configured by the PE chip based on the MatchStart microinstruction to the MatchLoop microinstruction with the output signal of the device under test. If the response patterns of multiple row vectors between the MatchStart and MatchLoop microinstructions all match successfully, the matching operation is stopped, and the successful matching result is taken as the pin matching result. If any row of the response patterns of multiple row vectors between the MatchStart and MatchLoop microinstructions fails to match, and the actual number of operations of the MatchStart microinstruction has not reached the first-level loop count, then the multiple rows of response patterns are re-acquired and the matching operation is performed until the actual number of operations of the MatchStart microinstruction reaches the first-level loop count, and the pin matching result corresponding to the first-level loop count is output. The pin matching result corresponding to the first-level loop count includes either a successful matching result or a failed matching result.

[0044] Specifically, across multiple lines of MatchStart micro-instructions to EndMatch micro-instructions, it is expected that the pattern and dummy can share a timing parameter, and the test unit continuously samples multiple lines of response patterns based on the same timing parameter.

[0045] Specifically, the PE chip compares the output signal of the device under test (DUT) with the expected level (VOH, the expected high level of the DUT output, and VOL, the expected low level of the DUT output; VOH and VOL remain constant within a test item) in the expected pattern to obtain the response pattern (comparison result). The test unit samples the response pattern according to the timing parameter, and then performs a matching operation between the response pattern of each row and the expected pattern of the corresponding row to obtain the matching result. Specifically, if the expected pattern of the same row is H and the response pattern is 1, the match is successful; if the expected pattern of the same row is L and the response pattern is 0, the match is successful; if the expected pattern of the same row is H and the response pattern is 0, the match fails; if the expected pattern of the same row is L and the response pattern is 1, the match fails; if the expected pattern of the same row is X and the response pattern is 1 or 0, the match is successful.

[0046] In another embodiment, the desired pattern and desired levels (VOH, VOL) ​​are configured separately in a pattern file. The test unit configures VOH and VOL to the PE chip. The PE chip receives VOH and VOL, and the CA comparator and CB comparator in the PE chip compare VOH and VOL with the actual output level of the device under test (DUT) to obtain the comparison results CA value and CB value. The test unit samples the CA value and CB value according to the timing parameter setting. If the actual output level is higher than VOH, the CA value is 1, otherwise it is 0. If the actual output level is higher than VOL, the CB value is 1, otherwise it is 0. The response pattern is a combination of CA value and CB value, which is represented by three combinations: 01, 00, and 11. The combination form 10 does not exist. Furthermore, the matching of expected and response patterns in the same row is as follows: If the expected pattern is H and the response pattern is 11, the match is successful; if the response pattern is 01 or 00, the match fails. If the expected pattern is L and the response pattern is 00, the match is successful; if the response pattern is 11 or 10, the match fails. If the expected pattern is M (expected output intermediate state) and the response pattern is 01, the match is successful; if the response pattern is 00 or 11, the match fails. If the expected pattern is X (regardless of input level), and the response pattern is 11, 00, or 01, all matches are successful.

[0047] Furthermore, it should be noted that both the expected pattern and the response pattern belong to the narrow sense of pattern, i.e., test vector. The expected pattern can be the sequence information of HHLLMX (H represents the expected input high level, L represents the expected input low level, M represents the expected output intermediate state or expected output intermediate level, and X represents that the input level is not important). The expected pattern can also include VOH, i.e. the expected high level output of the device under test, and VOL, i.e. the expected low level output of the device under test. The response pattern can be the sequence information of 01010 (or the comparison result of the output signal of the device under test and the expected pattern, represented by 2 bits).

[0048] Specifically, refer to Figure 2 The pin matching result of the DUT can be obtained by receiving the response pattern returned by the PE chip 400 after comparing the output signal of the device under test (DUT) with the expected pattern through the result statistics module 3144 in the test module 314. For example, the result statistics module 3144 can use 0 and 1 to represent the corresponding pin matching success and failure respectively, and obtain the pin matching result by combining them.

[0049] Since the response pattern represents the original comparison result of pin, the result statistics module 3144 counts the success and failure results of the response pattern from the start of the MatchStart micro-instruction to the end of the MatchLoop micro-instruction. If all the response patterns in this segment are successful, the match is considered successful, and the result of this successful match is output as the pin matching result. If any response pattern fails, the loop is considered to have failed, the actual number of operations of the MatchStart micro-instruction in this round is counted, and the next round of looping is started again until all the first-level loop counts of the MatchStart micro-instruction are executed (i.e., the actual number of operations of the MatchStart micro-instruction reaches the first-level loop count). Regardless of whether the match is successful or not, the pin matching result corresponding to the first-level loop count is output as the final matching result.

[0050] Specifically, such as Figure 5 As shown, the first column is a row vector, which can be understood as row numbers. The second column is a micro-instruction. Taking the matching of 5 pins of the device under test (DUT) as an example, the 5 columns on the right represent the expected pattern for pins 01, 02, 03, 04, and 05. Figure 5 It can be displayed on the host computer interface. The test module 314 configures the PE chip 400 according to the row vector order, repeatedly using multiple rows of expected patterns and corresponding timing parameters based on the matching microinstructions. It receives the response pattern returned by the PE chip 400 after comparing the output signal of the device under test (DUT) with the expected pattern. If there is a pin mismatch between the expected pattern and the response pattern, the matching loop continues, and the multiple rows of expected patterns are called again to configure the PE chip 400, until the matching loop reaches the first-level loop count (e.g., 8000 times). Figure 5 The expected pattern highlighted in red indicates that the corresponding pin failed to match after the matching loop reached the first-level loop count.

[0051] Understandably, please continue to refer to this. Figure 5 Taking pin03 as an example, the expected pattern of multiple rows is reused in a loop, specifically the expected pattern of multiple rows corresponding to rows 1216 to 1231, which are HLLHHHLH in sequence. From rows 1232 to 1236, five pins have no expected pattern configured, represented by a dummy. The purpose of executing the dummy in the second-level loop is to wait for the pin matching result of the previous first-level loop. It can be understood that in row 1237, the test unit 310 inputs an stimulus pattern of 1 to pin01 of the DUT.

[0052] When the test unit 310 is in asynchronous mode, after the test unit 310 executes a matching loop and obtains the pin matching result, if all pins are successfully matched, there is no need to continue the matching loop and the pin matching result can be determined; if there are pins that fail to match, the matching loop continues and the test unit 310 calls the expected pattern of multiple lines again to configure the pattern of the PE chip 400 until the matching loop reaches the first-level loop count, and the last obtained pin matching result is retained.

[0053] In one embodiment, after step S130, the method further includes: the test unit storing the matching failure result data into a result storage device. The matching failure result data includes the row vector of the matching failure, the matching pin information corresponding to the matching failure row vector, and the corresponding expected pattern and response pattern, wherein the matching pin information refers to the matching PIN number. Figure 2 As shown, the result statistics module 3144 can send the matching failure result data and storage instruction to the matching failure cache module 317 based on the response pattern received when the matching micro-instruction detection reaches the first-level loop count; the matching failure cache module 317 converts the matching failure result data according to the storage protocol according to the storage instruction and stores it into the result storage device 320.

[0054] Specifically, the result statistics module 3144 receives the response pattern returned by the PE chip 400 and analyzes it to obtain the pin matching result. Specifically, the result statistics module 3144 matches the expected pattern and the response pattern to obtain the pin matching result. To filter invalid data during the matching loop, it also sends a storage instruction to the matching failure cache module 317, controlling whether the matching failure cache module 317 performs a matching result storage operation on the result storage device 320. The result storage device 320 can be DDR or other types of storage devices. For example, when the storage instruction is 1, the matching failure cache module 317 does not perform a storage operation; when the storage instruction is 0, the matching failure cache module 317 performs a storage operation. After obtaining the pin matching result, when all pins are successfully matched, the result statistics module 3144 outputs a storage instruction of 0, controlling the matching failure cache module 317 to perform a successful matching result storage operation. Specifically, this can be done by setting the result storage device 320 to empty (or storing a successful matching flag) to indicate that all pins are successfully matched. When the matching loop reaches the first-level loop count, if there are still unmatched pins, the result statistics module 3144 outputs a storage instruction of 0, controlling the matching failure cache module 317 to perform a matching failure result data storage operation. Specifically, this can involve storing the vector row of the matching failure, the matching pin information corresponding to the matching failure vector, and the corresponding expected pattern and response pattern into the result storage device 320. Conversely, if all pins are successfully matched when the matching loop reaches the first-level loop count, the result statistics module 3144 also outputs a storage instruction of 0, controlling the matching failure cache module 317 to perform a matching success result storage operation.

[0055] Step S140: The test unit performs corresponding matching completion processing based on the mode setting parameters and pin matching results. It can be understood that after obtaining the pin matching results, the test unit 310 will perform different matching completion processing operations depending on the operating mode.

[0056] In one embodiment, step S140 includes step 142: when the test unit determines that it is in synchronous mode based on the mode setting parameters, it sends the pin matching result to the communication board; the communication board receives the pin matching result sent by each test unit in the test board, converts the pin matching result according to the test unit mapping parameters, obtains the site matching result of each test unit corresponding to the site, and determines that the pin matching result of the corresponding site has been received according to the site identifier carried in the test unit mapping parameters. If the site matching result meets the synchronous matching completion condition, then the pin result matching is completed.

[0057] Furthermore, when the mode setting parameters determine that it is in synchronous mode, after the test unit 310 performs each matching loop and obtains the pin matching result, it sends the pin matching result to the communication board 200. In this embodiment, as shown... Figure 2 As shown, in synchronous mode, the result statistics module 3144 receives the matching micro-instructions and expected pattern sent by the vector read / write control module 3142, and receives the response pattern returned by the PE chip 400 after comparing the output signal of the device under test (DUT) with the expected pattern. It analyzes and obtains the pin matching result of the DUT and sends it to the micro-instruction module 312. The micro-instruction module 312 sends the pin matching result obtained in each matching cycle to the communication board 200 through the uplink module 315. Specifically, when the matching cycle reaches the first-level cycle count, the micro-instruction module 312 also carries a "last" identifier in the uploaded pin matching result so that the communication board 200 can identify it as the last pin matching result after the first-level cycle count.

[0058] The conditions for successful synchronous matching are that each site successfully matches or the cyclic matching reaches the first-level cycle count. For example... Figure 2 As shown, the communication board 200 can connect to various test units 310 in multiple test boards 300, and receive the pin matching results sent by each test unit 310. The communication board 200 converts the pin matching results based on the test unit mapping parameters to obtain the site matching results of the sites associated with each test unit 310. For example, by combining the test unit mapping parameters to analyze whether all pins of the corresponding site (i.e., the site associated with each test unit 310) are successfully matched, 1 indicates that all pins of the corresponding site are successfully matched (i.e., the site matching is successful), and 0 indicates that there are pin matching failures in the corresponding site (i.e., the site matching fails), thus obtaining the site matching results.

[0059] Based on the converted site matching results and the site identifiers carried in the test unit mapping parameters, the communication board 200 determines whether all site matching results corresponding to the site identifiers have been obtained after the first round of matching. It analyzes whether all sites corresponding to the site identifiers have successfully matched. If so, the pin matching is complete. If only some sites have successfully matched (all pins of the DUT on a site have successfully matched in the current matching cycle, then this site has successfully matched; if one pin fails, then this site has failed), the successfully matched site is recorded, and subsequent cycles will not check for successfully matched sites. If no site matching is successful in this cycle, the communication board 200 continues to wait for the next matching cycle (e.g., the second round, the third round, etc.) to report the pin matching results of the unsuccessful sites from the previous round and convert them into site matching results, until it receives the pin matching results carrying the last identifier reported by the test unit 310. After conversion by the communication board 200, these results become the final site matching results for the corresponding sites, and the pin matching is complete. Regardless of whether all sites ultimately match successfully, the matching operation based on the matching micro-instruction ends.

[0060] Furthermore, with Figure 3 For example, different test boards 300 have different slot numbers (e.g., 01 and 02 represent different slot numbers of different test boards 300). In one test board 300, FE0 is associated with pin01 of the device under test (DUT0) where site0 is located, and FE1 is associated with pin02 of the device under test (DUT0) where site0 is located. site0 is the site corresponding to the site identifier. The communication board 200 finally counts the matching results of site0, which includes the corresponding test board slot number, test unit number, and the matching results of pins 01 and 02 of DUT0. If both pins are successful, site0 is considered to be successfully matched. If both pins reach the first-level loop count together, it is considered to be a timeout and site0 is considered to be unsuccessful.

[0061] In one embodiment, after step 142, the method further includes: the communication board generating a verification instruction based on the converted pin matching result and sending it to the test unit; the converted pin matching result is obtained by the test unit mapping parameters from the site matching result; after receiving the verification instruction, the test unit sets the status of the pins of the device under test that failed to match according to the configured status flags.

[0062] Specifically, after the pin matching is completed, the communication board 200 broadcasts a verification command to the corresponding test board 300, instructing the test unit 310 in the test board 300 to set the status of the pins of the device under test (DUT) that failed to match. Setting the status of the pins of the DUT that failed to match includes setting the pins of the DUT that failed to match to continue running the pattern, output high impedance, output low level, or output high level.

[0063] Specifically, after the pin matching is completed, the communication board 200 converts the successful and failed site matching results into transformed pin matching results (successful and failed pin matching results) based on the test unit mapping parameters and loads them into the verification command for broadcast. The test unit 310, based on the pin matching results carried in the verification command, performs status settings for the failed pins according to the configured status flags. The status flags can be stored in the storage module 311 along with the pattern file. After the downlink module 316 receives the verification command and sends it to the micro-instruction module 312, the micro-instruction module 312 extracts the status flags from the storage module 311 and sends the status flags and failed pin information to the vector cache module 3141. The vector cache module 3141 sets the status of the failed pins of the device under test (DUT) based on the status flags.

[0064] Furthermore, the pin matching results sent by the test unit to the communication board 200 only contain the concept of the test unit channel and do not have a corresponding relationship with the site. The communication board 200 binds the channel of the pin matching result to the corresponding site based on the site matching result of the test unit mapping parameters, and then converts it into a successful and unsuccessful pin matching result (i.e., the converted pin matching result, which contains the correspondence between the DUT matching pin and the site) based on the test unit mapping parameters and sends it to the corresponding test unit. The DUT pin of the successful site associated with the test unit is the successfully matched pin, and the DUT pin of the unsuccessful site associated with the test unit is the unsuccessful matched pin.

[0065] Depending on the type of status flag, the method for setting the status of a pin that fails to match the device under test (DUT) will vary. In this embodiment, there are four status flags: 2'b00 indicates that the failed pin continues to run the pattern; 2'b01 indicates that the failed pin is set to a high-impedance state, continuously outputting a high-impedance state or outputting 0; 2'b10 indicates that the failed pin runs drive0 and outputs a low level; 2'b11 indicates that the failed pin runs drive1 and outputs a high level. The first status flag indicates that the failed pin can be ignored and the pattern can continue to run. The latter three status flags indicate that the failed pin is configured to a corresponding locked state. The appropriate status flag can be selected according to the actual testing needs to set the status of the pin that fails to match the DUT.

[0066] Furthermore, after the communication board generates a verification command based on the converted pin matching result and sends it to the test unit, the method also includes: when the test unit detects that the number of matching completion loops it has executed is inconsistent with the number of matching completion loops carried by the verification command, it outputs an alarm message.

[0067] The number of loop completions is defined as the number of loops at which a matching operation is successfully completed when the site corresponding to the site identifier is successfully matched, or when the matching micro-instruction detects that the loop matching has reached the first-level loop count. If the site corresponding to the site identifier is successfully matched, the communication board 200 uses the number of loops at which the successful matching is detected as the number of loop completions. If the matching loop reaches the first-level loop count, the communication board 200 uses the first-level loop count as the number of loop completions. The communication board 200 broadcasts a verification instruction carrying the number of loop completions. The test unit 310 compares the number of loop completions carried in the verification instruction with the number of loop completions executed by itself. If they are inconsistent, an alarm message is output. The alarm message can be output in the form of audible and visual alarms, displaying setting information, sending an alarm signal to the host computer 100, or other methods, or a combination of multiple alarm methods.

[0068] In addition, after the communication board generates a verification command based on the converted pin matching result and sends it to the test unit, the method further includes: the communication board sending a continue execution command to the test unit; after receiving the continue execution command, the test unit extracts the next micro-instruction in the pattern file, as well as the corresponding pattern and the corresponding timing parameters, and performs the next operation.

[0069] The communication board 200 can broadcast a continue execution command to the test board 300. In the test unit 310, after receiving the continue execution command through the downlink module 316 and sending it to the micro-instruction module 312, the micro-instruction module 312 extracts the next micro-instruction from the pattern file, along with the corresponding pattern and timing parameters, for the next operation. Specifically, if a matching micro-instruction may appear later in the pattern file, the test unit 310 performs another matching operation. For pins whose status was set in the current matching operation, matching can continue in the next matching operation. If the next micro-instruction in the pattern file is a different type of micro-instruction, the test unit 310 performs the corresponding type of operation, and for pins whose status was set in the current matching operation, the set status is maintained.

[0070] In one embodiment, after step 142, the method further includes: when the cumulative number of verification commands issued by the communication board has not reached the set number of matching groups, sending a verification command and a continue execution command to the test unit; when the cumulative number of verification commands issued by the communication board reaches the set number of matching groups, sending a verification command and a continue execution command to the test unit, and exiting the matching data collection state.

[0071] Similarly, the number of matching groups can be configured on the communication board 200 via the host computer 100, which serves as the basis for determining how many matching operations need to be performed. After each pin result matching is completed, the communication board 200 sends a verification command and a continue execution command to the test unit 310. That is, the sent verification command can represent the number of matching operations completed.

[0072] If the cumulative number of verification commands issued does not reach the set number of matching groups, the communication board 200 continues to issue verification commands and continue execution commands to the test unit 310. The test unit 310 sets the status of the pins of the device under test (DUT) that failed to match according to the configured status flags, and outputs an alarm message when it detects that the number of matching completion loops it has executed is inconsistent with the number of matching completion loops carried in the verification command. After receiving the continue execution command, the test unit 310 also extracts the next micro-instruction (which can be a matching micro-instruction or other types of micro-instruction) from the pattern file, as well as the corresponding pattern and corresponding timing parameters, for the next operation.

[0073] If the cumulative number of verification commands issued reaches the set number of matching groups, it indicates that all matching operations have been completed. The communication board 200 continues to issue verification commands and continue execution commands to the test unit 310 and exits the matching data collection state, meaning it no longer waits to receive site matching results. The test unit 310 sets the status of the pins of the device under test (DUT) that failed to match according to the configured status flags, and outputs an alarm message when it detects that the number of matching completion loops it has executed is inconsistent with the number of matching completion loops carried by the verification command. After receiving the continue execution command, the test unit 310 also extracts the next micro-instruction (other types of micro-instructions) from the pattern file, as well as the corresponding pattern and corresponding timing parameters, for the next operation.

[0074] In one embodiment, step S140 may include step 144: If the test unit determines the mode to be asynchronous based on the mode setting parameters, and the pin matching result meets the asynchronous matching completion condition, then the pin result matching is complete, and the next microinstruction, the corresponding pattern, and the corresponding timing parameters in the pattern file are extracted for the next operation. The asynchronous matching completion condition includes that all channels of the test unit 310 match successfully during the execution of the MatchStart microinstruction to the MatchLoop microinstruction, or that the matching loop reaches the first-level loop count.

[0075] When the test unit 310 is in asynchronous mode, after the test unit 310 executes a matching loop and obtains the pin matching result, if all pins are successfully matched, there is no need to continue the matching loop and the pin matching result can be determined; if there are pins that fail to match, the matching loop continues and the test unit 310 calls the expected pattern of multiple lines again to configure the pattern of the PE chip 400 until the matching loop reaches the first-level loop count, and the last obtained pin matching result is retained.

[0076] The next microinstruction can be a matching microinstruction or other types of microinstructions. For example... Figure 2As shown, in asynchronous mode, there is a one-to-one correspondence between test unit 310 and the site. Therefore, the pin matching result obtained after one matching loop can represent the corresponding site matching result. During the execution process from MatchStart to MatchLoop, if all channels of test unit 310 match successfully, or the matching loop reaches the first-level loop count (the last time), then the pin result matching in asynchronous mode is considered complete, that is, the matching operation based on the matching micro-instruction ends. Test unit 310 extracts the next micro-instruction (matching micro-instruction or other type of micro-instruction) from the pattern file, the corresponding pattern, and the corresponding timing parameters for the next operation.

[0077] Furthermore, after step 144, the method further includes: the test unit sets the status of the pins of the device under test that failed to match according to the status flags in the pattern file; wherein, setting the status of the pins of the device under test that failed to match includes setting the pins of the device under test that failed to match to continue running the pattern, output high impedance, output low level, or output high level.

[0078] It is understandable that in asynchronous mode, the specific method by which the test unit 310 sets the status of the pins of the device under test (DUT) that fail to match is similar to that in synchronous mode, and will not be elaborated here.

[0079] In one embodiment, such as Figure 2 As shown, a chip tester is also provided, including a host computer 100, a communication board 200, and a test board 300. The test board 300 includes multiple test units 310. Each test unit 310 is connected to the host computer 100 through the communication board 200. The channel of each test unit 310 is connected to the pin of the device under test (DUT) of the corresponding site. The chip tester performs multi-line pattern matching to complete the processing according to the above method.

[0080] In one embodiment, the test board 300 further includes a PE chip 400; the test unit 310 includes a storage module 311, a micro-instruction module 312, a cache module 313, a test module 314, an uplink module 315, a downlink module 316, and a mode register (not shown in the figure). The micro-instruction module 312 is connected to the storage module 311, the cache module 313, the uplink module 315, the downlink module 316, and the mode register. The uplink module 315 is connected to the communication board 200, the downlink module 316 is connected to the communication board 200, the test module 314 is connected to the cache module 313 and the micro-instruction module 312, and the test module 314 is also connected to the pin of the device under test (DUT) of the corresponding site through the PE chip 400.

[0081] The microinstruction module 312 is configured to: extract mode setting parameters from the mode register, and extract matching microinstructions, row vectors, multi-line expected patterns and timing parameters from the pattern file from the storage module 311 and cache them in the cache module 313; and when the mode setting parameters determine that the synchronous mode is selected, send the received pin matching result to the communication board 200.

[0082] The test module 314 is configured to: read the matching micro-instruction, row vector, multi-line expected pattern and corresponding timing parameters from the cache module 313; perform pattern configuration on the PE chip 400 by cyclically reusing the multi-line expected pattern and corresponding timing parameters according to the row vector order based on the matching micro-instruction; and receive the response pattern returned by the PE chip 400 after comparing the output signal of the device under test (DUT) with the multi-line expected pattern, analyze the result of the pin matching of the DUT and send it to the micro-instruction module 312.

[0083] In one embodiment, the test module 314 includes a vector cache module 3141, a vector read / write control module 3142, a driver module 3143, and a result statistics module 3144. The vector cache module 3141 is connected to the cache module 313 and the vector read / write control module 3142. The vector read / write control module 3142 is connected to the driver module 3143 and the result statistics module 3144. The driver module 3143 is connected to the PE chip 400. The result statistics module 3144 is connected to the PE chip 400 and the microinstruction module 312.

[0084] The vector caching module 3141 is configured to retrieve the matching microinstructions, multi-line expected patterns and corresponding timing parameters from the caching module 313 and cache them.

[0085] The vector read / write control module 3142 is configured to read matching micro-instructions from the vector cache module in the order of row vectors, and use a two-level nested method to cyclically call multiple rows of expected patterns and corresponding timing parameters in the vector cache module 3141 and send them to the driver module 3143; the matching micro-instructions include the MatchStart micro-instruction, the MatchLoop micro-instruction, and the EndMatch micro-instruction.

[0086] The driver module 3143 is configured to perform pattern configuration on the PE chip 400 based on the received multi-line expected pattern and corresponding timing parameters.

[0087] The result statistics module 3144 is configured to: receive the matching micro-instruction and multi-line expected pattern sent by the vector read / write control module 3142; and sample the multi-line response pattern according to the timing parameter corresponding to each line expected pattern. The multi-line response pattern is obtained by comparing the multi-line expected pattern and corresponding timing parameter configured by the PE chip 400 based on the MatchStart micro-instruction to the MatchLoop micro-instruction with the output signal of the device under test (DUT); if the response patterns of multiple line vectors between the MatchStart micro-instruction and the MatchLoop micro-instruction are all successfully matched, the matching stops. The matching operation takes the successful matching result as the pin matching result. If any row in the response pattern of multiple row vectors between the MatchStart microinstruction and the MatchLoop microinstruction fails to match, and the actual number of operations of the current MatchStart microinstruction has not reached the first-level loop count, then multiple response patterns are reacquired and the matching operation is performed again until the actual number of operations of the MatchStart microinstruction reaches the first-level loop count. The pin matching result corresponding to the first-level loop count is output, and finally the pin matching result is sent to the microinstruction module 312. The pin matching result corresponding to the first-level loop count includes either a successful matching result or a failed matching result.

[0088] In one embodiment, the microinstruction module 312 is further configured to: when the asynchronous mode is determined based on the mode setting parameters, send the matching failure pin information sent by the result statistics module 3144 and the status flag in the pattern file to the vector cache module 3141; or when the synchronous mode is determined based on the mode setting parameters, send the matching failure pin information in the verification instruction issued by the communication board 200 and the status flag in the pattern file to the vector cache module 3141.

[0089] The vector cache module 3141 is also configured to: after the pin result matching is completed in synchronous or asynchronous mode, set the status of the pin that failed to match the device under test according to the configured status flag.

[0090] In one embodiment, the test unit 310 further includes a matching failure cache module 317, and the test board 300 further includes a result storage device 320. The matching failure cache module 317 is connected to the result statistics module 3144 and the result storage device 320.

[0091] The result statistics module 3144 is also configured to send the matching failure result data and storage instructions to the matching failure cache module 317; wherein, the matching failure result data includes the row vector of the matching failure, the matching pin information corresponding to the row vector of the matching failure, and the corresponding expected pattern and response pattern.

[0092] The matching failure caching module 317 is configured to convert the matching failure result data according to the storage protocol based on the storage instruction and store it into the result storage device 320.

[0093] As can be understood, the specific implementation method of the chip testing machine mentioned above has been explained in detail, and will not be repeated here.

[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for matching results of multi-line patterns, characterized in that, include: When the host computer carries matching micro-instructions in the pattern file, it determines the corresponding mode setting parameters according to the pattern file. The host computer sends the pattern file and mode setting parameters to the test unit in the test board. The test unit extracts the matching micro-instructions and multiple lines of expected patterns from the pattern file, and repeatedly reuses the multiple lines of expected patterns according to the matching micro-instructions to obtain the pin matching result obtained by matching the output signal of the device under test. The test unit performs the corresponding matching process based on the mode setting parameters and the pin matching result.

2. The method according to claim 1, characterized in that, When the host computer carries matching microinstructions in the pattern file, it determines the corresponding mode setting parameters based on the pattern file, including: When the host computer detects that the pattern file contains matching micro-instructions, it analyzes whether the matching pins of the device under test on each site are connected to the same test unit based on the test unit mapping parameters and the pattern file, and each site is connected to a different test unit. If the conditions are met, it is in asynchronous mode; otherwise, it is in synchronous mode, and the corresponding mode setting parameters are obtained. The test unit mapping parameters represent the correspondence between the site associated with the test unit and the test unit channel in different test boards.

3. The method according to claim 1, characterized in that, The pattern file also includes row vectors and timing parameters corresponding to matching micro-instructions; the test unit extracts the matching micro-instructions and multiple rows of expected patterns from the pattern file, and repeatedly reuses the multiple rows of expected patterns according to the matching micro-instructions to obtain the pin matching result obtained by matching the output signal of the device under test, including: The test unit extracts the matching micro-instructions, row vectors, expected pattern, and timing parameters from the pattern file, and performs pattern configuration on the PE chip by cyclically reusing the expected pattern and timing parameters of multiple rows according to the order of the row vectors and the matching micro-instructions. The test unit receives the response pattern returned by the PE chip after comparing the output signal of the device under test with the expected pattern, and analyzes it to obtain the pin matching result of the device under test.

4. The method according to claim 3, characterized in that, The PE chip is pattern-configured according to the desired pattern and timing parameters of multiple rows in a cyclic reuse manner based on the matching microinstructions, following the row vector order, including: Following the order of the row vectors, the expected pattern and corresponding timing parameters of multiple rows are called in a two-level nested manner according to the matching micro-instructions; The PE chip is configured with a pattern based on the multi-line expected pattern and the corresponding timing parameter.

5. The method according to claim 4, characterized in that, The matching micro-instructions include the MatchStart micro-instruction, the MatchLoop micro-instruction, and the EndMatch micro-instruction; following the order of the row vectors, the matching micro-instructions are used in a two-level nested loop to call multiple rows of expected patterns and corresponding timing parameters, including: The operands of the MatchStart microinstruction are used as the first-level loop count, and the operands of the MatchLoop microinstruction are used as the inner second-level loop count. The expected patterns and corresponding timing parameters of multiple rows from the MatchStart microinstruction to the EndMatch microinstruction are called in a loop according to the row vector order. The loop from the MatchStart microinstruction to the MatchLoop microinstruction is the first-level loop, and the loop from the MatchLoop microinstruction to the EndMatch microinstruction is the second-level loop.

6. The method according to claim 5, characterized in that, The test unit receives the response pattern returned by the PE chip after comparing the output signal of the device under test with the expected pattern, and analyzes it to obtain the pin matching result of the device under test, including: Multiple response patterns are sampled based on the timing parameters corresponding to each expected pattern. The multiple response patterns are obtained by comparing the multiple expected patterns and corresponding timing parameters configured by the PE chip based on the MatchStart microinstruction to the MatchLoop microinstruction with the output signal of the device under test. If the response patterns of multiple row vectors between the MatchStart micro-instruction and the MatchLoop micro-instruction all match successfully, the matching operation stops, and the successful matching results are used as the pin matching results. If any row in the response pattern of multiple row vectors between the MatchStart microinstruction and the MatchLoop microinstruction fails to match, and the actual number of operands of the current MatchStart microinstruction has not reached the first-level loop count, then multiple response patterns are reacquired and matching operations are performed until the actual number of operands of the MatchStart microinstruction reaches the first-level loop count. The pin matching result corresponding to the first-level loop count is then output, where the pin matching result corresponding to the first-level loop count includes either a successful match or a failed match.

7. The method according to claim 6, characterized in that, The test unit extracts matching micro-instructions and multiple lines of expected patterns from the pattern file. After repeatedly reusing the multiple lines of expected patterns according to the matching micro-instructions to obtain the pin matching result obtained by matching the output signal of the device under test, the test unit further includes: The test unit stores the matching failure result data into the result storage device; the matching failure result data includes the row vector of the matching failure, the matching pin information corresponding to the row vector of the matching failure, and the corresponding expected pattern and response pattern.

8. The method according to any one of claims 1 to 7, characterized in that, The testing unit performs corresponding matching processing based on the mode setting parameters and the pin matching result, including: If the test unit is set to asynchronous mode based on the mode setting parameters and the pin matching result meets the asynchronous matching completion condition, then the pin matching is completed. The next microinstruction, the corresponding pattern, and the corresponding timing parameters in the pattern file are then extracted for the next operation. In asynchronous mode, the test unit and the site are in one-to-one correspondence, and the pins of the device under test in the same site are connected to the channels of the same test unit. The asynchronous matching completion condition includes that all channels of the test unit are successfully matched during the execution of the MatchStart microinstruction to the MatchLoop microinstruction, or the matching loop reaches the first-level loop count.

9. The method according to claim 8, characterized in that, If the test unit is set to asynchronous mode based on the mode setting parameters, and the pin matching result meets the asynchronous matching completion condition, then after the pin result matching is completed, the test unit further includes: The test unit sets the status of pins that failed to match the device under test according to the status flags in the pattern file. Among them, the state settings of the pins of the device under test that failed to match include setting the pins of the device under test that failed to match to continue running the pattern, output high impedance, output low level, or output high level.

10. The method according to any one of claims 1 to 7, characterized in that, The host computer sends the test unit mapping parameters to the communication board, as well as the mode setting parameters and pattern file to the test unit; the test unit is configured to determine the working mode according to the mode setting parameters.

11. The method according to claim 10, characterized in that, The testing unit performs corresponding matching processing based on the mode setting parameters and the pin matching result, including: When the test unit determines that it is in synchronous mode based on the mode setting parameters, it sends the pin matching result to the communication board. In synchronous mode, the channel of the same test unit is connected to the pins of the device under test (DUT) of the same or different sites, and the pins of the DUT of the same site are connected to the channels of the same or different test units. The communication board receives the pin matching results sent by each test unit in the test board, converts the pin matching results according to the test unit mapping parameters to obtain the site matching results of each test unit's corresponding site, and determines that the pin matching results of the corresponding site have been received according to the site identifier carried in the test unit mapping parameters. If the site matching results meet the synchronous matching completion conditions, then the pin matching is completed.

12. The method according to claim 11, characterized in that, After determining that the pin matching result for the corresponding site has been received based on the site identifier carried in the test unit mapping parameters, and the site matching result meets the synchronous matching completion condition, the pin result matching is completed, and then the process further includes: The communication board generates a verification command based on the converted pin matching result and sends it to the test unit. The converted pin matching result is obtained by the test unit mapping parameters by converting the site matching result. After receiving the verification command, the test unit sets the status of the pins of the device under test that failed to match according to the configured status flags. Among them, the state settings of the pins of the device under test that failed to match include setting the pins of the device under test that failed to match to continue running the pattern, output high impedance, output low level, or output high level.

13. The method according to claim 12, characterized in that, The synchronization matching completion condition is that each site successfully matches or the cyclic matching reaches the first-level cycle count; after the communication board generates a verification command based on the converted pin matching result and sends it to the test unit, it also includes: When the test unit detects that the number of matching completion loops it executes is inconsistent with the number of matching completion loops carried by the verification command, it outputs an alarm message; The number of matching cycles is the number of cycles when the site identifier is successfully matched with the corresponding site, or when the matching micro-instruction detects that the cycle matching has reached the first-level cycle count.

14. The method according to claim 13, characterized in that, After the communication board generates a verification command based on the converted PIN matching result and sends it to the test unit, it also includes: The communication board sends a continue execution command to the test unit; After receiving the continue execution instruction, the test unit extracts the next micro-instruction, the corresponding pattern, and the corresponding timing parameters from the pattern file for the next operation.

15. The method according to claim 14, characterized in that, After determining that the pin matching result for the corresponding site has been received based on the site identifier carried in the test unit mapping parameters, and the site matching result meets the synchronous matching completion condition, the pin result matching is completed, and then the process further includes: When the number of verification commands issued cumulatively does not reach the set number of matching groups, the communication board sends a verification command and a continue execution command to the test unit. When the number of verification commands issued reaches the set number of matching groups, the communication board sends a verification command and a continue execution command to the test unit and exits the matching data collection state.

16. A chip testing machine, characterized in that, The device includes a host computer, a test board, and a communication board. The test board includes multiple test units, each of which is connected to the host computer via the communication board. The channel of each test unit is connected to the pin of the device under test (DUT) of the corresponding site. The chip tester performs multi-line pattern matching processing according to the method described in any one of claims 1 to 15.

17. The chip testing machine according to claim 16, characterized in that, The test board also includes a PE chip; the test unit includes a storage module, a micro-instruction module, a cache module, a test module, an uplink module, a downlink module, and a mode register. The micro-instruction module is connected to the storage module, the cache module, the uplink module, the downlink module, and the mode register. The uplink module is connected to the communication board, the downlink module is connected to the communication board, the test module is connected to the cache module and the micro-instruction module, and the test module is also connected to the pin of the device under test of the corresponding site through the PE chip. The micro-instruction module is configured to: extract mode setting parameters from the mode register, and extract matching micro-instructions, row vectors, multi-line expected patterns and timing parameters from the pattern file from the storage module and cache them in the cache module; and when the mode setting parameters determine that the synchronous mode is selected, send the received pin matching result to the communication board. The test module is configured to: read matching micro-instructions, row vectors, multi-row expected patterns, and corresponding timing parameters from the cache module; perform pattern configuration on the PE chip by cyclically reusing the multi-row expected patterns and corresponding timing parameters according to the order of the row vectors; and receive the response pattern returned by the PE chip after comparing the output signal of the device under test with the multi-row expected patterns, analyze the results to obtain the pin matching result of the device under test, and send it to the micro-instruction module.

18. The chip testing machine according to claim 17, characterized in that, The test module includes a vector cache module, a vector read / write control module, a driver module, and a result statistics module. The vector cache module is connected to the cache module and the vector read / write control module. The vector read / write control module is connected to the driver module and the result statistics module. The driver module is connected to the PE chip. The result statistics module is connected to the PE chip and the microinstruction module. The vector caching module is configured to: acquire the matching micro-instructions, multi-line expected patterns, and corresponding timing parameters from the caching module and cache them; The vector read / write control module is configured to: read matching micro-instructions from the vector cache module in the order of row vectors, and use a two-level nested approach to cyclically call multiple rows of expected patterns and corresponding timing parameters in the vector cache module and send them to the driver module; the matching micro-instructions include MatchStart micro-instructions, MatchLoop micro-instructions, and EndMatch micro-instructions; The driving module is configured to: configure the PE chip according to the received multiple lines of expected patterns and corresponding timing parameters; The result statistics module is configured to: receive the matching micro-instruction and multiple expected patterns sent by the vector read / write control module; and sample multiple response patterns according to the timing parameters corresponding to each expected pattern. The multiple response patterns are obtained by comparing the multiple expected patterns and corresponding timing parameters configured by the PE chip between the MatchStart micro-instruction and the MatchLoop micro-instruction with the output signal of the device under test. If the response patterns of multiple row vectors between the MatchStart micro-instruction and the MatchLoop micro-instruction are all successfully matched, the matching operation is stopped, and the successful matching result is taken as the pin matching result. If any row of the response patterns of multiple row vectors between the MatchStart micro-instruction and the MatchLoop micro-instruction fails to match, and the actual number of operations of the current MatchStart micro-instruction has not reached the first-level loop count, the multiple response patterns are re-acquired and the matching operation is performed until the actual number of operations of the MatchStart micro-instruction reaches the first-level loop count. The pin matching result corresponding to the first-level loop count is output, and finally the pin matching result is sent to the micro-instruction module. The pin matching result corresponding to the first-level loop count includes a successful matching result or a failed matching result.

19. The chip testing machine according to claim 18, characterized in that, The micro-instruction module is also configured to: when the asynchronous mode is determined based on the mode setting parameters, send the matching failure pin information sent by the result statistics module and the status flag in the pattern file to the vector cache module; or when the synchronous mode is determined based on the mode setting parameters, send the matching failure pin information in the verification instruction issued by the communication board and the status flag in the pattern file to the vector cache module. The vector cache module is also configured to: after the pin result matching is completed in synchronous or asynchronous mode, set the status of the pin that failed to match the device under test according to the configured status flag.

20. The chip testing machine according to claim 18, characterized in that, The test unit further includes a matching failure caching module, and the test board further includes a result storage device. The matching failure caching module is connected to the result statistics module and the result storage device. The result statistics module is further configured to send matching failure result data and storage instructions to the matching failure cache module; wherein, the matching failure result data includes the row vector of the matching failure, the matching pin information corresponding to the matching failure row vector, and the corresponding expected pattern and response pattern; The matching failure caching module is configured to: convert the matching failure result data according to the storage protocol based on the storage instruction, and store it into the result storage device.

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